31 */
32
33#ifndef _SYS_EFX_IMPL_H
34#define _SYS_EFX_IMPL_H
35
36#include "efsys.h"
37#include "efx.h"
38#include "efx_regs.h"
39#include "efx_regs_ef10.h"
40
41/* FIXME: Add definition for driver generated software events */
42#ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
43#define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
44#endif
45
46#include "efx_check.h"
47
48
49#if EFSYS_OPT_FALCON
50#include "falcon_impl.h"
51#endif /* EFSYS_OPT_FALCON */
52
53#if EFSYS_OPT_SIENA
54#include "siena_impl.h"
55#endif /* EFSYS_OPT_SIENA */
56
57#if EFSYS_OPT_HUNTINGTON
58#include "hunt_impl.h"
59#endif /* EFSYS_OPT_HUNTINGTON */
60
61#ifdef __cplusplus
62extern "C" {
63#endif
64
65#define EFX_MOD_MCDI 0x00000001
66#define EFX_MOD_PROBE 0x00000002
67#define EFX_MOD_NVRAM 0x00000004
68#define EFX_MOD_VPD 0x00000008
69#define EFX_MOD_NIC 0x00000010
70#define EFX_MOD_INTR 0x00000020
71#define EFX_MOD_EV 0x00000040
72#define EFX_MOD_RX 0x00000080
73#define EFX_MOD_TX 0x00000100
74#define EFX_MOD_PORT 0x00000200
75#define EFX_MOD_MON 0x00000400
76#define EFX_MOD_WOL 0x00000800
77#define EFX_MOD_FILTER 0x00001000
78#define EFX_MOD_PKTFILTER 0x00002000
79
80#define EFX_RESET_MAC 0x00000001
81#define EFX_RESET_PHY 0x00000002
82#define EFX_RESET_RXQ_ERR 0x00000004
83#define EFX_RESET_TXQ_ERR 0x00000008
84
85typedef enum efx_mac_type_e {
86 EFX_MAC_INVALID = 0,
87 EFX_MAC_FALCON_GMAC,
88 EFX_MAC_FALCON_XMAC,
89 EFX_MAC_SIENA,
90 EFX_MAC_HUNTINGTON,
91 EFX_MAC_NTYPES
92} efx_mac_type_t;
93
94typedef struct efx_ev_ops_s {
95 efx_rc_t (*eevo_init)(efx_nic_t *);
96 void (*eevo_fini)(efx_nic_t *);
97 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
98 efsys_mem_t *, size_t, uint32_t,
99 efx_evq_t *);
100 void (*eevo_qdestroy)(efx_evq_t *);
101 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
102 void (*eevo_qpost)(efx_evq_t *, uint16_t);
103 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
104#if EFSYS_OPT_QSTATS
105 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
106#endif
107} efx_ev_ops_t;
108
109typedef struct efx_tx_ops_s {
110 efx_rc_t (*etxo_init)(efx_nic_t *);
111 void (*etxo_fini)(efx_nic_t *);
112 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
113 unsigned int, unsigned int,
114 efsys_mem_t *, size_t,
115 uint32_t, uint16_t,
116 efx_evq_t *, efx_txq_t *,
117 unsigned int *);
118 void (*etxo_qdestroy)(efx_txq_t *);
119 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
120 unsigned int, unsigned int,
121 unsigned int *);
122 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
123 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
124 efx_rc_t (*etxo_qflush)(efx_txq_t *);
125 void (*etxo_qenable)(efx_txq_t *);
126 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
127 void (*etxo_qpio_disable)(efx_txq_t *);
128 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
129 size_t);
130 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
131 unsigned int *);
132 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
133 unsigned int, unsigned int,
134 unsigned int *);
135 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
136 size_t, boolean_t,
137 efx_desc_t *);
138 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
139 uint32_t, uint8_t,
140 efx_desc_t *);
141 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
142 efx_desc_t *);
143#if EFSYS_OPT_QSTATS
144 void (*etxo_qstats_update)(efx_txq_t *,
145 efsys_stat_t *);
146#endif
147} efx_tx_ops_t;
148
149typedef struct efx_rx_ops_s {
150 efx_rc_t (*erxo_init)(efx_nic_t *);
151 void (*erxo_fini)(efx_nic_t *);
152#if EFSYS_OPT_RX_HDR_SPLIT
153 efx_rc_t (*erxo_hdr_split_enable)(efx_nic_t *, unsigned int,
154 unsigned int);
155#endif
156#if EFSYS_OPT_RX_SCATTER
157 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
158#endif
159#if EFSYS_OPT_RX_SCALE
160 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
161 efx_rx_hash_type_t, boolean_t);
162 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
163 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
164 size_t);
165#endif
166 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
167 unsigned int, unsigned int,
168 unsigned int);
169 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
170 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
171 void (*erxo_qenable)(efx_rxq_t *);
172 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
173 unsigned int, efx_rxq_type_t,
174 efsys_mem_t *, size_t, uint32_t,
175 efx_evq_t *, efx_rxq_t *);
176 void (*erxo_qdestroy)(efx_rxq_t *);
177} efx_rx_ops_t;
178
179typedef struct efx_mac_ops_s {
180 efx_rc_t (*emo_reset)(efx_nic_t *); /* optional */
181 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
182 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
183 efx_rc_t (*emo_addr_set)(efx_nic_t *);
184 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
185 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
186 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
187 efx_rxq_t *, boolean_t);
188 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
189#if EFSYS_OPT_LOOPBACK
190 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
191 efx_loopback_type_t);
192#endif /* EFSYS_OPT_LOOPBACK */
193#if EFSYS_OPT_MAC_STATS
194 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
195 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
196 uint16_t, boolean_t);
197 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
198 efsys_stat_t *, uint32_t *);
199#endif /* EFSYS_OPT_MAC_STATS */
200} efx_mac_ops_t;
201
202typedef struct efx_phy_ops_s {
203 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
204 efx_rc_t (*epo_reset)(efx_nic_t *);
205 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
206 efx_rc_t (*epo_verify)(efx_nic_t *);
207 efx_rc_t (*epo_uplink_check)(efx_nic_t *,
208 boolean_t *); /* optional */
209 efx_rc_t (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
210 unsigned int *, uint32_t *);
211 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
212#if EFSYS_OPT_PHY_STATS
213 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
214 uint32_t *);
215#endif /* EFSYS_OPT_PHY_STATS */
216#if EFSYS_OPT_PHY_PROPS
217#if EFSYS_OPT_NAMES
218 const char *(*epo_prop_name)(efx_nic_t *, unsigned int);
219#endif /* EFSYS_OPT_PHY_PROPS */
220 efx_rc_t (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
221 uint32_t *);
222 efx_rc_t (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
223#endif /* EFSYS_OPT_PHY_PROPS */
224#if EFSYS_OPT_BIST
225 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
226 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
227 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
228 efx_bist_result_t *, uint32_t *,
229 unsigned long *, size_t);
230 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
231#endif /* EFSYS_OPT_BIST */
232} efx_phy_ops_t;
233
234#if EFSYS_OPT_FILTER
235typedef struct efx_filter_ops_s {
236 efx_rc_t (*efo_init)(efx_nic_t *);
237 void (*efo_fini)(efx_nic_t *);
238 efx_rc_t (*efo_restore)(efx_nic_t *);
239 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
240 boolean_t may_replace);
241 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
242 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
243 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
244 boolean_t, boolean_t, boolean_t,
245 uint8_t const *, int);
246} efx_filter_ops_t;
247
248extern __checkReturn efx_rc_t
249efx_filter_reconfigure(
250 __in efx_nic_t *enp,
251 __in_ecount(6) uint8_t const *mac_addr,
252 __in boolean_t all_unicst,
253 __in boolean_t mulcst,
254 __in boolean_t all_mulcst,
255 __in boolean_t brdcst,
256 __in_ecount(6*count) uint8_t const *addrs,
257 __in int count);
258
259#endif /* EFSYS_OPT_FILTER */
260
261typedef struct efx_pktfilter_ops_s {
262 efx_rc_t (*epfo_set)(efx_nic_t *,
263 boolean_t unicst,
264 boolean_t brdcast);
265#if EFSYS_OPT_MCAST_FILTER_LIST
266 efx_rc_t (*epfo_mcast_list_set)(efx_nic_t *,
267 uint8_t const *addrs, int count);
268#endif /* EFSYS_OPT_MCAST_FILTER_LIST */
269 efx_rc_t (*epfo_mcast_all)(efx_nic_t *);
270} efx_pktfilter_ops_t;
271
272typedef struct efx_port_s {
273 efx_mac_type_t ep_mac_type;
274 uint32_t ep_phy_type;
275 uint8_t ep_port;
276 uint32_t ep_mac_pdu;
277 uint8_t ep_mac_addr[6];
278 efx_link_mode_t ep_link_mode;
279 boolean_t ep_all_unicst;
280 boolean_t ep_mulcst;
281 boolean_t ep_all_mulcst;
282 boolean_t ep_brdcst;
283 unsigned int ep_fcntl;
284 boolean_t ep_fcntl_autoneg;
285 efx_oword_t ep_multicst_hash[2];
286 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
287 EFX_MAC_MULTICAST_LIST_MAX];
288 uint32_t ep_mulcst_addr_count;
289#if EFSYS_OPT_LOOPBACK
290 efx_loopback_type_t ep_loopback_type;
291 efx_link_mode_t ep_loopback_link_mode;
292#endif /* EFSYS_OPT_LOOPBACK */
293#if EFSYS_OPT_PHY_FLAGS
294 uint32_t ep_phy_flags;
295#endif /* EFSYS_OPT_PHY_FLAGS */
296#if EFSYS_OPT_PHY_LED_CONTROL
297 efx_phy_led_mode_t ep_phy_led_mode;
298#endif /* EFSYS_OPT_PHY_LED_CONTROL */
299 efx_phy_media_type_t ep_fixed_port_type;
300 efx_phy_media_type_t ep_module_type;
301 uint32_t ep_adv_cap_mask;
302 uint32_t ep_lp_cap_mask;
303 uint32_t ep_default_adv_cap_mask;
304 uint32_t ep_phy_cap_mask;
305#if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
306 union {
307 struct {
308 unsigned int bug10934_count;
309 } ep_txc43128;
310 struct {
311 unsigned int bug17190_count;
312 } ep_qt2025c;
313 };
314#endif
315 boolean_t ep_mac_poll_needed; /* falcon only */
316 boolean_t ep_mac_up; /* falcon only */
317 uint32_t ep_fwver; /* falcon only */
318 boolean_t ep_mac_drain;
319 boolean_t ep_mac_stats_pending;
320#if EFSYS_OPT_BIST
321 efx_bist_type_t ep_current_bist;
322#endif
323 efx_mac_ops_t *ep_emop;
324 efx_phy_ops_t *ep_epop;
325} efx_port_t;
326
327typedef struct efx_mon_ops_s {
328 efx_rc_t (*emo_reset)(efx_nic_t *);
329 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
330#if EFSYS_OPT_MON_STATS
331 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
332 efx_mon_stat_value_t *);
333#endif /* EFSYS_OPT_MON_STATS */
334} efx_mon_ops_t;
335
336typedef struct efx_mon_s {
337 efx_mon_type_t em_type;
338 efx_mon_ops_t *em_emop;
339} efx_mon_t;
340
341typedef struct efx_intr_ops_s {
342 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
343 void (*eio_enable)(efx_nic_t *);
344 void (*eio_disable)(efx_nic_t *);
345 void (*eio_disable_unlocked)(efx_nic_t *);
346 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
347 void (*eio_fini)(efx_nic_t *);
348} efx_intr_ops_t;
349
350typedef struct efx_intr_s {
351 efx_intr_ops_t *ei_eiop;
352 efsys_mem_t *ei_esmp;
353 efx_intr_type_t ei_type;
354 unsigned int ei_level;
355} efx_intr_t;
356
357typedef struct efx_nic_ops_s {
358 efx_rc_t (*eno_probe)(efx_nic_t *);
359 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
360 efx_rc_t (*eno_reset)(efx_nic_t *);
361 efx_rc_t (*eno_init)(efx_nic_t *);
362 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
363 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
364 uint32_t *, size_t *);
365#if EFSYS_OPT_DIAG
366 efx_rc_t (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
367 efx_rc_t (*eno_register_test)(efx_nic_t *);
368#endif /* EFSYS_OPT_DIAG */
369 void (*eno_fini)(efx_nic_t *);
370 void (*eno_unprobe)(efx_nic_t *);
371} efx_nic_ops_t;
372
373#ifndef EFX_TXQ_LIMIT_TARGET
374#define EFX_TXQ_LIMIT_TARGET 259
375#endif
376#ifndef EFX_RXQ_LIMIT_TARGET
377#define EFX_RXQ_LIMIT_TARGET 512
378#endif
379#ifndef EFX_TXQ_DC_SIZE
380#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
381#endif
382#ifndef EFX_RXQ_DC_SIZE
383#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
384#endif
385
386#if EFSYS_OPT_FILTER
387
388typedef struct falconsiena_filter_spec_s {
389 uint8_t fsfs_type;
390 uint32_t fsfs_flags;
391 uint32_t fsfs_dmaq_id;
392 uint32_t fsfs_dword[3];
393} falconsiena_filter_spec_t;
394
395typedef enum falconsiena_filter_type_e {
396 EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
397 EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */
398 EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
399 EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */
400
401#if EFSYS_OPT_SIENA
402 EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
403 EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
404
405 EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
406 EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
407 EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
408 EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */
409
410 EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */
411 EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */
412#endif /* EFSYS_OPT_SIENA */
413
414 EFX_FS_FILTER_NTYPES
415} falconsiena_filter_type_t;
416
417typedef enum falconsiena_filter_tbl_id_e {
418 EFX_FS_FILTER_TBL_RX_IP = 0,
419 EFX_FS_FILTER_TBL_RX_MAC,
420 EFX_FS_FILTER_TBL_TX_IP,
421 EFX_FS_FILTER_TBL_TX_MAC,
422 EFX_FS_FILTER_NTBLS
423} falconsiena_filter_tbl_id_t;
424
425typedef struct falconsiena_filter_tbl_s {
426 int fsft_size; /* number of entries */
427 int fsft_used; /* active count */
428 uint32_t *fsft_bitmap; /* active bitmap */
429 falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */
430} falconsiena_filter_tbl_t;
431
432typedef struct falconsiena_filter_s {
433 falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS];
434 unsigned int fsf_depth[EFX_FS_FILTER_NTYPES];
435} falconsiena_filter_t;
436
437typedef struct efx_filter_s {
438#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
439 falconsiena_filter_t *ef_falconsiena_filter;
440#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
441#if EFSYS_OPT_HUNTINGTON
442 hunt_filter_table_t *ef_hunt_filter_table;
443#endif /* EFSYS_OPT_HUNTINGTON */
444} efx_filter_t;
445
446extern void
447falconsiena_filter_tbl_clear(
448 __in efx_nic_t *enp,
449 __in falconsiena_filter_tbl_id_t tbl);
450
451#endif /* EFSYS_OPT_FILTER */
452
453#if EFSYS_OPT_MCDI
454
455typedef struct efx_mcdi_ops_s {
456 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
457 void (*emco_request_copyin)(efx_nic_t *, efx_mcdi_req_t *,
458 unsigned int, boolean_t, boolean_t);
459 boolean_t (*emco_request_poll)(efx_nic_t *);
460 void (*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *);
461 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
462 void (*emco_fini)(efx_nic_t *);
| 31 */
32
33#ifndef _SYS_EFX_IMPL_H
34#define _SYS_EFX_IMPL_H
35
36#include "efsys.h"
37#include "efx.h"
38#include "efx_regs.h"
39#include "efx_regs_ef10.h"
40
41/* FIXME: Add definition for driver generated software events */
42#ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
43#define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
44#endif
45
46#include "efx_check.h"
47
48
49#if EFSYS_OPT_FALCON
50#include "falcon_impl.h"
51#endif /* EFSYS_OPT_FALCON */
52
53#if EFSYS_OPT_SIENA
54#include "siena_impl.h"
55#endif /* EFSYS_OPT_SIENA */
56
57#if EFSYS_OPT_HUNTINGTON
58#include "hunt_impl.h"
59#endif /* EFSYS_OPT_HUNTINGTON */
60
61#ifdef __cplusplus
62extern "C" {
63#endif
64
65#define EFX_MOD_MCDI 0x00000001
66#define EFX_MOD_PROBE 0x00000002
67#define EFX_MOD_NVRAM 0x00000004
68#define EFX_MOD_VPD 0x00000008
69#define EFX_MOD_NIC 0x00000010
70#define EFX_MOD_INTR 0x00000020
71#define EFX_MOD_EV 0x00000040
72#define EFX_MOD_RX 0x00000080
73#define EFX_MOD_TX 0x00000100
74#define EFX_MOD_PORT 0x00000200
75#define EFX_MOD_MON 0x00000400
76#define EFX_MOD_WOL 0x00000800
77#define EFX_MOD_FILTER 0x00001000
78#define EFX_MOD_PKTFILTER 0x00002000
79
80#define EFX_RESET_MAC 0x00000001
81#define EFX_RESET_PHY 0x00000002
82#define EFX_RESET_RXQ_ERR 0x00000004
83#define EFX_RESET_TXQ_ERR 0x00000008
84
85typedef enum efx_mac_type_e {
86 EFX_MAC_INVALID = 0,
87 EFX_MAC_FALCON_GMAC,
88 EFX_MAC_FALCON_XMAC,
89 EFX_MAC_SIENA,
90 EFX_MAC_HUNTINGTON,
91 EFX_MAC_NTYPES
92} efx_mac_type_t;
93
94typedef struct efx_ev_ops_s {
95 efx_rc_t (*eevo_init)(efx_nic_t *);
96 void (*eevo_fini)(efx_nic_t *);
97 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
98 efsys_mem_t *, size_t, uint32_t,
99 efx_evq_t *);
100 void (*eevo_qdestroy)(efx_evq_t *);
101 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
102 void (*eevo_qpost)(efx_evq_t *, uint16_t);
103 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
104#if EFSYS_OPT_QSTATS
105 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
106#endif
107} efx_ev_ops_t;
108
109typedef struct efx_tx_ops_s {
110 efx_rc_t (*etxo_init)(efx_nic_t *);
111 void (*etxo_fini)(efx_nic_t *);
112 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
113 unsigned int, unsigned int,
114 efsys_mem_t *, size_t,
115 uint32_t, uint16_t,
116 efx_evq_t *, efx_txq_t *,
117 unsigned int *);
118 void (*etxo_qdestroy)(efx_txq_t *);
119 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
120 unsigned int, unsigned int,
121 unsigned int *);
122 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
123 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
124 efx_rc_t (*etxo_qflush)(efx_txq_t *);
125 void (*etxo_qenable)(efx_txq_t *);
126 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
127 void (*etxo_qpio_disable)(efx_txq_t *);
128 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
129 size_t);
130 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
131 unsigned int *);
132 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
133 unsigned int, unsigned int,
134 unsigned int *);
135 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
136 size_t, boolean_t,
137 efx_desc_t *);
138 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
139 uint32_t, uint8_t,
140 efx_desc_t *);
141 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
142 efx_desc_t *);
143#if EFSYS_OPT_QSTATS
144 void (*etxo_qstats_update)(efx_txq_t *,
145 efsys_stat_t *);
146#endif
147} efx_tx_ops_t;
148
149typedef struct efx_rx_ops_s {
150 efx_rc_t (*erxo_init)(efx_nic_t *);
151 void (*erxo_fini)(efx_nic_t *);
152#if EFSYS_OPT_RX_HDR_SPLIT
153 efx_rc_t (*erxo_hdr_split_enable)(efx_nic_t *, unsigned int,
154 unsigned int);
155#endif
156#if EFSYS_OPT_RX_SCATTER
157 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
158#endif
159#if EFSYS_OPT_RX_SCALE
160 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
161 efx_rx_hash_type_t, boolean_t);
162 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
163 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
164 size_t);
165#endif
166 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
167 unsigned int, unsigned int,
168 unsigned int);
169 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
170 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
171 void (*erxo_qenable)(efx_rxq_t *);
172 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
173 unsigned int, efx_rxq_type_t,
174 efsys_mem_t *, size_t, uint32_t,
175 efx_evq_t *, efx_rxq_t *);
176 void (*erxo_qdestroy)(efx_rxq_t *);
177} efx_rx_ops_t;
178
179typedef struct efx_mac_ops_s {
180 efx_rc_t (*emo_reset)(efx_nic_t *); /* optional */
181 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
182 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
183 efx_rc_t (*emo_addr_set)(efx_nic_t *);
184 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
185 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
186 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
187 efx_rxq_t *, boolean_t);
188 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
189#if EFSYS_OPT_LOOPBACK
190 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
191 efx_loopback_type_t);
192#endif /* EFSYS_OPT_LOOPBACK */
193#if EFSYS_OPT_MAC_STATS
194 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
195 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
196 uint16_t, boolean_t);
197 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
198 efsys_stat_t *, uint32_t *);
199#endif /* EFSYS_OPT_MAC_STATS */
200} efx_mac_ops_t;
201
202typedef struct efx_phy_ops_s {
203 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
204 efx_rc_t (*epo_reset)(efx_nic_t *);
205 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
206 efx_rc_t (*epo_verify)(efx_nic_t *);
207 efx_rc_t (*epo_uplink_check)(efx_nic_t *,
208 boolean_t *); /* optional */
209 efx_rc_t (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
210 unsigned int *, uint32_t *);
211 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
212#if EFSYS_OPT_PHY_STATS
213 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
214 uint32_t *);
215#endif /* EFSYS_OPT_PHY_STATS */
216#if EFSYS_OPT_PHY_PROPS
217#if EFSYS_OPT_NAMES
218 const char *(*epo_prop_name)(efx_nic_t *, unsigned int);
219#endif /* EFSYS_OPT_PHY_PROPS */
220 efx_rc_t (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
221 uint32_t *);
222 efx_rc_t (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
223#endif /* EFSYS_OPT_PHY_PROPS */
224#if EFSYS_OPT_BIST
225 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
226 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
227 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
228 efx_bist_result_t *, uint32_t *,
229 unsigned long *, size_t);
230 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
231#endif /* EFSYS_OPT_BIST */
232} efx_phy_ops_t;
233
234#if EFSYS_OPT_FILTER
235typedef struct efx_filter_ops_s {
236 efx_rc_t (*efo_init)(efx_nic_t *);
237 void (*efo_fini)(efx_nic_t *);
238 efx_rc_t (*efo_restore)(efx_nic_t *);
239 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
240 boolean_t may_replace);
241 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
242 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
243 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
244 boolean_t, boolean_t, boolean_t,
245 uint8_t const *, int);
246} efx_filter_ops_t;
247
248extern __checkReturn efx_rc_t
249efx_filter_reconfigure(
250 __in efx_nic_t *enp,
251 __in_ecount(6) uint8_t const *mac_addr,
252 __in boolean_t all_unicst,
253 __in boolean_t mulcst,
254 __in boolean_t all_mulcst,
255 __in boolean_t brdcst,
256 __in_ecount(6*count) uint8_t const *addrs,
257 __in int count);
258
259#endif /* EFSYS_OPT_FILTER */
260
261typedef struct efx_pktfilter_ops_s {
262 efx_rc_t (*epfo_set)(efx_nic_t *,
263 boolean_t unicst,
264 boolean_t brdcast);
265#if EFSYS_OPT_MCAST_FILTER_LIST
266 efx_rc_t (*epfo_mcast_list_set)(efx_nic_t *,
267 uint8_t const *addrs, int count);
268#endif /* EFSYS_OPT_MCAST_FILTER_LIST */
269 efx_rc_t (*epfo_mcast_all)(efx_nic_t *);
270} efx_pktfilter_ops_t;
271
272typedef struct efx_port_s {
273 efx_mac_type_t ep_mac_type;
274 uint32_t ep_phy_type;
275 uint8_t ep_port;
276 uint32_t ep_mac_pdu;
277 uint8_t ep_mac_addr[6];
278 efx_link_mode_t ep_link_mode;
279 boolean_t ep_all_unicst;
280 boolean_t ep_mulcst;
281 boolean_t ep_all_mulcst;
282 boolean_t ep_brdcst;
283 unsigned int ep_fcntl;
284 boolean_t ep_fcntl_autoneg;
285 efx_oword_t ep_multicst_hash[2];
286 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
287 EFX_MAC_MULTICAST_LIST_MAX];
288 uint32_t ep_mulcst_addr_count;
289#if EFSYS_OPT_LOOPBACK
290 efx_loopback_type_t ep_loopback_type;
291 efx_link_mode_t ep_loopback_link_mode;
292#endif /* EFSYS_OPT_LOOPBACK */
293#if EFSYS_OPT_PHY_FLAGS
294 uint32_t ep_phy_flags;
295#endif /* EFSYS_OPT_PHY_FLAGS */
296#if EFSYS_OPT_PHY_LED_CONTROL
297 efx_phy_led_mode_t ep_phy_led_mode;
298#endif /* EFSYS_OPT_PHY_LED_CONTROL */
299 efx_phy_media_type_t ep_fixed_port_type;
300 efx_phy_media_type_t ep_module_type;
301 uint32_t ep_adv_cap_mask;
302 uint32_t ep_lp_cap_mask;
303 uint32_t ep_default_adv_cap_mask;
304 uint32_t ep_phy_cap_mask;
305#if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
306 union {
307 struct {
308 unsigned int bug10934_count;
309 } ep_txc43128;
310 struct {
311 unsigned int bug17190_count;
312 } ep_qt2025c;
313 };
314#endif
315 boolean_t ep_mac_poll_needed; /* falcon only */
316 boolean_t ep_mac_up; /* falcon only */
317 uint32_t ep_fwver; /* falcon only */
318 boolean_t ep_mac_drain;
319 boolean_t ep_mac_stats_pending;
320#if EFSYS_OPT_BIST
321 efx_bist_type_t ep_current_bist;
322#endif
323 efx_mac_ops_t *ep_emop;
324 efx_phy_ops_t *ep_epop;
325} efx_port_t;
326
327typedef struct efx_mon_ops_s {
328 efx_rc_t (*emo_reset)(efx_nic_t *);
329 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
330#if EFSYS_OPT_MON_STATS
331 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
332 efx_mon_stat_value_t *);
333#endif /* EFSYS_OPT_MON_STATS */
334} efx_mon_ops_t;
335
336typedef struct efx_mon_s {
337 efx_mon_type_t em_type;
338 efx_mon_ops_t *em_emop;
339} efx_mon_t;
340
341typedef struct efx_intr_ops_s {
342 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
343 void (*eio_enable)(efx_nic_t *);
344 void (*eio_disable)(efx_nic_t *);
345 void (*eio_disable_unlocked)(efx_nic_t *);
346 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
347 void (*eio_fini)(efx_nic_t *);
348} efx_intr_ops_t;
349
350typedef struct efx_intr_s {
351 efx_intr_ops_t *ei_eiop;
352 efsys_mem_t *ei_esmp;
353 efx_intr_type_t ei_type;
354 unsigned int ei_level;
355} efx_intr_t;
356
357typedef struct efx_nic_ops_s {
358 efx_rc_t (*eno_probe)(efx_nic_t *);
359 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
360 efx_rc_t (*eno_reset)(efx_nic_t *);
361 efx_rc_t (*eno_init)(efx_nic_t *);
362 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
363 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
364 uint32_t *, size_t *);
365#if EFSYS_OPT_DIAG
366 efx_rc_t (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
367 efx_rc_t (*eno_register_test)(efx_nic_t *);
368#endif /* EFSYS_OPT_DIAG */
369 void (*eno_fini)(efx_nic_t *);
370 void (*eno_unprobe)(efx_nic_t *);
371} efx_nic_ops_t;
372
373#ifndef EFX_TXQ_LIMIT_TARGET
374#define EFX_TXQ_LIMIT_TARGET 259
375#endif
376#ifndef EFX_RXQ_LIMIT_TARGET
377#define EFX_RXQ_LIMIT_TARGET 512
378#endif
379#ifndef EFX_TXQ_DC_SIZE
380#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
381#endif
382#ifndef EFX_RXQ_DC_SIZE
383#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
384#endif
385
386#if EFSYS_OPT_FILTER
387
388typedef struct falconsiena_filter_spec_s {
389 uint8_t fsfs_type;
390 uint32_t fsfs_flags;
391 uint32_t fsfs_dmaq_id;
392 uint32_t fsfs_dword[3];
393} falconsiena_filter_spec_t;
394
395typedef enum falconsiena_filter_type_e {
396 EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
397 EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */
398 EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
399 EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */
400
401#if EFSYS_OPT_SIENA
402 EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
403 EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
404
405 EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
406 EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
407 EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
408 EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */
409
410 EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */
411 EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */
412#endif /* EFSYS_OPT_SIENA */
413
414 EFX_FS_FILTER_NTYPES
415} falconsiena_filter_type_t;
416
417typedef enum falconsiena_filter_tbl_id_e {
418 EFX_FS_FILTER_TBL_RX_IP = 0,
419 EFX_FS_FILTER_TBL_RX_MAC,
420 EFX_FS_FILTER_TBL_TX_IP,
421 EFX_FS_FILTER_TBL_TX_MAC,
422 EFX_FS_FILTER_NTBLS
423} falconsiena_filter_tbl_id_t;
424
425typedef struct falconsiena_filter_tbl_s {
426 int fsft_size; /* number of entries */
427 int fsft_used; /* active count */
428 uint32_t *fsft_bitmap; /* active bitmap */
429 falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */
430} falconsiena_filter_tbl_t;
431
432typedef struct falconsiena_filter_s {
433 falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS];
434 unsigned int fsf_depth[EFX_FS_FILTER_NTYPES];
435} falconsiena_filter_t;
436
437typedef struct efx_filter_s {
438#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
439 falconsiena_filter_t *ef_falconsiena_filter;
440#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
441#if EFSYS_OPT_HUNTINGTON
442 hunt_filter_table_t *ef_hunt_filter_table;
443#endif /* EFSYS_OPT_HUNTINGTON */
444} efx_filter_t;
445
446extern void
447falconsiena_filter_tbl_clear(
448 __in efx_nic_t *enp,
449 __in falconsiena_filter_tbl_id_t tbl);
450
451#endif /* EFSYS_OPT_FILTER */
452
453#if EFSYS_OPT_MCDI
454
455typedef struct efx_mcdi_ops_s {
456 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
457 void (*emco_request_copyin)(efx_nic_t *, efx_mcdi_req_t *,
458 unsigned int, boolean_t, boolean_t);
459 boolean_t (*emco_request_poll)(efx_nic_t *);
460 void (*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *);
461 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
462 void (*emco_fini)(efx_nic_t *);
|
467 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
468} efx_mcdi_ops_t;
469
470typedef struct efx_mcdi_s {
471 efx_mcdi_ops_t *em_emcop;
472 const efx_mcdi_transport_t *em_emtp;
473 efx_mcdi_iface_t em_emip;
474} efx_mcdi_t;
475
476#endif /* EFSYS_OPT_MCDI */
477
478#if EFSYS_OPT_NVRAM
479typedef struct efx_nvram_ops_s {
480#if EFSYS_OPT_DIAG
481 efx_rc_t (*envo_test)(efx_nic_t *);
482#endif /* EFSYS_OPT_DIAG */
483 efx_rc_t (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *);
484 efx_rc_t (*envo_get_version)(efx_nic_t *, efx_nvram_type_t,
485 uint32_t *, uint16_t *);
486 efx_rc_t (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *);
487 efx_rc_t (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t,
488 unsigned int, caddr_t, size_t);
489 efx_rc_t (*envo_erase)(efx_nic_t *, efx_nvram_type_t);
490 efx_rc_t (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t,
491 unsigned int, caddr_t, size_t);
492 void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t);
493 efx_rc_t (*envo_set_version)(efx_nic_t *, efx_nvram_type_t,
494 uint16_t *);
495
496} efx_nvram_ops_t;
497#endif /* EFSYS_OPT_NVRAM */
498
499#if EFSYS_OPT_VPD
500typedef struct efx_vpd_ops_s {
501 efx_rc_t (*evpdo_init)(efx_nic_t *);
502 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
503 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
504 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
505 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
506 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
507 efx_vpd_value_t *);
508 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
509 efx_vpd_value_t *);
510 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
511 efx_vpd_value_t *, unsigned int *);
512 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
513 void (*evpdo_fini)(efx_nic_t *);
514} efx_vpd_ops_t;
515#endif /* EFSYS_OPT_VPD */
516
517#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
518
519 __checkReturn efx_rc_t
520efx_mcdi_nvram_partitions(
521 __in efx_nic_t *enp,
522 __out_bcount(size) caddr_t data,
523 __in size_t size,
524 __out unsigned int *npartnp);
525
526 __checkReturn efx_rc_t
527efx_mcdi_nvram_metadata(
528 __in efx_nic_t *enp,
529 __in uint32_t partn,
530 __out uint32_t *subtypep,
531 __out_ecount(4) uint16_t version[4],
532 __out_bcount_opt(size) char *descp,
533 __in size_t size);
534
535 __checkReturn efx_rc_t
536efx_mcdi_nvram_info(
537 __in efx_nic_t *enp,
538 __in uint32_t partn,
539 __out_opt size_t *sizep,
540 __out_opt uint32_t *addressp,
541 __out_opt uint32_t *erase_sizep,
542 __out_opt uint32_t *write_sizep);
543
544 __checkReturn efx_rc_t
545efx_mcdi_nvram_update_start(
546 __in efx_nic_t *enp,
547 __in uint32_t partn);
548
549 __checkReturn efx_rc_t
550efx_mcdi_nvram_read(
551 __in efx_nic_t *enp,
552 __in uint32_t partn,
553 __in uint32_t offset,
554 __out_bcount(size) caddr_t data,
555 __in size_t size);
556
557 __checkReturn efx_rc_t
558efx_mcdi_nvram_erase(
559 __in efx_nic_t *enp,
560 __in uint32_t partn,
561 __in uint32_t offset,
562 __in size_t size);
563
564 __checkReturn efx_rc_t
565efx_mcdi_nvram_write(
566 __in efx_nic_t *enp,
567 __in uint32_t partn,
568 __in uint32_t offset,
569 __out_bcount(size) caddr_t data,
570 __in size_t size);
571
572 __checkReturn efx_rc_t
573efx_mcdi_nvram_update_finish(
574 __in efx_nic_t *enp,
575 __in uint32_t partn,
576 __in boolean_t reboot);
577
578#if EFSYS_OPT_DIAG
579
580 __checkReturn efx_rc_t
581efx_mcdi_nvram_test(
582 __in efx_nic_t *enp,
583 __in uint32_t partn);
584
585#endif /* EFSYS_OPT_DIAG */
586
587#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
588
589typedef struct efx_drv_cfg_s {
590 uint32_t edc_min_vi_count;
591 uint32_t edc_max_vi_count;
592
593 uint32_t edc_max_piobuf_count;
594 uint32_t edc_pio_alloc_size;
595} efx_drv_cfg_t;
596
597struct efx_nic_s {
598 uint32_t en_magic;
599 efx_family_t en_family;
600 uint32_t en_features;
601 efsys_identifier_t *en_esip;
602 efsys_lock_t *en_eslp;
603 efsys_bar_t *en_esbp;
604 unsigned int en_mod_flags;
605 unsigned int en_reset_flags;
606 efx_nic_cfg_t en_nic_cfg;
607 efx_drv_cfg_t en_drv_cfg;
608 efx_port_t en_port;
609 efx_mon_t en_mon;
610 efx_intr_t en_intr;
611 uint32_t en_ev_qcount;
612 uint32_t en_rx_qcount;
613 uint32_t en_tx_qcount;
614 efx_nic_ops_t *en_enop;
615 efx_ev_ops_t *en_eevop;
616 efx_tx_ops_t *en_etxop;
617 efx_rx_ops_t *en_erxop;
618#if EFSYS_OPT_FILTER
619 efx_filter_t en_filter;
620 efx_filter_ops_t *en_efop;
621#endif /* EFSYS_OPT_FILTER */
622 efx_pktfilter_ops_t *en_epfop;
623#if EFSYS_OPT_MCDI
624 efx_mcdi_t en_mcdi;
625#endif /* EFSYS_OPT_MCDI */
626#if EFSYS_OPT_NVRAM
627 efx_nvram_type_t en_nvram_locked;
628 efx_nvram_ops_t *en_envop;
629#endif /* EFSYS_OPT_NVRAM */
630#if EFSYS_OPT_VPD
631 efx_vpd_ops_t *en_evpdop;
632#endif /* EFSYS_OPT_VPD */
633#if EFSYS_OPT_RX_SCALE
634 efx_rx_hash_support_t en_hash_support;
635 efx_rx_scale_support_t en_rss_support;
636 uint32_t en_rss_context;
637#endif /* EFSYS_OPT_RX_SCALE */
638 uint32_t en_vport_id;
639 union {
640#if EFSYS_OPT_FALCON
641 struct {
642 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES];
643 falcon_i2c_t enu_fip;
644 boolean_t enu_i2c_locked;
645#if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
646 const uint8_t *enu_forced_cfg;
647#endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
648 uint8_t enu_mon_devid;
649#if EFSYS_OPT_PCIE_TUNE
650 unsigned int enu_nlanes;
651#endif /* EFSYS_OPT_PCIE_TUNE */
652 uint16_t enu_board_rev;
653 boolean_t enu_internal_sram;
654 uint8_t enu_sram_num_bank;
655 uint8_t enu_sram_bank_size;
656 } falcon;
657#endif /* EFSYS_OPT_FALCON */
658#if EFSYS_OPT_SIENA
659 struct {
660#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
661 unsigned int enu_partn_mask;
662#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
663#if EFSYS_OPT_VPD
664 caddr_t enu_svpd;
665 size_t enu_svpd_length;
666#endif /* EFSYS_OPT_VPD */
667 int enu_unused;
668 } siena;
669#endif /* EFSYS_OPT_SIENA */
670#if EFSYS_OPT_HUNTINGTON
671 struct {
672 int enu_vi_base;
673 int enu_vi_count;
674#if EFSYS_OPT_VPD
675 caddr_t enu_svpd;
676 size_t enu_svpd_length;
677#endif /* EFSYS_OPT_VPD */
678 efx_piobuf_handle_t enu_piobuf_handle[HUNT_PIOBUF_NBUFS];
679 uint32_t enu_piobuf_count;
680 uint32_t enu_pio_alloc_map[HUNT_PIOBUF_NBUFS];
681 uint32_t enu_pio_write_vi_base;
682 /* Memory BAR mapping regions */
683 uint32_t enu_uc_mem_map_offset;
684 size_t enu_uc_mem_map_size;
685 uint32_t enu_wc_mem_map_offset;
686 size_t enu_wc_mem_map_size;
687 } hunt;
688#endif /* EFSYS_OPT_HUNTINGTON */
689 } en_u;
690};
691
692
693#define EFX_NIC_MAGIC 0x02121996
694
695typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
696 const efx_ev_callbacks_t *, void *);
697
698typedef struct efx_evq_rxq_state_s {
699 unsigned int eers_rx_read_ptr;
700 unsigned int eers_rx_mask;
701} efx_evq_rxq_state_t;
702
703struct efx_evq_s {
704 uint32_t ee_magic;
705 efx_nic_t *ee_enp;
706 unsigned int ee_index;
707 unsigned int ee_mask;
708 efsys_mem_t *ee_esmp;
709#if EFSYS_OPT_QSTATS
710 uint32_t ee_stat[EV_NQSTATS];
711#endif /* EFSYS_OPT_QSTATS */
712
713 efx_ev_handler_t ee_rx;
714 efx_ev_handler_t ee_tx;
715 efx_ev_handler_t ee_driver;
716 efx_ev_handler_t ee_global;
717 efx_ev_handler_t ee_drv_gen;
718#if EFSYS_OPT_MCDI
719 efx_ev_handler_t ee_mcdi;
720#endif /* EFSYS_OPT_MCDI */
721
722 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
723};
724
725#define EFX_EVQ_MAGIC 0x08081997
726
727#define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
728#define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
729
730struct efx_rxq_s {
731 uint32_t er_magic;
732 efx_nic_t *er_enp;
733 efx_evq_t *er_eep;
734 unsigned int er_index;
735 unsigned int er_label;
736 unsigned int er_mask;
737 efsys_mem_t *er_esmp;
738};
739
740#define EFX_RXQ_MAGIC 0x15022005
741
742struct efx_txq_s {
743 uint32_t et_magic;
744 efx_nic_t *et_enp;
745 unsigned int et_index;
746 unsigned int et_mask;
747 efsys_mem_t *et_esmp;
748#if EFSYS_OPT_HUNTINGTON
749 uint32_t et_pio_bufnum;
750 uint32_t et_pio_blknum;
751 uint32_t et_pio_write_offset;
752 uint32_t et_pio_offset;
753 size_t et_pio_size;
754#endif
755#if EFSYS_OPT_QSTATS
756 uint32_t et_stat[TX_NQSTATS];
757#endif /* EFSYS_OPT_QSTATS */
758};
759
760#define EFX_TXQ_MAGIC 0x05092005
761
762#define EFX_MAC_ADDR_COPY(_dst, _src) \
763 do { \
764 (_dst)[0] = (_src)[0]; \
765 (_dst)[1] = (_src)[1]; \
766 (_dst)[2] = (_src)[2]; \
767 (_dst)[3] = (_src)[3]; \
768 (_dst)[4] = (_src)[4]; \
769 (_dst)[5] = (_src)[5]; \
770 _NOTE(CONSTANTCONDITION) \
771 } while (B_FALSE)
772
773#define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
774 do { \
775 uint16_t *_d = (uint16_t *)(_dst); \
776 _d[0] = 0xffff; \
777 _d[1] = 0xffff; \
778 _d[2] = 0xffff; \
779 _NOTE(CONSTANTCONDITION) \
780 } while (B_FALSE)
781
782#if EFSYS_OPT_CHECK_REG
783#define EFX_CHECK_REG(_enp, _reg) \
784 do { \
785 const char *name = #_reg; \
786 char min = name[4]; \
787 char max = name[5]; \
788 char rev; \
789 \
790 switch ((_enp)->en_family) { \
791 case EFX_FAMILY_FALCON: \
792 rev = 'B'; \
793 break; \
794 \
795 case EFX_FAMILY_SIENA: \
796 rev = 'C'; \
797 break; \
798 \
799 case EFX_FAMILY_HUNTINGTON: \
800 rev = 'D'; \
801 break; \
802 \
803 default: \
804 rev = '?'; \
805 break; \
806 } \
807 \
808 EFSYS_ASSERT3S(rev, >=, min); \
809 EFSYS_ASSERT3S(rev, <=, max); \
810 \
811 _NOTE(CONSTANTCONDITION) \
812 } while (B_FALSE)
813#else
814#define EFX_CHECK_REG(_enp, _reg) do { \
815 _NOTE(CONSTANTCONDITION) \
816 } while(B_FALSE)
817#endif
818
819#define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
820 do { \
821 EFX_CHECK_REG((_enp), (_reg)); \
822 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
823 (_edp), (_lock)); \
824 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
825 uint32_t, _reg ## _OFST, \
826 uint32_t, (_edp)->ed_u32[0]); \
827 _NOTE(CONSTANTCONDITION) \
828 } while (B_FALSE)
829
830#define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
831 do { \
832 EFX_CHECK_REG((_enp), (_reg)); \
833 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
834 uint32_t, _reg ## _OFST, \
835 uint32_t, (_edp)->ed_u32[0]); \
836 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
837 (_edp), (_lock)); \
838 _NOTE(CONSTANTCONDITION) \
839 } while (B_FALSE)
840
841#define EFX_BAR_READQ(_enp, _reg, _eqp) \
842 do { \
843 EFX_CHECK_REG((_enp), (_reg)); \
844 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
845 (_eqp)); \
846 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
847 uint32_t, _reg ## _OFST, \
848 uint32_t, (_eqp)->eq_u32[1], \
849 uint32_t, (_eqp)->eq_u32[0]); \
850 _NOTE(CONSTANTCONDITION) \
851 } while (B_FALSE)
852
853#define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
854 do { \
855 EFX_CHECK_REG((_enp), (_reg)); \
856 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
857 uint32_t, _reg ## _OFST, \
858 uint32_t, (_eqp)->eq_u32[1], \
859 uint32_t, (_eqp)->eq_u32[0]); \
860 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
861 (_eqp)); \
862 _NOTE(CONSTANTCONDITION) \
863 } while (B_FALSE)
864
865#define EFX_BAR_READO(_enp, _reg, _eop) \
866 do { \
867 EFX_CHECK_REG((_enp), (_reg)); \
868 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
869 (_eop), B_TRUE); \
870 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
871 uint32_t, _reg ## _OFST, \
872 uint32_t, (_eop)->eo_u32[3], \
873 uint32_t, (_eop)->eo_u32[2], \
874 uint32_t, (_eop)->eo_u32[1], \
875 uint32_t, (_eop)->eo_u32[0]); \
876 _NOTE(CONSTANTCONDITION) \
877 } while (B_FALSE)
878
879#define EFX_BAR_WRITEO(_enp, _reg, _eop) \
880 do { \
881 EFX_CHECK_REG((_enp), (_reg)); \
882 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
883 uint32_t, _reg ## _OFST, \
884 uint32_t, (_eop)->eo_u32[3], \
885 uint32_t, (_eop)->eo_u32[2], \
886 uint32_t, (_eop)->eo_u32[1], \
887 uint32_t, (_eop)->eo_u32[0]); \
888 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
889 (_eop), B_TRUE); \
890 _NOTE(CONSTANTCONDITION) \
891 } while (B_FALSE)
892
893#define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
894 do { \
895 EFX_CHECK_REG((_enp), (_reg)); \
896 EFSYS_BAR_READD((_enp)->en_esbp, \
897 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
898 (_edp), (_lock)); \
899 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
900 uint32_t, (_index), \
901 uint32_t, _reg ## _OFST, \
902 uint32_t, (_edp)->ed_u32[0]); \
903 _NOTE(CONSTANTCONDITION) \
904 } while (B_FALSE)
905
906#define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
907 do { \
908 EFX_CHECK_REG((_enp), (_reg)); \
909 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
910 uint32_t, (_index), \
911 uint32_t, _reg ## _OFST, \
912 uint32_t, (_edp)->ed_u32[0]); \
913 EFSYS_BAR_WRITED((_enp)->en_esbp, \
914 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
915 (_edp), (_lock)); \
916 _NOTE(CONSTANTCONDITION) \
917 } while (B_FALSE)
918
919#define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
920 do { \
921 EFX_CHECK_REG((_enp), (_reg)); \
922 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
923 uint32_t, (_index), \
924 uint32_t, _reg ## _OFST, \
925 uint32_t, (_edp)->ed_u32[0]); \
926 EFSYS_BAR_WRITED((_enp)->en_esbp, \
927 (_reg ## _OFST + \
928 (2 * sizeof (efx_dword_t)) + \
929 ((_index) * _reg ## _STEP)), \
930 (_edp), (_lock)); \
931 _NOTE(CONSTANTCONDITION) \
932 } while (B_FALSE)
933
934#define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
935 do { \
936 EFX_CHECK_REG((_enp), (_reg)); \
937 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
938 uint32_t, (_index), \
939 uint32_t, _reg ## _OFST, \
940 uint32_t, (_edp)->ed_u32[0]); \
941 EFSYS_BAR_WRITED((_enp)->en_esbp, \
942 (_reg ## _OFST + \
943 (3 * sizeof (efx_dword_t)) + \
944 ((_index) * _reg ## _STEP)), \
945 (_edp), (_lock)); \
946 _NOTE(CONSTANTCONDITION) \
947 } while (B_FALSE)
948
949#define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
950 do { \
951 EFX_CHECK_REG((_enp), (_reg)); \
952 EFSYS_BAR_READQ((_enp)->en_esbp, \
953 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
954 (_eqp)); \
955 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
956 uint32_t, (_index), \
957 uint32_t, _reg ## _OFST, \
958 uint32_t, (_eqp)->eq_u32[1], \
959 uint32_t, (_eqp)->eq_u32[0]); \
960 _NOTE(CONSTANTCONDITION) \
961 } while (B_FALSE)
962
963#define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
964 do { \
965 EFX_CHECK_REG((_enp), (_reg)); \
966 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
967 uint32_t, (_index), \
968 uint32_t, _reg ## _OFST, \
969 uint32_t, (_eqp)->eq_u32[1], \
970 uint32_t, (_eqp)->eq_u32[0]); \
971 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
972 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
973 (_eqp)); \
974 _NOTE(CONSTANTCONDITION) \
975 } while (B_FALSE)
976
977#define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
978 do { \
979 EFX_CHECK_REG((_enp), (_reg)); \
980 EFSYS_BAR_READO((_enp)->en_esbp, \
981 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
982 (_eop), (_lock)); \
983 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
984 uint32_t, (_index), \
985 uint32_t, _reg ## _OFST, \
986 uint32_t, (_eop)->eo_u32[3], \
987 uint32_t, (_eop)->eo_u32[2], \
988 uint32_t, (_eop)->eo_u32[1], \
989 uint32_t, (_eop)->eo_u32[0]); \
990 _NOTE(CONSTANTCONDITION) \
991 } while (B_FALSE)
992
993#define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
994 do { \
995 EFX_CHECK_REG((_enp), (_reg)); \
996 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
997 uint32_t, (_index), \
998 uint32_t, _reg ## _OFST, \
999 uint32_t, (_eop)->eo_u32[3], \
1000 uint32_t, (_eop)->eo_u32[2], \
1001 uint32_t, (_eop)->eo_u32[1], \
1002 uint32_t, (_eop)->eo_u32[0]); \
1003 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1004 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1005 (_eop), (_lock)); \
1006 _NOTE(CONSTANTCONDITION) \
1007 } while (B_FALSE)
1008
1009/*
1010 * Allow drivers to perform optimised 128-bit doorbell writes.
1011 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1012 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1013 * the need for locking in the host, and are the only ones known to be safe to
1014 * use 128-bites write with.
1015 */
1016#define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1017 do { \
1018 EFX_CHECK_REG((_enp), (_reg)); \
1019 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1020 const char *, \
1021 #_reg, \
1022 uint32_t, (_index), \
1023 uint32_t, _reg ## _OFST, \
1024 uint32_t, (_eop)->eo_u32[3], \
1025 uint32_t, (_eop)->eo_u32[2], \
1026 uint32_t, (_eop)->eo_u32[1], \
1027 uint32_t, (_eop)->eo_u32[0]); \
1028 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1029 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1030 (_eop)); \
1031 _NOTE(CONSTANTCONDITION) \
1032 } while (B_FALSE)
1033
1034#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1035 do { \
1036 unsigned int _new = (_wptr); \
1037 unsigned int _old = (_owptr); \
1038 \
1039 if ((_new) >= (_old)) \
1040 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1041 (_old) * sizeof (efx_desc_t), \
1042 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1043 else \
1044 /* \
1045 * It is cheaper to sync entire map than sync \
1046 * two parts especially when offset/size are \
1047 * ignored and entire map is synced in any case.\
1048 */ \
1049 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1050 0, \
1051 (_entries) * sizeof (efx_desc_t)); \
1052 _NOTE(CONSTANTCONDITION) \
1053 } while (B_FALSE)
1054
1055extern __checkReturn efx_rc_t
1056efx_nic_biu_test(
1057 __in efx_nic_t *enp);
1058
1059extern __checkReturn efx_rc_t
1060efx_mac_select(
1061 __in efx_nic_t *enp);
1062
1063extern void
1064efx_mac_multicast_hash_compute(
1065 __in_ecount(6*count) uint8_t const *addrs,
1066 __in int count,
1067 __out efx_oword_t *hash_low,
1068 __out efx_oword_t *hash_high);
1069
1070extern __checkReturn efx_rc_t
1071efx_phy_probe(
1072 __in efx_nic_t *enp);
1073
1074extern void
1075efx_phy_unprobe(
1076 __in efx_nic_t *enp);
1077
1078#if EFSYS_OPT_VPD
1079
1080/* VPD utility functions */
1081
1082extern __checkReturn efx_rc_t
1083efx_vpd_hunk_length(
1084 __in_bcount(size) caddr_t data,
1085 __in size_t size,
1086 __out size_t *lengthp);
1087
1088extern __checkReturn efx_rc_t
1089efx_vpd_hunk_verify(
1090 __in_bcount(size) caddr_t data,
1091 __in size_t size,
1092 __out_opt boolean_t *cksummedp);
1093
1094extern __checkReturn efx_rc_t
1095efx_vpd_hunk_reinit(
1096 __in_bcount(size) caddr_t data,
1097 __in size_t size,
1098 __in boolean_t wantpid);
1099
1100extern __checkReturn efx_rc_t
1101efx_vpd_hunk_get(
1102 __in_bcount(size) caddr_t data,
1103 __in size_t size,
1104 __in efx_vpd_tag_t tag,
1105 __in efx_vpd_keyword_t keyword,
1106 __out unsigned int *payloadp,
1107 __out uint8_t *paylenp);
1108
1109extern __checkReturn efx_rc_t
1110efx_vpd_hunk_next(
1111 __in_bcount(size) caddr_t data,
1112 __in size_t size,
1113 __out efx_vpd_tag_t *tagp,
1114 __out efx_vpd_keyword_t *keyword,
1115 __out_bcount_opt(*paylenp) unsigned int *payloadp,
1116 __out_opt uint8_t *paylenp,
1117 __inout unsigned int *contp);
1118
1119extern __checkReturn efx_rc_t
1120efx_vpd_hunk_set(
1121 __in_bcount(size) caddr_t data,
1122 __in size_t size,
1123 __in efx_vpd_value_t *evvp);
1124
1125#endif /* EFSYS_OPT_VPD */
1126
1127#if EFSYS_OPT_DIAG
1128
1129extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
1130
1131typedef struct efx_register_set_s {
1132 unsigned int address;
1133 unsigned int step;
1134 unsigned int rows;
1135 efx_oword_t mask;
1136} efx_register_set_t;
1137
1138extern __checkReturn efx_rc_t
1139efx_nic_test_registers(
1140 __in efx_nic_t *enp,
1141 __in efx_register_set_t *rsp,
1142 __in size_t count);
1143
1144extern __checkReturn efx_rc_t
1145efx_nic_test_tables(
1146 __in efx_nic_t *enp,
1147 __in efx_register_set_t *rsp,
1148 __in efx_pattern_type_t pattern,
1149 __in size_t count);
1150
1151#endif /* EFSYS_OPT_DIAG */
1152
1153#if EFSYS_OPT_MCDI
1154
1155extern __checkReturn efx_rc_t
1156efx_mcdi_set_workaround(
1157 __in efx_nic_t *enp,
1158 __in uint32_t type,
1159 __in boolean_t enabled,
1160 __out_opt uint32_t *flagsp);
1161
1162extern __checkReturn efx_rc_t
1163efx_mcdi_get_workarounds(
1164 __in efx_nic_t *enp,
1165 __out_opt uint32_t *implementedp,
1166 __out_opt uint32_t *enabledp);
1167
1168#endif /* EFSYS_OPT_MCDI */
1169
1170#ifdef __cplusplus
1171}
1172#endif
1173
1174#endif /* _SYS_EFX_IMPL_H */
| 464 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
465} efx_mcdi_ops_t;
466
467typedef struct efx_mcdi_s {
468 efx_mcdi_ops_t *em_emcop;
469 const efx_mcdi_transport_t *em_emtp;
470 efx_mcdi_iface_t em_emip;
471} efx_mcdi_t;
472
473#endif /* EFSYS_OPT_MCDI */
474
475#if EFSYS_OPT_NVRAM
476typedef struct efx_nvram_ops_s {
477#if EFSYS_OPT_DIAG
478 efx_rc_t (*envo_test)(efx_nic_t *);
479#endif /* EFSYS_OPT_DIAG */
480 efx_rc_t (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *);
481 efx_rc_t (*envo_get_version)(efx_nic_t *, efx_nvram_type_t,
482 uint32_t *, uint16_t *);
483 efx_rc_t (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *);
484 efx_rc_t (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t,
485 unsigned int, caddr_t, size_t);
486 efx_rc_t (*envo_erase)(efx_nic_t *, efx_nvram_type_t);
487 efx_rc_t (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t,
488 unsigned int, caddr_t, size_t);
489 void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t);
490 efx_rc_t (*envo_set_version)(efx_nic_t *, efx_nvram_type_t,
491 uint16_t *);
492
493} efx_nvram_ops_t;
494#endif /* EFSYS_OPT_NVRAM */
495
496#if EFSYS_OPT_VPD
497typedef struct efx_vpd_ops_s {
498 efx_rc_t (*evpdo_init)(efx_nic_t *);
499 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
500 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
501 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
502 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
503 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
504 efx_vpd_value_t *);
505 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
506 efx_vpd_value_t *);
507 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
508 efx_vpd_value_t *, unsigned int *);
509 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
510 void (*evpdo_fini)(efx_nic_t *);
511} efx_vpd_ops_t;
512#endif /* EFSYS_OPT_VPD */
513
514#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
515
516 __checkReturn efx_rc_t
517efx_mcdi_nvram_partitions(
518 __in efx_nic_t *enp,
519 __out_bcount(size) caddr_t data,
520 __in size_t size,
521 __out unsigned int *npartnp);
522
523 __checkReturn efx_rc_t
524efx_mcdi_nvram_metadata(
525 __in efx_nic_t *enp,
526 __in uint32_t partn,
527 __out uint32_t *subtypep,
528 __out_ecount(4) uint16_t version[4],
529 __out_bcount_opt(size) char *descp,
530 __in size_t size);
531
532 __checkReturn efx_rc_t
533efx_mcdi_nvram_info(
534 __in efx_nic_t *enp,
535 __in uint32_t partn,
536 __out_opt size_t *sizep,
537 __out_opt uint32_t *addressp,
538 __out_opt uint32_t *erase_sizep,
539 __out_opt uint32_t *write_sizep);
540
541 __checkReturn efx_rc_t
542efx_mcdi_nvram_update_start(
543 __in efx_nic_t *enp,
544 __in uint32_t partn);
545
546 __checkReturn efx_rc_t
547efx_mcdi_nvram_read(
548 __in efx_nic_t *enp,
549 __in uint32_t partn,
550 __in uint32_t offset,
551 __out_bcount(size) caddr_t data,
552 __in size_t size);
553
554 __checkReturn efx_rc_t
555efx_mcdi_nvram_erase(
556 __in efx_nic_t *enp,
557 __in uint32_t partn,
558 __in uint32_t offset,
559 __in size_t size);
560
561 __checkReturn efx_rc_t
562efx_mcdi_nvram_write(
563 __in efx_nic_t *enp,
564 __in uint32_t partn,
565 __in uint32_t offset,
566 __out_bcount(size) caddr_t data,
567 __in size_t size);
568
569 __checkReturn efx_rc_t
570efx_mcdi_nvram_update_finish(
571 __in efx_nic_t *enp,
572 __in uint32_t partn,
573 __in boolean_t reboot);
574
575#if EFSYS_OPT_DIAG
576
577 __checkReturn efx_rc_t
578efx_mcdi_nvram_test(
579 __in efx_nic_t *enp,
580 __in uint32_t partn);
581
582#endif /* EFSYS_OPT_DIAG */
583
584#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
585
586typedef struct efx_drv_cfg_s {
587 uint32_t edc_min_vi_count;
588 uint32_t edc_max_vi_count;
589
590 uint32_t edc_max_piobuf_count;
591 uint32_t edc_pio_alloc_size;
592} efx_drv_cfg_t;
593
594struct efx_nic_s {
595 uint32_t en_magic;
596 efx_family_t en_family;
597 uint32_t en_features;
598 efsys_identifier_t *en_esip;
599 efsys_lock_t *en_eslp;
600 efsys_bar_t *en_esbp;
601 unsigned int en_mod_flags;
602 unsigned int en_reset_flags;
603 efx_nic_cfg_t en_nic_cfg;
604 efx_drv_cfg_t en_drv_cfg;
605 efx_port_t en_port;
606 efx_mon_t en_mon;
607 efx_intr_t en_intr;
608 uint32_t en_ev_qcount;
609 uint32_t en_rx_qcount;
610 uint32_t en_tx_qcount;
611 efx_nic_ops_t *en_enop;
612 efx_ev_ops_t *en_eevop;
613 efx_tx_ops_t *en_etxop;
614 efx_rx_ops_t *en_erxop;
615#if EFSYS_OPT_FILTER
616 efx_filter_t en_filter;
617 efx_filter_ops_t *en_efop;
618#endif /* EFSYS_OPT_FILTER */
619 efx_pktfilter_ops_t *en_epfop;
620#if EFSYS_OPT_MCDI
621 efx_mcdi_t en_mcdi;
622#endif /* EFSYS_OPT_MCDI */
623#if EFSYS_OPT_NVRAM
624 efx_nvram_type_t en_nvram_locked;
625 efx_nvram_ops_t *en_envop;
626#endif /* EFSYS_OPT_NVRAM */
627#if EFSYS_OPT_VPD
628 efx_vpd_ops_t *en_evpdop;
629#endif /* EFSYS_OPT_VPD */
630#if EFSYS_OPT_RX_SCALE
631 efx_rx_hash_support_t en_hash_support;
632 efx_rx_scale_support_t en_rss_support;
633 uint32_t en_rss_context;
634#endif /* EFSYS_OPT_RX_SCALE */
635 uint32_t en_vport_id;
636 union {
637#if EFSYS_OPT_FALCON
638 struct {
639 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES];
640 falcon_i2c_t enu_fip;
641 boolean_t enu_i2c_locked;
642#if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
643 const uint8_t *enu_forced_cfg;
644#endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
645 uint8_t enu_mon_devid;
646#if EFSYS_OPT_PCIE_TUNE
647 unsigned int enu_nlanes;
648#endif /* EFSYS_OPT_PCIE_TUNE */
649 uint16_t enu_board_rev;
650 boolean_t enu_internal_sram;
651 uint8_t enu_sram_num_bank;
652 uint8_t enu_sram_bank_size;
653 } falcon;
654#endif /* EFSYS_OPT_FALCON */
655#if EFSYS_OPT_SIENA
656 struct {
657#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
658 unsigned int enu_partn_mask;
659#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
660#if EFSYS_OPT_VPD
661 caddr_t enu_svpd;
662 size_t enu_svpd_length;
663#endif /* EFSYS_OPT_VPD */
664 int enu_unused;
665 } siena;
666#endif /* EFSYS_OPT_SIENA */
667#if EFSYS_OPT_HUNTINGTON
668 struct {
669 int enu_vi_base;
670 int enu_vi_count;
671#if EFSYS_OPT_VPD
672 caddr_t enu_svpd;
673 size_t enu_svpd_length;
674#endif /* EFSYS_OPT_VPD */
675 efx_piobuf_handle_t enu_piobuf_handle[HUNT_PIOBUF_NBUFS];
676 uint32_t enu_piobuf_count;
677 uint32_t enu_pio_alloc_map[HUNT_PIOBUF_NBUFS];
678 uint32_t enu_pio_write_vi_base;
679 /* Memory BAR mapping regions */
680 uint32_t enu_uc_mem_map_offset;
681 size_t enu_uc_mem_map_size;
682 uint32_t enu_wc_mem_map_offset;
683 size_t enu_wc_mem_map_size;
684 } hunt;
685#endif /* EFSYS_OPT_HUNTINGTON */
686 } en_u;
687};
688
689
690#define EFX_NIC_MAGIC 0x02121996
691
692typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
693 const efx_ev_callbacks_t *, void *);
694
695typedef struct efx_evq_rxq_state_s {
696 unsigned int eers_rx_read_ptr;
697 unsigned int eers_rx_mask;
698} efx_evq_rxq_state_t;
699
700struct efx_evq_s {
701 uint32_t ee_magic;
702 efx_nic_t *ee_enp;
703 unsigned int ee_index;
704 unsigned int ee_mask;
705 efsys_mem_t *ee_esmp;
706#if EFSYS_OPT_QSTATS
707 uint32_t ee_stat[EV_NQSTATS];
708#endif /* EFSYS_OPT_QSTATS */
709
710 efx_ev_handler_t ee_rx;
711 efx_ev_handler_t ee_tx;
712 efx_ev_handler_t ee_driver;
713 efx_ev_handler_t ee_global;
714 efx_ev_handler_t ee_drv_gen;
715#if EFSYS_OPT_MCDI
716 efx_ev_handler_t ee_mcdi;
717#endif /* EFSYS_OPT_MCDI */
718
719 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
720};
721
722#define EFX_EVQ_MAGIC 0x08081997
723
724#define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
725#define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
726
727struct efx_rxq_s {
728 uint32_t er_magic;
729 efx_nic_t *er_enp;
730 efx_evq_t *er_eep;
731 unsigned int er_index;
732 unsigned int er_label;
733 unsigned int er_mask;
734 efsys_mem_t *er_esmp;
735};
736
737#define EFX_RXQ_MAGIC 0x15022005
738
739struct efx_txq_s {
740 uint32_t et_magic;
741 efx_nic_t *et_enp;
742 unsigned int et_index;
743 unsigned int et_mask;
744 efsys_mem_t *et_esmp;
745#if EFSYS_OPT_HUNTINGTON
746 uint32_t et_pio_bufnum;
747 uint32_t et_pio_blknum;
748 uint32_t et_pio_write_offset;
749 uint32_t et_pio_offset;
750 size_t et_pio_size;
751#endif
752#if EFSYS_OPT_QSTATS
753 uint32_t et_stat[TX_NQSTATS];
754#endif /* EFSYS_OPT_QSTATS */
755};
756
757#define EFX_TXQ_MAGIC 0x05092005
758
759#define EFX_MAC_ADDR_COPY(_dst, _src) \
760 do { \
761 (_dst)[0] = (_src)[0]; \
762 (_dst)[1] = (_src)[1]; \
763 (_dst)[2] = (_src)[2]; \
764 (_dst)[3] = (_src)[3]; \
765 (_dst)[4] = (_src)[4]; \
766 (_dst)[5] = (_src)[5]; \
767 _NOTE(CONSTANTCONDITION) \
768 } while (B_FALSE)
769
770#define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
771 do { \
772 uint16_t *_d = (uint16_t *)(_dst); \
773 _d[0] = 0xffff; \
774 _d[1] = 0xffff; \
775 _d[2] = 0xffff; \
776 _NOTE(CONSTANTCONDITION) \
777 } while (B_FALSE)
778
779#if EFSYS_OPT_CHECK_REG
780#define EFX_CHECK_REG(_enp, _reg) \
781 do { \
782 const char *name = #_reg; \
783 char min = name[4]; \
784 char max = name[5]; \
785 char rev; \
786 \
787 switch ((_enp)->en_family) { \
788 case EFX_FAMILY_FALCON: \
789 rev = 'B'; \
790 break; \
791 \
792 case EFX_FAMILY_SIENA: \
793 rev = 'C'; \
794 break; \
795 \
796 case EFX_FAMILY_HUNTINGTON: \
797 rev = 'D'; \
798 break; \
799 \
800 default: \
801 rev = '?'; \
802 break; \
803 } \
804 \
805 EFSYS_ASSERT3S(rev, >=, min); \
806 EFSYS_ASSERT3S(rev, <=, max); \
807 \
808 _NOTE(CONSTANTCONDITION) \
809 } while (B_FALSE)
810#else
811#define EFX_CHECK_REG(_enp, _reg) do { \
812 _NOTE(CONSTANTCONDITION) \
813 } while(B_FALSE)
814#endif
815
816#define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
817 do { \
818 EFX_CHECK_REG((_enp), (_reg)); \
819 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
820 (_edp), (_lock)); \
821 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
822 uint32_t, _reg ## _OFST, \
823 uint32_t, (_edp)->ed_u32[0]); \
824 _NOTE(CONSTANTCONDITION) \
825 } while (B_FALSE)
826
827#define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
828 do { \
829 EFX_CHECK_REG((_enp), (_reg)); \
830 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
831 uint32_t, _reg ## _OFST, \
832 uint32_t, (_edp)->ed_u32[0]); \
833 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
834 (_edp), (_lock)); \
835 _NOTE(CONSTANTCONDITION) \
836 } while (B_FALSE)
837
838#define EFX_BAR_READQ(_enp, _reg, _eqp) \
839 do { \
840 EFX_CHECK_REG((_enp), (_reg)); \
841 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
842 (_eqp)); \
843 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
844 uint32_t, _reg ## _OFST, \
845 uint32_t, (_eqp)->eq_u32[1], \
846 uint32_t, (_eqp)->eq_u32[0]); \
847 _NOTE(CONSTANTCONDITION) \
848 } while (B_FALSE)
849
850#define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
851 do { \
852 EFX_CHECK_REG((_enp), (_reg)); \
853 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
854 uint32_t, _reg ## _OFST, \
855 uint32_t, (_eqp)->eq_u32[1], \
856 uint32_t, (_eqp)->eq_u32[0]); \
857 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
858 (_eqp)); \
859 _NOTE(CONSTANTCONDITION) \
860 } while (B_FALSE)
861
862#define EFX_BAR_READO(_enp, _reg, _eop) \
863 do { \
864 EFX_CHECK_REG((_enp), (_reg)); \
865 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
866 (_eop), B_TRUE); \
867 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
868 uint32_t, _reg ## _OFST, \
869 uint32_t, (_eop)->eo_u32[3], \
870 uint32_t, (_eop)->eo_u32[2], \
871 uint32_t, (_eop)->eo_u32[1], \
872 uint32_t, (_eop)->eo_u32[0]); \
873 _NOTE(CONSTANTCONDITION) \
874 } while (B_FALSE)
875
876#define EFX_BAR_WRITEO(_enp, _reg, _eop) \
877 do { \
878 EFX_CHECK_REG((_enp), (_reg)); \
879 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
880 uint32_t, _reg ## _OFST, \
881 uint32_t, (_eop)->eo_u32[3], \
882 uint32_t, (_eop)->eo_u32[2], \
883 uint32_t, (_eop)->eo_u32[1], \
884 uint32_t, (_eop)->eo_u32[0]); \
885 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
886 (_eop), B_TRUE); \
887 _NOTE(CONSTANTCONDITION) \
888 } while (B_FALSE)
889
890#define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
891 do { \
892 EFX_CHECK_REG((_enp), (_reg)); \
893 EFSYS_BAR_READD((_enp)->en_esbp, \
894 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
895 (_edp), (_lock)); \
896 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
897 uint32_t, (_index), \
898 uint32_t, _reg ## _OFST, \
899 uint32_t, (_edp)->ed_u32[0]); \
900 _NOTE(CONSTANTCONDITION) \
901 } while (B_FALSE)
902
903#define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
904 do { \
905 EFX_CHECK_REG((_enp), (_reg)); \
906 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
907 uint32_t, (_index), \
908 uint32_t, _reg ## _OFST, \
909 uint32_t, (_edp)->ed_u32[0]); \
910 EFSYS_BAR_WRITED((_enp)->en_esbp, \
911 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
912 (_edp), (_lock)); \
913 _NOTE(CONSTANTCONDITION) \
914 } while (B_FALSE)
915
916#define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
917 do { \
918 EFX_CHECK_REG((_enp), (_reg)); \
919 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
920 uint32_t, (_index), \
921 uint32_t, _reg ## _OFST, \
922 uint32_t, (_edp)->ed_u32[0]); \
923 EFSYS_BAR_WRITED((_enp)->en_esbp, \
924 (_reg ## _OFST + \
925 (2 * sizeof (efx_dword_t)) + \
926 ((_index) * _reg ## _STEP)), \
927 (_edp), (_lock)); \
928 _NOTE(CONSTANTCONDITION) \
929 } while (B_FALSE)
930
931#define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
932 do { \
933 EFX_CHECK_REG((_enp), (_reg)); \
934 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
935 uint32_t, (_index), \
936 uint32_t, _reg ## _OFST, \
937 uint32_t, (_edp)->ed_u32[0]); \
938 EFSYS_BAR_WRITED((_enp)->en_esbp, \
939 (_reg ## _OFST + \
940 (3 * sizeof (efx_dword_t)) + \
941 ((_index) * _reg ## _STEP)), \
942 (_edp), (_lock)); \
943 _NOTE(CONSTANTCONDITION) \
944 } while (B_FALSE)
945
946#define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
947 do { \
948 EFX_CHECK_REG((_enp), (_reg)); \
949 EFSYS_BAR_READQ((_enp)->en_esbp, \
950 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
951 (_eqp)); \
952 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
953 uint32_t, (_index), \
954 uint32_t, _reg ## _OFST, \
955 uint32_t, (_eqp)->eq_u32[1], \
956 uint32_t, (_eqp)->eq_u32[0]); \
957 _NOTE(CONSTANTCONDITION) \
958 } while (B_FALSE)
959
960#define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
961 do { \
962 EFX_CHECK_REG((_enp), (_reg)); \
963 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
964 uint32_t, (_index), \
965 uint32_t, _reg ## _OFST, \
966 uint32_t, (_eqp)->eq_u32[1], \
967 uint32_t, (_eqp)->eq_u32[0]); \
968 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
969 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
970 (_eqp)); \
971 _NOTE(CONSTANTCONDITION) \
972 } while (B_FALSE)
973
974#define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
975 do { \
976 EFX_CHECK_REG((_enp), (_reg)); \
977 EFSYS_BAR_READO((_enp)->en_esbp, \
978 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
979 (_eop), (_lock)); \
980 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
981 uint32_t, (_index), \
982 uint32_t, _reg ## _OFST, \
983 uint32_t, (_eop)->eo_u32[3], \
984 uint32_t, (_eop)->eo_u32[2], \
985 uint32_t, (_eop)->eo_u32[1], \
986 uint32_t, (_eop)->eo_u32[0]); \
987 _NOTE(CONSTANTCONDITION) \
988 } while (B_FALSE)
989
990#define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
991 do { \
992 EFX_CHECK_REG((_enp), (_reg)); \
993 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
994 uint32_t, (_index), \
995 uint32_t, _reg ## _OFST, \
996 uint32_t, (_eop)->eo_u32[3], \
997 uint32_t, (_eop)->eo_u32[2], \
998 uint32_t, (_eop)->eo_u32[1], \
999 uint32_t, (_eop)->eo_u32[0]); \
1000 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1001 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1002 (_eop), (_lock)); \
1003 _NOTE(CONSTANTCONDITION) \
1004 } while (B_FALSE)
1005
1006/*
1007 * Allow drivers to perform optimised 128-bit doorbell writes.
1008 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1009 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1010 * the need for locking in the host, and are the only ones known to be safe to
1011 * use 128-bites write with.
1012 */
1013#define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1014 do { \
1015 EFX_CHECK_REG((_enp), (_reg)); \
1016 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1017 const char *, \
1018 #_reg, \
1019 uint32_t, (_index), \
1020 uint32_t, _reg ## _OFST, \
1021 uint32_t, (_eop)->eo_u32[3], \
1022 uint32_t, (_eop)->eo_u32[2], \
1023 uint32_t, (_eop)->eo_u32[1], \
1024 uint32_t, (_eop)->eo_u32[0]); \
1025 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1026 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1027 (_eop)); \
1028 _NOTE(CONSTANTCONDITION) \
1029 } while (B_FALSE)
1030
1031#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1032 do { \
1033 unsigned int _new = (_wptr); \
1034 unsigned int _old = (_owptr); \
1035 \
1036 if ((_new) >= (_old)) \
1037 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1038 (_old) * sizeof (efx_desc_t), \
1039 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1040 else \
1041 /* \
1042 * It is cheaper to sync entire map than sync \
1043 * two parts especially when offset/size are \
1044 * ignored and entire map is synced in any case.\
1045 */ \
1046 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1047 0, \
1048 (_entries) * sizeof (efx_desc_t)); \
1049 _NOTE(CONSTANTCONDITION) \
1050 } while (B_FALSE)
1051
1052extern __checkReturn efx_rc_t
1053efx_nic_biu_test(
1054 __in efx_nic_t *enp);
1055
1056extern __checkReturn efx_rc_t
1057efx_mac_select(
1058 __in efx_nic_t *enp);
1059
1060extern void
1061efx_mac_multicast_hash_compute(
1062 __in_ecount(6*count) uint8_t const *addrs,
1063 __in int count,
1064 __out efx_oword_t *hash_low,
1065 __out efx_oword_t *hash_high);
1066
1067extern __checkReturn efx_rc_t
1068efx_phy_probe(
1069 __in efx_nic_t *enp);
1070
1071extern void
1072efx_phy_unprobe(
1073 __in efx_nic_t *enp);
1074
1075#if EFSYS_OPT_VPD
1076
1077/* VPD utility functions */
1078
1079extern __checkReturn efx_rc_t
1080efx_vpd_hunk_length(
1081 __in_bcount(size) caddr_t data,
1082 __in size_t size,
1083 __out size_t *lengthp);
1084
1085extern __checkReturn efx_rc_t
1086efx_vpd_hunk_verify(
1087 __in_bcount(size) caddr_t data,
1088 __in size_t size,
1089 __out_opt boolean_t *cksummedp);
1090
1091extern __checkReturn efx_rc_t
1092efx_vpd_hunk_reinit(
1093 __in_bcount(size) caddr_t data,
1094 __in size_t size,
1095 __in boolean_t wantpid);
1096
1097extern __checkReturn efx_rc_t
1098efx_vpd_hunk_get(
1099 __in_bcount(size) caddr_t data,
1100 __in size_t size,
1101 __in efx_vpd_tag_t tag,
1102 __in efx_vpd_keyword_t keyword,
1103 __out unsigned int *payloadp,
1104 __out uint8_t *paylenp);
1105
1106extern __checkReturn efx_rc_t
1107efx_vpd_hunk_next(
1108 __in_bcount(size) caddr_t data,
1109 __in size_t size,
1110 __out efx_vpd_tag_t *tagp,
1111 __out efx_vpd_keyword_t *keyword,
1112 __out_bcount_opt(*paylenp) unsigned int *payloadp,
1113 __out_opt uint8_t *paylenp,
1114 __inout unsigned int *contp);
1115
1116extern __checkReturn efx_rc_t
1117efx_vpd_hunk_set(
1118 __in_bcount(size) caddr_t data,
1119 __in size_t size,
1120 __in efx_vpd_value_t *evvp);
1121
1122#endif /* EFSYS_OPT_VPD */
1123
1124#if EFSYS_OPT_DIAG
1125
1126extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
1127
1128typedef struct efx_register_set_s {
1129 unsigned int address;
1130 unsigned int step;
1131 unsigned int rows;
1132 efx_oword_t mask;
1133} efx_register_set_t;
1134
1135extern __checkReturn efx_rc_t
1136efx_nic_test_registers(
1137 __in efx_nic_t *enp,
1138 __in efx_register_set_t *rsp,
1139 __in size_t count);
1140
1141extern __checkReturn efx_rc_t
1142efx_nic_test_tables(
1143 __in efx_nic_t *enp,
1144 __in efx_register_set_t *rsp,
1145 __in efx_pattern_type_t pattern,
1146 __in size_t count);
1147
1148#endif /* EFSYS_OPT_DIAG */
1149
1150#if EFSYS_OPT_MCDI
1151
1152extern __checkReturn efx_rc_t
1153efx_mcdi_set_workaround(
1154 __in efx_nic_t *enp,
1155 __in uint32_t type,
1156 __in boolean_t enabled,
1157 __out_opt uint32_t *flagsp);
1158
1159extern __checkReturn efx_rc_t
1160efx_mcdi_get_workarounds(
1161 __in efx_nic_t *enp,
1162 __out_opt uint32_t *implementedp,
1163 __out_opt uint32_t *enabledp);
1164
1165#endif /* EFSYS_OPT_MCDI */
1166
1167#ifdef __cplusplus
1168}
1169#endif
1170
1171#endif /* _SYS_EFX_IMPL_H */
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