31 */
32
33#ifndef _SYS_EFX_IMPL_H
34#define _SYS_EFX_IMPL_H
35
36#include "efsys.h"
37#include "efx.h"
38#include "efx_regs.h"
39#include "efx_regs_ef10.h"
40
41/* FIXME: Add definition for driver generated software events */
42#ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
43#define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
44#endif
45
46#include "efx_check.h"
47
48
49#if EFSYS_OPT_FALCON
50#include "falcon_impl.h"
51#endif /* EFSYS_OPT_FALCON */
52
53#if EFSYS_OPT_SIENA
54#include "siena_impl.h"
55#endif /* EFSYS_OPT_SIENA */
56
57#if EFSYS_OPT_HUNTINGTON
58#include "hunt_impl.h"
59#endif /* EFSYS_OPT_HUNTINGTON */
60
61#ifdef __cplusplus
62extern "C" {
63#endif
64
65#define EFX_MOD_MCDI 0x00000001
66#define EFX_MOD_PROBE 0x00000002
67#define EFX_MOD_NVRAM 0x00000004
68#define EFX_MOD_VPD 0x00000008
69#define EFX_MOD_NIC 0x00000010
70#define EFX_MOD_INTR 0x00000020
71#define EFX_MOD_EV 0x00000040
72#define EFX_MOD_RX 0x00000080
73#define EFX_MOD_TX 0x00000100
74#define EFX_MOD_PORT 0x00000200
75#define EFX_MOD_MON 0x00000400
76#define EFX_MOD_WOL 0x00000800
77#define EFX_MOD_FILTER 0x00001000
78#define EFX_MOD_PKTFILTER 0x00002000
79
80#define EFX_RESET_MAC 0x00000001
81#define EFX_RESET_PHY 0x00000002
82#define EFX_RESET_RXQ_ERR 0x00000004
83#define EFX_RESET_TXQ_ERR 0x00000008
84
85typedef enum efx_mac_type_e {
86 EFX_MAC_INVALID = 0,
87 EFX_MAC_FALCON_GMAC,
88 EFX_MAC_FALCON_XMAC,
89 EFX_MAC_SIENA,
90 EFX_MAC_HUNTINGTON,
91 EFX_MAC_NTYPES
92} efx_mac_type_t;
93
94typedef struct efx_ev_ops_s {
95 efx_rc_t (*eevo_init)(efx_nic_t *);
96 void (*eevo_fini)(efx_nic_t *);
97 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
98 efsys_mem_t *, size_t, uint32_t,
99 efx_evq_t *);
100 void (*eevo_qdestroy)(efx_evq_t *);
101 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
102 void (*eevo_qpost)(efx_evq_t *, uint16_t);
103 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
104#if EFSYS_OPT_QSTATS
105 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
106#endif
107} efx_ev_ops_t;
108
109typedef struct efx_tx_ops_s {
110 efx_rc_t (*etxo_init)(efx_nic_t *);
111 void (*etxo_fini)(efx_nic_t *);
112 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
113 unsigned int, unsigned int,
114 efsys_mem_t *, size_t,
115 uint32_t, uint16_t,
116 efx_evq_t *, efx_txq_t *,
117 unsigned int *);
118 void (*etxo_qdestroy)(efx_txq_t *);
119 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
120 unsigned int, unsigned int,
121 unsigned int *);
122 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
123 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
124 efx_rc_t (*etxo_qflush)(efx_txq_t *);
125 void (*etxo_qenable)(efx_txq_t *);
126 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
127 void (*etxo_qpio_disable)(efx_txq_t *);
128 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
129 size_t);
130 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
131 unsigned int *);
132 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
133 unsigned int, unsigned int,
134 unsigned int *);
135 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
136 size_t, boolean_t,
137 efx_desc_t *);
138 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
139 uint32_t, uint8_t,
140 efx_desc_t *);
141 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
142 efx_desc_t *);
143#if EFSYS_OPT_QSTATS
144 void (*etxo_qstats_update)(efx_txq_t *,
145 efsys_stat_t *);
146#endif
147} efx_tx_ops_t;
148
149typedef struct efx_rx_ops_s {
150 efx_rc_t (*erxo_init)(efx_nic_t *);
151 void (*erxo_fini)(efx_nic_t *);
152#if EFSYS_OPT_RX_HDR_SPLIT
153 efx_rc_t (*erxo_hdr_split_enable)(efx_nic_t *, unsigned int,
154 unsigned int);
155#endif
156#if EFSYS_OPT_RX_SCATTER
157 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
158#endif
159#if EFSYS_OPT_RX_SCALE
160 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
161 efx_rx_hash_type_t, boolean_t);
162 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
163 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
164 size_t);
165#endif
166 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
167 unsigned int, unsigned int,
168 unsigned int);
169 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
170 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
171 void (*erxo_qenable)(efx_rxq_t *);
172 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
173 unsigned int, efx_rxq_type_t,
174 efsys_mem_t *, size_t, uint32_t,
175 efx_evq_t *, efx_rxq_t *);
176 void (*erxo_qdestroy)(efx_rxq_t *);
177} efx_rx_ops_t;
178
179typedef struct efx_mac_ops_s {
180 efx_rc_t (*emo_reset)(efx_nic_t *); /* optional */
181 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
182 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
183 efx_rc_t (*emo_addr_set)(efx_nic_t *);
184 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
185 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
186 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
187 efx_rxq_t *, boolean_t);
188 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
189#if EFSYS_OPT_LOOPBACK
190 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
191 efx_loopback_type_t);
192#endif /* EFSYS_OPT_LOOPBACK */
193#if EFSYS_OPT_MAC_STATS
194 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
195 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
196 uint16_t, boolean_t);
197 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
198 efsys_stat_t *, uint32_t *);
199#endif /* EFSYS_OPT_MAC_STATS */
200} efx_mac_ops_t;
201
202typedef struct efx_phy_ops_s {
203 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
204 efx_rc_t (*epo_reset)(efx_nic_t *);
205 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
206 efx_rc_t (*epo_verify)(efx_nic_t *);
207 efx_rc_t (*epo_uplink_check)(efx_nic_t *,
208 boolean_t *); /* optional */
209 efx_rc_t (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
210 unsigned int *, uint32_t *);
211 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
212#if EFSYS_OPT_PHY_STATS
213 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
214 uint32_t *);
215#endif /* EFSYS_OPT_PHY_STATS */
216#if EFSYS_OPT_PHY_PROPS
217#if EFSYS_OPT_NAMES
218 const char *(*epo_prop_name)(efx_nic_t *, unsigned int);
219#endif /* EFSYS_OPT_PHY_PROPS */
220 efx_rc_t (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
221 uint32_t *);
222 efx_rc_t (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
223#endif /* EFSYS_OPT_PHY_PROPS */
224#if EFSYS_OPT_BIST
225 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
226 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
227 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
228 efx_bist_result_t *, uint32_t *,
229 unsigned long *, size_t);
230 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
231#endif /* EFSYS_OPT_BIST */
232} efx_phy_ops_t;
233
234#if EFSYS_OPT_FILTER
235typedef struct efx_filter_ops_s {
236 efx_rc_t (*efo_init)(efx_nic_t *);
237 void (*efo_fini)(efx_nic_t *);
238 efx_rc_t (*efo_restore)(efx_nic_t *);
239 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
240 boolean_t may_replace);
241 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
242 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
243 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
244 boolean_t, boolean_t, boolean_t,
245 uint8_t const *, int);
246} efx_filter_ops_t;
247
248extern __checkReturn efx_rc_t
249efx_filter_reconfigure(
250 __in efx_nic_t *enp,
251 __in_ecount(6) uint8_t const *mac_addr,
252 __in boolean_t all_unicst,
253 __in boolean_t mulcst,
254 __in boolean_t all_mulcst,
255 __in boolean_t brdcst,
256 __in_ecount(6*count) uint8_t const *addrs,
257 __in int count);
258
259#endif /* EFSYS_OPT_FILTER */
260
261typedef struct efx_pktfilter_ops_s {
262 efx_rc_t (*epfo_set)(efx_nic_t *,
263 boolean_t unicst,
264 boolean_t brdcast);
265#if EFSYS_OPT_MCAST_FILTER_LIST
266 efx_rc_t (*epfo_mcast_list_set)(efx_nic_t *,
267 uint8_t const *addrs, int count);
268#endif /* EFSYS_OPT_MCAST_FILTER_LIST */
269 efx_rc_t (*epfo_mcast_all)(efx_nic_t *);
270} efx_pktfilter_ops_t;
271
272typedef struct efx_port_s {
273 efx_mac_type_t ep_mac_type;
274 uint32_t ep_phy_type;
275 uint8_t ep_port;
276 uint32_t ep_mac_pdu;
277 uint8_t ep_mac_addr[6];
278 efx_link_mode_t ep_link_mode;
279 boolean_t ep_all_unicst;
280 boolean_t ep_mulcst;
281 boolean_t ep_all_mulcst;
282 boolean_t ep_brdcst;
283 unsigned int ep_fcntl;
284 boolean_t ep_fcntl_autoneg;
285 efx_oword_t ep_multicst_hash[2];
286 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
287 EFX_MAC_MULTICAST_LIST_MAX];
288 uint32_t ep_mulcst_addr_count;
289#if EFSYS_OPT_LOOPBACK
290 efx_loopback_type_t ep_loopback_type;
291 efx_link_mode_t ep_loopback_link_mode;
292#endif /* EFSYS_OPT_LOOPBACK */
293#if EFSYS_OPT_PHY_FLAGS
294 uint32_t ep_phy_flags;
295#endif /* EFSYS_OPT_PHY_FLAGS */
296#if EFSYS_OPT_PHY_LED_CONTROL
297 efx_phy_led_mode_t ep_phy_led_mode;
298#endif /* EFSYS_OPT_PHY_LED_CONTROL */
299 efx_phy_media_type_t ep_fixed_port_type;
300 efx_phy_media_type_t ep_module_type;
301 uint32_t ep_adv_cap_mask;
302 uint32_t ep_lp_cap_mask;
303 uint32_t ep_default_adv_cap_mask;
304 uint32_t ep_phy_cap_mask;
305#if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
306 union {
307 struct {
308 unsigned int bug10934_count;
309 } ep_txc43128;
310 struct {
311 unsigned int bug17190_count;
312 } ep_qt2025c;
313 };
314#endif
315 boolean_t ep_mac_poll_needed; /* falcon only */
316 boolean_t ep_mac_up; /* falcon only */
317 uint32_t ep_fwver; /* falcon only */
318 boolean_t ep_mac_drain;
319 boolean_t ep_mac_stats_pending;
320#if EFSYS_OPT_BIST
321 efx_bist_type_t ep_current_bist;
322#endif
323 efx_mac_ops_t *ep_emop;
324 efx_phy_ops_t *ep_epop;
325} efx_port_t;
326
327typedef struct efx_mon_ops_s {
328 efx_rc_t (*emo_reset)(efx_nic_t *);
329 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
330#if EFSYS_OPT_MON_STATS
331 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
332 efx_mon_stat_value_t *);
333#endif /* EFSYS_OPT_MON_STATS */
334} efx_mon_ops_t;
335
336typedef struct efx_mon_s {
337 efx_mon_type_t em_type;
338 efx_mon_ops_t *em_emop;
339} efx_mon_t;
340
341typedef struct efx_intr_ops_s {
342 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
343 void (*eio_enable)(efx_nic_t *);
344 void (*eio_disable)(efx_nic_t *);
345 void (*eio_disable_unlocked)(efx_nic_t *);
346 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
347 void (*eio_fini)(efx_nic_t *);
348} efx_intr_ops_t;
349
350typedef struct efx_intr_s {
351 efx_intr_ops_t *ei_eiop;
352 efsys_mem_t *ei_esmp;
353 efx_intr_type_t ei_type;
354 unsigned int ei_level;
355} efx_intr_t;
356
357typedef struct efx_nic_ops_s {
358 efx_rc_t (*eno_probe)(efx_nic_t *);
359 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
360 efx_rc_t (*eno_reset)(efx_nic_t *);
361 efx_rc_t (*eno_init)(efx_nic_t *);
362 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
363 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
364 uint32_t *, size_t *);
365#if EFSYS_OPT_DIAG
366 efx_rc_t (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
367 efx_rc_t (*eno_register_test)(efx_nic_t *);
368#endif /* EFSYS_OPT_DIAG */
369 void (*eno_fini)(efx_nic_t *);
370 void (*eno_unprobe)(efx_nic_t *);
371} efx_nic_ops_t;
372
373#ifndef EFX_TXQ_LIMIT_TARGET
374#define EFX_TXQ_LIMIT_TARGET 259
375#endif
376#ifndef EFX_RXQ_LIMIT_TARGET
377#define EFX_RXQ_LIMIT_TARGET 512
378#endif
379#ifndef EFX_TXQ_DC_SIZE
380#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
381#endif
382#ifndef EFX_RXQ_DC_SIZE
383#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
384#endif
385
386#if EFSYS_OPT_FILTER
387
388typedef struct falconsiena_filter_spec_s {
389 uint8_t fsfs_type;
390 uint32_t fsfs_flags;
391 uint32_t fsfs_dmaq_id;
392 uint32_t fsfs_dword[3];
393} falconsiena_filter_spec_t;
394
395typedef enum falconsiena_filter_type_e {
396 EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
397 EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */
398 EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
399 EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */
400
401#if EFSYS_OPT_SIENA
402 EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
403 EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
404
405 EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
406 EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
407 EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
408 EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */
409
410 EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */
411 EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */
412#endif /* EFSYS_OPT_SIENA */
413
414 EFX_FS_FILTER_NTYPES
415} falconsiena_filter_type_t;
416
417typedef enum falconsiena_filter_tbl_id_e {
418 EFX_FS_FILTER_TBL_RX_IP = 0,
419 EFX_FS_FILTER_TBL_RX_MAC,
420 EFX_FS_FILTER_TBL_TX_IP,
421 EFX_FS_FILTER_TBL_TX_MAC,
422 EFX_FS_FILTER_NTBLS
423} falconsiena_filter_tbl_id_t;
424
425typedef struct falconsiena_filter_tbl_s {
426 int fsft_size; /* number of entries */
427 int fsft_used; /* active count */
428 uint32_t *fsft_bitmap; /* active bitmap */
429 falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */
430} falconsiena_filter_tbl_t;
431
432typedef struct falconsiena_filter_s {
433 falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS];
434 unsigned int fsf_depth[EFX_FS_FILTER_NTYPES];
435} falconsiena_filter_t;
436
437typedef struct efx_filter_s {
438#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
439 falconsiena_filter_t *ef_falconsiena_filter;
440#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
441#if EFSYS_OPT_HUNTINGTON
442 hunt_filter_table_t *ef_hunt_filter_table;
443#endif /* EFSYS_OPT_HUNTINGTON */
444} efx_filter_t;
445
446extern void
447falconsiena_filter_tbl_clear(
448 __in efx_nic_t *enp,
449 __in falconsiena_filter_tbl_id_t tbl);
450
451#endif /* EFSYS_OPT_FILTER */
452
453#if EFSYS_OPT_MCDI
454
455typedef struct efx_mcdi_ops_s {
456 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
457 void (*emco_request_copyin)(efx_nic_t *, efx_mcdi_req_t *,
458 unsigned int, boolean_t, boolean_t);
459 boolean_t (*emco_request_poll)(efx_nic_t *);
460 void (*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *);
461 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
462 void (*emco_fini)(efx_nic_t *);
463 efx_rc_t (*emco_fw_update_supported)(efx_nic_t *, boolean_t *);
464 efx_rc_t (*emco_macaddr_change_supported)(efx_nic_t *, boolean_t *);
465 efx_rc_t (*emco_link_control_supported)(efx_nic_t *, boolean_t *);
| 31 */
32
33#ifndef _SYS_EFX_IMPL_H
34#define _SYS_EFX_IMPL_H
35
36#include "efsys.h"
37#include "efx.h"
38#include "efx_regs.h"
39#include "efx_regs_ef10.h"
40
41/* FIXME: Add definition for driver generated software events */
42#ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
43#define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
44#endif
45
46#include "efx_check.h"
47
48
49#if EFSYS_OPT_FALCON
50#include "falcon_impl.h"
51#endif /* EFSYS_OPT_FALCON */
52
53#if EFSYS_OPT_SIENA
54#include "siena_impl.h"
55#endif /* EFSYS_OPT_SIENA */
56
57#if EFSYS_OPT_HUNTINGTON
58#include "hunt_impl.h"
59#endif /* EFSYS_OPT_HUNTINGTON */
60
61#ifdef __cplusplus
62extern "C" {
63#endif
64
65#define EFX_MOD_MCDI 0x00000001
66#define EFX_MOD_PROBE 0x00000002
67#define EFX_MOD_NVRAM 0x00000004
68#define EFX_MOD_VPD 0x00000008
69#define EFX_MOD_NIC 0x00000010
70#define EFX_MOD_INTR 0x00000020
71#define EFX_MOD_EV 0x00000040
72#define EFX_MOD_RX 0x00000080
73#define EFX_MOD_TX 0x00000100
74#define EFX_MOD_PORT 0x00000200
75#define EFX_MOD_MON 0x00000400
76#define EFX_MOD_WOL 0x00000800
77#define EFX_MOD_FILTER 0x00001000
78#define EFX_MOD_PKTFILTER 0x00002000
79
80#define EFX_RESET_MAC 0x00000001
81#define EFX_RESET_PHY 0x00000002
82#define EFX_RESET_RXQ_ERR 0x00000004
83#define EFX_RESET_TXQ_ERR 0x00000008
84
85typedef enum efx_mac_type_e {
86 EFX_MAC_INVALID = 0,
87 EFX_MAC_FALCON_GMAC,
88 EFX_MAC_FALCON_XMAC,
89 EFX_MAC_SIENA,
90 EFX_MAC_HUNTINGTON,
91 EFX_MAC_NTYPES
92} efx_mac_type_t;
93
94typedef struct efx_ev_ops_s {
95 efx_rc_t (*eevo_init)(efx_nic_t *);
96 void (*eevo_fini)(efx_nic_t *);
97 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
98 efsys_mem_t *, size_t, uint32_t,
99 efx_evq_t *);
100 void (*eevo_qdestroy)(efx_evq_t *);
101 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
102 void (*eevo_qpost)(efx_evq_t *, uint16_t);
103 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
104#if EFSYS_OPT_QSTATS
105 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
106#endif
107} efx_ev_ops_t;
108
109typedef struct efx_tx_ops_s {
110 efx_rc_t (*etxo_init)(efx_nic_t *);
111 void (*etxo_fini)(efx_nic_t *);
112 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
113 unsigned int, unsigned int,
114 efsys_mem_t *, size_t,
115 uint32_t, uint16_t,
116 efx_evq_t *, efx_txq_t *,
117 unsigned int *);
118 void (*etxo_qdestroy)(efx_txq_t *);
119 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
120 unsigned int, unsigned int,
121 unsigned int *);
122 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
123 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
124 efx_rc_t (*etxo_qflush)(efx_txq_t *);
125 void (*etxo_qenable)(efx_txq_t *);
126 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
127 void (*etxo_qpio_disable)(efx_txq_t *);
128 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
129 size_t);
130 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
131 unsigned int *);
132 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
133 unsigned int, unsigned int,
134 unsigned int *);
135 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
136 size_t, boolean_t,
137 efx_desc_t *);
138 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
139 uint32_t, uint8_t,
140 efx_desc_t *);
141 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
142 efx_desc_t *);
143#if EFSYS_OPT_QSTATS
144 void (*etxo_qstats_update)(efx_txq_t *,
145 efsys_stat_t *);
146#endif
147} efx_tx_ops_t;
148
149typedef struct efx_rx_ops_s {
150 efx_rc_t (*erxo_init)(efx_nic_t *);
151 void (*erxo_fini)(efx_nic_t *);
152#if EFSYS_OPT_RX_HDR_SPLIT
153 efx_rc_t (*erxo_hdr_split_enable)(efx_nic_t *, unsigned int,
154 unsigned int);
155#endif
156#if EFSYS_OPT_RX_SCATTER
157 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
158#endif
159#if EFSYS_OPT_RX_SCALE
160 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
161 efx_rx_hash_type_t, boolean_t);
162 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
163 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
164 size_t);
165#endif
166 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
167 unsigned int, unsigned int,
168 unsigned int);
169 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
170 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
171 void (*erxo_qenable)(efx_rxq_t *);
172 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
173 unsigned int, efx_rxq_type_t,
174 efsys_mem_t *, size_t, uint32_t,
175 efx_evq_t *, efx_rxq_t *);
176 void (*erxo_qdestroy)(efx_rxq_t *);
177} efx_rx_ops_t;
178
179typedef struct efx_mac_ops_s {
180 efx_rc_t (*emo_reset)(efx_nic_t *); /* optional */
181 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
182 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
183 efx_rc_t (*emo_addr_set)(efx_nic_t *);
184 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
185 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
186 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
187 efx_rxq_t *, boolean_t);
188 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
189#if EFSYS_OPT_LOOPBACK
190 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
191 efx_loopback_type_t);
192#endif /* EFSYS_OPT_LOOPBACK */
193#if EFSYS_OPT_MAC_STATS
194 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
195 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
196 uint16_t, boolean_t);
197 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
198 efsys_stat_t *, uint32_t *);
199#endif /* EFSYS_OPT_MAC_STATS */
200} efx_mac_ops_t;
201
202typedef struct efx_phy_ops_s {
203 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
204 efx_rc_t (*epo_reset)(efx_nic_t *);
205 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
206 efx_rc_t (*epo_verify)(efx_nic_t *);
207 efx_rc_t (*epo_uplink_check)(efx_nic_t *,
208 boolean_t *); /* optional */
209 efx_rc_t (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
210 unsigned int *, uint32_t *);
211 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
212#if EFSYS_OPT_PHY_STATS
213 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
214 uint32_t *);
215#endif /* EFSYS_OPT_PHY_STATS */
216#if EFSYS_OPT_PHY_PROPS
217#if EFSYS_OPT_NAMES
218 const char *(*epo_prop_name)(efx_nic_t *, unsigned int);
219#endif /* EFSYS_OPT_PHY_PROPS */
220 efx_rc_t (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
221 uint32_t *);
222 efx_rc_t (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
223#endif /* EFSYS_OPT_PHY_PROPS */
224#if EFSYS_OPT_BIST
225 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
226 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
227 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
228 efx_bist_result_t *, uint32_t *,
229 unsigned long *, size_t);
230 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
231#endif /* EFSYS_OPT_BIST */
232} efx_phy_ops_t;
233
234#if EFSYS_OPT_FILTER
235typedef struct efx_filter_ops_s {
236 efx_rc_t (*efo_init)(efx_nic_t *);
237 void (*efo_fini)(efx_nic_t *);
238 efx_rc_t (*efo_restore)(efx_nic_t *);
239 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
240 boolean_t may_replace);
241 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
242 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
243 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
244 boolean_t, boolean_t, boolean_t,
245 uint8_t const *, int);
246} efx_filter_ops_t;
247
248extern __checkReturn efx_rc_t
249efx_filter_reconfigure(
250 __in efx_nic_t *enp,
251 __in_ecount(6) uint8_t const *mac_addr,
252 __in boolean_t all_unicst,
253 __in boolean_t mulcst,
254 __in boolean_t all_mulcst,
255 __in boolean_t brdcst,
256 __in_ecount(6*count) uint8_t const *addrs,
257 __in int count);
258
259#endif /* EFSYS_OPT_FILTER */
260
261typedef struct efx_pktfilter_ops_s {
262 efx_rc_t (*epfo_set)(efx_nic_t *,
263 boolean_t unicst,
264 boolean_t brdcast);
265#if EFSYS_OPT_MCAST_FILTER_LIST
266 efx_rc_t (*epfo_mcast_list_set)(efx_nic_t *,
267 uint8_t const *addrs, int count);
268#endif /* EFSYS_OPT_MCAST_FILTER_LIST */
269 efx_rc_t (*epfo_mcast_all)(efx_nic_t *);
270} efx_pktfilter_ops_t;
271
272typedef struct efx_port_s {
273 efx_mac_type_t ep_mac_type;
274 uint32_t ep_phy_type;
275 uint8_t ep_port;
276 uint32_t ep_mac_pdu;
277 uint8_t ep_mac_addr[6];
278 efx_link_mode_t ep_link_mode;
279 boolean_t ep_all_unicst;
280 boolean_t ep_mulcst;
281 boolean_t ep_all_mulcst;
282 boolean_t ep_brdcst;
283 unsigned int ep_fcntl;
284 boolean_t ep_fcntl_autoneg;
285 efx_oword_t ep_multicst_hash[2];
286 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
287 EFX_MAC_MULTICAST_LIST_MAX];
288 uint32_t ep_mulcst_addr_count;
289#if EFSYS_OPT_LOOPBACK
290 efx_loopback_type_t ep_loopback_type;
291 efx_link_mode_t ep_loopback_link_mode;
292#endif /* EFSYS_OPT_LOOPBACK */
293#if EFSYS_OPT_PHY_FLAGS
294 uint32_t ep_phy_flags;
295#endif /* EFSYS_OPT_PHY_FLAGS */
296#if EFSYS_OPT_PHY_LED_CONTROL
297 efx_phy_led_mode_t ep_phy_led_mode;
298#endif /* EFSYS_OPT_PHY_LED_CONTROL */
299 efx_phy_media_type_t ep_fixed_port_type;
300 efx_phy_media_type_t ep_module_type;
301 uint32_t ep_adv_cap_mask;
302 uint32_t ep_lp_cap_mask;
303 uint32_t ep_default_adv_cap_mask;
304 uint32_t ep_phy_cap_mask;
305#if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
306 union {
307 struct {
308 unsigned int bug10934_count;
309 } ep_txc43128;
310 struct {
311 unsigned int bug17190_count;
312 } ep_qt2025c;
313 };
314#endif
315 boolean_t ep_mac_poll_needed; /* falcon only */
316 boolean_t ep_mac_up; /* falcon only */
317 uint32_t ep_fwver; /* falcon only */
318 boolean_t ep_mac_drain;
319 boolean_t ep_mac_stats_pending;
320#if EFSYS_OPT_BIST
321 efx_bist_type_t ep_current_bist;
322#endif
323 efx_mac_ops_t *ep_emop;
324 efx_phy_ops_t *ep_epop;
325} efx_port_t;
326
327typedef struct efx_mon_ops_s {
328 efx_rc_t (*emo_reset)(efx_nic_t *);
329 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
330#if EFSYS_OPT_MON_STATS
331 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
332 efx_mon_stat_value_t *);
333#endif /* EFSYS_OPT_MON_STATS */
334} efx_mon_ops_t;
335
336typedef struct efx_mon_s {
337 efx_mon_type_t em_type;
338 efx_mon_ops_t *em_emop;
339} efx_mon_t;
340
341typedef struct efx_intr_ops_s {
342 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
343 void (*eio_enable)(efx_nic_t *);
344 void (*eio_disable)(efx_nic_t *);
345 void (*eio_disable_unlocked)(efx_nic_t *);
346 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
347 void (*eio_fini)(efx_nic_t *);
348} efx_intr_ops_t;
349
350typedef struct efx_intr_s {
351 efx_intr_ops_t *ei_eiop;
352 efsys_mem_t *ei_esmp;
353 efx_intr_type_t ei_type;
354 unsigned int ei_level;
355} efx_intr_t;
356
357typedef struct efx_nic_ops_s {
358 efx_rc_t (*eno_probe)(efx_nic_t *);
359 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
360 efx_rc_t (*eno_reset)(efx_nic_t *);
361 efx_rc_t (*eno_init)(efx_nic_t *);
362 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
363 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
364 uint32_t *, size_t *);
365#if EFSYS_OPT_DIAG
366 efx_rc_t (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
367 efx_rc_t (*eno_register_test)(efx_nic_t *);
368#endif /* EFSYS_OPT_DIAG */
369 void (*eno_fini)(efx_nic_t *);
370 void (*eno_unprobe)(efx_nic_t *);
371} efx_nic_ops_t;
372
373#ifndef EFX_TXQ_LIMIT_TARGET
374#define EFX_TXQ_LIMIT_TARGET 259
375#endif
376#ifndef EFX_RXQ_LIMIT_TARGET
377#define EFX_RXQ_LIMIT_TARGET 512
378#endif
379#ifndef EFX_TXQ_DC_SIZE
380#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
381#endif
382#ifndef EFX_RXQ_DC_SIZE
383#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
384#endif
385
386#if EFSYS_OPT_FILTER
387
388typedef struct falconsiena_filter_spec_s {
389 uint8_t fsfs_type;
390 uint32_t fsfs_flags;
391 uint32_t fsfs_dmaq_id;
392 uint32_t fsfs_dword[3];
393} falconsiena_filter_spec_t;
394
395typedef enum falconsiena_filter_type_e {
396 EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
397 EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */
398 EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
399 EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */
400
401#if EFSYS_OPT_SIENA
402 EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
403 EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
404
405 EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
406 EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
407 EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
408 EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */
409
410 EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */
411 EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */
412#endif /* EFSYS_OPT_SIENA */
413
414 EFX_FS_FILTER_NTYPES
415} falconsiena_filter_type_t;
416
417typedef enum falconsiena_filter_tbl_id_e {
418 EFX_FS_FILTER_TBL_RX_IP = 0,
419 EFX_FS_FILTER_TBL_RX_MAC,
420 EFX_FS_FILTER_TBL_TX_IP,
421 EFX_FS_FILTER_TBL_TX_MAC,
422 EFX_FS_FILTER_NTBLS
423} falconsiena_filter_tbl_id_t;
424
425typedef struct falconsiena_filter_tbl_s {
426 int fsft_size; /* number of entries */
427 int fsft_used; /* active count */
428 uint32_t *fsft_bitmap; /* active bitmap */
429 falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */
430} falconsiena_filter_tbl_t;
431
432typedef struct falconsiena_filter_s {
433 falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS];
434 unsigned int fsf_depth[EFX_FS_FILTER_NTYPES];
435} falconsiena_filter_t;
436
437typedef struct efx_filter_s {
438#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
439 falconsiena_filter_t *ef_falconsiena_filter;
440#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
441#if EFSYS_OPT_HUNTINGTON
442 hunt_filter_table_t *ef_hunt_filter_table;
443#endif /* EFSYS_OPT_HUNTINGTON */
444} efx_filter_t;
445
446extern void
447falconsiena_filter_tbl_clear(
448 __in efx_nic_t *enp,
449 __in falconsiena_filter_tbl_id_t tbl);
450
451#endif /* EFSYS_OPT_FILTER */
452
453#if EFSYS_OPT_MCDI
454
455typedef struct efx_mcdi_ops_s {
456 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
457 void (*emco_request_copyin)(efx_nic_t *, efx_mcdi_req_t *,
458 unsigned int, boolean_t, boolean_t);
459 boolean_t (*emco_request_poll)(efx_nic_t *);
460 void (*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *);
461 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
462 void (*emco_fini)(efx_nic_t *);
463 efx_rc_t (*emco_fw_update_supported)(efx_nic_t *, boolean_t *);
464 efx_rc_t (*emco_macaddr_change_supported)(efx_nic_t *, boolean_t *);
465 efx_rc_t (*emco_link_control_supported)(efx_nic_t *, boolean_t *);
|
466} efx_mcdi_ops_t;
467
468typedef struct efx_mcdi_s {
469 efx_mcdi_ops_t *em_emcop;
470 const efx_mcdi_transport_t *em_emtp;
471 efx_mcdi_iface_t em_emip;
472} efx_mcdi_t;
473
474#endif /* EFSYS_OPT_MCDI */
475
476#if EFSYS_OPT_NVRAM
477typedef struct efx_nvram_ops_s {
478#if EFSYS_OPT_DIAG
479 efx_rc_t (*envo_test)(efx_nic_t *);
480#endif /* EFSYS_OPT_DIAG */
481 efx_rc_t (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *);
482 efx_rc_t (*envo_get_version)(efx_nic_t *, efx_nvram_type_t,
483 uint32_t *, uint16_t *);
484 efx_rc_t (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *);
485 efx_rc_t (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t,
486 unsigned int, caddr_t, size_t);
487 efx_rc_t (*envo_erase)(efx_nic_t *, efx_nvram_type_t);
488 efx_rc_t (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t,
489 unsigned int, caddr_t, size_t);
490 void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t);
491 efx_rc_t (*envo_set_version)(efx_nic_t *, efx_nvram_type_t,
492 uint16_t *);
493
494} efx_nvram_ops_t;
495#endif /* EFSYS_OPT_NVRAM */
496
497#if EFSYS_OPT_VPD
498typedef struct efx_vpd_ops_s {
499 efx_rc_t (*evpdo_init)(efx_nic_t *);
500 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
501 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
502 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
503 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
504 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
505 efx_vpd_value_t *);
506 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
507 efx_vpd_value_t *);
508 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
509 efx_vpd_value_t *, unsigned int *);
510 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
511 void (*evpdo_fini)(efx_nic_t *);
512} efx_vpd_ops_t;
513#endif /* EFSYS_OPT_VPD */
514
515#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
516
517 __checkReturn efx_rc_t
518efx_mcdi_nvram_partitions(
519 __in efx_nic_t *enp,
520 __out_bcount(size) caddr_t data,
521 __in size_t size,
522 __out unsigned int *npartnp);
523
524 __checkReturn efx_rc_t
525efx_mcdi_nvram_metadata(
526 __in efx_nic_t *enp,
527 __in uint32_t partn,
528 __out uint32_t *subtypep,
529 __out_ecount(4) uint16_t version[4],
530 __out_bcount_opt(size) char *descp,
531 __in size_t size);
532
533 __checkReturn efx_rc_t
534efx_mcdi_nvram_info(
535 __in efx_nic_t *enp,
536 __in uint32_t partn,
537 __out_opt size_t *sizep,
538 __out_opt uint32_t *addressp,
539 __out_opt uint32_t *erase_sizep,
540 __out_opt uint32_t *write_sizep);
541
542 __checkReturn efx_rc_t
543efx_mcdi_nvram_update_start(
544 __in efx_nic_t *enp,
545 __in uint32_t partn);
546
547 __checkReturn efx_rc_t
548efx_mcdi_nvram_read(
549 __in efx_nic_t *enp,
550 __in uint32_t partn,
551 __in uint32_t offset,
552 __out_bcount(size) caddr_t data,
553 __in size_t size);
554
555 __checkReturn efx_rc_t
556efx_mcdi_nvram_erase(
557 __in efx_nic_t *enp,
558 __in uint32_t partn,
559 __in uint32_t offset,
560 __in size_t size);
561
562 __checkReturn efx_rc_t
563efx_mcdi_nvram_write(
564 __in efx_nic_t *enp,
565 __in uint32_t partn,
566 __in uint32_t offset,
567 __out_bcount(size) caddr_t data,
568 __in size_t size);
569
570 __checkReturn efx_rc_t
571efx_mcdi_nvram_update_finish(
572 __in efx_nic_t *enp,
573 __in uint32_t partn,
574 __in boolean_t reboot);
575
576#if EFSYS_OPT_DIAG
577
578 __checkReturn efx_rc_t
579efx_mcdi_nvram_test(
580 __in efx_nic_t *enp,
581 __in uint32_t partn);
582
583#endif /* EFSYS_OPT_DIAG */
584
585#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
586
587typedef struct efx_drv_cfg_s {
588 uint32_t edc_min_vi_count;
589 uint32_t edc_max_vi_count;
590
591 uint32_t edc_max_piobuf_count;
592 uint32_t edc_pio_alloc_size;
593} efx_drv_cfg_t;
594
595struct efx_nic_s {
596 uint32_t en_magic;
597 efx_family_t en_family;
598 uint32_t en_features;
599 efsys_identifier_t *en_esip;
600 efsys_lock_t *en_eslp;
601 efsys_bar_t *en_esbp;
602 unsigned int en_mod_flags;
603 unsigned int en_reset_flags;
604 efx_nic_cfg_t en_nic_cfg;
605 efx_drv_cfg_t en_drv_cfg;
606 efx_port_t en_port;
607 efx_mon_t en_mon;
608 efx_intr_t en_intr;
609 uint32_t en_ev_qcount;
610 uint32_t en_rx_qcount;
611 uint32_t en_tx_qcount;
612 efx_nic_ops_t *en_enop;
613 efx_ev_ops_t *en_eevop;
614 efx_tx_ops_t *en_etxop;
615 efx_rx_ops_t *en_erxop;
616#if EFSYS_OPT_FILTER
617 efx_filter_t en_filter;
618 efx_filter_ops_t *en_efop;
619#endif /* EFSYS_OPT_FILTER */
620 efx_pktfilter_ops_t *en_epfop;
621#if EFSYS_OPT_MCDI
622 efx_mcdi_t en_mcdi;
623#endif /* EFSYS_OPT_MCDI */
624#if EFSYS_OPT_NVRAM
625 efx_nvram_type_t en_nvram_locked;
626 efx_nvram_ops_t *en_envop;
627#endif /* EFSYS_OPT_NVRAM */
628#if EFSYS_OPT_VPD
629 efx_vpd_ops_t *en_evpdop;
630#endif /* EFSYS_OPT_VPD */
631#if EFSYS_OPT_RX_SCALE
632 efx_rx_hash_support_t en_hash_support;
633 efx_rx_scale_support_t en_rss_support;
634 uint32_t en_rss_context;
635#endif /* EFSYS_OPT_RX_SCALE */
636 uint32_t en_vport_id;
637 union {
638#if EFSYS_OPT_FALCON
639 struct {
640 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES];
641 falcon_i2c_t enu_fip;
642 boolean_t enu_i2c_locked;
643#if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
644 const uint8_t *enu_forced_cfg;
645#endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
646 uint8_t enu_mon_devid;
647#if EFSYS_OPT_PCIE_TUNE
648 unsigned int enu_nlanes;
649#endif /* EFSYS_OPT_PCIE_TUNE */
650 uint16_t enu_board_rev;
651 boolean_t enu_internal_sram;
652 uint8_t enu_sram_num_bank;
653 uint8_t enu_sram_bank_size;
654 } falcon;
655#endif /* EFSYS_OPT_FALCON */
656#if EFSYS_OPT_SIENA
657 struct {
658#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
659 unsigned int enu_partn_mask;
660#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
661#if EFSYS_OPT_VPD
662 caddr_t enu_svpd;
663 size_t enu_svpd_length;
664#endif /* EFSYS_OPT_VPD */
665 int enu_unused;
666 } siena;
667#endif /* EFSYS_OPT_SIENA */
668#if EFSYS_OPT_HUNTINGTON
669 struct {
670 int enu_vi_base;
671 int enu_vi_count;
672#if EFSYS_OPT_VPD
673 caddr_t enu_svpd;
674 size_t enu_svpd_length;
675#endif /* EFSYS_OPT_VPD */
676 efx_piobuf_handle_t enu_piobuf_handle[HUNT_PIOBUF_NBUFS];
677 uint32_t enu_piobuf_count;
678 uint32_t enu_pio_alloc_map[HUNT_PIOBUF_NBUFS];
679 uint32_t enu_pio_write_vi_base;
680 /* Memory BAR mapping regions */
681 uint32_t enu_uc_mem_map_offset;
682 size_t enu_uc_mem_map_size;
683 uint32_t enu_wc_mem_map_offset;
684 size_t enu_wc_mem_map_size;
685 } hunt;
686#endif /* EFSYS_OPT_HUNTINGTON */
687 } en_u;
688};
689
690
691#define EFX_NIC_MAGIC 0x02121996
692
693typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
694 const efx_ev_callbacks_t *, void *);
695
696typedef struct efx_evq_rxq_state_s {
697 unsigned int eers_rx_read_ptr;
698 unsigned int eers_rx_mask;
699} efx_evq_rxq_state_t;
700
701struct efx_evq_s {
702 uint32_t ee_magic;
703 efx_nic_t *ee_enp;
704 unsigned int ee_index;
705 unsigned int ee_mask;
706 efsys_mem_t *ee_esmp;
707#if EFSYS_OPT_QSTATS
708 uint32_t ee_stat[EV_NQSTATS];
709#endif /* EFSYS_OPT_QSTATS */
710
711 efx_ev_handler_t ee_rx;
712 efx_ev_handler_t ee_tx;
713 efx_ev_handler_t ee_driver;
714 efx_ev_handler_t ee_global;
715 efx_ev_handler_t ee_drv_gen;
716#if EFSYS_OPT_MCDI
717 efx_ev_handler_t ee_mcdi;
718#endif /* EFSYS_OPT_MCDI */
719
720 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
721};
722
723#define EFX_EVQ_MAGIC 0x08081997
724
725#define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
726#define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
727
728struct efx_rxq_s {
729 uint32_t er_magic;
730 efx_nic_t *er_enp;
731 efx_evq_t *er_eep;
732 unsigned int er_index;
733 unsigned int er_label;
734 unsigned int er_mask;
735 efsys_mem_t *er_esmp;
736};
737
738#define EFX_RXQ_MAGIC 0x15022005
739
740struct efx_txq_s {
741 uint32_t et_magic;
742 efx_nic_t *et_enp;
743 unsigned int et_index;
744 unsigned int et_mask;
745 efsys_mem_t *et_esmp;
746#if EFSYS_OPT_HUNTINGTON
747 uint32_t et_pio_bufnum;
748 uint32_t et_pio_blknum;
749 uint32_t et_pio_write_offset;
750 uint32_t et_pio_offset;
751 size_t et_pio_size;
752#endif
753#if EFSYS_OPT_QSTATS
754 uint32_t et_stat[TX_NQSTATS];
755#endif /* EFSYS_OPT_QSTATS */
756};
757
758#define EFX_TXQ_MAGIC 0x05092005
759
760#define EFX_MAC_ADDR_COPY(_dst, _src) \
761 do { \
762 (_dst)[0] = (_src)[0]; \
763 (_dst)[1] = (_src)[1]; \
764 (_dst)[2] = (_src)[2]; \
765 (_dst)[3] = (_src)[3]; \
766 (_dst)[4] = (_src)[4]; \
767 (_dst)[5] = (_src)[5]; \
768 _NOTE(CONSTANTCONDITION) \
769 } while (B_FALSE)
770
771#define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
772 do { \
773 uint16_t *_d = (uint16_t *)(_dst); \
774 _d[0] = 0xffff; \
775 _d[1] = 0xffff; \
776 _d[2] = 0xffff; \
777 _NOTE(CONSTANTCONDITION) \
778 } while (B_FALSE)
779
780#if EFSYS_OPT_CHECK_REG
781#define EFX_CHECK_REG(_enp, _reg) \
782 do { \
783 const char *name = #_reg; \
784 char min = name[4]; \
785 char max = name[5]; \
786 char rev; \
787 \
788 switch ((_enp)->en_family) { \
789 case EFX_FAMILY_FALCON: \
790 rev = 'B'; \
791 break; \
792 \
793 case EFX_FAMILY_SIENA: \
794 rev = 'C'; \
795 break; \
796 \
797 case EFX_FAMILY_HUNTINGTON: \
798 rev = 'D'; \
799 break; \
800 \
801 default: \
802 rev = '?'; \
803 break; \
804 } \
805 \
806 EFSYS_ASSERT3S(rev, >=, min); \
807 EFSYS_ASSERT3S(rev, <=, max); \
808 \
809 _NOTE(CONSTANTCONDITION) \
810 } while (B_FALSE)
811#else
812#define EFX_CHECK_REG(_enp, _reg) do { \
813 _NOTE(CONSTANTCONDITION) \
814 } while(B_FALSE)
815#endif
816
817#define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
818 do { \
819 EFX_CHECK_REG((_enp), (_reg)); \
820 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
821 (_edp), (_lock)); \
822 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
823 uint32_t, _reg ## _OFST, \
824 uint32_t, (_edp)->ed_u32[0]); \
825 _NOTE(CONSTANTCONDITION) \
826 } while (B_FALSE)
827
828#define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
829 do { \
830 EFX_CHECK_REG((_enp), (_reg)); \
831 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
832 uint32_t, _reg ## _OFST, \
833 uint32_t, (_edp)->ed_u32[0]); \
834 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
835 (_edp), (_lock)); \
836 _NOTE(CONSTANTCONDITION) \
837 } while (B_FALSE)
838
839#define EFX_BAR_READQ(_enp, _reg, _eqp) \
840 do { \
841 EFX_CHECK_REG((_enp), (_reg)); \
842 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
843 (_eqp)); \
844 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
845 uint32_t, _reg ## _OFST, \
846 uint32_t, (_eqp)->eq_u32[1], \
847 uint32_t, (_eqp)->eq_u32[0]); \
848 _NOTE(CONSTANTCONDITION) \
849 } while (B_FALSE)
850
851#define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
852 do { \
853 EFX_CHECK_REG((_enp), (_reg)); \
854 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
855 uint32_t, _reg ## _OFST, \
856 uint32_t, (_eqp)->eq_u32[1], \
857 uint32_t, (_eqp)->eq_u32[0]); \
858 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
859 (_eqp)); \
860 _NOTE(CONSTANTCONDITION) \
861 } while (B_FALSE)
862
863#define EFX_BAR_READO(_enp, _reg, _eop) \
864 do { \
865 EFX_CHECK_REG((_enp), (_reg)); \
866 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
867 (_eop), B_TRUE); \
868 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
869 uint32_t, _reg ## _OFST, \
870 uint32_t, (_eop)->eo_u32[3], \
871 uint32_t, (_eop)->eo_u32[2], \
872 uint32_t, (_eop)->eo_u32[1], \
873 uint32_t, (_eop)->eo_u32[0]); \
874 _NOTE(CONSTANTCONDITION) \
875 } while (B_FALSE)
876
877#define EFX_BAR_WRITEO(_enp, _reg, _eop) \
878 do { \
879 EFX_CHECK_REG((_enp), (_reg)); \
880 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
881 uint32_t, _reg ## _OFST, \
882 uint32_t, (_eop)->eo_u32[3], \
883 uint32_t, (_eop)->eo_u32[2], \
884 uint32_t, (_eop)->eo_u32[1], \
885 uint32_t, (_eop)->eo_u32[0]); \
886 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
887 (_eop), B_TRUE); \
888 _NOTE(CONSTANTCONDITION) \
889 } while (B_FALSE)
890
891#define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
892 do { \
893 EFX_CHECK_REG((_enp), (_reg)); \
894 EFSYS_BAR_READD((_enp)->en_esbp, \
895 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
896 (_edp), (_lock)); \
897 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
898 uint32_t, (_index), \
899 uint32_t, _reg ## _OFST, \
900 uint32_t, (_edp)->ed_u32[0]); \
901 _NOTE(CONSTANTCONDITION) \
902 } while (B_FALSE)
903
904#define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
905 do { \
906 EFX_CHECK_REG((_enp), (_reg)); \
907 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
908 uint32_t, (_index), \
909 uint32_t, _reg ## _OFST, \
910 uint32_t, (_edp)->ed_u32[0]); \
911 EFSYS_BAR_WRITED((_enp)->en_esbp, \
912 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
913 (_edp), (_lock)); \
914 _NOTE(CONSTANTCONDITION) \
915 } while (B_FALSE)
916
917#define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
918 do { \
919 EFX_CHECK_REG((_enp), (_reg)); \
920 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
921 uint32_t, (_index), \
922 uint32_t, _reg ## _OFST, \
923 uint32_t, (_edp)->ed_u32[0]); \
924 EFSYS_BAR_WRITED((_enp)->en_esbp, \
925 (_reg ## _OFST + \
926 (2 * sizeof (efx_dword_t)) + \
927 ((_index) * _reg ## _STEP)), \
928 (_edp), (_lock)); \
929 _NOTE(CONSTANTCONDITION) \
930 } while (B_FALSE)
931
932#define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
933 do { \
934 EFX_CHECK_REG((_enp), (_reg)); \
935 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
936 uint32_t, (_index), \
937 uint32_t, _reg ## _OFST, \
938 uint32_t, (_edp)->ed_u32[0]); \
939 EFSYS_BAR_WRITED((_enp)->en_esbp, \
940 (_reg ## _OFST + \
941 (3 * sizeof (efx_dword_t)) + \
942 ((_index) * _reg ## _STEP)), \
943 (_edp), (_lock)); \
944 _NOTE(CONSTANTCONDITION) \
945 } while (B_FALSE)
946
947#define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
948 do { \
949 EFX_CHECK_REG((_enp), (_reg)); \
950 EFSYS_BAR_READQ((_enp)->en_esbp, \
951 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
952 (_eqp)); \
953 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
954 uint32_t, (_index), \
955 uint32_t, _reg ## _OFST, \
956 uint32_t, (_eqp)->eq_u32[1], \
957 uint32_t, (_eqp)->eq_u32[0]); \
958 _NOTE(CONSTANTCONDITION) \
959 } while (B_FALSE)
960
961#define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
962 do { \
963 EFX_CHECK_REG((_enp), (_reg)); \
964 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
965 uint32_t, (_index), \
966 uint32_t, _reg ## _OFST, \
967 uint32_t, (_eqp)->eq_u32[1], \
968 uint32_t, (_eqp)->eq_u32[0]); \
969 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
970 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
971 (_eqp)); \
972 _NOTE(CONSTANTCONDITION) \
973 } while (B_FALSE)
974
975#define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
976 do { \
977 EFX_CHECK_REG((_enp), (_reg)); \
978 EFSYS_BAR_READO((_enp)->en_esbp, \
979 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
980 (_eop), (_lock)); \
981 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
982 uint32_t, (_index), \
983 uint32_t, _reg ## _OFST, \
984 uint32_t, (_eop)->eo_u32[3], \
985 uint32_t, (_eop)->eo_u32[2], \
986 uint32_t, (_eop)->eo_u32[1], \
987 uint32_t, (_eop)->eo_u32[0]); \
988 _NOTE(CONSTANTCONDITION) \
989 } while (B_FALSE)
990
991#define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
992 do { \
993 EFX_CHECK_REG((_enp), (_reg)); \
994 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
995 uint32_t, (_index), \
996 uint32_t, _reg ## _OFST, \
997 uint32_t, (_eop)->eo_u32[3], \
998 uint32_t, (_eop)->eo_u32[2], \
999 uint32_t, (_eop)->eo_u32[1], \
1000 uint32_t, (_eop)->eo_u32[0]); \
1001 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1002 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1003 (_eop), (_lock)); \
1004 _NOTE(CONSTANTCONDITION) \
1005 } while (B_FALSE)
1006
1007/*
1008 * Allow drivers to perform optimised 128-bit doorbell writes.
1009 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1010 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1011 * the need for locking in the host, and are the only ones known to be safe to
1012 * use 128-bites write with.
1013 */
1014#define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1015 do { \
1016 EFX_CHECK_REG((_enp), (_reg)); \
1017 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1018 const char *, \
1019 #_reg, \
1020 uint32_t, (_index), \
1021 uint32_t, _reg ## _OFST, \
1022 uint32_t, (_eop)->eo_u32[3], \
1023 uint32_t, (_eop)->eo_u32[2], \
1024 uint32_t, (_eop)->eo_u32[1], \
1025 uint32_t, (_eop)->eo_u32[0]); \
1026 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1027 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1028 (_eop)); \
1029 _NOTE(CONSTANTCONDITION) \
1030 } while (B_FALSE)
1031
1032#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1033 do { \
1034 unsigned int _new = (_wptr); \
1035 unsigned int _old = (_owptr); \
1036 \
1037 if ((_new) >= (_old)) \
1038 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1039 (_old) * sizeof (efx_desc_t), \
1040 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1041 else \
1042 /* \
1043 * It is cheaper to sync entire map than sync \
1044 * two parts especially when offset/size are \
1045 * ignored and entire map is synced in any case.\
1046 */ \
1047 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1048 0, \
1049 (_entries) * sizeof (efx_desc_t)); \
1050 _NOTE(CONSTANTCONDITION) \
1051 } while (B_FALSE)
1052
1053extern __checkReturn efx_rc_t
1054efx_nic_biu_test(
1055 __in efx_nic_t *enp);
1056
1057extern __checkReturn efx_rc_t
1058efx_mac_select(
1059 __in efx_nic_t *enp);
1060
1061extern void
1062efx_mac_multicast_hash_compute(
1063 __in_ecount(6*count) uint8_t const *addrs,
1064 __in int count,
1065 __out efx_oword_t *hash_low,
1066 __out efx_oword_t *hash_high);
1067
1068extern __checkReturn efx_rc_t
1069efx_phy_probe(
1070 __in efx_nic_t *enp);
1071
1072extern void
1073efx_phy_unprobe(
1074 __in efx_nic_t *enp);
1075
1076#if EFSYS_OPT_VPD
1077
1078/* VPD utility functions */
1079
1080extern __checkReturn efx_rc_t
1081efx_vpd_hunk_length(
1082 __in_bcount(size) caddr_t data,
1083 __in size_t size,
1084 __out size_t *lengthp);
1085
1086extern __checkReturn efx_rc_t
1087efx_vpd_hunk_verify(
1088 __in_bcount(size) caddr_t data,
1089 __in size_t size,
1090 __out_opt boolean_t *cksummedp);
1091
1092extern __checkReturn efx_rc_t
1093efx_vpd_hunk_reinit(
1094 __in_bcount(size) caddr_t data,
1095 __in size_t size,
1096 __in boolean_t wantpid);
1097
1098extern __checkReturn efx_rc_t
1099efx_vpd_hunk_get(
1100 __in_bcount(size) caddr_t data,
1101 __in size_t size,
1102 __in efx_vpd_tag_t tag,
1103 __in efx_vpd_keyword_t keyword,
1104 __out unsigned int *payloadp,
1105 __out uint8_t *paylenp);
1106
1107extern __checkReturn efx_rc_t
1108efx_vpd_hunk_next(
1109 __in_bcount(size) caddr_t data,
1110 __in size_t size,
1111 __out efx_vpd_tag_t *tagp,
1112 __out efx_vpd_keyword_t *keyword,
1113 __out_bcount_opt(*paylenp) unsigned int *payloadp,
1114 __out_opt uint8_t *paylenp,
1115 __inout unsigned int *contp);
1116
1117extern __checkReturn efx_rc_t
1118efx_vpd_hunk_set(
1119 __in_bcount(size) caddr_t data,
1120 __in size_t size,
1121 __in efx_vpd_value_t *evvp);
1122
1123#endif /* EFSYS_OPT_VPD */
1124
1125#if EFSYS_OPT_DIAG
1126
1127extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
1128
1129typedef struct efx_register_set_s {
1130 unsigned int address;
1131 unsigned int step;
1132 unsigned int rows;
1133 efx_oword_t mask;
1134} efx_register_set_t;
1135
1136extern __checkReturn efx_rc_t
1137efx_nic_test_registers(
1138 __in efx_nic_t *enp,
1139 __in efx_register_set_t *rsp,
1140 __in size_t count);
1141
1142extern __checkReturn efx_rc_t
1143efx_nic_test_tables(
1144 __in efx_nic_t *enp,
1145 __in efx_register_set_t *rsp,
1146 __in efx_pattern_type_t pattern,
1147 __in size_t count);
1148
1149#endif /* EFSYS_OPT_DIAG */
1150
1151#if EFSYS_OPT_MCDI
1152
1153extern __checkReturn efx_rc_t
1154efx_mcdi_set_workaround(
1155 __in efx_nic_t *enp,
1156 __in uint32_t type,
1157 __in boolean_t enabled,
1158 __out_opt uint32_t *flagsp);
1159
1160extern __checkReturn efx_rc_t
1161efx_mcdi_get_workarounds(
1162 __in efx_nic_t *enp,
1163 __out_opt uint32_t *implementedp,
1164 __out_opt uint32_t *enabledp);
1165
1166#endif /* EFSYS_OPT_MCDI */
1167
1168#ifdef __cplusplus
1169}
1170#endif
1171
1172#endif /* _SYS_EFX_IMPL_H */
| 467} efx_mcdi_ops_t;
468
469typedef struct efx_mcdi_s {
470 efx_mcdi_ops_t *em_emcop;
471 const efx_mcdi_transport_t *em_emtp;
472 efx_mcdi_iface_t em_emip;
473} efx_mcdi_t;
474
475#endif /* EFSYS_OPT_MCDI */
476
477#if EFSYS_OPT_NVRAM
478typedef struct efx_nvram_ops_s {
479#if EFSYS_OPT_DIAG
480 efx_rc_t (*envo_test)(efx_nic_t *);
481#endif /* EFSYS_OPT_DIAG */
482 efx_rc_t (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *);
483 efx_rc_t (*envo_get_version)(efx_nic_t *, efx_nvram_type_t,
484 uint32_t *, uint16_t *);
485 efx_rc_t (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *);
486 efx_rc_t (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t,
487 unsigned int, caddr_t, size_t);
488 efx_rc_t (*envo_erase)(efx_nic_t *, efx_nvram_type_t);
489 efx_rc_t (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t,
490 unsigned int, caddr_t, size_t);
491 void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t);
492 efx_rc_t (*envo_set_version)(efx_nic_t *, efx_nvram_type_t,
493 uint16_t *);
494
495} efx_nvram_ops_t;
496#endif /* EFSYS_OPT_NVRAM */
497
498#if EFSYS_OPT_VPD
499typedef struct efx_vpd_ops_s {
500 efx_rc_t (*evpdo_init)(efx_nic_t *);
501 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
502 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
503 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
504 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
505 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
506 efx_vpd_value_t *);
507 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
508 efx_vpd_value_t *);
509 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
510 efx_vpd_value_t *, unsigned int *);
511 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
512 void (*evpdo_fini)(efx_nic_t *);
513} efx_vpd_ops_t;
514#endif /* EFSYS_OPT_VPD */
515
516#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
517
518 __checkReturn efx_rc_t
519efx_mcdi_nvram_partitions(
520 __in efx_nic_t *enp,
521 __out_bcount(size) caddr_t data,
522 __in size_t size,
523 __out unsigned int *npartnp);
524
525 __checkReturn efx_rc_t
526efx_mcdi_nvram_metadata(
527 __in efx_nic_t *enp,
528 __in uint32_t partn,
529 __out uint32_t *subtypep,
530 __out_ecount(4) uint16_t version[4],
531 __out_bcount_opt(size) char *descp,
532 __in size_t size);
533
534 __checkReturn efx_rc_t
535efx_mcdi_nvram_info(
536 __in efx_nic_t *enp,
537 __in uint32_t partn,
538 __out_opt size_t *sizep,
539 __out_opt uint32_t *addressp,
540 __out_opt uint32_t *erase_sizep,
541 __out_opt uint32_t *write_sizep);
542
543 __checkReturn efx_rc_t
544efx_mcdi_nvram_update_start(
545 __in efx_nic_t *enp,
546 __in uint32_t partn);
547
548 __checkReturn efx_rc_t
549efx_mcdi_nvram_read(
550 __in efx_nic_t *enp,
551 __in uint32_t partn,
552 __in uint32_t offset,
553 __out_bcount(size) caddr_t data,
554 __in size_t size);
555
556 __checkReturn efx_rc_t
557efx_mcdi_nvram_erase(
558 __in efx_nic_t *enp,
559 __in uint32_t partn,
560 __in uint32_t offset,
561 __in size_t size);
562
563 __checkReturn efx_rc_t
564efx_mcdi_nvram_write(
565 __in efx_nic_t *enp,
566 __in uint32_t partn,
567 __in uint32_t offset,
568 __out_bcount(size) caddr_t data,
569 __in size_t size);
570
571 __checkReturn efx_rc_t
572efx_mcdi_nvram_update_finish(
573 __in efx_nic_t *enp,
574 __in uint32_t partn,
575 __in boolean_t reboot);
576
577#if EFSYS_OPT_DIAG
578
579 __checkReturn efx_rc_t
580efx_mcdi_nvram_test(
581 __in efx_nic_t *enp,
582 __in uint32_t partn);
583
584#endif /* EFSYS_OPT_DIAG */
585
586#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
587
588typedef struct efx_drv_cfg_s {
589 uint32_t edc_min_vi_count;
590 uint32_t edc_max_vi_count;
591
592 uint32_t edc_max_piobuf_count;
593 uint32_t edc_pio_alloc_size;
594} efx_drv_cfg_t;
595
596struct efx_nic_s {
597 uint32_t en_magic;
598 efx_family_t en_family;
599 uint32_t en_features;
600 efsys_identifier_t *en_esip;
601 efsys_lock_t *en_eslp;
602 efsys_bar_t *en_esbp;
603 unsigned int en_mod_flags;
604 unsigned int en_reset_flags;
605 efx_nic_cfg_t en_nic_cfg;
606 efx_drv_cfg_t en_drv_cfg;
607 efx_port_t en_port;
608 efx_mon_t en_mon;
609 efx_intr_t en_intr;
610 uint32_t en_ev_qcount;
611 uint32_t en_rx_qcount;
612 uint32_t en_tx_qcount;
613 efx_nic_ops_t *en_enop;
614 efx_ev_ops_t *en_eevop;
615 efx_tx_ops_t *en_etxop;
616 efx_rx_ops_t *en_erxop;
617#if EFSYS_OPT_FILTER
618 efx_filter_t en_filter;
619 efx_filter_ops_t *en_efop;
620#endif /* EFSYS_OPT_FILTER */
621 efx_pktfilter_ops_t *en_epfop;
622#if EFSYS_OPT_MCDI
623 efx_mcdi_t en_mcdi;
624#endif /* EFSYS_OPT_MCDI */
625#if EFSYS_OPT_NVRAM
626 efx_nvram_type_t en_nvram_locked;
627 efx_nvram_ops_t *en_envop;
628#endif /* EFSYS_OPT_NVRAM */
629#if EFSYS_OPT_VPD
630 efx_vpd_ops_t *en_evpdop;
631#endif /* EFSYS_OPT_VPD */
632#if EFSYS_OPT_RX_SCALE
633 efx_rx_hash_support_t en_hash_support;
634 efx_rx_scale_support_t en_rss_support;
635 uint32_t en_rss_context;
636#endif /* EFSYS_OPT_RX_SCALE */
637 uint32_t en_vport_id;
638 union {
639#if EFSYS_OPT_FALCON
640 struct {
641 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES];
642 falcon_i2c_t enu_fip;
643 boolean_t enu_i2c_locked;
644#if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
645 const uint8_t *enu_forced_cfg;
646#endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
647 uint8_t enu_mon_devid;
648#if EFSYS_OPT_PCIE_TUNE
649 unsigned int enu_nlanes;
650#endif /* EFSYS_OPT_PCIE_TUNE */
651 uint16_t enu_board_rev;
652 boolean_t enu_internal_sram;
653 uint8_t enu_sram_num_bank;
654 uint8_t enu_sram_bank_size;
655 } falcon;
656#endif /* EFSYS_OPT_FALCON */
657#if EFSYS_OPT_SIENA
658 struct {
659#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
660 unsigned int enu_partn_mask;
661#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
662#if EFSYS_OPT_VPD
663 caddr_t enu_svpd;
664 size_t enu_svpd_length;
665#endif /* EFSYS_OPT_VPD */
666 int enu_unused;
667 } siena;
668#endif /* EFSYS_OPT_SIENA */
669#if EFSYS_OPT_HUNTINGTON
670 struct {
671 int enu_vi_base;
672 int enu_vi_count;
673#if EFSYS_OPT_VPD
674 caddr_t enu_svpd;
675 size_t enu_svpd_length;
676#endif /* EFSYS_OPT_VPD */
677 efx_piobuf_handle_t enu_piobuf_handle[HUNT_PIOBUF_NBUFS];
678 uint32_t enu_piobuf_count;
679 uint32_t enu_pio_alloc_map[HUNT_PIOBUF_NBUFS];
680 uint32_t enu_pio_write_vi_base;
681 /* Memory BAR mapping regions */
682 uint32_t enu_uc_mem_map_offset;
683 size_t enu_uc_mem_map_size;
684 uint32_t enu_wc_mem_map_offset;
685 size_t enu_wc_mem_map_size;
686 } hunt;
687#endif /* EFSYS_OPT_HUNTINGTON */
688 } en_u;
689};
690
691
692#define EFX_NIC_MAGIC 0x02121996
693
694typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
695 const efx_ev_callbacks_t *, void *);
696
697typedef struct efx_evq_rxq_state_s {
698 unsigned int eers_rx_read_ptr;
699 unsigned int eers_rx_mask;
700} efx_evq_rxq_state_t;
701
702struct efx_evq_s {
703 uint32_t ee_magic;
704 efx_nic_t *ee_enp;
705 unsigned int ee_index;
706 unsigned int ee_mask;
707 efsys_mem_t *ee_esmp;
708#if EFSYS_OPT_QSTATS
709 uint32_t ee_stat[EV_NQSTATS];
710#endif /* EFSYS_OPT_QSTATS */
711
712 efx_ev_handler_t ee_rx;
713 efx_ev_handler_t ee_tx;
714 efx_ev_handler_t ee_driver;
715 efx_ev_handler_t ee_global;
716 efx_ev_handler_t ee_drv_gen;
717#if EFSYS_OPT_MCDI
718 efx_ev_handler_t ee_mcdi;
719#endif /* EFSYS_OPT_MCDI */
720
721 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
722};
723
724#define EFX_EVQ_MAGIC 0x08081997
725
726#define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
727#define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
728
729struct efx_rxq_s {
730 uint32_t er_magic;
731 efx_nic_t *er_enp;
732 efx_evq_t *er_eep;
733 unsigned int er_index;
734 unsigned int er_label;
735 unsigned int er_mask;
736 efsys_mem_t *er_esmp;
737};
738
739#define EFX_RXQ_MAGIC 0x15022005
740
741struct efx_txq_s {
742 uint32_t et_magic;
743 efx_nic_t *et_enp;
744 unsigned int et_index;
745 unsigned int et_mask;
746 efsys_mem_t *et_esmp;
747#if EFSYS_OPT_HUNTINGTON
748 uint32_t et_pio_bufnum;
749 uint32_t et_pio_blknum;
750 uint32_t et_pio_write_offset;
751 uint32_t et_pio_offset;
752 size_t et_pio_size;
753#endif
754#if EFSYS_OPT_QSTATS
755 uint32_t et_stat[TX_NQSTATS];
756#endif /* EFSYS_OPT_QSTATS */
757};
758
759#define EFX_TXQ_MAGIC 0x05092005
760
761#define EFX_MAC_ADDR_COPY(_dst, _src) \
762 do { \
763 (_dst)[0] = (_src)[0]; \
764 (_dst)[1] = (_src)[1]; \
765 (_dst)[2] = (_src)[2]; \
766 (_dst)[3] = (_src)[3]; \
767 (_dst)[4] = (_src)[4]; \
768 (_dst)[5] = (_src)[5]; \
769 _NOTE(CONSTANTCONDITION) \
770 } while (B_FALSE)
771
772#define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
773 do { \
774 uint16_t *_d = (uint16_t *)(_dst); \
775 _d[0] = 0xffff; \
776 _d[1] = 0xffff; \
777 _d[2] = 0xffff; \
778 _NOTE(CONSTANTCONDITION) \
779 } while (B_FALSE)
780
781#if EFSYS_OPT_CHECK_REG
782#define EFX_CHECK_REG(_enp, _reg) \
783 do { \
784 const char *name = #_reg; \
785 char min = name[4]; \
786 char max = name[5]; \
787 char rev; \
788 \
789 switch ((_enp)->en_family) { \
790 case EFX_FAMILY_FALCON: \
791 rev = 'B'; \
792 break; \
793 \
794 case EFX_FAMILY_SIENA: \
795 rev = 'C'; \
796 break; \
797 \
798 case EFX_FAMILY_HUNTINGTON: \
799 rev = 'D'; \
800 break; \
801 \
802 default: \
803 rev = '?'; \
804 break; \
805 } \
806 \
807 EFSYS_ASSERT3S(rev, >=, min); \
808 EFSYS_ASSERT3S(rev, <=, max); \
809 \
810 _NOTE(CONSTANTCONDITION) \
811 } while (B_FALSE)
812#else
813#define EFX_CHECK_REG(_enp, _reg) do { \
814 _NOTE(CONSTANTCONDITION) \
815 } while(B_FALSE)
816#endif
817
818#define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
819 do { \
820 EFX_CHECK_REG((_enp), (_reg)); \
821 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
822 (_edp), (_lock)); \
823 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
824 uint32_t, _reg ## _OFST, \
825 uint32_t, (_edp)->ed_u32[0]); \
826 _NOTE(CONSTANTCONDITION) \
827 } while (B_FALSE)
828
829#define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
830 do { \
831 EFX_CHECK_REG((_enp), (_reg)); \
832 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
833 uint32_t, _reg ## _OFST, \
834 uint32_t, (_edp)->ed_u32[0]); \
835 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
836 (_edp), (_lock)); \
837 _NOTE(CONSTANTCONDITION) \
838 } while (B_FALSE)
839
840#define EFX_BAR_READQ(_enp, _reg, _eqp) \
841 do { \
842 EFX_CHECK_REG((_enp), (_reg)); \
843 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
844 (_eqp)); \
845 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
846 uint32_t, _reg ## _OFST, \
847 uint32_t, (_eqp)->eq_u32[1], \
848 uint32_t, (_eqp)->eq_u32[0]); \
849 _NOTE(CONSTANTCONDITION) \
850 } while (B_FALSE)
851
852#define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
853 do { \
854 EFX_CHECK_REG((_enp), (_reg)); \
855 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
856 uint32_t, _reg ## _OFST, \
857 uint32_t, (_eqp)->eq_u32[1], \
858 uint32_t, (_eqp)->eq_u32[0]); \
859 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
860 (_eqp)); \
861 _NOTE(CONSTANTCONDITION) \
862 } while (B_FALSE)
863
864#define EFX_BAR_READO(_enp, _reg, _eop) \
865 do { \
866 EFX_CHECK_REG((_enp), (_reg)); \
867 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
868 (_eop), B_TRUE); \
869 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
870 uint32_t, _reg ## _OFST, \
871 uint32_t, (_eop)->eo_u32[3], \
872 uint32_t, (_eop)->eo_u32[2], \
873 uint32_t, (_eop)->eo_u32[1], \
874 uint32_t, (_eop)->eo_u32[0]); \
875 _NOTE(CONSTANTCONDITION) \
876 } while (B_FALSE)
877
878#define EFX_BAR_WRITEO(_enp, _reg, _eop) \
879 do { \
880 EFX_CHECK_REG((_enp), (_reg)); \
881 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
882 uint32_t, _reg ## _OFST, \
883 uint32_t, (_eop)->eo_u32[3], \
884 uint32_t, (_eop)->eo_u32[2], \
885 uint32_t, (_eop)->eo_u32[1], \
886 uint32_t, (_eop)->eo_u32[0]); \
887 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
888 (_eop), B_TRUE); \
889 _NOTE(CONSTANTCONDITION) \
890 } while (B_FALSE)
891
892#define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
893 do { \
894 EFX_CHECK_REG((_enp), (_reg)); \
895 EFSYS_BAR_READD((_enp)->en_esbp, \
896 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
897 (_edp), (_lock)); \
898 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
899 uint32_t, (_index), \
900 uint32_t, _reg ## _OFST, \
901 uint32_t, (_edp)->ed_u32[0]); \
902 _NOTE(CONSTANTCONDITION) \
903 } while (B_FALSE)
904
905#define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
906 do { \
907 EFX_CHECK_REG((_enp), (_reg)); \
908 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
909 uint32_t, (_index), \
910 uint32_t, _reg ## _OFST, \
911 uint32_t, (_edp)->ed_u32[0]); \
912 EFSYS_BAR_WRITED((_enp)->en_esbp, \
913 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
914 (_edp), (_lock)); \
915 _NOTE(CONSTANTCONDITION) \
916 } while (B_FALSE)
917
918#define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
919 do { \
920 EFX_CHECK_REG((_enp), (_reg)); \
921 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
922 uint32_t, (_index), \
923 uint32_t, _reg ## _OFST, \
924 uint32_t, (_edp)->ed_u32[0]); \
925 EFSYS_BAR_WRITED((_enp)->en_esbp, \
926 (_reg ## _OFST + \
927 (2 * sizeof (efx_dword_t)) + \
928 ((_index) * _reg ## _STEP)), \
929 (_edp), (_lock)); \
930 _NOTE(CONSTANTCONDITION) \
931 } while (B_FALSE)
932
933#define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
934 do { \
935 EFX_CHECK_REG((_enp), (_reg)); \
936 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
937 uint32_t, (_index), \
938 uint32_t, _reg ## _OFST, \
939 uint32_t, (_edp)->ed_u32[0]); \
940 EFSYS_BAR_WRITED((_enp)->en_esbp, \
941 (_reg ## _OFST + \
942 (3 * sizeof (efx_dword_t)) + \
943 ((_index) * _reg ## _STEP)), \
944 (_edp), (_lock)); \
945 _NOTE(CONSTANTCONDITION) \
946 } while (B_FALSE)
947
948#define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
949 do { \
950 EFX_CHECK_REG((_enp), (_reg)); \
951 EFSYS_BAR_READQ((_enp)->en_esbp, \
952 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
953 (_eqp)); \
954 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
955 uint32_t, (_index), \
956 uint32_t, _reg ## _OFST, \
957 uint32_t, (_eqp)->eq_u32[1], \
958 uint32_t, (_eqp)->eq_u32[0]); \
959 _NOTE(CONSTANTCONDITION) \
960 } while (B_FALSE)
961
962#define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
963 do { \
964 EFX_CHECK_REG((_enp), (_reg)); \
965 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
966 uint32_t, (_index), \
967 uint32_t, _reg ## _OFST, \
968 uint32_t, (_eqp)->eq_u32[1], \
969 uint32_t, (_eqp)->eq_u32[0]); \
970 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
971 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
972 (_eqp)); \
973 _NOTE(CONSTANTCONDITION) \
974 } while (B_FALSE)
975
976#define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
977 do { \
978 EFX_CHECK_REG((_enp), (_reg)); \
979 EFSYS_BAR_READO((_enp)->en_esbp, \
980 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
981 (_eop), (_lock)); \
982 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
983 uint32_t, (_index), \
984 uint32_t, _reg ## _OFST, \
985 uint32_t, (_eop)->eo_u32[3], \
986 uint32_t, (_eop)->eo_u32[2], \
987 uint32_t, (_eop)->eo_u32[1], \
988 uint32_t, (_eop)->eo_u32[0]); \
989 _NOTE(CONSTANTCONDITION) \
990 } while (B_FALSE)
991
992#define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
993 do { \
994 EFX_CHECK_REG((_enp), (_reg)); \
995 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
996 uint32_t, (_index), \
997 uint32_t, _reg ## _OFST, \
998 uint32_t, (_eop)->eo_u32[3], \
999 uint32_t, (_eop)->eo_u32[2], \
1000 uint32_t, (_eop)->eo_u32[1], \
1001 uint32_t, (_eop)->eo_u32[0]); \
1002 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1003 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1004 (_eop), (_lock)); \
1005 _NOTE(CONSTANTCONDITION) \
1006 } while (B_FALSE)
1007
1008/*
1009 * Allow drivers to perform optimised 128-bit doorbell writes.
1010 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1011 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1012 * the need for locking in the host, and are the only ones known to be safe to
1013 * use 128-bites write with.
1014 */
1015#define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1016 do { \
1017 EFX_CHECK_REG((_enp), (_reg)); \
1018 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1019 const char *, \
1020 #_reg, \
1021 uint32_t, (_index), \
1022 uint32_t, _reg ## _OFST, \
1023 uint32_t, (_eop)->eo_u32[3], \
1024 uint32_t, (_eop)->eo_u32[2], \
1025 uint32_t, (_eop)->eo_u32[1], \
1026 uint32_t, (_eop)->eo_u32[0]); \
1027 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1028 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1029 (_eop)); \
1030 _NOTE(CONSTANTCONDITION) \
1031 } while (B_FALSE)
1032
1033#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1034 do { \
1035 unsigned int _new = (_wptr); \
1036 unsigned int _old = (_owptr); \
1037 \
1038 if ((_new) >= (_old)) \
1039 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1040 (_old) * sizeof (efx_desc_t), \
1041 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1042 else \
1043 /* \
1044 * It is cheaper to sync entire map than sync \
1045 * two parts especially when offset/size are \
1046 * ignored and entire map is synced in any case.\
1047 */ \
1048 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1049 0, \
1050 (_entries) * sizeof (efx_desc_t)); \
1051 _NOTE(CONSTANTCONDITION) \
1052 } while (B_FALSE)
1053
1054extern __checkReturn efx_rc_t
1055efx_nic_biu_test(
1056 __in efx_nic_t *enp);
1057
1058extern __checkReturn efx_rc_t
1059efx_mac_select(
1060 __in efx_nic_t *enp);
1061
1062extern void
1063efx_mac_multicast_hash_compute(
1064 __in_ecount(6*count) uint8_t const *addrs,
1065 __in int count,
1066 __out efx_oword_t *hash_low,
1067 __out efx_oword_t *hash_high);
1068
1069extern __checkReturn efx_rc_t
1070efx_phy_probe(
1071 __in efx_nic_t *enp);
1072
1073extern void
1074efx_phy_unprobe(
1075 __in efx_nic_t *enp);
1076
1077#if EFSYS_OPT_VPD
1078
1079/* VPD utility functions */
1080
1081extern __checkReturn efx_rc_t
1082efx_vpd_hunk_length(
1083 __in_bcount(size) caddr_t data,
1084 __in size_t size,
1085 __out size_t *lengthp);
1086
1087extern __checkReturn efx_rc_t
1088efx_vpd_hunk_verify(
1089 __in_bcount(size) caddr_t data,
1090 __in size_t size,
1091 __out_opt boolean_t *cksummedp);
1092
1093extern __checkReturn efx_rc_t
1094efx_vpd_hunk_reinit(
1095 __in_bcount(size) caddr_t data,
1096 __in size_t size,
1097 __in boolean_t wantpid);
1098
1099extern __checkReturn efx_rc_t
1100efx_vpd_hunk_get(
1101 __in_bcount(size) caddr_t data,
1102 __in size_t size,
1103 __in efx_vpd_tag_t tag,
1104 __in efx_vpd_keyword_t keyword,
1105 __out unsigned int *payloadp,
1106 __out uint8_t *paylenp);
1107
1108extern __checkReturn efx_rc_t
1109efx_vpd_hunk_next(
1110 __in_bcount(size) caddr_t data,
1111 __in size_t size,
1112 __out efx_vpd_tag_t *tagp,
1113 __out efx_vpd_keyword_t *keyword,
1114 __out_bcount_opt(*paylenp) unsigned int *payloadp,
1115 __out_opt uint8_t *paylenp,
1116 __inout unsigned int *contp);
1117
1118extern __checkReturn efx_rc_t
1119efx_vpd_hunk_set(
1120 __in_bcount(size) caddr_t data,
1121 __in size_t size,
1122 __in efx_vpd_value_t *evvp);
1123
1124#endif /* EFSYS_OPT_VPD */
1125
1126#if EFSYS_OPT_DIAG
1127
1128extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
1129
1130typedef struct efx_register_set_s {
1131 unsigned int address;
1132 unsigned int step;
1133 unsigned int rows;
1134 efx_oword_t mask;
1135} efx_register_set_t;
1136
1137extern __checkReturn efx_rc_t
1138efx_nic_test_registers(
1139 __in efx_nic_t *enp,
1140 __in efx_register_set_t *rsp,
1141 __in size_t count);
1142
1143extern __checkReturn efx_rc_t
1144efx_nic_test_tables(
1145 __in efx_nic_t *enp,
1146 __in efx_register_set_t *rsp,
1147 __in efx_pattern_type_t pattern,
1148 __in size_t count);
1149
1150#endif /* EFSYS_OPT_DIAG */
1151
1152#if EFSYS_OPT_MCDI
1153
1154extern __checkReturn efx_rc_t
1155efx_mcdi_set_workaround(
1156 __in efx_nic_t *enp,
1157 __in uint32_t type,
1158 __in boolean_t enabled,
1159 __out_opt uint32_t *flagsp);
1160
1161extern __checkReturn efx_rc_t
1162efx_mcdi_get_workarounds(
1163 __in efx_nic_t *enp,
1164 __out_opt uint32_t *implementedp,
1165 __out_opt uint32_t *enabledp);
1166
1167#endif /* EFSYS_OPT_MCDI */
1168
1169#ifdef __cplusplus
1170}
1171#endif
1172
1173#endif /* _SYS_EFX_IMPL_H */
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