31 */ 32 33#ifndef _SYS_EFX_IMPL_H 34#define _SYS_EFX_IMPL_H 35 36#include "efsys.h" 37#include "efx.h" 38#include "efx_regs.h" 39#include "efx_regs_ef10.h" 40 41/* FIXME: Add definition for driver generated software events */ 42#ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 43#define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 44#endif 45 46#include "efx_check.h" 47 48 49#if EFSYS_OPT_FALCON 50#include "falcon_impl.h" 51#endif /* EFSYS_OPT_FALCON */ 52 53#if EFSYS_OPT_SIENA 54#include "siena_impl.h" 55#endif /* EFSYS_OPT_SIENA */ 56 57#if EFSYS_OPT_HUNTINGTON 58#include "hunt_impl.h" 59#endif /* EFSYS_OPT_HUNTINGTON */ 60 61#ifdef __cplusplus 62extern "C" { 63#endif 64 65#define EFX_MOD_MCDI 0x00000001 66#define EFX_MOD_PROBE 0x00000002 67#define EFX_MOD_NVRAM 0x00000004 68#define EFX_MOD_VPD 0x00000008 69#define EFX_MOD_NIC 0x00000010 70#define EFX_MOD_INTR 0x00000020 71#define EFX_MOD_EV 0x00000040 72#define EFX_MOD_RX 0x00000080 73#define EFX_MOD_TX 0x00000100 74#define EFX_MOD_PORT 0x00000200 75#define EFX_MOD_MON 0x00000400 76#define EFX_MOD_WOL 0x00000800 77#define EFX_MOD_FILTER 0x00001000 78#define EFX_MOD_PKTFILTER 0x00002000 79 80#define EFX_RESET_MAC 0x00000001 81#define EFX_RESET_PHY 0x00000002 82#define EFX_RESET_RXQ_ERR 0x00000004 83#define EFX_RESET_TXQ_ERR 0x00000008 84 85typedef enum efx_mac_type_e { 86 EFX_MAC_INVALID = 0, 87 EFX_MAC_FALCON_GMAC, 88 EFX_MAC_FALCON_XMAC, 89 EFX_MAC_SIENA, 90 EFX_MAC_HUNTINGTON, 91 EFX_MAC_NTYPES 92} efx_mac_type_t; 93 94typedef struct efx_ev_ops_s { 95 efx_rc_t (*eevo_init)(efx_nic_t *); 96 void (*eevo_fini)(efx_nic_t *); 97 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 98 efsys_mem_t *, size_t, uint32_t, 99 efx_evq_t *); 100 void (*eevo_qdestroy)(efx_evq_t *); 101 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 102 void (*eevo_qpost)(efx_evq_t *, uint16_t); 103 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 104#if EFSYS_OPT_QSTATS 105 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 106#endif 107} efx_ev_ops_t; 108 109typedef struct efx_tx_ops_s { 110 efx_rc_t (*etxo_init)(efx_nic_t *); 111 void (*etxo_fini)(efx_nic_t *); 112 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 113 unsigned int, unsigned int, 114 efsys_mem_t *, size_t, 115 uint32_t, uint16_t, 116 efx_evq_t *, efx_txq_t *, 117 unsigned int *); 118 void (*etxo_qdestroy)(efx_txq_t *); 119 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 120 unsigned int, unsigned int, 121 unsigned int *); 122 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 123 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 124 efx_rc_t (*etxo_qflush)(efx_txq_t *); 125 void (*etxo_qenable)(efx_txq_t *); 126 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 127 void (*etxo_qpio_disable)(efx_txq_t *); 128 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t, 129 size_t); 130 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 131 unsigned int *); 132 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 133 unsigned int, unsigned int, 134 unsigned int *); 135 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 136 size_t, boolean_t, 137 efx_desc_t *); 138 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 139 uint32_t, uint8_t, 140 efx_desc_t *); 141 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 142 efx_desc_t *); 143#if EFSYS_OPT_QSTATS 144 void (*etxo_qstats_update)(efx_txq_t *, 145 efsys_stat_t *); 146#endif 147} efx_tx_ops_t; 148 149typedef struct efx_rx_ops_s { 150 efx_rc_t (*erxo_init)(efx_nic_t *); 151 void (*erxo_fini)(efx_nic_t *); 152#if EFSYS_OPT_RX_HDR_SPLIT 153 efx_rc_t (*erxo_hdr_split_enable)(efx_nic_t *, unsigned int, 154 unsigned int); 155#endif 156#if EFSYS_OPT_RX_SCATTER 157 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 158#endif 159#if EFSYS_OPT_RX_SCALE 160 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t, 161 efx_rx_hash_type_t, boolean_t); 162 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t); 163 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *, 164 size_t); 165#endif 166 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 167 unsigned int, unsigned int, 168 unsigned int); 169 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 170 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 171 void (*erxo_qenable)(efx_rxq_t *); 172 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 173 unsigned int, efx_rxq_type_t, 174 efsys_mem_t *, size_t, uint32_t, 175 efx_evq_t *, efx_rxq_t *); 176 void (*erxo_qdestroy)(efx_rxq_t *); 177} efx_rx_ops_t; 178 179typedef struct efx_mac_ops_s { 180 efx_rc_t (*emo_reset)(efx_nic_t *); /* optional */ 181 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 182 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 183 efx_rc_t (*emo_addr_set)(efx_nic_t *); 184 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 185 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 186 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 187 efx_rxq_t *, boolean_t); 188 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 189#if EFSYS_OPT_LOOPBACK 190 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 191 efx_loopback_type_t); 192#endif /* EFSYS_OPT_LOOPBACK */ 193#if EFSYS_OPT_MAC_STATS 194 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 195 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 196 uint16_t, boolean_t); 197 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 198 efsys_stat_t *, uint32_t *); 199#endif /* EFSYS_OPT_MAC_STATS */ 200} efx_mac_ops_t; 201 202typedef struct efx_phy_ops_s { 203 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 204 efx_rc_t (*epo_reset)(efx_nic_t *); 205 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 206 efx_rc_t (*epo_verify)(efx_nic_t *); 207 efx_rc_t (*epo_uplink_check)(efx_nic_t *, 208 boolean_t *); /* optional */ 209 efx_rc_t (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *, 210 unsigned int *, uint32_t *); 211 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 212#if EFSYS_OPT_PHY_STATS 213 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 214 uint32_t *); 215#endif /* EFSYS_OPT_PHY_STATS */ 216#if EFSYS_OPT_PHY_PROPS 217#if EFSYS_OPT_NAMES 218 const char *(*epo_prop_name)(efx_nic_t *, unsigned int); 219#endif /* EFSYS_OPT_PHY_PROPS */ 220 efx_rc_t (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t, 221 uint32_t *); 222 efx_rc_t (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t); 223#endif /* EFSYS_OPT_PHY_PROPS */ 224#if EFSYS_OPT_BIST 225 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 226 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 227 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 228 efx_bist_result_t *, uint32_t *, 229 unsigned long *, size_t); 230 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 231#endif /* EFSYS_OPT_BIST */ 232} efx_phy_ops_t; 233 234#if EFSYS_OPT_FILTER 235typedef struct efx_filter_ops_s { 236 efx_rc_t (*efo_init)(efx_nic_t *); 237 void (*efo_fini)(efx_nic_t *); 238 efx_rc_t (*efo_restore)(efx_nic_t *); 239 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 240 boolean_t may_replace); 241 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 242 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *); 243 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 244 boolean_t, boolean_t, boolean_t, 245 uint8_t const *, int); 246} efx_filter_ops_t; 247 248extern __checkReturn efx_rc_t 249efx_filter_reconfigure( 250 __in efx_nic_t *enp, 251 __in_ecount(6) uint8_t const *mac_addr, 252 __in boolean_t all_unicst, 253 __in boolean_t mulcst, 254 __in boolean_t all_mulcst, 255 __in boolean_t brdcst, 256 __in_ecount(6*count) uint8_t const *addrs, 257 __in int count); 258 259#endif /* EFSYS_OPT_FILTER */ 260 261typedef struct efx_pktfilter_ops_s { 262 efx_rc_t (*epfo_set)(efx_nic_t *, 263 boolean_t unicst, 264 boolean_t brdcast); 265#if EFSYS_OPT_MCAST_FILTER_LIST 266 efx_rc_t (*epfo_mcast_list_set)(efx_nic_t *, 267 uint8_t const *addrs, int count); 268#endif /* EFSYS_OPT_MCAST_FILTER_LIST */ 269 efx_rc_t (*epfo_mcast_all)(efx_nic_t *); 270} efx_pktfilter_ops_t; 271 272typedef struct efx_port_s { 273 efx_mac_type_t ep_mac_type; 274 uint32_t ep_phy_type; 275 uint8_t ep_port; 276 uint32_t ep_mac_pdu; 277 uint8_t ep_mac_addr[6]; 278 efx_link_mode_t ep_link_mode; 279 boolean_t ep_all_unicst; 280 boolean_t ep_mulcst; 281 boolean_t ep_all_mulcst; 282 boolean_t ep_brdcst; 283 unsigned int ep_fcntl; 284 boolean_t ep_fcntl_autoneg; 285 efx_oword_t ep_multicst_hash[2]; 286 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 287 EFX_MAC_MULTICAST_LIST_MAX]; 288 uint32_t ep_mulcst_addr_count; 289#if EFSYS_OPT_LOOPBACK 290 efx_loopback_type_t ep_loopback_type; 291 efx_link_mode_t ep_loopback_link_mode; 292#endif /* EFSYS_OPT_LOOPBACK */ 293#if EFSYS_OPT_PHY_FLAGS 294 uint32_t ep_phy_flags; 295#endif /* EFSYS_OPT_PHY_FLAGS */ 296#if EFSYS_OPT_PHY_LED_CONTROL 297 efx_phy_led_mode_t ep_phy_led_mode; 298#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 299 efx_phy_media_type_t ep_fixed_port_type; 300 efx_phy_media_type_t ep_module_type; 301 uint32_t ep_adv_cap_mask; 302 uint32_t ep_lp_cap_mask; 303 uint32_t ep_default_adv_cap_mask; 304 uint32_t ep_phy_cap_mask; 305#if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C 306 union { 307 struct { 308 unsigned int bug10934_count; 309 } ep_txc43128; 310 struct { 311 unsigned int bug17190_count; 312 } ep_qt2025c; 313 }; 314#endif 315 boolean_t ep_mac_poll_needed; /* falcon only */ 316 boolean_t ep_mac_up; /* falcon only */ 317 uint32_t ep_fwver; /* falcon only */ 318 boolean_t ep_mac_drain; 319 boolean_t ep_mac_stats_pending; 320#if EFSYS_OPT_BIST 321 efx_bist_type_t ep_current_bist; 322#endif 323 efx_mac_ops_t *ep_emop; 324 efx_phy_ops_t *ep_epop; 325} efx_port_t; 326 327typedef struct efx_mon_ops_s { 328 efx_rc_t (*emo_reset)(efx_nic_t *); 329 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 330#if EFSYS_OPT_MON_STATS 331 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 332 efx_mon_stat_value_t *); 333#endif /* EFSYS_OPT_MON_STATS */ 334} efx_mon_ops_t; 335 336typedef struct efx_mon_s { 337 efx_mon_type_t em_type; 338 efx_mon_ops_t *em_emop; 339} efx_mon_t; 340 341typedef struct efx_intr_ops_s { 342 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 343 void (*eio_enable)(efx_nic_t *); 344 void (*eio_disable)(efx_nic_t *); 345 void (*eio_disable_unlocked)(efx_nic_t *); 346 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 347 void (*eio_fini)(efx_nic_t *); 348} efx_intr_ops_t; 349 350typedef struct efx_intr_s { 351 efx_intr_ops_t *ei_eiop; 352 efsys_mem_t *ei_esmp; 353 efx_intr_type_t ei_type; 354 unsigned int ei_level; 355} efx_intr_t; 356 357typedef struct efx_nic_ops_s { 358 efx_rc_t (*eno_probe)(efx_nic_t *); 359 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 360 efx_rc_t (*eno_reset)(efx_nic_t *); 361 efx_rc_t (*eno_init)(efx_nic_t *); 362 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 363 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 364 uint32_t *, size_t *); 365#if EFSYS_OPT_DIAG 366 efx_rc_t (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t); 367 efx_rc_t (*eno_register_test)(efx_nic_t *); 368#endif /* EFSYS_OPT_DIAG */ 369 void (*eno_fini)(efx_nic_t *); 370 void (*eno_unprobe)(efx_nic_t *); 371} efx_nic_ops_t; 372 373#ifndef EFX_TXQ_LIMIT_TARGET 374#define EFX_TXQ_LIMIT_TARGET 259 375#endif 376#ifndef EFX_RXQ_LIMIT_TARGET 377#define EFX_RXQ_LIMIT_TARGET 512 378#endif 379#ifndef EFX_TXQ_DC_SIZE 380#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */ 381#endif 382#ifndef EFX_RXQ_DC_SIZE 383#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */ 384#endif 385 386#if EFSYS_OPT_FILTER 387 388typedef struct falconsiena_filter_spec_s { 389 uint8_t fsfs_type; 390 uint32_t fsfs_flags; 391 uint32_t fsfs_dmaq_id; 392 uint32_t fsfs_dword[3]; 393} falconsiena_filter_spec_t; 394 395typedef enum falconsiena_filter_type_e { 396 EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */ 397 EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */ 398 EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */ 399 EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */ 400 401#if EFSYS_OPT_SIENA 402 EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 403 EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 404 405 EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 406 EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 407 EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 408 EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */ 409 410 EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */ 411 EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */ 412#endif /* EFSYS_OPT_SIENA */ 413 414 EFX_FS_FILTER_NTYPES 415} falconsiena_filter_type_t; 416 417typedef enum falconsiena_filter_tbl_id_e { 418 EFX_FS_FILTER_TBL_RX_IP = 0, 419 EFX_FS_FILTER_TBL_RX_MAC, 420 EFX_FS_FILTER_TBL_TX_IP, 421 EFX_FS_FILTER_TBL_TX_MAC, 422 EFX_FS_FILTER_NTBLS 423} falconsiena_filter_tbl_id_t; 424 425typedef struct falconsiena_filter_tbl_s { 426 int fsft_size; /* number of entries */ 427 int fsft_used; /* active count */ 428 uint32_t *fsft_bitmap; /* active bitmap */ 429 falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */ 430} falconsiena_filter_tbl_t; 431 432typedef struct falconsiena_filter_s { 433 falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS]; 434 unsigned int fsf_depth[EFX_FS_FILTER_NTYPES]; 435} falconsiena_filter_t; 436 437typedef struct efx_filter_s { 438#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA 439 falconsiena_filter_t *ef_falconsiena_filter; 440#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ 441#if EFSYS_OPT_HUNTINGTON 442 hunt_filter_table_t *ef_hunt_filter_table; 443#endif /* EFSYS_OPT_HUNTINGTON */ 444} efx_filter_t; 445 446extern void 447falconsiena_filter_tbl_clear( 448 __in efx_nic_t *enp, 449 __in falconsiena_filter_tbl_id_t tbl); 450 451#endif /* EFSYS_OPT_FILTER */ 452 453#if EFSYS_OPT_MCDI 454 455typedef struct efx_mcdi_ops_s { 456 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 457 void (*emco_request_copyin)(efx_nic_t *, efx_mcdi_req_t *, 458 unsigned int, boolean_t, boolean_t); 459 boolean_t (*emco_request_poll)(efx_nic_t *); 460 void (*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *); 461 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 462 void (*emco_fini)(efx_nic_t *); 463 efx_rc_t (*emco_fw_update_supported)(efx_nic_t *, boolean_t *); 464 efx_rc_t (*emco_macaddr_change_supported)(efx_nic_t *, boolean_t *);
| 31 */ 32 33#ifndef _SYS_EFX_IMPL_H 34#define _SYS_EFX_IMPL_H 35 36#include "efsys.h" 37#include "efx.h" 38#include "efx_regs.h" 39#include "efx_regs_ef10.h" 40 41/* FIXME: Add definition for driver generated software events */ 42#ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 43#define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 44#endif 45 46#include "efx_check.h" 47 48 49#if EFSYS_OPT_FALCON 50#include "falcon_impl.h" 51#endif /* EFSYS_OPT_FALCON */ 52 53#if EFSYS_OPT_SIENA 54#include "siena_impl.h" 55#endif /* EFSYS_OPT_SIENA */ 56 57#if EFSYS_OPT_HUNTINGTON 58#include "hunt_impl.h" 59#endif /* EFSYS_OPT_HUNTINGTON */ 60 61#ifdef __cplusplus 62extern "C" { 63#endif 64 65#define EFX_MOD_MCDI 0x00000001 66#define EFX_MOD_PROBE 0x00000002 67#define EFX_MOD_NVRAM 0x00000004 68#define EFX_MOD_VPD 0x00000008 69#define EFX_MOD_NIC 0x00000010 70#define EFX_MOD_INTR 0x00000020 71#define EFX_MOD_EV 0x00000040 72#define EFX_MOD_RX 0x00000080 73#define EFX_MOD_TX 0x00000100 74#define EFX_MOD_PORT 0x00000200 75#define EFX_MOD_MON 0x00000400 76#define EFX_MOD_WOL 0x00000800 77#define EFX_MOD_FILTER 0x00001000 78#define EFX_MOD_PKTFILTER 0x00002000 79 80#define EFX_RESET_MAC 0x00000001 81#define EFX_RESET_PHY 0x00000002 82#define EFX_RESET_RXQ_ERR 0x00000004 83#define EFX_RESET_TXQ_ERR 0x00000008 84 85typedef enum efx_mac_type_e { 86 EFX_MAC_INVALID = 0, 87 EFX_MAC_FALCON_GMAC, 88 EFX_MAC_FALCON_XMAC, 89 EFX_MAC_SIENA, 90 EFX_MAC_HUNTINGTON, 91 EFX_MAC_NTYPES 92} efx_mac_type_t; 93 94typedef struct efx_ev_ops_s { 95 efx_rc_t (*eevo_init)(efx_nic_t *); 96 void (*eevo_fini)(efx_nic_t *); 97 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 98 efsys_mem_t *, size_t, uint32_t, 99 efx_evq_t *); 100 void (*eevo_qdestroy)(efx_evq_t *); 101 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 102 void (*eevo_qpost)(efx_evq_t *, uint16_t); 103 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 104#if EFSYS_OPT_QSTATS 105 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 106#endif 107} efx_ev_ops_t; 108 109typedef struct efx_tx_ops_s { 110 efx_rc_t (*etxo_init)(efx_nic_t *); 111 void (*etxo_fini)(efx_nic_t *); 112 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 113 unsigned int, unsigned int, 114 efsys_mem_t *, size_t, 115 uint32_t, uint16_t, 116 efx_evq_t *, efx_txq_t *, 117 unsigned int *); 118 void (*etxo_qdestroy)(efx_txq_t *); 119 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 120 unsigned int, unsigned int, 121 unsigned int *); 122 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 123 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 124 efx_rc_t (*etxo_qflush)(efx_txq_t *); 125 void (*etxo_qenable)(efx_txq_t *); 126 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 127 void (*etxo_qpio_disable)(efx_txq_t *); 128 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t, 129 size_t); 130 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 131 unsigned int *); 132 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 133 unsigned int, unsigned int, 134 unsigned int *); 135 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 136 size_t, boolean_t, 137 efx_desc_t *); 138 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 139 uint32_t, uint8_t, 140 efx_desc_t *); 141 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 142 efx_desc_t *); 143#if EFSYS_OPT_QSTATS 144 void (*etxo_qstats_update)(efx_txq_t *, 145 efsys_stat_t *); 146#endif 147} efx_tx_ops_t; 148 149typedef struct efx_rx_ops_s { 150 efx_rc_t (*erxo_init)(efx_nic_t *); 151 void (*erxo_fini)(efx_nic_t *); 152#if EFSYS_OPT_RX_HDR_SPLIT 153 efx_rc_t (*erxo_hdr_split_enable)(efx_nic_t *, unsigned int, 154 unsigned int); 155#endif 156#if EFSYS_OPT_RX_SCATTER 157 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 158#endif 159#if EFSYS_OPT_RX_SCALE 160 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t, 161 efx_rx_hash_type_t, boolean_t); 162 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t); 163 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *, 164 size_t); 165#endif 166 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 167 unsigned int, unsigned int, 168 unsigned int); 169 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 170 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 171 void (*erxo_qenable)(efx_rxq_t *); 172 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 173 unsigned int, efx_rxq_type_t, 174 efsys_mem_t *, size_t, uint32_t, 175 efx_evq_t *, efx_rxq_t *); 176 void (*erxo_qdestroy)(efx_rxq_t *); 177} efx_rx_ops_t; 178 179typedef struct efx_mac_ops_s { 180 efx_rc_t (*emo_reset)(efx_nic_t *); /* optional */ 181 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 182 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 183 efx_rc_t (*emo_addr_set)(efx_nic_t *); 184 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 185 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 186 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 187 efx_rxq_t *, boolean_t); 188 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 189#if EFSYS_OPT_LOOPBACK 190 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 191 efx_loopback_type_t); 192#endif /* EFSYS_OPT_LOOPBACK */ 193#if EFSYS_OPT_MAC_STATS 194 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 195 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 196 uint16_t, boolean_t); 197 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 198 efsys_stat_t *, uint32_t *); 199#endif /* EFSYS_OPT_MAC_STATS */ 200} efx_mac_ops_t; 201 202typedef struct efx_phy_ops_s { 203 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 204 efx_rc_t (*epo_reset)(efx_nic_t *); 205 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 206 efx_rc_t (*epo_verify)(efx_nic_t *); 207 efx_rc_t (*epo_uplink_check)(efx_nic_t *, 208 boolean_t *); /* optional */ 209 efx_rc_t (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *, 210 unsigned int *, uint32_t *); 211 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 212#if EFSYS_OPT_PHY_STATS 213 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 214 uint32_t *); 215#endif /* EFSYS_OPT_PHY_STATS */ 216#if EFSYS_OPT_PHY_PROPS 217#if EFSYS_OPT_NAMES 218 const char *(*epo_prop_name)(efx_nic_t *, unsigned int); 219#endif /* EFSYS_OPT_PHY_PROPS */ 220 efx_rc_t (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t, 221 uint32_t *); 222 efx_rc_t (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t); 223#endif /* EFSYS_OPT_PHY_PROPS */ 224#if EFSYS_OPT_BIST 225 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 226 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 227 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 228 efx_bist_result_t *, uint32_t *, 229 unsigned long *, size_t); 230 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 231#endif /* EFSYS_OPT_BIST */ 232} efx_phy_ops_t; 233 234#if EFSYS_OPT_FILTER 235typedef struct efx_filter_ops_s { 236 efx_rc_t (*efo_init)(efx_nic_t *); 237 void (*efo_fini)(efx_nic_t *); 238 efx_rc_t (*efo_restore)(efx_nic_t *); 239 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 240 boolean_t may_replace); 241 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 242 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *); 243 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 244 boolean_t, boolean_t, boolean_t, 245 uint8_t const *, int); 246} efx_filter_ops_t; 247 248extern __checkReturn efx_rc_t 249efx_filter_reconfigure( 250 __in efx_nic_t *enp, 251 __in_ecount(6) uint8_t const *mac_addr, 252 __in boolean_t all_unicst, 253 __in boolean_t mulcst, 254 __in boolean_t all_mulcst, 255 __in boolean_t brdcst, 256 __in_ecount(6*count) uint8_t const *addrs, 257 __in int count); 258 259#endif /* EFSYS_OPT_FILTER */ 260 261typedef struct efx_pktfilter_ops_s { 262 efx_rc_t (*epfo_set)(efx_nic_t *, 263 boolean_t unicst, 264 boolean_t brdcast); 265#if EFSYS_OPT_MCAST_FILTER_LIST 266 efx_rc_t (*epfo_mcast_list_set)(efx_nic_t *, 267 uint8_t const *addrs, int count); 268#endif /* EFSYS_OPT_MCAST_FILTER_LIST */ 269 efx_rc_t (*epfo_mcast_all)(efx_nic_t *); 270} efx_pktfilter_ops_t; 271 272typedef struct efx_port_s { 273 efx_mac_type_t ep_mac_type; 274 uint32_t ep_phy_type; 275 uint8_t ep_port; 276 uint32_t ep_mac_pdu; 277 uint8_t ep_mac_addr[6]; 278 efx_link_mode_t ep_link_mode; 279 boolean_t ep_all_unicst; 280 boolean_t ep_mulcst; 281 boolean_t ep_all_mulcst; 282 boolean_t ep_brdcst; 283 unsigned int ep_fcntl; 284 boolean_t ep_fcntl_autoneg; 285 efx_oword_t ep_multicst_hash[2]; 286 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 287 EFX_MAC_MULTICAST_LIST_MAX]; 288 uint32_t ep_mulcst_addr_count; 289#if EFSYS_OPT_LOOPBACK 290 efx_loopback_type_t ep_loopback_type; 291 efx_link_mode_t ep_loopback_link_mode; 292#endif /* EFSYS_OPT_LOOPBACK */ 293#if EFSYS_OPT_PHY_FLAGS 294 uint32_t ep_phy_flags; 295#endif /* EFSYS_OPT_PHY_FLAGS */ 296#if EFSYS_OPT_PHY_LED_CONTROL 297 efx_phy_led_mode_t ep_phy_led_mode; 298#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 299 efx_phy_media_type_t ep_fixed_port_type; 300 efx_phy_media_type_t ep_module_type; 301 uint32_t ep_adv_cap_mask; 302 uint32_t ep_lp_cap_mask; 303 uint32_t ep_default_adv_cap_mask; 304 uint32_t ep_phy_cap_mask; 305#if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C 306 union { 307 struct { 308 unsigned int bug10934_count; 309 } ep_txc43128; 310 struct { 311 unsigned int bug17190_count; 312 } ep_qt2025c; 313 }; 314#endif 315 boolean_t ep_mac_poll_needed; /* falcon only */ 316 boolean_t ep_mac_up; /* falcon only */ 317 uint32_t ep_fwver; /* falcon only */ 318 boolean_t ep_mac_drain; 319 boolean_t ep_mac_stats_pending; 320#if EFSYS_OPT_BIST 321 efx_bist_type_t ep_current_bist; 322#endif 323 efx_mac_ops_t *ep_emop; 324 efx_phy_ops_t *ep_epop; 325} efx_port_t; 326 327typedef struct efx_mon_ops_s { 328 efx_rc_t (*emo_reset)(efx_nic_t *); 329 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 330#if EFSYS_OPT_MON_STATS 331 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 332 efx_mon_stat_value_t *); 333#endif /* EFSYS_OPT_MON_STATS */ 334} efx_mon_ops_t; 335 336typedef struct efx_mon_s { 337 efx_mon_type_t em_type; 338 efx_mon_ops_t *em_emop; 339} efx_mon_t; 340 341typedef struct efx_intr_ops_s { 342 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 343 void (*eio_enable)(efx_nic_t *); 344 void (*eio_disable)(efx_nic_t *); 345 void (*eio_disable_unlocked)(efx_nic_t *); 346 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 347 void (*eio_fini)(efx_nic_t *); 348} efx_intr_ops_t; 349 350typedef struct efx_intr_s { 351 efx_intr_ops_t *ei_eiop; 352 efsys_mem_t *ei_esmp; 353 efx_intr_type_t ei_type; 354 unsigned int ei_level; 355} efx_intr_t; 356 357typedef struct efx_nic_ops_s { 358 efx_rc_t (*eno_probe)(efx_nic_t *); 359 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 360 efx_rc_t (*eno_reset)(efx_nic_t *); 361 efx_rc_t (*eno_init)(efx_nic_t *); 362 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 363 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 364 uint32_t *, size_t *); 365#if EFSYS_OPT_DIAG 366 efx_rc_t (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t); 367 efx_rc_t (*eno_register_test)(efx_nic_t *); 368#endif /* EFSYS_OPT_DIAG */ 369 void (*eno_fini)(efx_nic_t *); 370 void (*eno_unprobe)(efx_nic_t *); 371} efx_nic_ops_t; 372 373#ifndef EFX_TXQ_LIMIT_TARGET 374#define EFX_TXQ_LIMIT_TARGET 259 375#endif 376#ifndef EFX_RXQ_LIMIT_TARGET 377#define EFX_RXQ_LIMIT_TARGET 512 378#endif 379#ifndef EFX_TXQ_DC_SIZE 380#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */ 381#endif 382#ifndef EFX_RXQ_DC_SIZE 383#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */ 384#endif 385 386#if EFSYS_OPT_FILTER 387 388typedef struct falconsiena_filter_spec_s { 389 uint8_t fsfs_type; 390 uint32_t fsfs_flags; 391 uint32_t fsfs_dmaq_id; 392 uint32_t fsfs_dword[3]; 393} falconsiena_filter_spec_t; 394 395typedef enum falconsiena_filter_type_e { 396 EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */ 397 EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */ 398 EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */ 399 EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */ 400 401#if EFSYS_OPT_SIENA 402 EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 403 EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 404 405 EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 406 EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 407 EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 408 EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */ 409 410 EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */ 411 EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */ 412#endif /* EFSYS_OPT_SIENA */ 413 414 EFX_FS_FILTER_NTYPES 415} falconsiena_filter_type_t; 416 417typedef enum falconsiena_filter_tbl_id_e { 418 EFX_FS_FILTER_TBL_RX_IP = 0, 419 EFX_FS_FILTER_TBL_RX_MAC, 420 EFX_FS_FILTER_TBL_TX_IP, 421 EFX_FS_FILTER_TBL_TX_MAC, 422 EFX_FS_FILTER_NTBLS 423} falconsiena_filter_tbl_id_t; 424 425typedef struct falconsiena_filter_tbl_s { 426 int fsft_size; /* number of entries */ 427 int fsft_used; /* active count */ 428 uint32_t *fsft_bitmap; /* active bitmap */ 429 falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */ 430} falconsiena_filter_tbl_t; 431 432typedef struct falconsiena_filter_s { 433 falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS]; 434 unsigned int fsf_depth[EFX_FS_FILTER_NTYPES]; 435} falconsiena_filter_t; 436 437typedef struct efx_filter_s { 438#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA 439 falconsiena_filter_t *ef_falconsiena_filter; 440#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ 441#if EFSYS_OPT_HUNTINGTON 442 hunt_filter_table_t *ef_hunt_filter_table; 443#endif /* EFSYS_OPT_HUNTINGTON */ 444} efx_filter_t; 445 446extern void 447falconsiena_filter_tbl_clear( 448 __in efx_nic_t *enp, 449 __in falconsiena_filter_tbl_id_t tbl); 450 451#endif /* EFSYS_OPT_FILTER */ 452 453#if EFSYS_OPT_MCDI 454 455typedef struct efx_mcdi_ops_s { 456 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 457 void (*emco_request_copyin)(efx_nic_t *, efx_mcdi_req_t *, 458 unsigned int, boolean_t, boolean_t); 459 boolean_t (*emco_request_poll)(efx_nic_t *); 460 void (*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *); 461 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 462 void (*emco_fini)(efx_nic_t *); 463 efx_rc_t (*emco_fw_update_supported)(efx_nic_t *, boolean_t *); 464 efx_rc_t (*emco_macaddr_change_supported)(efx_nic_t *, boolean_t *);
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465} efx_mcdi_ops_t; 466 467typedef struct efx_mcdi_s { 468 efx_mcdi_ops_t *em_emcop; 469 const efx_mcdi_transport_t *em_emtp; 470 efx_mcdi_iface_t em_emip; 471} efx_mcdi_t; 472 473#endif /* EFSYS_OPT_MCDI */ 474 475#if EFSYS_OPT_NVRAM 476typedef struct efx_nvram_ops_s { 477#if EFSYS_OPT_DIAG 478 efx_rc_t (*envo_test)(efx_nic_t *); 479#endif /* EFSYS_OPT_DIAG */ 480 efx_rc_t (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *); 481 efx_rc_t (*envo_get_version)(efx_nic_t *, efx_nvram_type_t, 482 uint32_t *, uint16_t *); 483 efx_rc_t (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *); 484 efx_rc_t (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t, 485 unsigned int, caddr_t, size_t); 486 efx_rc_t (*envo_erase)(efx_nic_t *, efx_nvram_type_t); 487 efx_rc_t (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t, 488 unsigned int, caddr_t, size_t); 489 void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t); 490 efx_rc_t (*envo_set_version)(efx_nic_t *, efx_nvram_type_t, 491 uint16_t *); 492 493} efx_nvram_ops_t; 494#endif /* EFSYS_OPT_NVRAM */ 495 496#if EFSYS_OPT_VPD 497typedef struct efx_vpd_ops_s { 498 efx_rc_t (*evpdo_init)(efx_nic_t *); 499 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 500 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 501 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 502 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 503 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 504 efx_vpd_value_t *); 505 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 506 efx_vpd_value_t *); 507 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 508 efx_vpd_value_t *, unsigned int *); 509 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 510 void (*evpdo_fini)(efx_nic_t *); 511} efx_vpd_ops_t; 512#endif /* EFSYS_OPT_VPD */ 513 514#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 515 516 __checkReturn efx_rc_t 517efx_mcdi_nvram_partitions( 518 __in efx_nic_t *enp, 519 __out_bcount(size) caddr_t data, 520 __in size_t size, 521 __out unsigned int *npartnp); 522 523 __checkReturn efx_rc_t 524efx_mcdi_nvram_metadata( 525 __in efx_nic_t *enp, 526 __in uint32_t partn, 527 __out uint32_t *subtypep, 528 __out_ecount(4) uint16_t version[4], 529 __out_bcount_opt(size) char *descp, 530 __in size_t size); 531 532 __checkReturn efx_rc_t 533efx_mcdi_nvram_info( 534 __in efx_nic_t *enp, 535 __in uint32_t partn, 536 __out_opt size_t *sizep, 537 __out_opt uint32_t *addressp, 538 __out_opt uint32_t *erase_sizep); 539 540 __checkReturn efx_rc_t 541efx_mcdi_nvram_update_start( 542 __in efx_nic_t *enp, 543 __in uint32_t partn); 544 545 __checkReturn efx_rc_t 546efx_mcdi_nvram_read( 547 __in efx_nic_t *enp, 548 __in uint32_t partn, 549 __in uint32_t offset, 550 __out_bcount(size) caddr_t data, 551 __in size_t size); 552 553 __checkReturn efx_rc_t 554efx_mcdi_nvram_erase( 555 __in efx_nic_t *enp, 556 __in uint32_t partn, 557 __in uint32_t offset, 558 __in size_t size); 559 560 __checkReturn efx_rc_t 561efx_mcdi_nvram_write( 562 __in efx_nic_t *enp, 563 __in uint32_t partn, 564 __in uint32_t offset, 565 __out_bcount(size) caddr_t data, 566 __in size_t size); 567 568 __checkReturn efx_rc_t 569efx_mcdi_nvram_update_finish( 570 __in efx_nic_t *enp, 571 __in uint32_t partn, 572 __in boolean_t reboot); 573 574#if EFSYS_OPT_DIAG 575 576 __checkReturn efx_rc_t 577efx_mcdi_nvram_test( 578 __in efx_nic_t *enp, 579 __in uint32_t partn); 580 581#endif /* EFSYS_OPT_DIAG */ 582 583#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 584 585typedef struct efx_drv_cfg_s { 586 uint32_t edc_min_vi_count; 587 uint32_t edc_max_vi_count; 588 589 uint32_t edc_max_piobuf_count; 590 uint32_t edc_pio_alloc_size; 591} efx_drv_cfg_t; 592 593struct efx_nic_s { 594 uint32_t en_magic; 595 efx_family_t en_family; 596 uint32_t en_features; 597 efsys_identifier_t *en_esip; 598 efsys_lock_t *en_eslp; 599 efsys_bar_t *en_esbp; 600 unsigned int en_mod_flags; 601 unsigned int en_reset_flags; 602 efx_nic_cfg_t en_nic_cfg; 603 efx_drv_cfg_t en_drv_cfg; 604 efx_port_t en_port; 605 efx_mon_t en_mon; 606 efx_intr_t en_intr; 607 uint32_t en_ev_qcount; 608 uint32_t en_rx_qcount; 609 uint32_t en_tx_qcount; 610 efx_nic_ops_t *en_enop; 611 efx_ev_ops_t *en_eevop; 612 efx_tx_ops_t *en_etxop; 613 efx_rx_ops_t *en_erxop; 614#if EFSYS_OPT_FILTER 615 efx_filter_t en_filter; 616 efx_filter_ops_t *en_efop; 617#endif /* EFSYS_OPT_FILTER */ 618 efx_pktfilter_ops_t *en_epfop; 619#if EFSYS_OPT_MCDI 620 efx_mcdi_t en_mcdi; 621#endif /* EFSYS_OPT_MCDI */ 622#if EFSYS_OPT_NVRAM 623 efx_nvram_type_t en_nvram_locked; 624 efx_nvram_ops_t *en_envop; 625#endif /* EFSYS_OPT_NVRAM */ 626#if EFSYS_OPT_VPD 627 efx_vpd_ops_t *en_evpdop; 628#endif /* EFSYS_OPT_VPD */ 629#if EFSYS_OPT_RX_SCALE 630 efx_rx_hash_support_t en_hash_support; 631 efx_rx_scale_support_t en_rss_support; 632 uint32_t en_rss_context; 633#endif /* EFSYS_OPT_RX_SCALE */ 634 uint32_t en_vport_id; 635 union { 636#if EFSYS_OPT_FALCON 637 struct { 638 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES]; 639 falcon_i2c_t enu_fip; 640 boolean_t enu_i2c_locked; 641#if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE 642 const uint8_t *enu_forced_cfg; 643#endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */ 644 uint8_t enu_mon_devid; 645#if EFSYS_OPT_PCIE_TUNE 646 unsigned int enu_nlanes; 647#endif /* EFSYS_OPT_PCIE_TUNE */ 648 uint16_t enu_board_rev; 649 boolean_t enu_internal_sram; 650 uint8_t enu_sram_num_bank; 651 uint8_t enu_sram_bank_size; 652 } falcon; 653#endif /* EFSYS_OPT_FALCON */ 654#if EFSYS_OPT_SIENA 655 struct { 656#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 657 unsigned int enu_partn_mask; 658#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 659#if EFSYS_OPT_VPD 660 caddr_t enu_svpd; 661 size_t enu_svpd_length; 662#endif /* EFSYS_OPT_VPD */ 663 int enu_unused; 664 } siena; 665#endif /* EFSYS_OPT_SIENA */ 666#if EFSYS_OPT_HUNTINGTON 667 struct { 668 int enu_vi_base; 669 int enu_vi_count; 670#if EFSYS_OPT_VPD 671 caddr_t enu_svpd; 672 size_t enu_svpd_length; 673#endif /* EFSYS_OPT_VPD */ 674 efx_piobuf_handle_t enu_piobuf_handle[HUNT_PIOBUF_NBUFS]; 675 uint32_t enu_piobuf_count; 676 uint32_t enu_pio_alloc_map[HUNT_PIOBUF_NBUFS]; 677 uint32_t enu_pio_write_vi_base; 678 /* Memory BAR mapping regions */ 679 uint32_t enu_uc_mem_map_offset; 680 size_t enu_uc_mem_map_size; 681 uint32_t enu_wc_mem_map_offset; 682 size_t enu_wc_mem_map_size; 683 } hunt; 684#endif /* EFSYS_OPT_HUNTINGTON */ 685 } en_u; 686}; 687 688 689#define EFX_NIC_MAGIC 0x02121996 690 691typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 692 const efx_ev_callbacks_t *, void *); 693 694typedef struct efx_evq_rxq_state_s { 695 unsigned int eers_rx_read_ptr; 696 unsigned int eers_rx_mask; 697} efx_evq_rxq_state_t; 698 699struct efx_evq_s { 700 uint32_t ee_magic; 701 efx_nic_t *ee_enp; 702 unsigned int ee_index; 703 unsigned int ee_mask; 704 efsys_mem_t *ee_esmp; 705#if EFSYS_OPT_QSTATS 706 uint32_t ee_stat[EV_NQSTATS]; 707#endif /* EFSYS_OPT_QSTATS */ 708 709 efx_ev_handler_t ee_rx; 710 efx_ev_handler_t ee_tx; 711 efx_ev_handler_t ee_driver; 712 efx_ev_handler_t ee_global; 713 efx_ev_handler_t ee_drv_gen; 714#if EFSYS_OPT_MCDI 715 efx_ev_handler_t ee_mcdi; 716#endif /* EFSYS_OPT_MCDI */ 717 718 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 719}; 720 721#define EFX_EVQ_MAGIC 0x08081997 722 723#define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */ 724#define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 725 726struct efx_rxq_s { 727 uint32_t er_magic; 728 efx_nic_t *er_enp; 729 efx_evq_t *er_eep; 730 unsigned int er_index; 731 unsigned int er_label; 732 unsigned int er_mask; 733 efsys_mem_t *er_esmp; 734}; 735 736#define EFX_RXQ_MAGIC 0x15022005 737 738struct efx_txq_s { 739 uint32_t et_magic; 740 efx_nic_t *et_enp; 741 unsigned int et_index; 742 unsigned int et_mask; 743 efsys_mem_t *et_esmp; 744#if EFSYS_OPT_HUNTINGTON 745 uint32_t et_pio_bufnum; 746 uint32_t et_pio_blknum; 747 uint32_t et_pio_write_offset; 748 uint32_t et_pio_offset; 749 size_t et_pio_size; 750#endif 751#if EFSYS_OPT_QSTATS 752 uint32_t et_stat[TX_NQSTATS]; 753#endif /* EFSYS_OPT_QSTATS */ 754}; 755 756#define EFX_TXQ_MAGIC 0x05092005 757 758#define EFX_MAC_ADDR_COPY(_dst, _src) \ 759 do { \ 760 (_dst)[0] = (_src)[0]; \ 761 (_dst)[1] = (_src)[1]; \ 762 (_dst)[2] = (_src)[2]; \ 763 (_dst)[3] = (_src)[3]; \ 764 (_dst)[4] = (_src)[4]; \ 765 (_dst)[5] = (_src)[5]; \ 766 _NOTE(CONSTANTCONDITION) \ 767 } while (B_FALSE) 768 769#define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 770 do { \ 771 uint16_t *_d = (uint16_t *)(_dst); \ 772 _d[0] = 0xffff; \ 773 _d[1] = 0xffff; \ 774 _d[2] = 0xffff; \ 775 _NOTE(CONSTANTCONDITION) \ 776 } while (B_FALSE) 777 778#if EFSYS_OPT_CHECK_REG 779#define EFX_CHECK_REG(_enp, _reg) \ 780 do { \ 781 const char *name = #_reg; \ 782 char min = name[4]; \ 783 char max = name[5]; \ 784 char rev; \ 785 \ 786 switch ((_enp)->en_family) { \ 787 case EFX_FAMILY_FALCON: \ 788 rev = 'B'; \ 789 break; \ 790 \ 791 case EFX_FAMILY_SIENA: \ 792 rev = 'C'; \ 793 break; \ 794 \ 795 case EFX_FAMILY_HUNTINGTON: \ 796 rev = 'D'; \ 797 break; \ 798 \ 799 default: \ 800 rev = '?'; \ 801 break; \ 802 } \ 803 \ 804 EFSYS_ASSERT3S(rev, >=, min); \ 805 EFSYS_ASSERT3S(rev, <=, max); \ 806 \ 807 _NOTE(CONSTANTCONDITION) \ 808 } while (B_FALSE) 809#else 810#define EFX_CHECK_REG(_enp, _reg) do { \ 811 _NOTE(CONSTANTCONDITION) \ 812 } while(B_FALSE) 813#endif 814 815#define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 816 do { \ 817 EFX_CHECK_REG((_enp), (_reg)); \ 818 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 819 (_edp), (_lock)); \ 820 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 821 uint32_t, _reg ## _OFST, \ 822 uint32_t, (_edp)->ed_u32[0]); \ 823 _NOTE(CONSTANTCONDITION) \ 824 } while (B_FALSE) 825 826#define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 827 do { \ 828 EFX_CHECK_REG((_enp), (_reg)); \ 829 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 830 uint32_t, _reg ## _OFST, \ 831 uint32_t, (_edp)->ed_u32[0]); \ 832 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 833 (_edp), (_lock)); \ 834 _NOTE(CONSTANTCONDITION) \ 835 } while (B_FALSE) 836 837#define EFX_BAR_READQ(_enp, _reg, _eqp) \ 838 do { \ 839 EFX_CHECK_REG((_enp), (_reg)); \ 840 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 841 (_eqp)); \ 842 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 843 uint32_t, _reg ## _OFST, \ 844 uint32_t, (_eqp)->eq_u32[1], \ 845 uint32_t, (_eqp)->eq_u32[0]); \ 846 _NOTE(CONSTANTCONDITION) \ 847 } while (B_FALSE) 848 849#define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 850 do { \ 851 EFX_CHECK_REG((_enp), (_reg)); \ 852 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 853 uint32_t, _reg ## _OFST, \ 854 uint32_t, (_eqp)->eq_u32[1], \ 855 uint32_t, (_eqp)->eq_u32[0]); \ 856 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 857 (_eqp)); \ 858 _NOTE(CONSTANTCONDITION) \ 859 } while (B_FALSE) 860 861#define EFX_BAR_READO(_enp, _reg, _eop) \ 862 do { \ 863 EFX_CHECK_REG((_enp), (_reg)); \ 864 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 865 (_eop), B_TRUE); \ 866 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 867 uint32_t, _reg ## _OFST, \ 868 uint32_t, (_eop)->eo_u32[3], \ 869 uint32_t, (_eop)->eo_u32[2], \ 870 uint32_t, (_eop)->eo_u32[1], \ 871 uint32_t, (_eop)->eo_u32[0]); \ 872 _NOTE(CONSTANTCONDITION) \ 873 } while (B_FALSE) 874 875#define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 876 do { \ 877 EFX_CHECK_REG((_enp), (_reg)); \ 878 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 879 uint32_t, _reg ## _OFST, \ 880 uint32_t, (_eop)->eo_u32[3], \ 881 uint32_t, (_eop)->eo_u32[2], \ 882 uint32_t, (_eop)->eo_u32[1], \ 883 uint32_t, (_eop)->eo_u32[0]); \ 884 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 885 (_eop), B_TRUE); \ 886 _NOTE(CONSTANTCONDITION) \ 887 } while (B_FALSE) 888 889#define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 890 do { \ 891 EFX_CHECK_REG((_enp), (_reg)); \ 892 EFSYS_BAR_READD((_enp)->en_esbp, \ 893 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 894 (_edp), (_lock)); \ 895 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 896 uint32_t, (_index), \ 897 uint32_t, _reg ## _OFST, \ 898 uint32_t, (_edp)->ed_u32[0]); \ 899 _NOTE(CONSTANTCONDITION) \ 900 } while (B_FALSE) 901 902#define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 903 do { \ 904 EFX_CHECK_REG((_enp), (_reg)); \ 905 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 906 uint32_t, (_index), \ 907 uint32_t, _reg ## _OFST, \ 908 uint32_t, (_edp)->ed_u32[0]); \ 909 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 910 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 911 (_edp), (_lock)); \ 912 _NOTE(CONSTANTCONDITION) \ 913 } while (B_FALSE) 914 915#define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \ 916 do { \ 917 EFX_CHECK_REG((_enp), (_reg)); \ 918 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 919 uint32_t, (_index), \ 920 uint32_t, _reg ## _OFST, \ 921 uint32_t, (_edp)->ed_u32[0]); \ 922 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 923 (_reg ## _OFST + \ 924 (2 * sizeof (efx_dword_t)) + \ 925 ((_index) * _reg ## _STEP)), \ 926 (_edp), (_lock)); \ 927 _NOTE(CONSTANTCONDITION) \ 928 } while (B_FALSE) 929 930#define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 931 do { \ 932 EFX_CHECK_REG((_enp), (_reg)); \ 933 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 934 uint32_t, (_index), \ 935 uint32_t, _reg ## _OFST, \ 936 uint32_t, (_edp)->ed_u32[0]); \ 937 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 938 (_reg ## _OFST + \ 939 (3 * sizeof (efx_dword_t)) + \ 940 ((_index) * _reg ## _STEP)), \ 941 (_edp), (_lock)); \ 942 _NOTE(CONSTANTCONDITION) \ 943 } while (B_FALSE) 944 945#define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 946 do { \ 947 EFX_CHECK_REG((_enp), (_reg)); \ 948 EFSYS_BAR_READQ((_enp)->en_esbp, \ 949 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 950 (_eqp)); \ 951 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 952 uint32_t, (_index), \ 953 uint32_t, _reg ## _OFST, \ 954 uint32_t, (_eqp)->eq_u32[1], \ 955 uint32_t, (_eqp)->eq_u32[0]); \ 956 _NOTE(CONSTANTCONDITION) \ 957 } while (B_FALSE) 958 959#define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 960 do { \ 961 EFX_CHECK_REG((_enp), (_reg)); \ 962 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 963 uint32_t, (_index), \ 964 uint32_t, _reg ## _OFST, \ 965 uint32_t, (_eqp)->eq_u32[1], \ 966 uint32_t, (_eqp)->eq_u32[0]); \ 967 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 968 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 969 (_eqp)); \ 970 _NOTE(CONSTANTCONDITION) \ 971 } while (B_FALSE) 972 973#define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 974 do { \ 975 EFX_CHECK_REG((_enp), (_reg)); \ 976 EFSYS_BAR_READO((_enp)->en_esbp, \ 977 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 978 (_eop), (_lock)); \ 979 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 980 uint32_t, (_index), \ 981 uint32_t, _reg ## _OFST, \ 982 uint32_t, (_eop)->eo_u32[3], \ 983 uint32_t, (_eop)->eo_u32[2], \ 984 uint32_t, (_eop)->eo_u32[1], \ 985 uint32_t, (_eop)->eo_u32[0]); \ 986 _NOTE(CONSTANTCONDITION) \ 987 } while (B_FALSE) 988 989#define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 990 do { \ 991 EFX_CHECK_REG((_enp), (_reg)); \ 992 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 993 uint32_t, (_index), \ 994 uint32_t, _reg ## _OFST, \ 995 uint32_t, (_eop)->eo_u32[3], \ 996 uint32_t, (_eop)->eo_u32[2], \ 997 uint32_t, (_eop)->eo_u32[1], \ 998 uint32_t, (_eop)->eo_u32[0]); \ 999 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1000 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1001 (_eop), (_lock)); \ 1002 _NOTE(CONSTANTCONDITION) \ 1003 } while (B_FALSE) 1004 1005/* 1006 * Allow drivers to perform optimised 128-bit doorbell writes. 1007 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1008 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1009 * the need for locking in the host, and are the only ones known to be safe to 1010 * use 128-bites write with. 1011 */ 1012#define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1013 do { \ 1014 EFX_CHECK_REG((_enp), (_reg)); \ 1015 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \ 1016 const char *, \ 1017 #_reg, \ 1018 uint32_t, (_index), \ 1019 uint32_t, _reg ## _OFST, \ 1020 uint32_t, (_eop)->eo_u32[3], \ 1021 uint32_t, (_eop)->eo_u32[2], \ 1022 uint32_t, (_eop)->eo_u32[1], \ 1023 uint32_t, (_eop)->eo_u32[0]); \ 1024 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1025 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1026 (_eop)); \ 1027 _NOTE(CONSTANTCONDITION) \ 1028 } while (B_FALSE) 1029 1030#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \ 1031 do { \ 1032 unsigned int _new = (_wptr); \ 1033 unsigned int _old = (_owptr); \ 1034 \ 1035 if ((_new) >= (_old)) \ 1036 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1037 (_old) * sizeof (efx_desc_t), \ 1038 ((_new) - (_old)) * sizeof (efx_desc_t)); \ 1039 else \ 1040 /* \ 1041 * It is cheaper to sync entire map than sync \ 1042 * two parts especially when offset/size are \ 1043 * ignored and entire map is synced in any case.\ 1044 */ \ 1045 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1046 0, \ 1047 (_entries) * sizeof (efx_desc_t)); \ 1048 _NOTE(CONSTANTCONDITION) \ 1049 } while (B_FALSE) 1050 1051extern __checkReturn efx_rc_t 1052efx_nic_biu_test( 1053 __in efx_nic_t *enp); 1054 1055extern __checkReturn efx_rc_t 1056efx_mac_select( 1057 __in efx_nic_t *enp); 1058 1059extern void 1060efx_mac_multicast_hash_compute( 1061 __in_ecount(6*count) uint8_t const *addrs, 1062 __in int count, 1063 __out efx_oword_t *hash_low, 1064 __out efx_oword_t *hash_high); 1065 1066extern __checkReturn efx_rc_t 1067efx_phy_probe( 1068 __in efx_nic_t *enp); 1069 1070extern void 1071efx_phy_unprobe( 1072 __in efx_nic_t *enp); 1073 1074#if EFSYS_OPT_VPD 1075 1076/* VPD utility functions */ 1077 1078extern __checkReturn efx_rc_t 1079efx_vpd_hunk_length( 1080 __in_bcount(size) caddr_t data, 1081 __in size_t size, 1082 __out size_t *lengthp); 1083 1084extern __checkReturn efx_rc_t 1085efx_vpd_hunk_verify( 1086 __in_bcount(size) caddr_t data, 1087 __in size_t size, 1088 __out_opt boolean_t *cksummedp); 1089 1090extern __checkReturn efx_rc_t 1091efx_vpd_hunk_reinit( 1092 __in_bcount(size) caddr_t data, 1093 __in size_t size, 1094 __in boolean_t wantpid); 1095 1096extern __checkReturn efx_rc_t 1097efx_vpd_hunk_get( 1098 __in_bcount(size) caddr_t data, 1099 __in size_t size, 1100 __in efx_vpd_tag_t tag, 1101 __in efx_vpd_keyword_t keyword, 1102 __out unsigned int *payloadp, 1103 __out uint8_t *paylenp); 1104 1105extern __checkReturn efx_rc_t 1106efx_vpd_hunk_next( 1107 __in_bcount(size) caddr_t data, 1108 __in size_t size, 1109 __out efx_vpd_tag_t *tagp, 1110 __out efx_vpd_keyword_t *keyword, 1111 __out_bcount_opt(*paylenp) unsigned int *payloadp, 1112 __out_opt uint8_t *paylenp, 1113 __inout unsigned int *contp); 1114 1115extern __checkReturn efx_rc_t 1116efx_vpd_hunk_set( 1117 __in_bcount(size) caddr_t data, 1118 __in size_t size, 1119 __in efx_vpd_value_t *evvp); 1120 1121#endif /* EFSYS_OPT_VPD */ 1122 1123#if EFSYS_OPT_DIAG 1124 1125extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[]; 1126 1127typedef struct efx_register_set_s { 1128 unsigned int address; 1129 unsigned int step; 1130 unsigned int rows; 1131 efx_oword_t mask; 1132} efx_register_set_t; 1133 1134extern __checkReturn efx_rc_t 1135efx_nic_test_registers( 1136 __in efx_nic_t *enp, 1137 __in efx_register_set_t *rsp, 1138 __in size_t count); 1139 1140extern __checkReturn efx_rc_t 1141efx_nic_test_tables( 1142 __in efx_nic_t *enp, 1143 __in efx_register_set_t *rsp, 1144 __in efx_pattern_type_t pattern, 1145 __in size_t count); 1146 1147#endif /* EFSYS_OPT_DIAG */ 1148 1149#if EFSYS_OPT_MCDI 1150 1151extern __checkReturn efx_rc_t 1152efx_mcdi_set_workaround( 1153 __in efx_nic_t *enp, 1154 __in uint32_t type, 1155 __in boolean_t enabled, 1156 __out_opt uint32_t *flagsp); 1157 1158extern __checkReturn efx_rc_t 1159efx_mcdi_get_workarounds( 1160 __in efx_nic_t *enp, 1161 __out_opt uint32_t *implementedp, 1162 __out_opt uint32_t *enabledp); 1163 1164#endif /* EFSYS_OPT_MCDI */ 1165 1166#ifdef __cplusplus 1167} 1168#endif 1169 1170#endif /* _SYS_EFX_IMPL_H */
| 466} efx_mcdi_ops_t; 467 468typedef struct efx_mcdi_s { 469 efx_mcdi_ops_t *em_emcop; 470 const efx_mcdi_transport_t *em_emtp; 471 efx_mcdi_iface_t em_emip; 472} efx_mcdi_t; 473 474#endif /* EFSYS_OPT_MCDI */ 475 476#if EFSYS_OPT_NVRAM 477typedef struct efx_nvram_ops_s { 478#if EFSYS_OPT_DIAG 479 efx_rc_t (*envo_test)(efx_nic_t *); 480#endif /* EFSYS_OPT_DIAG */ 481 efx_rc_t (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *); 482 efx_rc_t (*envo_get_version)(efx_nic_t *, efx_nvram_type_t, 483 uint32_t *, uint16_t *); 484 efx_rc_t (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *); 485 efx_rc_t (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t, 486 unsigned int, caddr_t, size_t); 487 efx_rc_t (*envo_erase)(efx_nic_t *, efx_nvram_type_t); 488 efx_rc_t (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t, 489 unsigned int, caddr_t, size_t); 490 void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t); 491 efx_rc_t (*envo_set_version)(efx_nic_t *, efx_nvram_type_t, 492 uint16_t *); 493 494} efx_nvram_ops_t; 495#endif /* EFSYS_OPT_NVRAM */ 496 497#if EFSYS_OPT_VPD 498typedef struct efx_vpd_ops_s { 499 efx_rc_t (*evpdo_init)(efx_nic_t *); 500 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 501 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 502 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 503 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 504 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 505 efx_vpd_value_t *); 506 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 507 efx_vpd_value_t *); 508 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 509 efx_vpd_value_t *, unsigned int *); 510 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 511 void (*evpdo_fini)(efx_nic_t *); 512} efx_vpd_ops_t; 513#endif /* EFSYS_OPT_VPD */ 514 515#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 516 517 __checkReturn efx_rc_t 518efx_mcdi_nvram_partitions( 519 __in efx_nic_t *enp, 520 __out_bcount(size) caddr_t data, 521 __in size_t size, 522 __out unsigned int *npartnp); 523 524 __checkReturn efx_rc_t 525efx_mcdi_nvram_metadata( 526 __in efx_nic_t *enp, 527 __in uint32_t partn, 528 __out uint32_t *subtypep, 529 __out_ecount(4) uint16_t version[4], 530 __out_bcount_opt(size) char *descp, 531 __in size_t size); 532 533 __checkReturn efx_rc_t 534efx_mcdi_nvram_info( 535 __in efx_nic_t *enp, 536 __in uint32_t partn, 537 __out_opt size_t *sizep, 538 __out_opt uint32_t *addressp, 539 __out_opt uint32_t *erase_sizep); 540 541 __checkReturn efx_rc_t 542efx_mcdi_nvram_update_start( 543 __in efx_nic_t *enp, 544 __in uint32_t partn); 545 546 __checkReturn efx_rc_t 547efx_mcdi_nvram_read( 548 __in efx_nic_t *enp, 549 __in uint32_t partn, 550 __in uint32_t offset, 551 __out_bcount(size) caddr_t data, 552 __in size_t size); 553 554 __checkReturn efx_rc_t 555efx_mcdi_nvram_erase( 556 __in efx_nic_t *enp, 557 __in uint32_t partn, 558 __in uint32_t offset, 559 __in size_t size); 560 561 __checkReturn efx_rc_t 562efx_mcdi_nvram_write( 563 __in efx_nic_t *enp, 564 __in uint32_t partn, 565 __in uint32_t offset, 566 __out_bcount(size) caddr_t data, 567 __in size_t size); 568 569 __checkReturn efx_rc_t 570efx_mcdi_nvram_update_finish( 571 __in efx_nic_t *enp, 572 __in uint32_t partn, 573 __in boolean_t reboot); 574 575#if EFSYS_OPT_DIAG 576 577 __checkReturn efx_rc_t 578efx_mcdi_nvram_test( 579 __in efx_nic_t *enp, 580 __in uint32_t partn); 581 582#endif /* EFSYS_OPT_DIAG */ 583 584#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 585 586typedef struct efx_drv_cfg_s { 587 uint32_t edc_min_vi_count; 588 uint32_t edc_max_vi_count; 589 590 uint32_t edc_max_piobuf_count; 591 uint32_t edc_pio_alloc_size; 592} efx_drv_cfg_t; 593 594struct efx_nic_s { 595 uint32_t en_magic; 596 efx_family_t en_family; 597 uint32_t en_features; 598 efsys_identifier_t *en_esip; 599 efsys_lock_t *en_eslp; 600 efsys_bar_t *en_esbp; 601 unsigned int en_mod_flags; 602 unsigned int en_reset_flags; 603 efx_nic_cfg_t en_nic_cfg; 604 efx_drv_cfg_t en_drv_cfg; 605 efx_port_t en_port; 606 efx_mon_t en_mon; 607 efx_intr_t en_intr; 608 uint32_t en_ev_qcount; 609 uint32_t en_rx_qcount; 610 uint32_t en_tx_qcount; 611 efx_nic_ops_t *en_enop; 612 efx_ev_ops_t *en_eevop; 613 efx_tx_ops_t *en_etxop; 614 efx_rx_ops_t *en_erxop; 615#if EFSYS_OPT_FILTER 616 efx_filter_t en_filter; 617 efx_filter_ops_t *en_efop; 618#endif /* EFSYS_OPT_FILTER */ 619 efx_pktfilter_ops_t *en_epfop; 620#if EFSYS_OPT_MCDI 621 efx_mcdi_t en_mcdi; 622#endif /* EFSYS_OPT_MCDI */ 623#if EFSYS_OPT_NVRAM 624 efx_nvram_type_t en_nvram_locked; 625 efx_nvram_ops_t *en_envop; 626#endif /* EFSYS_OPT_NVRAM */ 627#if EFSYS_OPT_VPD 628 efx_vpd_ops_t *en_evpdop; 629#endif /* EFSYS_OPT_VPD */ 630#if EFSYS_OPT_RX_SCALE 631 efx_rx_hash_support_t en_hash_support; 632 efx_rx_scale_support_t en_rss_support; 633 uint32_t en_rss_context; 634#endif /* EFSYS_OPT_RX_SCALE */ 635 uint32_t en_vport_id; 636 union { 637#if EFSYS_OPT_FALCON 638 struct { 639 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES]; 640 falcon_i2c_t enu_fip; 641 boolean_t enu_i2c_locked; 642#if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE 643 const uint8_t *enu_forced_cfg; 644#endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */ 645 uint8_t enu_mon_devid; 646#if EFSYS_OPT_PCIE_TUNE 647 unsigned int enu_nlanes; 648#endif /* EFSYS_OPT_PCIE_TUNE */ 649 uint16_t enu_board_rev; 650 boolean_t enu_internal_sram; 651 uint8_t enu_sram_num_bank; 652 uint8_t enu_sram_bank_size; 653 } falcon; 654#endif /* EFSYS_OPT_FALCON */ 655#if EFSYS_OPT_SIENA 656 struct { 657#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 658 unsigned int enu_partn_mask; 659#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 660#if EFSYS_OPT_VPD 661 caddr_t enu_svpd; 662 size_t enu_svpd_length; 663#endif /* EFSYS_OPT_VPD */ 664 int enu_unused; 665 } siena; 666#endif /* EFSYS_OPT_SIENA */ 667#if EFSYS_OPT_HUNTINGTON 668 struct { 669 int enu_vi_base; 670 int enu_vi_count; 671#if EFSYS_OPT_VPD 672 caddr_t enu_svpd; 673 size_t enu_svpd_length; 674#endif /* EFSYS_OPT_VPD */ 675 efx_piobuf_handle_t enu_piobuf_handle[HUNT_PIOBUF_NBUFS]; 676 uint32_t enu_piobuf_count; 677 uint32_t enu_pio_alloc_map[HUNT_PIOBUF_NBUFS]; 678 uint32_t enu_pio_write_vi_base; 679 /* Memory BAR mapping regions */ 680 uint32_t enu_uc_mem_map_offset; 681 size_t enu_uc_mem_map_size; 682 uint32_t enu_wc_mem_map_offset; 683 size_t enu_wc_mem_map_size; 684 } hunt; 685#endif /* EFSYS_OPT_HUNTINGTON */ 686 } en_u; 687}; 688 689 690#define EFX_NIC_MAGIC 0x02121996 691 692typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 693 const efx_ev_callbacks_t *, void *); 694 695typedef struct efx_evq_rxq_state_s { 696 unsigned int eers_rx_read_ptr; 697 unsigned int eers_rx_mask; 698} efx_evq_rxq_state_t; 699 700struct efx_evq_s { 701 uint32_t ee_magic; 702 efx_nic_t *ee_enp; 703 unsigned int ee_index; 704 unsigned int ee_mask; 705 efsys_mem_t *ee_esmp; 706#if EFSYS_OPT_QSTATS 707 uint32_t ee_stat[EV_NQSTATS]; 708#endif /* EFSYS_OPT_QSTATS */ 709 710 efx_ev_handler_t ee_rx; 711 efx_ev_handler_t ee_tx; 712 efx_ev_handler_t ee_driver; 713 efx_ev_handler_t ee_global; 714 efx_ev_handler_t ee_drv_gen; 715#if EFSYS_OPT_MCDI 716 efx_ev_handler_t ee_mcdi; 717#endif /* EFSYS_OPT_MCDI */ 718 719 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 720}; 721 722#define EFX_EVQ_MAGIC 0x08081997 723 724#define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */ 725#define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 726 727struct efx_rxq_s { 728 uint32_t er_magic; 729 efx_nic_t *er_enp; 730 efx_evq_t *er_eep; 731 unsigned int er_index; 732 unsigned int er_label; 733 unsigned int er_mask; 734 efsys_mem_t *er_esmp; 735}; 736 737#define EFX_RXQ_MAGIC 0x15022005 738 739struct efx_txq_s { 740 uint32_t et_magic; 741 efx_nic_t *et_enp; 742 unsigned int et_index; 743 unsigned int et_mask; 744 efsys_mem_t *et_esmp; 745#if EFSYS_OPT_HUNTINGTON 746 uint32_t et_pio_bufnum; 747 uint32_t et_pio_blknum; 748 uint32_t et_pio_write_offset; 749 uint32_t et_pio_offset; 750 size_t et_pio_size; 751#endif 752#if EFSYS_OPT_QSTATS 753 uint32_t et_stat[TX_NQSTATS]; 754#endif /* EFSYS_OPT_QSTATS */ 755}; 756 757#define EFX_TXQ_MAGIC 0x05092005 758 759#define EFX_MAC_ADDR_COPY(_dst, _src) \ 760 do { \ 761 (_dst)[0] = (_src)[0]; \ 762 (_dst)[1] = (_src)[1]; \ 763 (_dst)[2] = (_src)[2]; \ 764 (_dst)[3] = (_src)[3]; \ 765 (_dst)[4] = (_src)[4]; \ 766 (_dst)[5] = (_src)[5]; \ 767 _NOTE(CONSTANTCONDITION) \ 768 } while (B_FALSE) 769 770#define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 771 do { \ 772 uint16_t *_d = (uint16_t *)(_dst); \ 773 _d[0] = 0xffff; \ 774 _d[1] = 0xffff; \ 775 _d[2] = 0xffff; \ 776 _NOTE(CONSTANTCONDITION) \ 777 } while (B_FALSE) 778 779#if EFSYS_OPT_CHECK_REG 780#define EFX_CHECK_REG(_enp, _reg) \ 781 do { \ 782 const char *name = #_reg; \ 783 char min = name[4]; \ 784 char max = name[5]; \ 785 char rev; \ 786 \ 787 switch ((_enp)->en_family) { \ 788 case EFX_FAMILY_FALCON: \ 789 rev = 'B'; \ 790 break; \ 791 \ 792 case EFX_FAMILY_SIENA: \ 793 rev = 'C'; \ 794 break; \ 795 \ 796 case EFX_FAMILY_HUNTINGTON: \ 797 rev = 'D'; \ 798 break; \ 799 \ 800 default: \ 801 rev = '?'; \ 802 break; \ 803 } \ 804 \ 805 EFSYS_ASSERT3S(rev, >=, min); \ 806 EFSYS_ASSERT3S(rev, <=, max); \ 807 \ 808 _NOTE(CONSTANTCONDITION) \ 809 } while (B_FALSE) 810#else 811#define EFX_CHECK_REG(_enp, _reg) do { \ 812 _NOTE(CONSTANTCONDITION) \ 813 } while(B_FALSE) 814#endif 815 816#define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 817 do { \ 818 EFX_CHECK_REG((_enp), (_reg)); \ 819 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 820 (_edp), (_lock)); \ 821 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 822 uint32_t, _reg ## _OFST, \ 823 uint32_t, (_edp)->ed_u32[0]); \ 824 _NOTE(CONSTANTCONDITION) \ 825 } while (B_FALSE) 826 827#define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 828 do { \ 829 EFX_CHECK_REG((_enp), (_reg)); \ 830 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 831 uint32_t, _reg ## _OFST, \ 832 uint32_t, (_edp)->ed_u32[0]); \ 833 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 834 (_edp), (_lock)); \ 835 _NOTE(CONSTANTCONDITION) \ 836 } while (B_FALSE) 837 838#define EFX_BAR_READQ(_enp, _reg, _eqp) \ 839 do { \ 840 EFX_CHECK_REG((_enp), (_reg)); \ 841 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 842 (_eqp)); \ 843 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 844 uint32_t, _reg ## _OFST, \ 845 uint32_t, (_eqp)->eq_u32[1], \ 846 uint32_t, (_eqp)->eq_u32[0]); \ 847 _NOTE(CONSTANTCONDITION) \ 848 } while (B_FALSE) 849 850#define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 851 do { \ 852 EFX_CHECK_REG((_enp), (_reg)); \ 853 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 854 uint32_t, _reg ## _OFST, \ 855 uint32_t, (_eqp)->eq_u32[1], \ 856 uint32_t, (_eqp)->eq_u32[0]); \ 857 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 858 (_eqp)); \ 859 _NOTE(CONSTANTCONDITION) \ 860 } while (B_FALSE) 861 862#define EFX_BAR_READO(_enp, _reg, _eop) \ 863 do { \ 864 EFX_CHECK_REG((_enp), (_reg)); \ 865 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 866 (_eop), B_TRUE); \ 867 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 868 uint32_t, _reg ## _OFST, \ 869 uint32_t, (_eop)->eo_u32[3], \ 870 uint32_t, (_eop)->eo_u32[2], \ 871 uint32_t, (_eop)->eo_u32[1], \ 872 uint32_t, (_eop)->eo_u32[0]); \ 873 _NOTE(CONSTANTCONDITION) \ 874 } while (B_FALSE) 875 876#define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 877 do { \ 878 EFX_CHECK_REG((_enp), (_reg)); \ 879 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 880 uint32_t, _reg ## _OFST, \ 881 uint32_t, (_eop)->eo_u32[3], \ 882 uint32_t, (_eop)->eo_u32[2], \ 883 uint32_t, (_eop)->eo_u32[1], \ 884 uint32_t, (_eop)->eo_u32[0]); \ 885 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 886 (_eop), B_TRUE); \ 887 _NOTE(CONSTANTCONDITION) \ 888 } while (B_FALSE) 889 890#define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 891 do { \ 892 EFX_CHECK_REG((_enp), (_reg)); \ 893 EFSYS_BAR_READD((_enp)->en_esbp, \ 894 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 895 (_edp), (_lock)); \ 896 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 897 uint32_t, (_index), \ 898 uint32_t, _reg ## _OFST, \ 899 uint32_t, (_edp)->ed_u32[0]); \ 900 _NOTE(CONSTANTCONDITION) \ 901 } while (B_FALSE) 902 903#define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 904 do { \ 905 EFX_CHECK_REG((_enp), (_reg)); \ 906 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 907 uint32_t, (_index), \ 908 uint32_t, _reg ## _OFST, \ 909 uint32_t, (_edp)->ed_u32[0]); \ 910 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 911 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 912 (_edp), (_lock)); \ 913 _NOTE(CONSTANTCONDITION) \ 914 } while (B_FALSE) 915 916#define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \ 917 do { \ 918 EFX_CHECK_REG((_enp), (_reg)); \ 919 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 920 uint32_t, (_index), \ 921 uint32_t, _reg ## _OFST, \ 922 uint32_t, (_edp)->ed_u32[0]); \ 923 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 924 (_reg ## _OFST + \ 925 (2 * sizeof (efx_dword_t)) + \ 926 ((_index) * _reg ## _STEP)), \ 927 (_edp), (_lock)); \ 928 _NOTE(CONSTANTCONDITION) \ 929 } while (B_FALSE) 930 931#define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 932 do { \ 933 EFX_CHECK_REG((_enp), (_reg)); \ 934 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 935 uint32_t, (_index), \ 936 uint32_t, _reg ## _OFST, \ 937 uint32_t, (_edp)->ed_u32[0]); \ 938 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 939 (_reg ## _OFST + \ 940 (3 * sizeof (efx_dword_t)) + \ 941 ((_index) * _reg ## _STEP)), \ 942 (_edp), (_lock)); \ 943 _NOTE(CONSTANTCONDITION) \ 944 } while (B_FALSE) 945 946#define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 947 do { \ 948 EFX_CHECK_REG((_enp), (_reg)); \ 949 EFSYS_BAR_READQ((_enp)->en_esbp, \ 950 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 951 (_eqp)); \ 952 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 953 uint32_t, (_index), \ 954 uint32_t, _reg ## _OFST, \ 955 uint32_t, (_eqp)->eq_u32[1], \ 956 uint32_t, (_eqp)->eq_u32[0]); \ 957 _NOTE(CONSTANTCONDITION) \ 958 } while (B_FALSE) 959 960#define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 961 do { \ 962 EFX_CHECK_REG((_enp), (_reg)); \ 963 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 964 uint32_t, (_index), \ 965 uint32_t, _reg ## _OFST, \ 966 uint32_t, (_eqp)->eq_u32[1], \ 967 uint32_t, (_eqp)->eq_u32[0]); \ 968 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 969 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 970 (_eqp)); \ 971 _NOTE(CONSTANTCONDITION) \ 972 } while (B_FALSE) 973 974#define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 975 do { \ 976 EFX_CHECK_REG((_enp), (_reg)); \ 977 EFSYS_BAR_READO((_enp)->en_esbp, \ 978 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 979 (_eop), (_lock)); \ 980 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 981 uint32_t, (_index), \ 982 uint32_t, _reg ## _OFST, \ 983 uint32_t, (_eop)->eo_u32[3], \ 984 uint32_t, (_eop)->eo_u32[2], \ 985 uint32_t, (_eop)->eo_u32[1], \ 986 uint32_t, (_eop)->eo_u32[0]); \ 987 _NOTE(CONSTANTCONDITION) \ 988 } while (B_FALSE) 989 990#define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 991 do { \ 992 EFX_CHECK_REG((_enp), (_reg)); \ 993 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 994 uint32_t, (_index), \ 995 uint32_t, _reg ## _OFST, \ 996 uint32_t, (_eop)->eo_u32[3], \ 997 uint32_t, (_eop)->eo_u32[2], \ 998 uint32_t, (_eop)->eo_u32[1], \ 999 uint32_t, (_eop)->eo_u32[0]); \ 1000 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1001 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1002 (_eop), (_lock)); \ 1003 _NOTE(CONSTANTCONDITION) \ 1004 } while (B_FALSE) 1005 1006/* 1007 * Allow drivers to perform optimised 128-bit doorbell writes. 1008 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1009 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1010 * the need for locking in the host, and are the only ones known to be safe to 1011 * use 128-bites write with. 1012 */ 1013#define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1014 do { \ 1015 EFX_CHECK_REG((_enp), (_reg)); \ 1016 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \ 1017 const char *, \ 1018 #_reg, \ 1019 uint32_t, (_index), \ 1020 uint32_t, _reg ## _OFST, \ 1021 uint32_t, (_eop)->eo_u32[3], \ 1022 uint32_t, (_eop)->eo_u32[2], \ 1023 uint32_t, (_eop)->eo_u32[1], \ 1024 uint32_t, (_eop)->eo_u32[0]); \ 1025 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1026 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1027 (_eop)); \ 1028 _NOTE(CONSTANTCONDITION) \ 1029 } while (B_FALSE) 1030 1031#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \ 1032 do { \ 1033 unsigned int _new = (_wptr); \ 1034 unsigned int _old = (_owptr); \ 1035 \ 1036 if ((_new) >= (_old)) \ 1037 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1038 (_old) * sizeof (efx_desc_t), \ 1039 ((_new) - (_old)) * sizeof (efx_desc_t)); \ 1040 else \ 1041 /* \ 1042 * It is cheaper to sync entire map than sync \ 1043 * two parts especially when offset/size are \ 1044 * ignored and entire map is synced in any case.\ 1045 */ \ 1046 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1047 0, \ 1048 (_entries) * sizeof (efx_desc_t)); \ 1049 _NOTE(CONSTANTCONDITION) \ 1050 } while (B_FALSE) 1051 1052extern __checkReturn efx_rc_t 1053efx_nic_biu_test( 1054 __in efx_nic_t *enp); 1055 1056extern __checkReturn efx_rc_t 1057efx_mac_select( 1058 __in efx_nic_t *enp); 1059 1060extern void 1061efx_mac_multicast_hash_compute( 1062 __in_ecount(6*count) uint8_t const *addrs, 1063 __in int count, 1064 __out efx_oword_t *hash_low, 1065 __out efx_oword_t *hash_high); 1066 1067extern __checkReturn efx_rc_t 1068efx_phy_probe( 1069 __in efx_nic_t *enp); 1070 1071extern void 1072efx_phy_unprobe( 1073 __in efx_nic_t *enp); 1074 1075#if EFSYS_OPT_VPD 1076 1077/* VPD utility functions */ 1078 1079extern __checkReturn efx_rc_t 1080efx_vpd_hunk_length( 1081 __in_bcount(size) caddr_t data, 1082 __in size_t size, 1083 __out size_t *lengthp); 1084 1085extern __checkReturn efx_rc_t 1086efx_vpd_hunk_verify( 1087 __in_bcount(size) caddr_t data, 1088 __in size_t size, 1089 __out_opt boolean_t *cksummedp); 1090 1091extern __checkReturn efx_rc_t 1092efx_vpd_hunk_reinit( 1093 __in_bcount(size) caddr_t data, 1094 __in size_t size, 1095 __in boolean_t wantpid); 1096 1097extern __checkReturn efx_rc_t 1098efx_vpd_hunk_get( 1099 __in_bcount(size) caddr_t data, 1100 __in size_t size, 1101 __in efx_vpd_tag_t tag, 1102 __in efx_vpd_keyword_t keyword, 1103 __out unsigned int *payloadp, 1104 __out uint8_t *paylenp); 1105 1106extern __checkReturn efx_rc_t 1107efx_vpd_hunk_next( 1108 __in_bcount(size) caddr_t data, 1109 __in size_t size, 1110 __out efx_vpd_tag_t *tagp, 1111 __out efx_vpd_keyword_t *keyword, 1112 __out_bcount_opt(*paylenp) unsigned int *payloadp, 1113 __out_opt uint8_t *paylenp, 1114 __inout unsigned int *contp); 1115 1116extern __checkReturn efx_rc_t 1117efx_vpd_hunk_set( 1118 __in_bcount(size) caddr_t data, 1119 __in size_t size, 1120 __in efx_vpd_value_t *evvp); 1121 1122#endif /* EFSYS_OPT_VPD */ 1123 1124#if EFSYS_OPT_DIAG 1125 1126extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[]; 1127 1128typedef struct efx_register_set_s { 1129 unsigned int address; 1130 unsigned int step; 1131 unsigned int rows; 1132 efx_oword_t mask; 1133} efx_register_set_t; 1134 1135extern __checkReturn efx_rc_t 1136efx_nic_test_registers( 1137 __in efx_nic_t *enp, 1138 __in efx_register_set_t *rsp, 1139 __in size_t count); 1140 1141extern __checkReturn efx_rc_t 1142efx_nic_test_tables( 1143 __in efx_nic_t *enp, 1144 __in efx_register_set_t *rsp, 1145 __in efx_pattern_type_t pattern, 1146 __in size_t count); 1147 1148#endif /* EFSYS_OPT_DIAG */ 1149 1150#if EFSYS_OPT_MCDI 1151 1152extern __checkReturn efx_rc_t 1153efx_mcdi_set_workaround( 1154 __in efx_nic_t *enp, 1155 __in uint32_t type, 1156 __in boolean_t enabled, 1157 __out_opt uint32_t *flagsp); 1158 1159extern __checkReturn efx_rc_t 1160efx_mcdi_get_workarounds( 1161 __in efx_nic_t *enp, 1162 __out_opt uint32_t *implementedp, 1163 __out_opt uint32_t *enabledp); 1164 1165#endif /* EFSYS_OPT_MCDI */ 1166 1167#ifdef __cplusplus 1168} 1169#endif 1170 1171#endif /* _SYS_EFX_IMPL_H */
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