1/*-
2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: head/sys/dev/sfxge/common/efx_impl.h 299318 2016-05-10 06:51:20Z arybchik $
31 */
32
33#ifndef _SYS_EFX_IMPL_H
34#define _SYS_EFX_IMPL_H
35
36#include "efsys.h"
37#include "efx_check.h"
38#include "efx.h"
39#include "efx_regs.h"
40#include "efx_regs_ef10.h"
41
42/* FIXME: Add definition for driver generated software events */
43#ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
44#define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
45#endif
46
47
48#if EFSYS_OPT_FALCON
49#include "falcon_impl.h"
50#endif /* EFSYS_OPT_FALCON */
51
52#if EFSYS_OPT_SIENA
53#include "siena_impl.h"
54#endif /* EFSYS_OPT_SIENA */
55
56#if EFSYS_OPT_HUNTINGTON
57#include "hunt_impl.h"
58#endif /* EFSYS_OPT_HUNTINGTON */
59
60#if EFSYS_OPT_MEDFORD
61#include "medford_impl.h"
62#endif /* EFSYS_OPT_MEDFORD */
63
64#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
65#include "ef10_impl.h"
66#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
67
68#ifdef __cplusplus
69extern "C" {
70#endif
71
72#define EFX_MOD_MCDI 0x00000001
73#define EFX_MOD_PROBE 0x00000002
74#define EFX_MOD_NVRAM 0x00000004
75#define EFX_MOD_VPD 0x00000008
76#define EFX_MOD_NIC 0x00000010
77#define EFX_MOD_INTR 0x00000020
78#define EFX_MOD_EV 0x00000040
79#define EFX_MOD_RX 0x00000080
80#define EFX_MOD_TX 0x00000100
81#define EFX_MOD_PORT 0x00000200
82#define EFX_MOD_MON 0x00000400
83#define EFX_MOD_WOL 0x00000800
84#define EFX_MOD_FILTER 0x00001000
85#define EFX_MOD_PKTFILTER 0x00002000
86#define EFX_MOD_LIC 0x00004000
87
88#define EFX_RESET_MAC 0x00000001
89#define EFX_RESET_PHY 0x00000002
90#define EFX_RESET_RXQ_ERR 0x00000004
91#define EFX_RESET_TXQ_ERR 0x00000008
92
93typedef enum efx_mac_type_e {
94 EFX_MAC_INVALID = 0,
95 EFX_MAC_FALCON_GMAC,
96 EFX_MAC_FALCON_XMAC,
97 EFX_MAC_SIENA,
98 EFX_MAC_HUNTINGTON,
99 EFX_MAC_MEDFORD,
100 EFX_MAC_NTYPES
101} efx_mac_type_t;
102
103typedef struct efx_ev_ops_s {
104 efx_rc_t (*eevo_init)(efx_nic_t *);
105 void (*eevo_fini)(efx_nic_t *);
106 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
107 efsys_mem_t *, size_t, uint32_t,
108 efx_evq_t *);
109 void (*eevo_qdestroy)(efx_evq_t *);
110 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
111 void (*eevo_qpost)(efx_evq_t *, uint16_t);
112 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
113#if EFSYS_OPT_QSTATS
114 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
115#endif
116} efx_ev_ops_t;
117
118typedef struct efx_tx_ops_s {
119 efx_rc_t (*etxo_init)(efx_nic_t *);
120 void (*etxo_fini)(efx_nic_t *);
121 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
122 unsigned int, unsigned int,
123 efsys_mem_t *, size_t,
124 uint32_t, uint16_t,
125 efx_evq_t *, efx_txq_t *,
126 unsigned int *);
127 void (*etxo_qdestroy)(efx_txq_t *);
128 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
129 unsigned int, unsigned int,
130 unsigned int *);
131 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
132 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
133 efx_rc_t (*etxo_qflush)(efx_txq_t *);
134 void (*etxo_qenable)(efx_txq_t *);
135 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
136 void (*etxo_qpio_disable)(efx_txq_t *);
137 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
138 size_t);
139 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
140 unsigned int *);
141 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
142 unsigned int, unsigned int,
143 unsigned int *);
144 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
145 size_t, boolean_t,
146 efx_desc_t *);
147 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
148 uint32_t, uint8_t,
149 efx_desc_t *);
150 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
151 uint32_t, uint16_t,
152 efx_desc_t *, int);
153 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
154 efx_desc_t *);
155#if EFSYS_OPT_QSTATS
156 void (*etxo_qstats_update)(efx_txq_t *,
157 efsys_stat_t *);
158#endif
159} efx_tx_ops_t;
160
161typedef struct efx_rx_ops_s {
162 efx_rc_t (*erxo_init)(efx_nic_t *);
163 void (*erxo_fini)(efx_nic_t *);
164#if EFSYS_OPT_RX_SCATTER
165 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
166#endif
167#if EFSYS_OPT_RX_SCALE
168 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
169 efx_rx_hash_type_t, boolean_t);
170 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
171 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
172 size_t);
173 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
174 uint8_t *);
175#endif /* EFSYS_OPT_RX_SCALE */
176 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
177 uint16_t *);
178 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
179 unsigned int, unsigned int,
180 unsigned int);
181 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
182 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
183 void (*erxo_qenable)(efx_rxq_t *);
184 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
185 unsigned int, efx_rxq_type_t,
186 efsys_mem_t *, size_t, uint32_t,
187 efx_evq_t *, efx_rxq_t *);
188 void (*erxo_qdestroy)(efx_rxq_t *);
189} efx_rx_ops_t;
190
191typedef struct efx_mac_ops_s {
192 efx_rc_t (*emo_reset)(efx_nic_t *); /* optional */
193 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
194 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
195 efx_rc_t (*emo_addr_set)(efx_nic_t *);
196 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
197 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
198 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
199 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
200 efx_rxq_t *, boolean_t);
201 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
202#if EFSYS_OPT_LOOPBACK
203 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
204 efx_loopback_type_t);
205#endif /* EFSYS_OPT_LOOPBACK */
206#if EFSYS_OPT_MAC_STATS
207 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
208 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
209 uint16_t, boolean_t);
210 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
211 efsys_stat_t *, uint32_t *);
212#endif /* EFSYS_OPT_MAC_STATS */
213} efx_mac_ops_t;
214
215typedef struct efx_phy_ops_s {
216 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
217 efx_rc_t (*epo_reset)(efx_nic_t *);
218 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
219 efx_rc_t (*epo_verify)(efx_nic_t *);
220 efx_rc_t (*epo_uplink_check)(efx_nic_t *,
221 boolean_t *); /* optional */
222 efx_rc_t (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
223 unsigned int *, uint32_t *);
224 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
225#if EFSYS_OPT_PHY_STATS
226 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
227 uint32_t *);
228#endif /* EFSYS_OPT_PHY_STATS */
229#if EFSYS_OPT_PHY_PROPS
230#if EFSYS_OPT_NAMES
231 const char *(*epo_prop_name)(efx_nic_t *, unsigned int);
232#endif /* EFSYS_OPT_PHY_PROPS */
233 efx_rc_t (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
234 uint32_t *);
235 efx_rc_t (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
236#endif /* EFSYS_OPT_PHY_PROPS */
237#if EFSYS_OPT_BIST
238 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
239 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
240 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
241 efx_bist_result_t *, uint32_t *,
242 unsigned long *, size_t);
243 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
244#endif /* EFSYS_OPT_BIST */
245} efx_phy_ops_t;
246
247#if EFSYS_OPT_FILTER
248typedef struct efx_filter_ops_s {
249 efx_rc_t (*efo_init)(efx_nic_t *);
250 void (*efo_fini)(efx_nic_t *);
251 efx_rc_t (*efo_restore)(efx_nic_t *);
252 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
253 boolean_t may_replace);
254 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
255 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
256 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
257 boolean_t, boolean_t, boolean_t,
258 uint8_t const *, int);
259} efx_filter_ops_t;
260
261extern __checkReturn efx_rc_t
262efx_filter_reconfigure(
263 __in efx_nic_t *enp,
264 __in_ecount(6) uint8_t const *mac_addr,
265 __in boolean_t all_unicst,
266 __in boolean_t mulcst,
267 __in boolean_t all_mulcst,
268 __in boolean_t brdcst,
269 __in_ecount(6*count) uint8_t const *addrs,
270 __in int count);
271
272#endif /* EFSYS_OPT_FILTER */
273
274
275typedef struct efx_port_s {
276 efx_mac_type_t ep_mac_type;
277 uint32_t ep_phy_type;
278 uint8_t ep_port;
279 uint32_t ep_mac_pdu;
280 uint8_t ep_mac_addr[6];
281 efx_link_mode_t ep_link_mode;
282 boolean_t ep_all_unicst;
283 boolean_t ep_mulcst;
284 boolean_t ep_all_mulcst;
285 boolean_t ep_brdcst;
286 unsigned int ep_fcntl;
287 boolean_t ep_fcntl_autoneg;
288 efx_oword_t ep_multicst_hash[2];
289 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
290 EFX_MAC_MULTICAST_LIST_MAX];
291 uint32_t ep_mulcst_addr_count;
292#if EFSYS_OPT_LOOPBACK
293 efx_loopback_type_t ep_loopback_type;
294 efx_link_mode_t ep_loopback_link_mode;
295#endif /* EFSYS_OPT_LOOPBACK */
296#if EFSYS_OPT_PHY_FLAGS
297 uint32_t ep_phy_flags;
298#endif /* EFSYS_OPT_PHY_FLAGS */
299#if EFSYS_OPT_PHY_LED_CONTROL
300 efx_phy_led_mode_t ep_phy_led_mode;
301#endif /* EFSYS_OPT_PHY_LED_CONTROL */
302 efx_phy_media_type_t ep_fixed_port_type;
303 efx_phy_media_type_t ep_module_type;
304 uint32_t ep_adv_cap_mask;
305 uint32_t ep_lp_cap_mask;
306 uint32_t ep_default_adv_cap_mask;
307 uint32_t ep_phy_cap_mask;
308#if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
309 union {
310 struct {
311 unsigned int bug10934_count;
312 } ep_txc43128;
313 struct {
314 unsigned int bug17190_count;
315 } ep_qt2025c;
316 };
317#endif
318 boolean_t ep_mac_poll_needed; /* falcon only */
319 boolean_t ep_mac_up; /* falcon only */
320 uint32_t ep_fwver; /* falcon only */
321 boolean_t ep_mac_drain;
322 boolean_t ep_mac_stats_pending;
323#if EFSYS_OPT_BIST
324 efx_bist_type_t ep_current_bist;
325#endif
326 efx_mac_ops_t *ep_emop;
327 efx_phy_ops_t *ep_epop;
328} efx_port_t;
329
330typedef struct efx_mon_ops_s {
331 efx_rc_t (*emo_reset)(efx_nic_t *);
332 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
333#if EFSYS_OPT_MON_STATS
334 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
335 efx_mon_stat_value_t *);
336#endif /* EFSYS_OPT_MON_STATS */
337} efx_mon_ops_t;
338
339typedef struct efx_mon_s {
340 efx_mon_type_t em_type;
341 efx_mon_ops_t *em_emop;
342} efx_mon_t;
343
344typedef struct efx_intr_ops_s {
345 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
346 void (*eio_enable)(efx_nic_t *);
347 void (*eio_disable)(efx_nic_t *);
348 void (*eio_disable_unlocked)(efx_nic_t *);
349 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
350 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
351 void (*eio_status_message)(efx_nic_t *, unsigned int,
352 boolean_t *);
353 void (*eio_fatal)(efx_nic_t *);
354 void (*eio_fini)(efx_nic_t *);
355} efx_intr_ops_t;
356
357typedef struct efx_intr_s {
358 efx_intr_ops_t *ei_eiop;
359 efsys_mem_t *ei_esmp;
360 efx_intr_type_t ei_type;
361 unsigned int ei_level;
362} efx_intr_t;
363
364typedef struct efx_nic_ops_s {
365 efx_rc_t (*eno_probe)(efx_nic_t *);
366 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
367 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
368 efx_rc_t (*eno_reset)(efx_nic_t *);
369 efx_rc_t (*eno_init)(efx_nic_t *);
370 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
371 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
372 uint32_t *, size_t *);
373#if EFSYS_OPT_DIAG
374 efx_rc_t (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
375 efx_rc_t (*eno_register_test)(efx_nic_t *);
376#endif /* EFSYS_OPT_DIAG */
377 void (*eno_fini)(efx_nic_t *);
378 void (*eno_unprobe)(efx_nic_t *);
379} efx_nic_ops_t;
380
381#ifndef EFX_TXQ_LIMIT_TARGET
382#define EFX_TXQ_LIMIT_TARGET 259
383#endif
384#ifndef EFX_RXQ_LIMIT_TARGET
385#define EFX_RXQ_LIMIT_TARGET 512
386#endif
387#ifndef EFX_TXQ_DC_SIZE
388#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
389#endif
390#ifndef EFX_RXQ_DC_SIZE
391#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
392#endif
393
394#if EFSYS_OPT_FILTER
395
396typedef struct falconsiena_filter_spec_s {
397 uint8_t fsfs_type;
398 uint32_t fsfs_flags;
399 uint32_t fsfs_dmaq_id;
400 uint32_t fsfs_dword[3];
401} falconsiena_filter_spec_t;
402
403typedef enum falconsiena_filter_type_e {
404 EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
405 EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */
406 EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
407 EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */
408
409#if EFSYS_OPT_SIENA
410 EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
411 EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
412
413 EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
414 EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
415 EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
416 EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */
417
418 EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */
419 EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */
420#endif /* EFSYS_OPT_SIENA */
421
422 EFX_FS_FILTER_NTYPES
423} falconsiena_filter_type_t;
424
425typedef enum falconsiena_filter_tbl_id_e {
426 EFX_FS_FILTER_TBL_RX_IP = 0,
427 EFX_FS_FILTER_TBL_RX_MAC,
428 EFX_FS_FILTER_TBL_TX_IP,
429 EFX_FS_FILTER_TBL_TX_MAC,
430 EFX_FS_FILTER_NTBLS
431} falconsiena_filter_tbl_id_t;
432
433typedef struct falconsiena_filter_tbl_s {
434 int fsft_size; /* number of entries */
435 int fsft_used; /* active count */
436 uint32_t *fsft_bitmap; /* active bitmap */
437 falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */
438} falconsiena_filter_tbl_t;
439
440typedef struct falconsiena_filter_s {
441 falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS];
442 unsigned int fsf_depth[EFX_FS_FILTER_NTYPES];
443} falconsiena_filter_t;
444
445typedef struct efx_filter_s {
446#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
447 falconsiena_filter_t *ef_falconsiena_filter;
448#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
449#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
450 ef10_filter_table_t *ef_ef10_filter_table;
451#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
452} efx_filter_t;
453
454extern void
455falconsiena_filter_tbl_clear(
456 __in efx_nic_t *enp,
457 __in falconsiena_filter_tbl_id_t tbl);
458
459#endif /* EFSYS_OPT_FILTER */
460
461#if EFSYS_OPT_MCDI
462
463typedef struct efx_mcdi_ops_s {
464 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
465 void (*emco_send_request)(efx_nic_t *, void *, size_t,
466 void *, size_t);
467 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
468 boolean_t (*emco_poll_response)(efx_nic_t *);
469 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
470 void (*emco_fini)(efx_nic_t *);
471 efx_rc_t (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
472} efx_mcdi_ops_t;
473
474typedef struct efx_mcdi_s {
475 efx_mcdi_ops_t *em_emcop;
476 const efx_mcdi_transport_t *em_emtp;
477 efx_mcdi_iface_t em_emip;
478} efx_mcdi_t;
479
480#endif /* EFSYS_OPT_MCDI */
481
482#if EFSYS_OPT_NVRAM
483typedef struct efx_nvram_ops_s {
484#if EFSYS_OPT_DIAG
485 efx_rc_t (*envo_test)(efx_nic_t *);
486#endif /* EFSYS_OPT_DIAG */
487 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
488 uint32_t *);
489 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
490 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
491 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
492 unsigned int, caddr_t, size_t);
493 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
494 unsigned int, size_t);
495 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
496 unsigned int, caddr_t, size_t);
497 void (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
498 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
499 uint32_t *, uint16_t *);
500 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
501 uint16_t *);
502 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t,
503 caddr_t, size_t);
504} efx_nvram_ops_t;
505#endif /* EFSYS_OPT_NVRAM */
506
507extern __checkReturn efx_rc_t
508efx_nvram_tlv_validate(
509 __in efx_nic_t *enp,
510 __in uint32_t partn,
511 __in_bcount(partn_size) caddr_t partn_data,
512 __in size_t partn_size);
513
514
515#if EFSYS_OPT_VPD
516typedef struct efx_vpd_ops_s {
517 efx_rc_t (*evpdo_init)(efx_nic_t *);
518 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
519 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
520 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
521 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
522 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
523 efx_vpd_value_t *);
524 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
525 efx_vpd_value_t *);
526 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
527 efx_vpd_value_t *, unsigned int *);
528 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
529 void (*evpdo_fini)(efx_nic_t *);
530} efx_vpd_ops_t;
531#endif /* EFSYS_OPT_VPD */
532
533#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
534
535 __checkReturn efx_rc_t
536efx_mcdi_nvram_partitions(
537 __in efx_nic_t *enp,
538 __out_bcount(size) caddr_t data,
539 __in size_t size,
540 __out unsigned int *npartnp);
541
542 __checkReturn efx_rc_t
543efx_mcdi_nvram_metadata(
544 __in efx_nic_t *enp,
545 __in uint32_t partn,
546 __out uint32_t *subtypep,
547 __out_ecount(4) uint16_t version[4],
548 __out_bcount_opt(size) char *descp,
549 __in size_t size);
550
551 __checkReturn efx_rc_t
552efx_mcdi_nvram_info(
553 __in efx_nic_t *enp,
554 __in uint32_t partn,
555 __out_opt size_t *sizep,
556 __out_opt uint32_t *addressp,
557 __out_opt uint32_t *erase_sizep,
558 __out_opt uint32_t *write_sizep);
559
560 __checkReturn efx_rc_t
561efx_mcdi_nvram_update_start(
562 __in efx_nic_t *enp,
563 __in uint32_t partn);
564
565 __checkReturn efx_rc_t
566efx_mcdi_nvram_read(
567 __in efx_nic_t *enp,
568 __in uint32_t partn,
569 __in uint32_t offset,
570 __out_bcount(size) caddr_t data,
571 __in size_t size,
572 __in uint32_t mode);
573
574 __checkReturn efx_rc_t
575efx_mcdi_nvram_erase(
576 __in efx_nic_t *enp,
577 __in uint32_t partn,
578 __in uint32_t offset,
579 __in size_t size);
580
581 __checkReturn efx_rc_t
582efx_mcdi_nvram_write(
583 __in efx_nic_t *enp,
584 __in uint32_t partn,
585 __in uint32_t offset,
586 __out_bcount(size) caddr_t data,
587 __in size_t size);
588
589 __checkReturn efx_rc_t
590efx_mcdi_nvram_update_finish(
591 __in efx_nic_t *enp,
592 __in uint32_t partn,
593 __in boolean_t reboot);
594
595#if EFSYS_OPT_DIAG
596
597 __checkReturn efx_rc_t
598efx_mcdi_nvram_test(
599 __in efx_nic_t *enp,
600 __in uint32_t partn);
601
602#endif /* EFSYS_OPT_DIAG */
603
604#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
605
606#if EFSYS_OPT_LICENSING
607
608typedef struct efx_lic_ops_s {
609 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
610 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
611 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
612 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
613 size_t *, uint8_t *);
614} efx_lic_ops_t;
615
616#endif
617
618typedef struct efx_drv_cfg_s {
619 uint32_t edc_min_vi_count;
620 uint32_t edc_max_vi_count;
621
622 uint32_t edc_max_piobuf_count;
623 uint32_t edc_pio_alloc_size;
624} efx_drv_cfg_t;
625
626struct efx_nic_s {
627 uint32_t en_magic;
628 efx_family_t en_family;
629 uint32_t en_features;
630 efsys_identifier_t *en_esip;
631 efsys_lock_t *en_eslp;
632 efsys_bar_t *en_esbp;
633 unsigned int en_mod_flags;
634 unsigned int en_reset_flags;
635 efx_nic_cfg_t en_nic_cfg;
636 efx_drv_cfg_t en_drv_cfg;
637 efx_port_t en_port;
638 efx_mon_t en_mon;
639 efx_intr_t en_intr;
640 uint32_t en_ev_qcount;
641 uint32_t en_rx_qcount;
642 uint32_t en_tx_qcount;
643 efx_nic_ops_t *en_enop;
644 efx_ev_ops_t *en_eevop;
645 efx_tx_ops_t *en_etxop;
646 efx_rx_ops_t *en_erxop;
647#if EFSYS_OPT_FILTER
648 efx_filter_t en_filter;
649 efx_filter_ops_t *en_efop;
650#endif /* EFSYS_OPT_FILTER */
651#if EFSYS_OPT_MCDI
652 efx_mcdi_t en_mcdi;
653#endif /* EFSYS_OPT_MCDI */
654#if EFSYS_OPT_NVRAM
655 efx_nvram_type_t en_nvram_locked;
656 efx_nvram_ops_t *en_envop;
657#endif /* EFSYS_OPT_NVRAM */
658#if EFSYS_OPT_VPD
659 efx_vpd_ops_t *en_evpdop;
660#endif /* EFSYS_OPT_VPD */
661#if EFSYS_OPT_RX_SCALE
662 efx_rx_hash_support_t en_hash_support;
663 efx_rx_scale_support_t en_rss_support;
664 uint32_t en_rss_context;
665#endif /* EFSYS_OPT_RX_SCALE */
666 uint32_t en_vport_id;
667#if EFSYS_OPT_LICENSING
668 efx_lic_ops_t *en_elop;
669#endif
670 union {
671#if EFSYS_OPT_FALCON
672 struct {
673 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES];
674 falcon_i2c_t enu_fip;
675 boolean_t enu_i2c_locked;
676#if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
677 const uint8_t *enu_forced_cfg;
678#endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
679 uint8_t enu_mon_devid;
680 uint16_t enu_board_rev;
681 boolean_t enu_internal_sram;
682 uint8_t enu_sram_num_bank;
683 uint8_t enu_sram_bank_size;
684 } falcon;
685#endif /* EFSYS_OPT_FALCON */
686#if EFSYS_OPT_SIENA
687 struct {
688#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
689 unsigned int enu_partn_mask;
690#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
691#if EFSYS_OPT_VPD
692 caddr_t enu_svpd;
693 size_t enu_svpd_length;
694#endif /* EFSYS_OPT_VPD */
695 int enu_unused;
696 } siena;
697#endif /* EFSYS_OPT_SIENA */
698 int enu_unused;
699 } en_u;
700#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
701 union en_arch {
702 struct {
703 int ena_vi_base;
704 int ena_vi_count;
705 int ena_vi_shift;
706#if EFSYS_OPT_VPD
707 caddr_t ena_svpd;
708 size_t ena_svpd_length;
709#endif /* EFSYS_OPT_VPD */
710 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
711 uint32_t ena_piobuf_count;
712 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
713 uint32_t ena_pio_write_vi_base;
714 /* Memory BAR mapping regions */
715 uint32_t ena_uc_mem_map_offset;
716 size_t ena_uc_mem_map_size;
717 uint32_t ena_wc_mem_map_offset;
718 size_t ena_wc_mem_map_size;
719 } ef10;
720 } en_arch;
721#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
722};
723
724
725#define EFX_NIC_MAGIC 0x02121996
726
727typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
728 const efx_ev_callbacks_t *, void *);
729
730typedef struct efx_evq_rxq_state_s {
731 unsigned int eers_rx_read_ptr;
732 unsigned int eers_rx_mask;
733} efx_evq_rxq_state_t;
734
735struct efx_evq_s {
736 uint32_t ee_magic;
737 efx_nic_t *ee_enp;
738 unsigned int ee_index;
739 unsigned int ee_mask;
740 efsys_mem_t *ee_esmp;
741#if EFSYS_OPT_QSTATS
742 uint32_t ee_stat[EV_NQSTATS];
743#endif /* EFSYS_OPT_QSTATS */
744
745 efx_ev_handler_t ee_rx;
746 efx_ev_handler_t ee_tx;
747 efx_ev_handler_t ee_driver;
748 efx_ev_handler_t ee_global;
749 efx_ev_handler_t ee_drv_gen;
750#if EFSYS_OPT_MCDI
751 efx_ev_handler_t ee_mcdi;
752#endif /* EFSYS_OPT_MCDI */
753
754 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
755};
756
757#define EFX_EVQ_MAGIC 0x08081997
758
759#define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
760#define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
761
762struct efx_rxq_s {
763 uint32_t er_magic;
764 efx_nic_t *er_enp;
765 efx_evq_t *er_eep;
766 unsigned int er_index;
767 unsigned int er_label;
768 unsigned int er_mask;
769 efsys_mem_t *er_esmp;
770};
771
772#define EFX_RXQ_MAGIC 0x15022005
773
774struct efx_txq_s {
775 uint32_t et_magic;
776 efx_nic_t *et_enp;
777 unsigned int et_index;
778 unsigned int et_mask;
779 efsys_mem_t *et_esmp;
780#if EFSYS_OPT_HUNTINGTON
781 uint32_t et_pio_bufnum;
782 uint32_t et_pio_blknum;
783 uint32_t et_pio_write_offset;
784 uint32_t et_pio_offset;
785 size_t et_pio_size;
786#endif
787#if EFSYS_OPT_QSTATS
788 uint32_t et_stat[TX_NQSTATS];
789#endif /* EFSYS_OPT_QSTATS */
790};
791
792#define EFX_TXQ_MAGIC 0x05092005
793
794#define EFX_MAC_ADDR_COPY(_dst, _src) \
795 do { \
796 (_dst)[0] = (_src)[0]; \
797 (_dst)[1] = (_src)[1]; \
798 (_dst)[2] = (_src)[2]; \
799 (_dst)[3] = (_src)[3]; \
800 (_dst)[4] = (_src)[4]; \
801 (_dst)[5] = (_src)[5]; \
802 _NOTE(CONSTANTCONDITION) \
803 } while (B_FALSE)
804
805#define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
806 do { \
807 uint16_t *_d = (uint16_t *)(_dst); \
808 _d[0] = 0xffff; \
809 _d[1] = 0xffff; \
810 _d[2] = 0xffff; \
811 _NOTE(CONSTANTCONDITION) \
812 } while (B_FALSE)
813
814#if EFSYS_OPT_CHECK_REG
815#define EFX_CHECK_REG(_enp, _reg) \
816 do { \
817 const char *name = #_reg; \
818 char min = name[4]; \
819 char max = name[5]; \
820 char rev; \
821 \
822 switch ((_enp)->en_family) { \
823 case EFX_FAMILY_FALCON: \
824 rev = 'B'; \
825 break; \
826 \
827 case EFX_FAMILY_SIENA: \
828 rev = 'C'; \
829 break; \
830 \
831 case EFX_FAMILY_HUNTINGTON: \
832 rev = 'D'; \
833 break; \
834 \
835 case EFX_FAMILY_MEDFORD: \
836 rev = 'E'; \
837 break; \
838 \
839 default: \
840 rev = '?'; \
841 break; \
842 } \
843 \
844 EFSYS_ASSERT3S(rev, >=, min); \
845 EFSYS_ASSERT3S(rev, <=, max); \
846 \
847 _NOTE(CONSTANTCONDITION) \
848 } while (B_FALSE)
849#else
850#define EFX_CHECK_REG(_enp, _reg) do { \
851 _NOTE(CONSTANTCONDITION) \
852 } while(B_FALSE)
853#endif
854
855#define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
856 do { \
857 EFX_CHECK_REG((_enp), (_reg)); \
858 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
859 (_edp), (_lock)); \
860 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
861 uint32_t, _reg ## _OFST, \
862 uint32_t, (_edp)->ed_u32[0]); \
863 _NOTE(CONSTANTCONDITION) \
864 } while (B_FALSE)
865
866#define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
867 do { \
868 EFX_CHECK_REG((_enp), (_reg)); \
869 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
870 uint32_t, _reg ## _OFST, \
871 uint32_t, (_edp)->ed_u32[0]); \
872 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
873 (_edp), (_lock)); \
874 _NOTE(CONSTANTCONDITION) \
875 } while (B_FALSE)
876
877#define EFX_BAR_READQ(_enp, _reg, _eqp) \
878 do { \
879 EFX_CHECK_REG((_enp), (_reg)); \
880 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
881 (_eqp)); \
882 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
883 uint32_t, _reg ## _OFST, \
884 uint32_t, (_eqp)->eq_u32[1], \
885 uint32_t, (_eqp)->eq_u32[0]); \
886 _NOTE(CONSTANTCONDITION) \
887 } while (B_FALSE)
888
889#define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
890 do { \
891 EFX_CHECK_REG((_enp), (_reg)); \
892 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
893 uint32_t, _reg ## _OFST, \
894 uint32_t, (_eqp)->eq_u32[1], \
895 uint32_t, (_eqp)->eq_u32[0]); \
896 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
897 (_eqp)); \
898 _NOTE(CONSTANTCONDITION) \
899 } while (B_FALSE)
900
901#define EFX_BAR_READO(_enp, _reg, _eop) \
902 do { \
903 EFX_CHECK_REG((_enp), (_reg)); \
904 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
905 (_eop), B_TRUE); \
906 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
907 uint32_t, _reg ## _OFST, \
908 uint32_t, (_eop)->eo_u32[3], \
909 uint32_t, (_eop)->eo_u32[2], \
910 uint32_t, (_eop)->eo_u32[1], \
911 uint32_t, (_eop)->eo_u32[0]); \
912 _NOTE(CONSTANTCONDITION) \
913 } while (B_FALSE)
914
915#define EFX_BAR_WRITEO(_enp, _reg, _eop) \
916 do { \
917 EFX_CHECK_REG((_enp), (_reg)); \
918 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
919 uint32_t, _reg ## _OFST, \
920 uint32_t, (_eop)->eo_u32[3], \
921 uint32_t, (_eop)->eo_u32[2], \
922 uint32_t, (_eop)->eo_u32[1], \
923 uint32_t, (_eop)->eo_u32[0]); \
924 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
925 (_eop), B_TRUE); \
926 _NOTE(CONSTANTCONDITION) \
927 } while (B_FALSE)
928
929#define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
930 do { \
931 EFX_CHECK_REG((_enp), (_reg)); \
932 EFSYS_BAR_READD((_enp)->en_esbp, \
933 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
934 (_edp), (_lock)); \
935 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
936 uint32_t, (_index), \
937 uint32_t, _reg ## _OFST, \
938 uint32_t, (_edp)->ed_u32[0]); \
939 _NOTE(CONSTANTCONDITION) \
940 } while (B_FALSE)
941
942#define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
943 do { \
944 EFX_CHECK_REG((_enp), (_reg)); \
945 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
946 uint32_t, (_index), \
947 uint32_t, _reg ## _OFST, \
948 uint32_t, (_edp)->ed_u32[0]); \
949 EFSYS_BAR_WRITED((_enp)->en_esbp, \
950 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
951 (_edp), (_lock)); \
952 _NOTE(CONSTANTCONDITION) \
953 } while (B_FALSE)
954
955#define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
956 do { \
957 EFX_CHECK_REG((_enp), (_reg)); \
958 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
959 uint32_t, (_index), \
960 uint32_t, _reg ## _OFST, \
961 uint32_t, (_edp)->ed_u32[0]); \
962 EFSYS_BAR_WRITED((_enp)->en_esbp, \
963 (_reg ## _OFST + \
964 (2 * sizeof (efx_dword_t)) + \
965 ((_index) * _reg ## _STEP)), \
966 (_edp), (_lock)); \
967 _NOTE(CONSTANTCONDITION) \
968 } while (B_FALSE)
969
970#define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
971 do { \
972 EFX_CHECK_REG((_enp), (_reg)); \
973 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
974 uint32_t, (_index), \
975 uint32_t, _reg ## _OFST, \
976 uint32_t, (_edp)->ed_u32[0]); \
977 EFSYS_BAR_WRITED((_enp)->en_esbp, \
978 (_reg ## _OFST + \
979 (3 * sizeof (efx_dword_t)) + \
980 ((_index) * _reg ## _STEP)), \
981 (_edp), (_lock)); \
982 _NOTE(CONSTANTCONDITION) \
983 } while (B_FALSE)
984
985#define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
986 do { \
987 EFX_CHECK_REG((_enp), (_reg)); \
988 EFSYS_BAR_READQ((_enp)->en_esbp, \
989 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
990 (_eqp)); \
991 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
992 uint32_t, (_index), \
993 uint32_t, _reg ## _OFST, \
994 uint32_t, (_eqp)->eq_u32[1], \
995 uint32_t, (_eqp)->eq_u32[0]); \
996 _NOTE(CONSTANTCONDITION) \
997 } while (B_FALSE)
998
999#define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
1000 do { \
1001 EFX_CHECK_REG((_enp), (_reg)); \
1002 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
1003 uint32_t, (_index), \
1004 uint32_t, _reg ## _OFST, \
1005 uint32_t, (_eqp)->eq_u32[1], \
1006 uint32_t, (_eqp)->eq_u32[0]); \
1007 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
1008 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1009 (_eqp)); \
1010 _NOTE(CONSTANTCONDITION) \
1011 } while (B_FALSE)
1012
1013#define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
1014 do { \
1015 EFX_CHECK_REG((_enp), (_reg)); \
1016 EFSYS_BAR_READO((_enp)->en_esbp, \
1017 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1018 (_eop), (_lock)); \
1019 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
1020 uint32_t, (_index), \
1021 uint32_t, _reg ## _OFST, \
1022 uint32_t, (_eop)->eo_u32[3], \
1023 uint32_t, (_eop)->eo_u32[2], \
1024 uint32_t, (_eop)->eo_u32[1], \
1025 uint32_t, (_eop)->eo_u32[0]); \
1026 _NOTE(CONSTANTCONDITION) \
1027 } while (B_FALSE)
1028
1029#define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1030 do { \
1031 EFX_CHECK_REG((_enp), (_reg)); \
1032 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1033 uint32_t, (_index), \
1034 uint32_t, _reg ## _OFST, \
1035 uint32_t, (_eop)->eo_u32[3], \
1036 uint32_t, (_eop)->eo_u32[2], \
1037 uint32_t, (_eop)->eo_u32[1], \
1038 uint32_t, (_eop)->eo_u32[0]); \
1039 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1040 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1041 (_eop), (_lock)); \
1042 _NOTE(CONSTANTCONDITION) \
1043 } while (B_FALSE)
1044
1045/*
1046 * Allow drivers to perform optimised 128-bit doorbell writes.
1047 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1048 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1049 * the need for locking in the host, and are the only ones known to be safe to
1050 * use 128-bites write with.
1051 */
1052#define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1053 do { \
1054 EFX_CHECK_REG((_enp), (_reg)); \
1055 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1056 const char *, \
1057 #_reg, \
1058 uint32_t, (_index), \
1059 uint32_t, _reg ## _OFST, \
1060 uint32_t, (_eop)->eo_u32[3], \
1061 uint32_t, (_eop)->eo_u32[2], \
1062 uint32_t, (_eop)->eo_u32[1], \
1063 uint32_t, (_eop)->eo_u32[0]); \
1064 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1065 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1066 (_eop)); \
1067 _NOTE(CONSTANTCONDITION) \
1068 } while (B_FALSE)
1069
1070#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1071 do { \
1072 unsigned int _new = (_wptr); \
1073 unsigned int _old = (_owptr); \
1074 \
1075 if ((_new) >= (_old)) \
1076 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1077 (_old) * sizeof (efx_desc_t), \
1078 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1079 else \
1080 /* \
1081 * It is cheaper to sync entire map than sync \
1082 * two parts especially when offset/size are \
1083 * ignored and entire map is synced in any case.\
1084 */ \
1085 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1086 0, \
1087 (_entries) * sizeof (efx_desc_t)); \
1088 _NOTE(CONSTANTCONDITION) \
1089 } while (B_FALSE)
1090
1091extern __checkReturn efx_rc_t
1092efx_nic_biu_test(
1093 __in efx_nic_t *enp);
1094
1095extern __checkReturn efx_rc_t
1096efx_mac_select(
1097 __in efx_nic_t *enp);
1098
1099extern void
1100efx_mac_multicast_hash_compute(
1101 __in_ecount(6*count) uint8_t const *addrs,
1102 __in int count,
1103 __out efx_oword_t *hash_low,
1104 __out efx_oword_t *hash_high);
1105
1106extern __checkReturn efx_rc_t
1107efx_phy_probe(
1108 __in efx_nic_t *enp);
1109
1110extern void
1111efx_phy_unprobe(
1112 __in efx_nic_t *enp);
1113
1114#if EFSYS_OPT_VPD
1115
1116/* VPD utility functions */
1117
1118extern __checkReturn efx_rc_t
1119efx_vpd_hunk_length(
1120 __in_bcount(size) caddr_t data,
1121 __in size_t size,
1122 __out size_t *lengthp);
1123
1124extern __checkReturn efx_rc_t
1125efx_vpd_hunk_verify(
1126 __in_bcount(size) caddr_t data,
1127 __in size_t size,
1128 __out_opt boolean_t *cksummedp);
1129
1130extern __checkReturn efx_rc_t
1131efx_vpd_hunk_reinit(
1132 __in_bcount(size) caddr_t data,
1133 __in size_t size,
1134 __in boolean_t wantpid);
1135
1136extern __checkReturn efx_rc_t
1137efx_vpd_hunk_get(
1138 __in_bcount(size) caddr_t data,
1139 __in size_t size,
1140 __in efx_vpd_tag_t tag,
1141 __in efx_vpd_keyword_t keyword,
1142 __out unsigned int *payloadp,
1143 __out uint8_t *paylenp);
1144
1145extern __checkReturn efx_rc_t
1146efx_vpd_hunk_next(
1147 __in_bcount(size) caddr_t data,
1148 __in size_t size,
1149 __out efx_vpd_tag_t *tagp,
1150 __out efx_vpd_keyword_t *keyword,
1151 __out_opt unsigned int *payloadp,
1152 __out_opt uint8_t *paylenp,
1153 __inout unsigned int *contp);
1154
1155extern __checkReturn efx_rc_t
1156efx_vpd_hunk_set(
1157 __in_bcount(size) caddr_t data,
1158 __in size_t size,
1159 __in efx_vpd_value_t *evvp);
1160
1161#endif /* EFSYS_OPT_VPD */
1162
1163#if EFSYS_OPT_DIAG
1164
1165extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
1166
1167typedef struct efx_register_set_s {
1168 unsigned int address;
1169 unsigned int step;
1170 unsigned int rows;
1171 efx_oword_t mask;
1172} efx_register_set_t;
1173
1174extern __checkReturn efx_rc_t
1175efx_nic_test_registers(
1176 __in efx_nic_t *enp,
1177 __in efx_register_set_t *rsp,
1178 __in size_t count);
1179
1180extern __checkReturn efx_rc_t
1181efx_nic_test_tables(
1182 __in efx_nic_t *enp,
1183 __in efx_register_set_t *rsp,
1184 __in efx_pattern_type_t pattern,
1185 __in size_t count);
1186
1187#endif /* EFSYS_OPT_DIAG */
1188
1189#if EFSYS_OPT_MCDI
1190
1191extern __checkReturn efx_rc_t
1192efx_mcdi_set_workaround(
1193 __in efx_nic_t *enp,
1194 __in uint32_t type,
1195 __in boolean_t enabled,
1196 __out_opt uint32_t *flagsp);
1197
1198extern __checkReturn efx_rc_t
1199efx_mcdi_get_workarounds(
1200 __in efx_nic_t *enp,
1201 __out_opt uint32_t *implementedp,
1202 __out_opt uint32_t *enabledp);
1203
1204#endif /* EFSYS_OPT_MCDI */
1205
1206#ifdef __cplusplus
1207}
1208#endif
1209
1210#endif /* _SYS_EFX_IMPL_H */
2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: head/sys/dev/sfxge/common/efx_impl.h 299318 2016-05-10 06:51:20Z arybchik $
31 */
32
33#ifndef _SYS_EFX_IMPL_H
34#define _SYS_EFX_IMPL_H
35
36#include "efsys.h"
37#include "efx_check.h"
38#include "efx.h"
39#include "efx_regs.h"
40#include "efx_regs_ef10.h"
41
42/* FIXME: Add definition for driver generated software events */
43#ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
44#define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
45#endif
46
47
48#if EFSYS_OPT_FALCON
49#include "falcon_impl.h"
50#endif /* EFSYS_OPT_FALCON */
51
52#if EFSYS_OPT_SIENA
53#include "siena_impl.h"
54#endif /* EFSYS_OPT_SIENA */
55
56#if EFSYS_OPT_HUNTINGTON
57#include "hunt_impl.h"
58#endif /* EFSYS_OPT_HUNTINGTON */
59
60#if EFSYS_OPT_MEDFORD
61#include "medford_impl.h"
62#endif /* EFSYS_OPT_MEDFORD */
63
64#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
65#include "ef10_impl.h"
66#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
67
68#ifdef __cplusplus
69extern "C" {
70#endif
71
72#define EFX_MOD_MCDI 0x00000001
73#define EFX_MOD_PROBE 0x00000002
74#define EFX_MOD_NVRAM 0x00000004
75#define EFX_MOD_VPD 0x00000008
76#define EFX_MOD_NIC 0x00000010
77#define EFX_MOD_INTR 0x00000020
78#define EFX_MOD_EV 0x00000040
79#define EFX_MOD_RX 0x00000080
80#define EFX_MOD_TX 0x00000100
81#define EFX_MOD_PORT 0x00000200
82#define EFX_MOD_MON 0x00000400
83#define EFX_MOD_WOL 0x00000800
84#define EFX_MOD_FILTER 0x00001000
85#define EFX_MOD_PKTFILTER 0x00002000
86#define EFX_MOD_LIC 0x00004000
87
88#define EFX_RESET_MAC 0x00000001
89#define EFX_RESET_PHY 0x00000002
90#define EFX_RESET_RXQ_ERR 0x00000004
91#define EFX_RESET_TXQ_ERR 0x00000008
92
93typedef enum efx_mac_type_e {
94 EFX_MAC_INVALID = 0,
95 EFX_MAC_FALCON_GMAC,
96 EFX_MAC_FALCON_XMAC,
97 EFX_MAC_SIENA,
98 EFX_MAC_HUNTINGTON,
99 EFX_MAC_MEDFORD,
100 EFX_MAC_NTYPES
101} efx_mac_type_t;
102
103typedef struct efx_ev_ops_s {
104 efx_rc_t (*eevo_init)(efx_nic_t *);
105 void (*eevo_fini)(efx_nic_t *);
106 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
107 efsys_mem_t *, size_t, uint32_t,
108 efx_evq_t *);
109 void (*eevo_qdestroy)(efx_evq_t *);
110 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
111 void (*eevo_qpost)(efx_evq_t *, uint16_t);
112 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
113#if EFSYS_OPT_QSTATS
114 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
115#endif
116} efx_ev_ops_t;
117
118typedef struct efx_tx_ops_s {
119 efx_rc_t (*etxo_init)(efx_nic_t *);
120 void (*etxo_fini)(efx_nic_t *);
121 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
122 unsigned int, unsigned int,
123 efsys_mem_t *, size_t,
124 uint32_t, uint16_t,
125 efx_evq_t *, efx_txq_t *,
126 unsigned int *);
127 void (*etxo_qdestroy)(efx_txq_t *);
128 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
129 unsigned int, unsigned int,
130 unsigned int *);
131 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
132 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
133 efx_rc_t (*etxo_qflush)(efx_txq_t *);
134 void (*etxo_qenable)(efx_txq_t *);
135 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
136 void (*etxo_qpio_disable)(efx_txq_t *);
137 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
138 size_t);
139 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
140 unsigned int *);
141 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
142 unsigned int, unsigned int,
143 unsigned int *);
144 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
145 size_t, boolean_t,
146 efx_desc_t *);
147 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
148 uint32_t, uint8_t,
149 efx_desc_t *);
150 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
151 uint32_t, uint16_t,
152 efx_desc_t *, int);
153 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
154 efx_desc_t *);
155#if EFSYS_OPT_QSTATS
156 void (*etxo_qstats_update)(efx_txq_t *,
157 efsys_stat_t *);
158#endif
159} efx_tx_ops_t;
160
161typedef struct efx_rx_ops_s {
162 efx_rc_t (*erxo_init)(efx_nic_t *);
163 void (*erxo_fini)(efx_nic_t *);
164#if EFSYS_OPT_RX_SCATTER
165 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
166#endif
167#if EFSYS_OPT_RX_SCALE
168 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
169 efx_rx_hash_type_t, boolean_t);
170 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
171 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
172 size_t);
173 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
174 uint8_t *);
175#endif /* EFSYS_OPT_RX_SCALE */
176 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
177 uint16_t *);
178 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
179 unsigned int, unsigned int,
180 unsigned int);
181 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
182 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
183 void (*erxo_qenable)(efx_rxq_t *);
184 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
185 unsigned int, efx_rxq_type_t,
186 efsys_mem_t *, size_t, uint32_t,
187 efx_evq_t *, efx_rxq_t *);
188 void (*erxo_qdestroy)(efx_rxq_t *);
189} efx_rx_ops_t;
190
191typedef struct efx_mac_ops_s {
192 efx_rc_t (*emo_reset)(efx_nic_t *); /* optional */
193 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
194 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
195 efx_rc_t (*emo_addr_set)(efx_nic_t *);
196 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
197 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
198 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
199 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
200 efx_rxq_t *, boolean_t);
201 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
202#if EFSYS_OPT_LOOPBACK
203 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
204 efx_loopback_type_t);
205#endif /* EFSYS_OPT_LOOPBACK */
206#if EFSYS_OPT_MAC_STATS
207 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
208 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
209 uint16_t, boolean_t);
210 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
211 efsys_stat_t *, uint32_t *);
212#endif /* EFSYS_OPT_MAC_STATS */
213} efx_mac_ops_t;
214
215typedef struct efx_phy_ops_s {
216 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
217 efx_rc_t (*epo_reset)(efx_nic_t *);
218 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
219 efx_rc_t (*epo_verify)(efx_nic_t *);
220 efx_rc_t (*epo_uplink_check)(efx_nic_t *,
221 boolean_t *); /* optional */
222 efx_rc_t (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
223 unsigned int *, uint32_t *);
224 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
225#if EFSYS_OPT_PHY_STATS
226 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
227 uint32_t *);
228#endif /* EFSYS_OPT_PHY_STATS */
229#if EFSYS_OPT_PHY_PROPS
230#if EFSYS_OPT_NAMES
231 const char *(*epo_prop_name)(efx_nic_t *, unsigned int);
232#endif /* EFSYS_OPT_PHY_PROPS */
233 efx_rc_t (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
234 uint32_t *);
235 efx_rc_t (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
236#endif /* EFSYS_OPT_PHY_PROPS */
237#if EFSYS_OPT_BIST
238 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
239 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
240 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
241 efx_bist_result_t *, uint32_t *,
242 unsigned long *, size_t);
243 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
244#endif /* EFSYS_OPT_BIST */
245} efx_phy_ops_t;
246
247#if EFSYS_OPT_FILTER
248typedef struct efx_filter_ops_s {
249 efx_rc_t (*efo_init)(efx_nic_t *);
250 void (*efo_fini)(efx_nic_t *);
251 efx_rc_t (*efo_restore)(efx_nic_t *);
252 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
253 boolean_t may_replace);
254 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
255 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
256 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
257 boolean_t, boolean_t, boolean_t,
258 uint8_t const *, int);
259} efx_filter_ops_t;
260
261extern __checkReturn efx_rc_t
262efx_filter_reconfigure(
263 __in efx_nic_t *enp,
264 __in_ecount(6) uint8_t const *mac_addr,
265 __in boolean_t all_unicst,
266 __in boolean_t mulcst,
267 __in boolean_t all_mulcst,
268 __in boolean_t brdcst,
269 __in_ecount(6*count) uint8_t const *addrs,
270 __in int count);
271
272#endif /* EFSYS_OPT_FILTER */
273
274
275typedef struct efx_port_s {
276 efx_mac_type_t ep_mac_type;
277 uint32_t ep_phy_type;
278 uint8_t ep_port;
279 uint32_t ep_mac_pdu;
280 uint8_t ep_mac_addr[6];
281 efx_link_mode_t ep_link_mode;
282 boolean_t ep_all_unicst;
283 boolean_t ep_mulcst;
284 boolean_t ep_all_mulcst;
285 boolean_t ep_brdcst;
286 unsigned int ep_fcntl;
287 boolean_t ep_fcntl_autoneg;
288 efx_oword_t ep_multicst_hash[2];
289 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
290 EFX_MAC_MULTICAST_LIST_MAX];
291 uint32_t ep_mulcst_addr_count;
292#if EFSYS_OPT_LOOPBACK
293 efx_loopback_type_t ep_loopback_type;
294 efx_link_mode_t ep_loopback_link_mode;
295#endif /* EFSYS_OPT_LOOPBACK */
296#if EFSYS_OPT_PHY_FLAGS
297 uint32_t ep_phy_flags;
298#endif /* EFSYS_OPT_PHY_FLAGS */
299#if EFSYS_OPT_PHY_LED_CONTROL
300 efx_phy_led_mode_t ep_phy_led_mode;
301#endif /* EFSYS_OPT_PHY_LED_CONTROL */
302 efx_phy_media_type_t ep_fixed_port_type;
303 efx_phy_media_type_t ep_module_type;
304 uint32_t ep_adv_cap_mask;
305 uint32_t ep_lp_cap_mask;
306 uint32_t ep_default_adv_cap_mask;
307 uint32_t ep_phy_cap_mask;
308#if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
309 union {
310 struct {
311 unsigned int bug10934_count;
312 } ep_txc43128;
313 struct {
314 unsigned int bug17190_count;
315 } ep_qt2025c;
316 };
317#endif
318 boolean_t ep_mac_poll_needed; /* falcon only */
319 boolean_t ep_mac_up; /* falcon only */
320 uint32_t ep_fwver; /* falcon only */
321 boolean_t ep_mac_drain;
322 boolean_t ep_mac_stats_pending;
323#if EFSYS_OPT_BIST
324 efx_bist_type_t ep_current_bist;
325#endif
326 efx_mac_ops_t *ep_emop;
327 efx_phy_ops_t *ep_epop;
328} efx_port_t;
329
330typedef struct efx_mon_ops_s {
331 efx_rc_t (*emo_reset)(efx_nic_t *);
332 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
333#if EFSYS_OPT_MON_STATS
334 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
335 efx_mon_stat_value_t *);
336#endif /* EFSYS_OPT_MON_STATS */
337} efx_mon_ops_t;
338
339typedef struct efx_mon_s {
340 efx_mon_type_t em_type;
341 efx_mon_ops_t *em_emop;
342} efx_mon_t;
343
344typedef struct efx_intr_ops_s {
345 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
346 void (*eio_enable)(efx_nic_t *);
347 void (*eio_disable)(efx_nic_t *);
348 void (*eio_disable_unlocked)(efx_nic_t *);
349 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
350 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
351 void (*eio_status_message)(efx_nic_t *, unsigned int,
352 boolean_t *);
353 void (*eio_fatal)(efx_nic_t *);
354 void (*eio_fini)(efx_nic_t *);
355} efx_intr_ops_t;
356
357typedef struct efx_intr_s {
358 efx_intr_ops_t *ei_eiop;
359 efsys_mem_t *ei_esmp;
360 efx_intr_type_t ei_type;
361 unsigned int ei_level;
362} efx_intr_t;
363
364typedef struct efx_nic_ops_s {
365 efx_rc_t (*eno_probe)(efx_nic_t *);
366 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
367 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
368 efx_rc_t (*eno_reset)(efx_nic_t *);
369 efx_rc_t (*eno_init)(efx_nic_t *);
370 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
371 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
372 uint32_t *, size_t *);
373#if EFSYS_OPT_DIAG
374 efx_rc_t (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
375 efx_rc_t (*eno_register_test)(efx_nic_t *);
376#endif /* EFSYS_OPT_DIAG */
377 void (*eno_fini)(efx_nic_t *);
378 void (*eno_unprobe)(efx_nic_t *);
379} efx_nic_ops_t;
380
381#ifndef EFX_TXQ_LIMIT_TARGET
382#define EFX_TXQ_LIMIT_TARGET 259
383#endif
384#ifndef EFX_RXQ_LIMIT_TARGET
385#define EFX_RXQ_LIMIT_TARGET 512
386#endif
387#ifndef EFX_TXQ_DC_SIZE
388#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
389#endif
390#ifndef EFX_RXQ_DC_SIZE
391#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
392#endif
393
394#if EFSYS_OPT_FILTER
395
396typedef struct falconsiena_filter_spec_s {
397 uint8_t fsfs_type;
398 uint32_t fsfs_flags;
399 uint32_t fsfs_dmaq_id;
400 uint32_t fsfs_dword[3];
401} falconsiena_filter_spec_t;
402
403typedef enum falconsiena_filter_type_e {
404 EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
405 EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */
406 EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
407 EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */
408
409#if EFSYS_OPT_SIENA
410 EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
411 EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
412
413 EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
414 EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
415 EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
416 EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */
417
418 EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */
419 EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */
420#endif /* EFSYS_OPT_SIENA */
421
422 EFX_FS_FILTER_NTYPES
423} falconsiena_filter_type_t;
424
425typedef enum falconsiena_filter_tbl_id_e {
426 EFX_FS_FILTER_TBL_RX_IP = 0,
427 EFX_FS_FILTER_TBL_RX_MAC,
428 EFX_FS_FILTER_TBL_TX_IP,
429 EFX_FS_FILTER_TBL_TX_MAC,
430 EFX_FS_FILTER_NTBLS
431} falconsiena_filter_tbl_id_t;
432
433typedef struct falconsiena_filter_tbl_s {
434 int fsft_size; /* number of entries */
435 int fsft_used; /* active count */
436 uint32_t *fsft_bitmap; /* active bitmap */
437 falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */
438} falconsiena_filter_tbl_t;
439
440typedef struct falconsiena_filter_s {
441 falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS];
442 unsigned int fsf_depth[EFX_FS_FILTER_NTYPES];
443} falconsiena_filter_t;
444
445typedef struct efx_filter_s {
446#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
447 falconsiena_filter_t *ef_falconsiena_filter;
448#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
449#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
450 ef10_filter_table_t *ef_ef10_filter_table;
451#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
452} efx_filter_t;
453
454extern void
455falconsiena_filter_tbl_clear(
456 __in efx_nic_t *enp,
457 __in falconsiena_filter_tbl_id_t tbl);
458
459#endif /* EFSYS_OPT_FILTER */
460
461#if EFSYS_OPT_MCDI
462
463typedef struct efx_mcdi_ops_s {
464 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
465 void (*emco_send_request)(efx_nic_t *, void *, size_t,
466 void *, size_t);
467 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
468 boolean_t (*emco_poll_response)(efx_nic_t *);
469 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
470 void (*emco_fini)(efx_nic_t *);
471 efx_rc_t (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
472} efx_mcdi_ops_t;
473
474typedef struct efx_mcdi_s {
475 efx_mcdi_ops_t *em_emcop;
476 const efx_mcdi_transport_t *em_emtp;
477 efx_mcdi_iface_t em_emip;
478} efx_mcdi_t;
479
480#endif /* EFSYS_OPT_MCDI */
481
482#if EFSYS_OPT_NVRAM
483typedef struct efx_nvram_ops_s {
484#if EFSYS_OPT_DIAG
485 efx_rc_t (*envo_test)(efx_nic_t *);
486#endif /* EFSYS_OPT_DIAG */
487 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
488 uint32_t *);
489 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
490 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
491 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
492 unsigned int, caddr_t, size_t);
493 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
494 unsigned int, size_t);
495 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
496 unsigned int, caddr_t, size_t);
497 void (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
498 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
499 uint32_t *, uint16_t *);
500 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
501 uint16_t *);
502 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t,
503 caddr_t, size_t);
504} efx_nvram_ops_t;
505#endif /* EFSYS_OPT_NVRAM */
506
507extern __checkReturn efx_rc_t
508efx_nvram_tlv_validate(
509 __in efx_nic_t *enp,
510 __in uint32_t partn,
511 __in_bcount(partn_size) caddr_t partn_data,
512 __in size_t partn_size);
513
514
515#if EFSYS_OPT_VPD
516typedef struct efx_vpd_ops_s {
517 efx_rc_t (*evpdo_init)(efx_nic_t *);
518 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
519 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
520 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
521 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
522 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
523 efx_vpd_value_t *);
524 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
525 efx_vpd_value_t *);
526 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
527 efx_vpd_value_t *, unsigned int *);
528 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
529 void (*evpdo_fini)(efx_nic_t *);
530} efx_vpd_ops_t;
531#endif /* EFSYS_OPT_VPD */
532
533#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
534
535 __checkReturn efx_rc_t
536efx_mcdi_nvram_partitions(
537 __in efx_nic_t *enp,
538 __out_bcount(size) caddr_t data,
539 __in size_t size,
540 __out unsigned int *npartnp);
541
542 __checkReturn efx_rc_t
543efx_mcdi_nvram_metadata(
544 __in efx_nic_t *enp,
545 __in uint32_t partn,
546 __out uint32_t *subtypep,
547 __out_ecount(4) uint16_t version[4],
548 __out_bcount_opt(size) char *descp,
549 __in size_t size);
550
551 __checkReturn efx_rc_t
552efx_mcdi_nvram_info(
553 __in efx_nic_t *enp,
554 __in uint32_t partn,
555 __out_opt size_t *sizep,
556 __out_opt uint32_t *addressp,
557 __out_opt uint32_t *erase_sizep,
558 __out_opt uint32_t *write_sizep);
559
560 __checkReturn efx_rc_t
561efx_mcdi_nvram_update_start(
562 __in efx_nic_t *enp,
563 __in uint32_t partn);
564
565 __checkReturn efx_rc_t
566efx_mcdi_nvram_read(
567 __in efx_nic_t *enp,
568 __in uint32_t partn,
569 __in uint32_t offset,
570 __out_bcount(size) caddr_t data,
571 __in size_t size,
572 __in uint32_t mode);
573
574 __checkReturn efx_rc_t
575efx_mcdi_nvram_erase(
576 __in efx_nic_t *enp,
577 __in uint32_t partn,
578 __in uint32_t offset,
579 __in size_t size);
580
581 __checkReturn efx_rc_t
582efx_mcdi_nvram_write(
583 __in efx_nic_t *enp,
584 __in uint32_t partn,
585 __in uint32_t offset,
586 __out_bcount(size) caddr_t data,
587 __in size_t size);
588
589 __checkReturn efx_rc_t
590efx_mcdi_nvram_update_finish(
591 __in efx_nic_t *enp,
592 __in uint32_t partn,
593 __in boolean_t reboot);
594
595#if EFSYS_OPT_DIAG
596
597 __checkReturn efx_rc_t
598efx_mcdi_nvram_test(
599 __in efx_nic_t *enp,
600 __in uint32_t partn);
601
602#endif /* EFSYS_OPT_DIAG */
603
604#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
605
606#if EFSYS_OPT_LICENSING
607
608typedef struct efx_lic_ops_s {
609 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
610 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
611 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
612 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
613 size_t *, uint8_t *);
614} efx_lic_ops_t;
615
616#endif
617
618typedef struct efx_drv_cfg_s {
619 uint32_t edc_min_vi_count;
620 uint32_t edc_max_vi_count;
621
622 uint32_t edc_max_piobuf_count;
623 uint32_t edc_pio_alloc_size;
624} efx_drv_cfg_t;
625
626struct efx_nic_s {
627 uint32_t en_magic;
628 efx_family_t en_family;
629 uint32_t en_features;
630 efsys_identifier_t *en_esip;
631 efsys_lock_t *en_eslp;
632 efsys_bar_t *en_esbp;
633 unsigned int en_mod_flags;
634 unsigned int en_reset_flags;
635 efx_nic_cfg_t en_nic_cfg;
636 efx_drv_cfg_t en_drv_cfg;
637 efx_port_t en_port;
638 efx_mon_t en_mon;
639 efx_intr_t en_intr;
640 uint32_t en_ev_qcount;
641 uint32_t en_rx_qcount;
642 uint32_t en_tx_qcount;
643 efx_nic_ops_t *en_enop;
644 efx_ev_ops_t *en_eevop;
645 efx_tx_ops_t *en_etxop;
646 efx_rx_ops_t *en_erxop;
647#if EFSYS_OPT_FILTER
648 efx_filter_t en_filter;
649 efx_filter_ops_t *en_efop;
650#endif /* EFSYS_OPT_FILTER */
651#if EFSYS_OPT_MCDI
652 efx_mcdi_t en_mcdi;
653#endif /* EFSYS_OPT_MCDI */
654#if EFSYS_OPT_NVRAM
655 efx_nvram_type_t en_nvram_locked;
656 efx_nvram_ops_t *en_envop;
657#endif /* EFSYS_OPT_NVRAM */
658#if EFSYS_OPT_VPD
659 efx_vpd_ops_t *en_evpdop;
660#endif /* EFSYS_OPT_VPD */
661#if EFSYS_OPT_RX_SCALE
662 efx_rx_hash_support_t en_hash_support;
663 efx_rx_scale_support_t en_rss_support;
664 uint32_t en_rss_context;
665#endif /* EFSYS_OPT_RX_SCALE */
666 uint32_t en_vport_id;
667#if EFSYS_OPT_LICENSING
668 efx_lic_ops_t *en_elop;
669#endif
670 union {
671#if EFSYS_OPT_FALCON
672 struct {
673 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES];
674 falcon_i2c_t enu_fip;
675 boolean_t enu_i2c_locked;
676#if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
677 const uint8_t *enu_forced_cfg;
678#endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
679 uint8_t enu_mon_devid;
680 uint16_t enu_board_rev;
681 boolean_t enu_internal_sram;
682 uint8_t enu_sram_num_bank;
683 uint8_t enu_sram_bank_size;
684 } falcon;
685#endif /* EFSYS_OPT_FALCON */
686#if EFSYS_OPT_SIENA
687 struct {
688#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
689 unsigned int enu_partn_mask;
690#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
691#if EFSYS_OPT_VPD
692 caddr_t enu_svpd;
693 size_t enu_svpd_length;
694#endif /* EFSYS_OPT_VPD */
695 int enu_unused;
696 } siena;
697#endif /* EFSYS_OPT_SIENA */
698 int enu_unused;
699 } en_u;
700#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
701 union en_arch {
702 struct {
703 int ena_vi_base;
704 int ena_vi_count;
705 int ena_vi_shift;
706#if EFSYS_OPT_VPD
707 caddr_t ena_svpd;
708 size_t ena_svpd_length;
709#endif /* EFSYS_OPT_VPD */
710 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
711 uint32_t ena_piobuf_count;
712 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
713 uint32_t ena_pio_write_vi_base;
714 /* Memory BAR mapping regions */
715 uint32_t ena_uc_mem_map_offset;
716 size_t ena_uc_mem_map_size;
717 uint32_t ena_wc_mem_map_offset;
718 size_t ena_wc_mem_map_size;
719 } ef10;
720 } en_arch;
721#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
722};
723
724
725#define EFX_NIC_MAGIC 0x02121996
726
727typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
728 const efx_ev_callbacks_t *, void *);
729
730typedef struct efx_evq_rxq_state_s {
731 unsigned int eers_rx_read_ptr;
732 unsigned int eers_rx_mask;
733} efx_evq_rxq_state_t;
734
735struct efx_evq_s {
736 uint32_t ee_magic;
737 efx_nic_t *ee_enp;
738 unsigned int ee_index;
739 unsigned int ee_mask;
740 efsys_mem_t *ee_esmp;
741#if EFSYS_OPT_QSTATS
742 uint32_t ee_stat[EV_NQSTATS];
743#endif /* EFSYS_OPT_QSTATS */
744
745 efx_ev_handler_t ee_rx;
746 efx_ev_handler_t ee_tx;
747 efx_ev_handler_t ee_driver;
748 efx_ev_handler_t ee_global;
749 efx_ev_handler_t ee_drv_gen;
750#if EFSYS_OPT_MCDI
751 efx_ev_handler_t ee_mcdi;
752#endif /* EFSYS_OPT_MCDI */
753
754 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
755};
756
757#define EFX_EVQ_MAGIC 0x08081997
758
759#define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
760#define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
761
762struct efx_rxq_s {
763 uint32_t er_magic;
764 efx_nic_t *er_enp;
765 efx_evq_t *er_eep;
766 unsigned int er_index;
767 unsigned int er_label;
768 unsigned int er_mask;
769 efsys_mem_t *er_esmp;
770};
771
772#define EFX_RXQ_MAGIC 0x15022005
773
774struct efx_txq_s {
775 uint32_t et_magic;
776 efx_nic_t *et_enp;
777 unsigned int et_index;
778 unsigned int et_mask;
779 efsys_mem_t *et_esmp;
780#if EFSYS_OPT_HUNTINGTON
781 uint32_t et_pio_bufnum;
782 uint32_t et_pio_blknum;
783 uint32_t et_pio_write_offset;
784 uint32_t et_pio_offset;
785 size_t et_pio_size;
786#endif
787#if EFSYS_OPT_QSTATS
788 uint32_t et_stat[TX_NQSTATS];
789#endif /* EFSYS_OPT_QSTATS */
790};
791
792#define EFX_TXQ_MAGIC 0x05092005
793
794#define EFX_MAC_ADDR_COPY(_dst, _src) \
795 do { \
796 (_dst)[0] = (_src)[0]; \
797 (_dst)[1] = (_src)[1]; \
798 (_dst)[2] = (_src)[2]; \
799 (_dst)[3] = (_src)[3]; \
800 (_dst)[4] = (_src)[4]; \
801 (_dst)[5] = (_src)[5]; \
802 _NOTE(CONSTANTCONDITION) \
803 } while (B_FALSE)
804
805#define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
806 do { \
807 uint16_t *_d = (uint16_t *)(_dst); \
808 _d[0] = 0xffff; \
809 _d[1] = 0xffff; \
810 _d[2] = 0xffff; \
811 _NOTE(CONSTANTCONDITION) \
812 } while (B_FALSE)
813
814#if EFSYS_OPT_CHECK_REG
815#define EFX_CHECK_REG(_enp, _reg) \
816 do { \
817 const char *name = #_reg; \
818 char min = name[4]; \
819 char max = name[5]; \
820 char rev; \
821 \
822 switch ((_enp)->en_family) { \
823 case EFX_FAMILY_FALCON: \
824 rev = 'B'; \
825 break; \
826 \
827 case EFX_FAMILY_SIENA: \
828 rev = 'C'; \
829 break; \
830 \
831 case EFX_FAMILY_HUNTINGTON: \
832 rev = 'D'; \
833 break; \
834 \
835 case EFX_FAMILY_MEDFORD: \
836 rev = 'E'; \
837 break; \
838 \
839 default: \
840 rev = '?'; \
841 break; \
842 } \
843 \
844 EFSYS_ASSERT3S(rev, >=, min); \
845 EFSYS_ASSERT3S(rev, <=, max); \
846 \
847 _NOTE(CONSTANTCONDITION) \
848 } while (B_FALSE)
849#else
850#define EFX_CHECK_REG(_enp, _reg) do { \
851 _NOTE(CONSTANTCONDITION) \
852 } while(B_FALSE)
853#endif
854
855#define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
856 do { \
857 EFX_CHECK_REG((_enp), (_reg)); \
858 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
859 (_edp), (_lock)); \
860 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
861 uint32_t, _reg ## _OFST, \
862 uint32_t, (_edp)->ed_u32[0]); \
863 _NOTE(CONSTANTCONDITION) \
864 } while (B_FALSE)
865
866#define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
867 do { \
868 EFX_CHECK_REG((_enp), (_reg)); \
869 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
870 uint32_t, _reg ## _OFST, \
871 uint32_t, (_edp)->ed_u32[0]); \
872 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
873 (_edp), (_lock)); \
874 _NOTE(CONSTANTCONDITION) \
875 } while (B_FALSE)
876
877#define EFX_BAR_READQ(_enp, _reg, _eqp) \
878 do { \
879 EFX_CHECK_REG((_enp), (_reg)); \
880 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
881 (_eqp)); \
882 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
883 uint32_t, _reg ## _OFST, \
884 uint32_t, (_eqp)->eq_u32[1], \
885 uint32_t, (_eqp)->eq_u32[0]); \
886 _NOTE(CONSTANTCONDITION) \
887 } while (B_FALSE)
888
889#define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
890 do { \
891 EFX_CHECK_REG((_enp), (_reg)); \
892 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
893 uint32_t, _reg ## _OFST, \
894 uint32_t, (_eqp)->eq_u32[1], \
895 uint32_t, (_eqp)->eq_u32[0]); \
896 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
897 (_eqp)); \
898 _NOTE(CONSTANTCONDITION) \
899 } while (B_FALSE)
900
901#define EFX_BAR_READO(_enp, _reg, _eop) \
902 do { \
903 EFX_CHECK_REG((_enp), (_reg)); \
904 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
905 (_eop), B_TRUE); \
906 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
907 uint32_t, _reg ## _OFST, \
908 uint32_t, (_eop)->eo_u32[3], \
909 uint32_t, (_eop)->eo_u32[2], \
910 uint32_t, (_eop)->eo_u32[1], \
911 uint32_t, (_eop)->eo_u32[0]); \
912 _NOTE(CONSTANTCONDITION) \
913 } while (B_FALSE)
914
915#define EFX_BAR_WRITEO(_enp, _reg, _eop) \
916 do { \
917 EFX_CHECK_REG((_enp), (_reg)); \
918 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
919 uint32_t, _reg ## _OFST, \
920 uint32_t, (_eop)->eo_u32[3], \
921 uint32_t, (_eop)->eo_u32[2], \
922 uint32_t, (_eop)->eo_u32[1], \
923 uint32_t, (_eop)->eo_u32[0]); \
924 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
925 (_eop), B_TRUE); \
926 _NOTE(CONSTANTCONDITION) \
927 } while (B_FALSE)
928
929#define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
930 do { \
931 EFX_CHECK_REG((_enp), (_reg)); \
932 EFSYS_BAR_READD((_enp)->en_esbp, \
933 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
934 (_edp), (_lock)); \
935 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
936 uint32_t, (_index), \
937 uint32_t, _reg ## _OFST, \
938 uint32_t, (_edp)->ed_u32[0]); \
939 _NOTE(CONSTANTCONDITION) \
940 } while (B_FALSE)
941
942#define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
943 do { \
944 EFX_CHECK_REG((_enp), (_reg)); \
945 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
946 uint32_t, (_index), \
947 uint32_t, _reg ## _OFST, \
948 uint32_t, (_edp)->ed_u32[0]); \
949 EFSYS_BAR_WRITED((_enp)->en_esbp, \
950 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
951 (_edp), (_lock)); \
952 _NOTE(CONSTANTCONDITION) \
953 } while (B_FALSE)
954
955#define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
956 do { \
957 EFX_CHECK_REG((_enp), (_reg)); \
958 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
959 uint32_t, (_index), \
960 uint32_t, _reg ## _OFST, \
961 uint32_t, (_edp)->ed_u32[0]); \
962 EFSYS_BAR_WRITED((_enp)->en_esbp, \
963 (_reg ## _OFST + \
964 (2 * sizeof (efx_dword_t)) + \
965 ((_index) * _reg ## _STEP)), \
966 (_edp), (_lock)); \
967 _NOTE(CONSTANTCONDITION) \
968 } while (B_FALSE)
969
970#define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
971 do { \
972 EFX_CHECK_REG((_enp), (_reg)); \
973 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
974 uint32_t, (_index), \
975 uint32_t, _reg ## _OFST, \
976 uint32_t, (_edp)->ed_u32[0]); \
977 EFSYS_BAR_WRITED((_enp)->en_esbp, \
978 (_reg ## _OFST + \
979 (3 * sizeof (efx_dword_t)) + \
980 ((_index) * _reg ## _STEP)), \
981 (_edp), (_lock)); \
982 _NOTE(CONSTANTCONDITION) \
983 } while (B_FALSE)
984
985#define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
986 do { \
987 EFX_CHECK_REG((_enp), (_reg)); \
988 EFSYS_BAR_READQ((_enp)->en_esbp, \
989 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
990 (_eqp)); \
991 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
992 uint32_t, (_index), \
993 uint32_t, _reg ## _OFST, \
994 uint32_t, (_eqp)->eq_u32[1], \
995 uint32_t, (_eqp)->eq_u32[0]); \
996 _NOTE(CONSTANTCONDITION) \
997 } while (B_FALSE)
998
999#define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
1000 do { \
1001 EFX_CHECK_REG((_enp), (_reg)); \
1002 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
1003 uint32_t, (_index), \
1004 uint32_t, _reg ## _OFST, \
1005 uint32_t, (_eqp)->eq_u32[1], \
1006 uint32_t, (_eqp)->eq_u32[0]); \
1007 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
1008 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1009 (_eqp)); \
1010 _NOTE(CONSTANTCONDITION) \
1011 } while (B_FALSE)
1012
1013#define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
1014 do { \
1015 EFX_CHECK_REG((_enp), (_reg)); \
1016 EFSYS_BAR_READO((_enp)->en_esbp, \
1017 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1018 (_eop), (_lock)); \
1019 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
1020 uint32_t, (_index), \
1021 uint32_t, _reg ## _OFST, \
1022 uint32_t, (_eop)->eo_u32[3], \
1023 uint32_t, (_eop)->eo_u32[2], \
1024 uint32_t, (_eop)->eo_u32[1], \
1025 uint32_t, (_eop)->eo_u32[0]); \
1026 _NOTE(CONSTANTCONDITION) \
1027 } while (B_FALSE)
1028
1029#define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1030 do { \
1031 EFX_CHECK_REG((_enp), (_reg)); \
1032 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1033 uint32_t, (_index), \
1034 uint32_t, _reg ## _OFST, \
1035 uint32_t, (_eop)->eo_u32[3], \
1036 uint32_t, (_eop)->eo_u32[2], \
1037 uint32_t, (_eop)->eo_u32[1], \
1038 uint32_t, (_eop)->eo_u32[0]); \
1039 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1040 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1041 (_eop), (_lock)); \
1042 _NOTE(CONSTANTCONDITION) \
1043 } while (B_FALSE)
1044
1045/*
1046 * Allow drivers to perform optimised 128-bit doorbell writes.
1047 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1048 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1049 * the need for locking in the host, and are the only ones known to be safe to
1050 * use 128-bites write with.
1051 */
1052#define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1053 do { \
1054 EFX_CHECK_REG((_enp), (_reg)); \
1055 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1056 const char *, \
1057 #_reg, \
1058 uint32_t, (_index), \
1059 uint32_t, _reg ## _OFST, \
1060 uint32_t, (_eop)->eo_u32[3], \
1061 uint32_t, (_eop)->eo_u32[2], \
1062 uint32_t, (_eop)->eo_u32[1], \
1063 uint32_t, (_eop)->eo_u32[0]); \
1064 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1065 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1066 (_eop)); \
1067 _NOTE(CONSTANTCONDITION) \
1068 } while (B_FALSE)
1069
1070#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1071 do { \
1072 unsigned int _new = (_wptr); \
1073 unsigned int _old = (_owptr); \
1074 \
1075 if ((_new) >= (_old)) \
1076 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1077 (_old) * sizeof (efx_desc_t), \
1078 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1079 else \
1080 /* \
1081 * It is cheaper to sync entire map than sync \
1082 * two parts especially when offset/size are \
1083 * ignored and entire map is synced in any case.\
1084 */ \
1085 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1086 0, \
1087 (_entries) * sizeof (efx_desc_t)); \
1088 _NOTE(CONSTANTCONDITION) \
1089 } while (B_FALSE)
1090
1091extern __checkReturn efx_rc_t
1092efx_nic_biu_test(
1093 __in efx_nic_t *enp);
1094
1095extern __checkReturn efx_rc_t
1096efx_mac_select(
1097 __in efx_nic_t *enp);
1098
1099extern void
1100efx_mac_multicast_hash_compute(
1101 __in_ecount(6*count) uint8_t const *addrs,
1102 __in int count,
1103 __out efx_oword_t *hash_low,
1104 __out efx_oword_t *hash_high);
1105
1106extern __checkReturn efx_rc_t
1107efx_phy_probe(
1108 __in efx_nic_t *enp);
1109
1110extern void
1111efx_phy_unprobe(
1112 __in efx_nic_t *enp);
1113
1114#if EFSYS_OPT_VPD
1115
1116/* VPD utility functions */
1117
1118extern __checkReturn efx_rc_t
1119efx_vpd_hunk_length(
1120 __in_bcount(size) caddr_t data,
1121 __in size_t size,
1122 __out size_t *lengthp);
1123
1124extern __checkReturn efx_rc_t
1125efx_vpd_hunk_verify(
1126 __in_bcount(size) caddr_t data,
1127 __in size_t size,
1128 __out_opt boolean_t *cksummedp);
1129
1130extern __checkReturn efx_rc_t
1131efx_vpd_hunk_reinit(
1132 __in_bcount(size) caddr_t data,
1133 __in size_t size,
1134 __in boolean_t wantpid);
1135
1136extern __checkReturn efx_rc_t
1137efx_vpd_hunk_get(
1138 __in_bcount(size) caddr_t data,
1139 __in size_t size,
1140 __in efx_vpd_tag_t tag,
1141 __in efx_vpd_keyword_t keyword,
1142 __out unsigned int *payloadp,
1143 __out uint8_t *paylenp);
1144
1145extern __checkReturn efx_rc_t
1146efx_vpd_hunk_next(
1147 __in_bcount(size) caddr_t data,
1148 __in size_t size,
1149 __out efx_vpd_tag_t *tagp,
1150 __out efx_vpd_keyword_t *keyword,
1151 __out_opt unsigned int *payloadp,
1152 __out_opt uint8_t *paylenp,
1153 __inout unsigned int *contp);
1154
1155extern __checkReturn efx_rc_t
1156efx_vpd_hunk_set(
1157 __in_bcount(size) caddr_t data,
1158 __in size_t size,
1159 __in efx_vpd_value_t *evvp);
1160
1161#endif /* EFSYS_OPT_VPD */
1162
1163#if EFSYS_OPT_DIAG
1164
1165extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
1166
1167typedef struct efx_register_set_s {
1168 unsigned int address;
1169 unsigned int step;
1170 unsigned int rows;
1171 efx_oword_t mask;
1172} efx_register_set_t;
1173
1174extern __checkReturn efx_rc_t
1175efx_nic_test_registers(
1176 __in efx_nic_t *enp,
1177 __in efx_register_set_t *rsp,
1178 __in size_t count);
1179
1180extern __checkReturn efx_rc_t
1181efx_nic_test_tables(
1182 __in efx_nic_t *enp,
1183 __in efx_register_set_t *rsp,
1184 __in efx_pattern_type_t pattern,
1185 __in size_t count);
1186
1187#endif /* EFSYS_OPT_DIAG */
1188
1189#if EFSYS_OPT_MCDI
1190
1191extern __checkReturn efx_rc_t
1192efx_mcdi_set_workaround(
1193 __in efx_nic_t *enp,
1194 __in uint32_t type,
1195 __in boolean_t enabled,
1196 __out_opt uint32_t *flagsp);
1197
1198extern __checkReturn efx_rc_t
1199efx_mcdi_get_workarounds(
1200 __in efx_nic_t *enp,
1201 __out_opt uint32_t *implementedp,
1202 __out_opt uint32_t *enabledp);
1203
1204#endif /* EFSYS_OPT_MCDI */
1205
1206#ifdef __cplusplus
1207}
1208#endif
1209
1210#endif /* _SYS_EFX_IMPL_H */