33
34#include "efx.h"
35#include "efx_impl.h"
36#if EFSYS_OPT_MON_MCDI
37#include "mcdi_mon.h"
38#endif
39
40#if EFSYS_OPT_QSTATS
41#define EFX_EV_QSTAT_INCR(_eep, _stat) \
42 do { \
43 (_eep)->ee_stat[_stat]++; \
44 _NOTE(CONSTANTCONDITION) \
45 } while (B_FALSE)
46#else
47#define EFX_EV_QSTAT_INCR(_eep, _stat)
48#endif
49
50#define EFX_EV_PRESENT(_qword) \
51 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
52 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
53
54
55
56#if EFSYS_OPT_SIENA
57
58static __checkReturn efx_rc_t
59siena_ev_init(
60 __in efx_nic_t *enp);
61
62static void
63siena_ev_fini(
64 __in efx_nic_t *enp);
65
66static __checkReturn efx_rc_t
67siena_ev_qcreate(
68 __in efx_nic_t *enp,
69 __in unsigned int index,
70 __in efsys_mem_t *esmp,
71 __in size_t n,
72 __in uint32_t id,
73 __in efx_evq_t *eep);
74
75static void
76siena_ev_qdestroy(
77 __in efx_evq_t *eep);
78
79static __checkReturn efx_rc_t
80siena_ev_qprime(
81 __in efx_evq_t *eep,
82 __in unsigned int count);
83
84static void
85siena_ev_qpoll(
86 __in efx_evq_t *eep,
87 __inout unsigned int *countp,
88 __in const efx_ev_callbacks_t *eecp,
89 __in_opt void *arg);
90
91static void
92siena_ev_qpost(
93 __in efx_evq_t *eep,
94 __in uint16_t data);
95
96static __checkReturn efx_rc_t
97siena_ev_qmoderate(
98 __in efx_evq_t *eep,
99 __in unsigned int us);
100
101#if EFSYS_OPT_QSTATS
102static void
103siena_ev_qstats_update(
104 __in efx_evq_t *eep,
105 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
106
107#endif
108
109#endif /* EFSYS_OPT_SIENA */
110
111#if EFSYS_OPT_SIENA
112static const efx_ev_ops_t __efx_ev_siena_ops = {
113 siena_ev_init, /* eevo_init */
114 siena_ev_fini, /* eevo_fini */
115 siena_ev_qcreate, /* eevo_qcreate */
116 siena_ev_qdestroy, /* eevo_qdestroy */
117 siena_ev_qprime, /* eevo_qprime */
118 siena_ev_qpost, /* eevo_qpost */
119 siena_ev_qmoderate, /* eevo_qmoderate */
120#if EFSYS_OPT_QSTATS
121 siena_ev_qstats_update, /* eevo_qstats_update */
122#endif
123};
124#endif /* EFSYS_OPT_SIENA */
125
126#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
127static const efx_ev_ops_t __efx_ev_ef10_ops = {
128 ef10_ev_init, /* eevo_init */
129 ef10_ev_fini, /* eevo_fini */
130 ef10_ev_qcreate, /* eevo_qcreate */
131 ef10_ev_qdestroy, /* eevo_qdestroy */
132 ef10_ev_qprime, /* eevo_qprime */
133 ef10_ev_qpost, /* eevo_qpost */
134 ef10_ev_qmoderate, /* eevo_qmoderate */
135#if EFSYS_OPT_QSTATS
136 ef10_ev_qstats_update, /* eevo_qstats_update */
137#endif
138};
139#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
140
141
142 __checkReturn efx_rc_t
143efx_ev_init(
144 __in efx_nic_t *enp)
145{
146 const efx_ev_ops_t *eevop;
147 efx_rc_t rc;
148
149 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
150 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
151
152 if (enp->en_mod_flags & EFX_MOD_EV) {
153 rc = EINVAL;
154 goto fail1;
155 }
156
157 switch (enp->en_family) {
158#if EFSYS_OPT_SIENA
159 case EFX_FAMILY_SIENA:
160 eevop = &__efx_ev_siena_ops;
161 break;
162#endif /* EFSYS_OPT_SIENA */
163
164#if EFSYS_OPT_HUNTINGTON
165 case EFX_FAMILY_HUNTINGTON:
166 eevop = &__efx_ev_ef10_ops;
167 break;
168#endif /* EFSYS_OPT_HUNTINGTON */
169
170#if EFSYS_OPT_MEDFORD
171 case EFX_FAMILY_MEDFORD:
172 eevop = &__efx_ev_ef10_ops;
173 break;
174#endif /* EFSYS_OPT_MEDFORD */
175
176 default:
177 EFSYS_ASSERT(0);
178 rc = ENOTSUP;
179 goto fail1;
180 }
181
182 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
183
184 if ((rc = eevop->eevo_init(enp)) != 0)
185 goto fail2;
186
187 enp->en_eevop = eevop;
188 enp->en_mod_flags |= EFX_MOD_EV;
189 return (0);
190
191fail2:
192 EFSYS_PROBE(fail2);
193
194fail1:
195 EFSYS_PROBE1(fail1, efx_rc_t, rc);
196
197 enp->en_eevop = NULL;
198 enp->en_mod_flags &= ~EFX_MOD_EV;
199 return (rc);
200}
201
202 void
203efx_ev_fini(
204 __in efx_nic_t *enp)
205{
206 const efx_ev_ops_t *eevop = enp->en_eevop;
207
208 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
209 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
210 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
211 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
212 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
213 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
214
215 eevop->eevo_fini(enp);
216
217 enp->en_eevop = NULL;
218 enp->en_mod_flags &= ~EFX_MOD_EV;
219}
220
221
222 __checkReturn efx_rc_t
223efx_ev_qcreate(
224 __in efx_nic_t *enp,
225 __in unsigned int index,
226 __in efsys_mem_t *esmp,
227 __in size_t n,
228 __in uint32_t id,
229 __deref_out efx_evq_t **eepp)
230{
231 const efx_ev_ops_t *eevop = enp->en_eevop;
232 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
233 efx_evq_t *eep;
234 efx_rc_t rc;
235
236 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
237 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
238
239 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
240
241 /* Allocate an EVQ object */
242 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
243 if (eep == NULL) {
244 rc = ENOMEM;
245 goto fail1;
246 }
247
248 eep->ee_magic = EFX_EVQ_MAGIC;
249 eep->ee_enp = enp;
250 eep->ee_index = index;
251 eep->ee_mask = n - 1;
252 eep->ee_esmp = esmp;
253
254 /*
255 * Set outputs before the queue is created because interrupts may be
256 * raised for events immediately after the queue is created, before the
257 * function call below returns. See bug58606.
258 *
259 * The eepp pointer passed in by the client must therefore point to data
260 * shared with the client's event processing context.
261 */
262 enp->en_ev_qcount++;
263 *eepp = eep;
264
265 if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, eep)) != 0)
266 goto fail2;
267
268 return (0);
269
270fail2:
271 EFSYS_PROBE(fail2);
272
273 *eepp = NULL;
274 enp->en_ev_qcount--;
275 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
276fail1:
277 EFSYS_PROBE1(fail1, efx_rc_t, rc);
278 return (rc);
279}
280
281 void
282efx_ev_qdestroy(
283 __in efx_evq_t *eep)
284{
285 efx_nic_t *enp = eep->ee_enp;
286 const efx_ev_ops_t *eevop = enp->en_eevop;
287
288 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
289
290 EFSYS_ASSERT(enp->en_ev_qcount != 0);
291 --enp->en_ev_qcount;
292
293 eevop->eevo_qdestroy(eep);
294
295 /* Free the EVQ object */
296 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
297}
298
299 __checkReturn efx_rc_t
300efx_ev_qprime(
301 __in efx_evq_t *eep,
302 __in unsigned int count)
303{
304 efx_nic_t *enp = eep->ee_enp;
305 const efx_ev_ops_t *eevop = enp->en_eevop;
306 efx_rc_t rc;
307
308 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
309
310 if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
311 rc = EINVAL;
312 goto fail1;
313 }
314
315 if ((rc = eevop->eevo_qprime(eep, count)) != 0)
316 goto fail2;
317
318 return (0);
319
320fail2:
321 EFSYS_PROBE(fail2);
322fail1:
323 EFSYS_PROBE1(fail1, efx_rc_t, rc);
324 return (rc);
325}
326
327 __checkReturn boolean_t
328efx_ev_qpending(
329 __in efx_evq_t *eep,
330 __in unsigned int count)
331{
332 size_t offset;
333 efx_qword_t qword;
334
335 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
336
337 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
338 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
339
340 return (EFX_EV_PRESENT(qword));
341}
342
343#if EFSYS_OPT_EV_PREFETCH
344
345 void
346efx_ev_qprefetch(
347 __in efx_evq_t *eep,
348 __in unsigned int count)
349{
350 efx_nic_t *enp = eep->ee_enp;
351 unsigned int offset;
352
353 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
354
355 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
356 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
357}
358
359#endif /* EFSYS_OPT_EV_PREFETCH */
360
361 void
362efx_ev_qpoll(
363 __in efx_evq_t *eep,
364 __inout unsigned int *countp,
365 __in const efx_ev_callbacks_t *eecp,
366 __in_opt void *arg)
367{
368 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
369
370 /*
371 * FIXME: Huntington will require support for hardware event batching
372 * and merging, which will need a different ev_qpoll implementation.
373 *
374 * Without those features the Falcon/Siena code can be used unchanged.
375 */
376 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
377 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
378
379 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
380 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
381 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
382 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
383 FSE_AZ_EV_CODE_DRV_GEN_EV);
384#if EFSYS_OPT_MCDI
385 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
386 FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
387#endif
388 siena_ev_qpoll(eep, countp, eecp, arg);
389}
390
391 void
392efx_ev_qpost(
393 __in efx_evq_t *eep,
394 __in uint16_t data)
395{
396 efx_nic_t *enp = eep->ee_enp;
397 const efx_ev_ops_t *eevop = enp->en_eevop;
398
399 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
400
401 EFSYS_ASSERT(eevop != NULL &&
402 eevop->eevo_qpost != NULL);
403
404 eevop->eevo_qpost(eep, data);
405}
406
407 __checkReturn efx_rc_t
408efx_ev_qmoderate(
409 __in efx_evq_t *eep,
410 __in unsigned int us)
411{
412 efx_nic_t *enp = eep->ee_enp;
413 const efx_ev_ops_t *eevop = enp->en_eevop;
414 efx_rc_t rc;
415
416 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
417
418 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
419 goto fail1;
420
421 return (0);
422
423fail1:
424 EFSYS_PROBE1(fail1, efx_rc_t, rc);
425 return (rc);
426}
427
428#if EFSYS_OPT_QSTATS
429 void
430efx_ev_qstats_update(
431 __in efx_evq_t *eep,
432 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
433
434{ efx_nic_t *enp = eep->ee_enp;
435 const efx_ev_ops_t *eevop = enp->en_eevop;
436
437 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
438
439 eevop->eevo_qstats_update(eep, stat);
440}
441
442#endif /* EFSYS_OPT_QSTATS */
443
444#if EFSYS_OPT_SIENA
445
446static __checkReturn efx_rc_t
447siena_ev_init(
448 __in efx_nic_t *enp)
449{
450 efx_oword_t oword;
451
452 /*
453 * Program the event queue for receive and transmit queue
454 * flush events.
455 */
456 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
457 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
458 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
459
460 return (0);
461
462}
463
464static __checkReturn boolean_t
465siena_ev_rx_not_ok(
466 __in efx_evq_t *eep,
467 __in efx_qword_t *eqp,
468 __in uint32_t label,
469 __in uint32_t id,
470 __inout uint16_t *flagsp)
471{
472 boolean_t ignore = B_FALSE;
473
474 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
475 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
476 EFSYS_PROBE(tobe_disc);
477 /*
478 * Assume this is a unicast address mismatch, unless below
479 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
480 * EV_RX_PAUSE_FRM_ERR is set.
481 */
482 (*flagsp) |= EFX_ADDR_MISMATCH;
483 }
484
485 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
486 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
487 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
488 (*flagsp) |= EFX_DISCARD;
489
490#if EFSYS_OPT_RX_SCATTER
491 /*
492 * Lookout for payload queue ran dry errors and ignore them.
493 *
494 * Sadly for the header/data split cases, the descriptor
495 * pointer in this event refers to the header queue and
496 * therefore cannot be easily detected as duplicate.
497 * So we drop these and rely on the receive processing seeing
498 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
499 * the partially received packet.
500 */
501 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
502 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
503 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
504 ignore = B_TRUE;
505#endif /* EFSYS_OPT_RX_SCATTER */
506 }
507
508 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
509 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
510 EFSYS_PROBE(crc_err);
511 (*flagsp) &= ~EFX_ADDR_MISMATCH;
512 (*flagsp) |= EFX_DISCARD;
513 }
514
515 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
516 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
517 EFSYS_PROBE(pause_frm_err);
518 (*flagsp) &= ~EFX_ADDR_MISMATCH;
519 (*flagsp) |= EFX_DISCARD;
520 }
521
522 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
523 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
524 EFSYS_PROBE(owner_id_err);
525 (*flagsp) |= EFX_DISCARD;
526 }
527
528 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
529 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
530 EFSYS_PROBE(ipv4_err);
531 (*flagsp) &= ~EFX_CKSUM_IPV4;
532 }
533
534 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
535 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
536 EFSYS_PROBE(udp_chk_err);
537 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
538 }
539
540 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
541 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
542
543 /*
544 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
545 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
546 * condition.
547 */
548 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
549 }
550
551 return (ignore);
552}
553
554static __checkReturn boolean_t
555siena_ev_rx(
556 __in efx_evq_t *eep,
557 __in efx_qword_t *eqp,
558 __in const efx_ev_callbacks_t *eecp,
559 __in_opt void *arg)
560{
561 uint32_t id;
562 uint32_t size;
563 uint32_t label;
564 boolean_t ok;
565#if EFSYS_OPT_RX_SCATTER
566 boolean_t sop;
567 boolean_t jumbo_cont;
568#endif /* EFSYS_OPT_RX_SCATTER */
569 uint32_t hdr_type;
570 boolean_t is_v6;
571 uint16_t flags;
572 boolean_t ignore;
573 boolean_t should_abort;
574
575 EFX_EV_QSTAT_INCR(eep, EV_RX);
576
577 /* Basic packet information */
578 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
579 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
580 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
581 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
582
583#if EFSYS_OPT_RX_SCATTER
584 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
585 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
586#endif /* EFSYS_OPT_RX_SCATTER */
587
588 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
589
590 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
591
592 /*
593 * If packet is marked as OK and packet type is TCP/IP or
594 * UDP/IP or other IP, then we can rely on the hardware checksums.
595 */
596 switch (hdr_type) {
597 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
598 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
599 if (is_v6) {
600 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
601 flags |= EFX_PKT_IPV6;
602 } else {
603 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
604 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
605 }
606 break;
607
608 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
609 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
610 if (is_v6) {
611 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
612 flags |= EFX_PKT_IPV6;
613 } else {
614 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
615 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
616 }
617 break;
618
619 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
620 if (is_v6) {
621 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
622 flags = EFX_PKT_IPV6;
623 } else {
624 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
625 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
626 }
627 break;
628
629 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
630 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
631 flags = 0;
632 break;
633
634 default:
635 EFSYS_ASSERT(B_FALSE);
636 flags = 0;
637 break;
638 }
639
640#if EFSYS_OPT_RX_SCATTER
641 /* Report scatter and header/lookahead split buffer flags */
642 if (sop)
643 flags |= EFX_PKT_START;
644 if (jumbo_cont)
645 flags |= EFX_PKT_CONT;
646#endif /* EFSYS_OPT_RX_SCATTER */
647
648 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
649 if (!ok) {
650 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
651 if (ignore) {
652 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
653 uint32_t, size, uint16_t, flags);
654
655 return (B_FALSE);
656 }
657 }
658
659 /* If we're not discarding the packet then it is ok */
660 if (~flags & EFX_DISCARD)
661 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
662
663 /* Detect multicast packets that didn't match the filter */
664 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
665 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
666
667 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
668 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
669 } else {
670 EFSYS_PROBE(mcast_mismatch);
671 flags |= EFX_ADDR_MISMATCH;
672 }
673 } else {
674 flags |= EFX_PKT_UNICAST;
675 }
676
677 /*
678 * The packet parser in Siena can abort parsing packets under
679 * certain error conditions, setting the PKT_NOT_PARSED bit
680 * (which clears PKT_OK). If this is set, then don't trust
681 * the PKT_TYPE field.
682 */
683 if (!ok) {
684 uint32_t parse_err;
685
686 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
687 if (parse_err != 0)
688 flags |= EFX_CHECK_VLAN;
689 }
690
691 if (~flags & EFX_CHECK_VLAN) {
692 uint32_t pkt_type;
693
694 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
695 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
696 flags |= EFX_PKT_VLAN_TAGGED;
697 }
698
699 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
700 uint32_t, size, uint16_t, flags);
701
702 EFSYS_ASSERT(eecp->eec_rx != NULL);
703 should_abort = eecp->eec_rx(arg, label, id, size, flags);
704
705 return (should_abort);
706}
707
708static __checkReturn boolean_t
709siena_ev_tx(
710 __in efx_evq_t *eep,
711 __in efx_qword_t *eqp,
712 __in const efx_ev_callbacks_t *eecp,
713 __in_opt void *arg)
714{
715 uint32_t id;
716 uint32_t label;
717 boolean_t should_abort;
718
719 EFX_EV_QSTAT_INCR(eep, EV_TX);
720
721 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
722 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
723 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
724 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
725
726 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
727 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
728
729 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
730
731 EFSYS_ASSERT(eecp->eec_tx != NULL);
732 should_abort = eecp->eec_tx(arg, label, id);
733
734 return (should_abort);
735 }
736
737 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
738 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
739 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
740 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
741
742 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
743 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
744
745 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
746 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
747
748 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
749 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
750
751 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
752 return (B_FALSE);
753}
754
755static __checkReturn boolean_t
756siena_ev_global(
757 __in efx_evq_t *eep,
758 __in efx_qword_t *eqp,
759 __in const efx_ev_callbacks_t *eecp,
760 __in_opt void *arg)
761{
762 _NOTE(ARGUNUSED(eqp, eecp, arg))
763
764 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
765
766 return (B_FALSE);
767}
768
769static __checkReturn boolean_t
770siena_ev_driver(
771 __in efx_evq_t *eep,
772 __in efx_qword_t *eqp,
773 __in const efx_ev_callbacks_t *eecp,
774 __in_opt void *arg)
775{
776 boolean_t should_abort;
777
778 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
779 should_abort = B_FALSE;
780
781 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
782 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
783 uint32_t txq_index;
784
785 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
786
787 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
788
789 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
790
791 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
792 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
793
794 break;
795 }
796 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
797 uint32_t rxq_index;
798 uint32_t failed;
799
800 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
801 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
802
803 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
804 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
805
806 if (failed) {
807 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
808
809 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
810
811 should_abort = eecp->eec_rxq_flush_failed(arg,
812 rxq_index);
813 } else {
814 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
815
816 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
817
818 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
819 }
820
821 break;
822 }
823 case FSE_AZ_EVQ_INIT_DONE_EV:
824 EFSYS_ASSERT(eecp->eec_initialized != NULL);
825 should_abort = eecp->eec_initialized(arg);
826
827 break;
828
829 case FSE_AZ_EVQ_NOT_EN_EV:
830 EFSYS_PROBE(evq_not_en);
831 break;
832
833 case FSE_AZ_SRM_UPD_DONE_EV: {
834 uint32_t code;
835
836 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
837
838 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
839
840 EFSYS_ASSERT(eecp->eec_sram != NULL);
841 should_abort = eecp->eec_sram(arg, code);
842
843 break;
844 }
845 case FSE_AZ_WAKE_UP_EV: {
846 uint32_t id;
847
848 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
849
850 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
851 should_abort = eecp->eec_wake_up(arg, id);
852
853 break;
854 }
855 case FSE_AZ_TX_PKT_NON_TCP_UDP:
856 EFSYS_PROBE(tx_pkt_non_tcp_udp);
857 break;
858
859 case FSE_AZ_TIMER_EV: {
860 uint32_t id;
861
862 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
863
864 EFSYS_ASSERT(eecp->eec_timer != NULL);
865 should_abort = eecp->eec_timer(arg, id);
866
867 break;
868 }
869 case FSE_AZ_RX_DSC_ERROR_EV:
870 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
871
872 EFSYS_PROBE(rx_dsc_error);
873
874 EFSYS_ASSERT(eecp->eec_exception != NULL);
875 should_abort = eecp->eec_exception(arg,
876 EFX_EXCEPTION_RX_DSC_ERROR, 0);
877
878 break;
879
880 case FSE_AZ_TX_DSC_ERROR_EV:
881 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
882
883 EFSYS_PROBE(tx_dsc_error);
884
885 EFSYS_ASSERT(eecp->eec_exception != NULL);
886 should_abort = eecp->eec_exception(arg,
887 EFX_EXCEPTION_TX_DSC_ERROR, 0);
888
889 break;
890
891 default:
892 break;
893 }
894
895 return (should_abort);
896}
897
898static __checkReturn boolean_t
899siena_ev_drv_gen(
900 __in efx_evq_t *eep,
901 __in efx_qword_t *eqp,
902 __in const efx_ev_callbacks_t *eecp,
903 __in_opt void *arg)
904{
905 uint32_t data;
906 boolean_t should_abort;
907
908 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
909
910 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
911 if (data >= ((uint32_t)1 << 16)) {
912 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
913 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
914 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
915 return (B_TRUE);
916 }
917
918 EFSYS_ASSERT(eecp->eec_software != NULL);
919 should_abort = eecp->eec_software(arg, (uint16_t)data);
920
921 return (should_abort);
922}
923
924#if EFSYS_OPT_MCDI
925
926static __checkReturn boolean_t
927siena_ev_mcdi(
928 __in efx_evq_t *eep,
929 __in efx_qword_t *eqp,
930 __in const efx_ev_callbacks_t *eecp,
931 __in_opt void *arg)
932{
933 efx_nic_t *enp = eep->ee_enp;
934 unsigned code;
935 boolean_t should_abort = B_FALSE;
936
937 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
938
939 if (enp->en_family != EFX_FAMILY_SIENA)
940 goto out;
941
942 EFSYS_ASSERT(eecp->eec_link_change != NULL);
943 EFSYS_ASSERT(eecp->eec_exception != NULL);
944#if EFSYS_OPT_MON_STATS
945 EFSYS_ASSERT(eecp->eec_monitor != NULL);
946#endif
947
948 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
949
950 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
951 switch (code) {
952 case MCDI_EVENT_CODE_BADSSERT:
953 efx_mcdi_ev_death(enp, EINTR);
954 break;
955
956 case MCDI_EVENT_CODE_CMDDONE:
957 efx_mcdi_ev_cpl(enp,
958 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
959 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
960 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
961 break;
962
963 case MCDI_EVENT_CODE_LINKCHANGE: {
964 efx_link_mode_t link_mode;
965
966 siena_phy_link_ev(enp, eqp, &link_mode);
967 should_abort = eecp->eec_link_change(arg, link_mode);
968 break;
969 }
970 case MCDI_EVENT_CODE_SENSOREVT: {
971#if EFSYS_OPT_MON_STATS
972 efx_mon_stat_t id;
973 efx_mon_stat_value_t value;
974 efx_rc_t rc;
975
976 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
977 should_abort = eecp->eec_monitor(arg, id, value);
978 else if (rc == ENOTSUP) {
979 should_abort = eecp->eec_exception(arg,
980 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
981 MCDI_EV_FIELD(eqp, DATA));
982 } else
983 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
984#else
985 should_abort = B_FALSE;
986#endif
987 break;
988 }
989 case MCDI_EVENT_CODE_SCHEDERR:
990 /* Informational only */
991 break;
992
993 case MCDI_EVENT_CODE_REBOOT:
994 efx_mcdi_ev_death(enp, EIO);
995 break;
996
997 case MCDI_EVENT_CODE_MAC_STATS_DMA:
998#if EFSYS_OPT_MAC_STATS
999 if (eecp->eec_mac_stats != NULL) {
1000 eecp->eec_mac_stats(arg,
1001 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1002 }
1003#endif
1004 break;
1005
1006 case MCDI_EVENT_CODE_FWALERT: {
1007 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1008
1009 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1010 should_abort = eecp->eec_exception(arg,
1011 EFX_EXCEPTION_FWALERT_SRAM,
1012 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1013 else
1014 should_abort = eecp->eec_exception(arg,
1015 EFX_EXCEPTION_UNKNOWN_FWALERT,
1016 MCDI_EV_FIELD(eqp, DATA));
1017 break;
1018 }
1019
1020 default:
1021 EFSYS_PROBE1(mc_pcol_error, int, code);
1022 break;
1023 }
1024
1025out:
1026 return (should_abort);
1027}
1028
1029#endif /* EFSYS_OPT_MCDI */
1030
1031static __checkReturn efx_rc_t
1032siena_ev_qprime(
1033 __in efx_evq_t *eep,
1034 __in unsigned int count)
1035{
1036 efx_nic_t *enp = eep->ee_enp;
1037 uint32_t rptr;
1038 efx_dword_t dword;
1039
1040 rptr = count & eep->ee_mask;
1041
1042 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1043
1044 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1045 &dword, B_FALSE);
1046
1047 return (0);
1048}
1049
1050#define EFX_EV_BATCH 8
1051
1052static void
1053siena_ev_qpoll(
1054 __in efx_evq_t *eep,
1055 __inout unsigned int *countp,
1056 __in const efx_ev_callbacks_t *eecp,
1057 __in_opt void *arg)
1058{
1059 efx_qword_t ev[EFX_EV_BATCH];
1060 unsigned int batch;
1061 unsigned int total;
1062 unsigned int count;
1063 unsigned int index;
1064 size_t offset;
1065
1066 EFSYS_ASSERT(countp != NULL);
1067 EFSYS_ASSERT(eecp != NULL);
1068
1069 count = *countp;
1070 do {
1071 /* Read up until the end of the batch period */
1072 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
1073 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1074 for (total = 0; total < batch; ++total) {
1075 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
1076
1077 if (!EFX_EV_PRESENT(ev[total]))
1078 break;
1079
1080 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
1081 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
1082 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
1083
1084 offset += sizeof (efx_qword_t);
1085 }
1086
1087#if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
1088 /*
1089 * Prefetch the next batch when we get within PREFETCH_PERIOD
1090 * of a completed batch. If the batch is smaller, then prefetch
1091 * immediately.
1092 */
1093 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
1094 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1095#endif /* EFSYS_OPT_EV_PREFETCH */
1096
1097 /* Process the batch of events */
1098 for (index = 0; index < total; ++index) {
1099 boolean_t should_abort;
1100 uint32_t code;
1101
1102#if EFSYS_OPT_EV_PREFETCH
1103 /* Prefetch if we've now reached the batch period */
1104 if (total == batch &&
1105 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
1106 offset = (count + batch) & eep->ee_mask;
1107 offset *= sizeof (efx_qword_t);
1108
1109 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1110 }
1111#endif /* EFSYS_OPT_EV_PREFETCH */
1112
1113 EFX_EV_QSTAT_INCR(eep, EV_ALL);
1114
1115 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
1116 switch (code) {
1117 case FSE_AZ_EV_CODE_RX_EV:
1118 should_abort = eep->ee_rx(eep,
1119 &(ev[index]), eecp, arg);
1120 break;
1121 case FSE_AZ_EV_CODE_TX_EV:
1122 should_abort = eep->ee_tx(eep,
1123 &(ev[index]), eecp, arg);
1124 break;
1125 case FSE_AZ_EV_CODE_DRIVER_EV:
1126 should_abort = eep->ee_driver(eep,
1127 &(ev[index]), eecp, arg);
1128 break;
1129 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1130 should_abort = eep->ee_drv_gen(eep,
1131 &(ev[index]), eecp, arg);
1132 break;
1133#if EFSYS_OPT_MCDI
1134 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
1135 should_abort = eep->ee_mcdi(eep,
1136 &(ev[index]), eecp, arg);
1137 break;
1138#endif
1139 case FSE_AZ_EV_CODE_GLOBAL_EV:
1140 if (eep->ee_global) {
1141 should_abort = eep->ee_global(eep,
1142 &(ev[index]), eecp, arg);
1143 break;
1144 }
1145 /* else fallthrough */
1146 default:
1147 EFSYS_PROBE3(bad_event,
1148 unsigned int, eep->ee_index,
1149 uint32_t,
1150 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
1151 uint32_t,
1152 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
1153
1154 EFSYS_ASSERT(eecp->eec_exception != NULL);
1155 (void) eecp->eec_exception(arg,
1156 EFX_EXCEPTION_EV_ERROR, code);
1157 should_abort = B_TRUE;
1158 }
1159 if (should_abort) {
1160 /* Ignore subsequent events */
1161 total = index + 1;
1162 break;
1163 }
1164 }
1165
1166 /*
1167 * Now that the hardware has most likely moved onto dma'ing
1168 * into the next cache line, clear the processed events. Take
1169 * care to only clear out events that we've processed
1170 */
1171 EFX_SET_QWORD(ev[0]);
1172 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1173 for (index = 0; index < total; ++index) {
1174 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
1175 offset += sizeof (efx_qword_t);
1176 }
1177
1178 count += total;
1179
1180 } while (total == batch);
1181
1182 *countp = count;
1183}
1184
1185static void
1186siena_ev_qpost(
1187 __in efx_evq_t *eep,
1188 __in uint16_t data)
1189{
1190 efx_nic_t *enp = eep->ee_enp;
1191 efx_qword_t ev;
1192 efx_oword_t oword;
1193
1194 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1195 FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1196
1197 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1198 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1199 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1200
1201 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1202}
1203
1204static __checkReturn efx_rc_t
1205siena_ev_qmoderate(
1206 __in efx_evq_t *eep,
1207 __in unsigned int us)
1208{
1209 efx_nic_t *enp = eep->ee_enp;
1210 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1211 unsigned int locked;
1212 efx_dword_t dword;
1213 efx_rc_t rc;
1214
1215 if (us > encp->enc_evq_timer_max_us) {
1216 rc = EINVAL;
1217 goto fail1;
1218 }
1219
1220 /* If the value is zero then disable the timer */
1221 if (us == 0) {
1222 EFX_POPULATE_DWORD_2(dword,
1223 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1224 FRF_CZ_TC_TIMER_VAL, 0);
1225 } else {
1226 uint32_t timer_val;
1227
1228 /* Calculate the timer value in quanta */
1229 timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns;
1230
1231 /* Moderation value is base 0 so we need to deduct 1 */
1232 if (timer_val > 0)
1233 timer_val--;
1234
1235 EFX_POPULATE_DWORD_2(dword,
1236 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1237 FRF_CZ_TC_TIMER_VAL, timer_val);
1238 }
1239
1240 locked = (eep->ee_index == 0) ? 1 : 0;
1241
1242 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1243 eep->ee_index, &dword, locked);
1244
1245 return (0);
1246
1247fail1:
1248 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1249
1250 return (rc);
1251}
1252
1253static __checkReturn efx_rc_t
1254siena_ev_qcreate(
1255 __in efx_nic_t *enp,
1256 __in unsigned int index,
1257 __in efsys_mem_t *esmp,
1258 __in size_t n,
1259 __in uint32_t id,
1260 __in efx_evq_t *eep)
1261{
1262 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1263 uint32_t size;
1264 efx_oword_t oword;
1265 efx_rc_t rc;
1266
|