1/*-
2 * Copyright (c) 2006-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: head/sys/dev/sfxge/common/efx.h 293891 2016-01-14 09:05:51Z arybchik $
31 */
32
33#ifndef _SYS_EFX_H
34#define _SYS_EFX_H
35
36#include "efsys.h"
37#include "efx_phy_ids.h"
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43#define EFX_STATIC_ASSERT(_cond) \
44 ((void)sizeof(char[(_cond) ? 1 : -1]))
45
46#define EFX_ARRAY_SIZE(_array) \
47 (sizeof(_array) / sizeof((_array)[0]))
48
49#define EFX_FIELD_OFFSET(_type, _field) \
50 ((size_t) &(((_type *)0)->_field))
51
52/* Return codes */
53
54typedef __success(return == 0) int efx_rc_t;
55
56
57/* Chip families */
58
59typedef enum efx_family_e {
60 EFX_FAMILY_INVALID,
61 EFX_FAMILY_FALCON,
62 EFX_FAMILY_SIENA,
63 EFX_FAMILY_HUNTINGTON,
64 EFX_FAMILY_MEDFORD,
65 EFX_FAMILY_NTYPES
66} efx_family_t;
67
68extern __checkReturn efx_rc_t
69efx_family(
70 __in uint16_t venid,
71 __in uint16_t devid,
72 __out efx_family_t *efp);
73
74extern __checkReturn efx_rc_t
75efx_infer_family(
76 __in efsys_bar_t *esbp,
77 __out efx_family_t *efp);
78
79#define EFX_PCI_VENID_SFC 0x1924
80
81#define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
82
83#define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
84#define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
85#define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
86
87#define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
88#define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
89#define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
90
91#define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
92#define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
93
94#define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
95#define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
96#define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
97
98#define EFX_MEM_BAR 2
99
100/* Error codes */
101
102enum {
103 EFX_ERR_INVALID,
104 EFX_ERR_SRAM_OOB,
105 EFX_ERR_BUFID_DC_OOB,
106 EFX_ERR_MEM_PERR,
107 EFX_ERR_RBUF_OWN,
108 EFX_ERR_TBUF_OWN,
109 EFX_ERR_RDESQ_OWN,
110 EFX_ERR_TDESQ_OWN,
111 EFX_ERR_EVQ_OWN,
112 EFX_ERR_EVFF_OFLO,
113 EFX_ERR_ILL_ADDR,
114 EFX_ERR_SRAM_PERR,
115 EFX_ERR_NCODES
116};
117
118/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
119extern __checkReturn uint32_t
120efx_crc32_calculate(
121 __in uint32_t crc_init,
122 __in_ecount(length) uint8_t const *input,
123 __in int length);
124
125
126/* Type prototypes */
127
128typedef struct efx_rxq_s efx_rxq_t;
129
130/* NIC */
131
132typedef struct efx_nic_s efx_nic_t;
133
134#define EFX_NIC_FUNC_PRIMARY 0x00000001
135#define EFX_NIC_FUNC_LINKCTRL 0x00000002
136#define EFX_NIC_FUNC_TRUSTED 0x00000004
137
138
139extern __checkReturn efx_rc_t
140efx_nic_create(
141 __in efx_family_t family,
142 __in efsys_identifier_t *esip,
143 __in efsys_bar_t *esbp,
144 __in efsys_lock_t *eslp,
145 __deref_out efx_nic_t **enpp);
146
147extern __checkReturn efx_rc_t
148efx_nic_probe(
149 __in efx_nic_t *enp);
150
151#if EFSYS_OPT_PCIE_TUNE
152
153extern __checkReturn efx_rc_t
154efx_nic_pcie_tune(
155 __in efx_nic_t *enp,
156 unsigned int nlanes);
157
158extern __checkReturn efx_rc_t
159efx_nic_pcie_extended_sync(
160 __in efx_nic_t *enp);
161
162#endif /* EFSYS_OPT_PCIE_TUNE */
163
164extern __checkReturn efx_rc_t
165efx_nic_init(
166 __in efx_nic_t *enp);
167
168extern __checkReturn efx_rc_t
169efx_nic_reset(
170 __in efx_nic_t *enp);
171
172#if EFSYS_OPT_DIAG
173
174extern __checkReturn efx_rc_t
175efx_nic_register_test(
176 __in efx_nic_t *enp);
177
178#endif /* EFSYS_OPT_DIAG */
179
180extern void
181efx_nic_fini(
182 __in efx_nic_t *enp);
183
184extern void
185efx_nic_unprobe(
186 __in efx_nic_t *enp);
187
188extern void
189efx_nic_destroy(
190 __in efx_nic_t *enp);
191
192#if EFSYS_OPT_MCDI
193
194#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
195/* Huntington and Medford require MCDIv2 commands */
196#define WITH_MCDI_V2 1
197#endif
198
199typedef struct efx_mcdi_req_s efx_mcdi_req_t;
200
201typedef enum efx_mcdi_exception_e {
202 EFX_MCDI_EXCEPTION_MC_REBOOT,
203 EFX_MCDI_EXCEPTION_MC_BADASSERT,
204} efx_mcdi_exception_t;
205
206#if EFSYS_OPT_MCDI_LOGGING
207typedef enum efx_log_msg_e
208{
209 EFX_LOG_INVALID,
210 EFX_LOG_MCDI_REQUEST,
211 EFX_LOG_MCDI_RESPONSE,
212} efx_log_msg_t;
213#endif /* EFSYS_OPT_MCDI_LOGGING */
214
215typedef struct efx_mcdi_transport_s {
216 void *emt_context;
217 efsys_mem_t *emt_dma_mem;
218 void (*emt_execute)(void *, efx_mcdi_req_t *);
219 void (*emt_ev_cpl)(void *);
220 void (*emt_exception)(void *, efx_mcdi_exception_t);
221#if EFSYS_OPT_MCDI_LOGGING
222 void (*emt_logger)(void *, efx_log_msg_t,
223 void *, size_t, void *, size_t);
224#endif /* EFSYS_OPT_MCDI_LOGGING */
225#if EFSYS_OPT_MCDI_PROXY_AUTH
226 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
227#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
228} efx_mcdi_transport_t;
229
230extern __checkReturn efx_rc_t
231efx_mcdi_init(
232 __in efx_nic_t *enp,
233 __in const efx_mcdi_transport_t *mtp);
234
235extern __checkReturn efx_rc_t
236efx_mcdi_reboot(
237 __in efx_nic_t *enp);
238
239 void
240efx_mcdi_new_epoch(
241 __in efx_nic_t *enp);
242
243extern void
244efx_mcdi_request_start(
245 __in efx_nic_t *enp,
246 __in efx_mcdi_req_t *emrp,
247 __in boolean_t ev_cpl);
248
249extern __checkReturn boolean_t
250efx_mcdi_request_poll(
251 __in efx_nic_t *enp);
252
253extern __checkReturn boolean_t
254efx_mcdi_request_abort(
255 __in efx_nic_t *enp);
256
257extern void
258efx_mcdi_fini(
259 __in efx_nic_t *enp);
260
261#endif /* EFSYS_OPT_MCDI */
262
263/* INTR */
264
265#define EFX_NINTR_FALCON 64
266#define EFX_NINTR_SIENA 1024
267
268typedef enum efx_intr_type_e {
269 EFX_INTR_INVALID = 0,
270 EFX_INTR_LINE,
271 EFX_INTR_MESSAGE,
272 EFX_INTR_NTYPES
273} efx_intr_type_t;
274
275#define EFX_INTR_SIZE (sizeof (efx_oword_t))
276
277extern __checkReturn efx_rc_t
278efx_intr_init(
279 __in efx_nic_t *enp,
280 __in efx_intr_type_t type,
281 __in efsys_mem_t *esmp);
282
283extern void
284efx_intr_enable(
285 __in efx_nic_t *enp);
286
287extern void
288efx_intr_disable(
289 __in efx_nic_t *enp);
290
291extern void
292efx_intr_disable_unlocked(
293 __in efx_nic_t *enp);
294
295#define EFX_INTR_NEVQS 32
296
297extern __checkReturn efx_rc_t
298efx_intr_trigger(
299 __in efx_nic_t *enp,
300 __in unsigned int level);
301
302extern void
303efx_intr_status_line(
304 __in efx_nic_t *enp,
305 __out boolean_t *fatalp,
306 __out uint32_t *maskp);
307
308extern void
309efx_intr_status_message(
310 __in efx_nic_t *enp,
311 __in unsigned int message,
312 __out boolean_t *fatalp);
313
314extern void
315efx_intr_fatal(
316 __in efx_nic_t *enp);
317
318extern void
319efx_intr_fini(
320 __in efx_nic_t *enp);
321
322/* MAC */
323
324#if EFSYS_OPT_MAC_STATS
325
326/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
327typedef enum efx_mac_stat_e {
328 EFX_MAC_RX_OCTETS,
329 EFX_MAC_RX_PKTS,
330 EFX_MAC_RX_UNICST_PKTS,
331 EFX_MAC_RX_MULTICST_PKTS,
332 EFX_MAC_RX_BRDCST_PKTS,
333 EFX_MAC_RX_PAUSE_PKTS,
334 EFX_MAC_RX_LE_64_PKTS,
335 EFX_MAC_RX_65_TO_127_PKTS,
336 EFX_MAC_RX_128_TO_255_PKTS,
337 EFX_MAC_RX_256_TO_511_PKTS,
338 EFX_MAC_RX_512_TO_1023_PKTS,
339 EFX_MAC_RX_1024_TO_15XX_PKTS,
340 EFX_MAC_RX_GE_15XX_PKTS,
341 EFX_MAC_RX_ERRORS,
342 EFX_MAC_RX_FCS_ERRORS,
343 EFX_MAC_RX_DROP_EVENTS,
344 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
345 EFX_MAC_RX_SYMBOL_ERRORS,
346 EFX_MAC_RX_ALIGN_ERRORS,
347 EFX_MAC_RX_INTERNAL_ERRORS,
348 EFX_MAC_RX_JABBER_PKTS,
349 EFX_MAC_RX_LANE0_CHAR_ERR,
350 EFX_MAC_RX_LANE1_CHAR_ERR,
351 EFX_MAC_RX_LANE2_CHAR_ERR,
352 EFX_MAC_RX_LANE3_CHAR_ERR,
353 EFX_MAC_RX_LANE0_DISP_ERR,
354 EFX_MAC_RX_LANE1_DISP_ERR,
355 EFX_MAC_RX_LANE2_DISP_ERR,
356 EFX_MAC_RX_LANE3_DISP_ERR,
357 EFX_MAC_RX_MATCH_FAULT,
358 EFX_MAC_RX_NODESC_DROP_CNT,
359 EFX_MAC_TX_OCTETS,
360 EFX_MAC_TX_PKTS,
361 EFX_MAC_TX_UNICST_PKTS,
362 EFX_MAC_TX_MULTICST_PKTS,
363 EFX_MAC_TX_BRDCST_PKTS,
364 EFX_MAC_TX_PAUSE_PKTS,
365 EFX_MAC_TX_LE_64_PKTS,
366 EFX_MAC_TX_65_TO_127_PKTS,
367 EFX_MAC_TX_128_TO_255_PKTS,
368 EFX_MAC_TX_256_TO_511_PKTS,
369 EFX_MAC_TX_512_TO_1023_PKTS,
370 EFX_MAC_TX_1024_TO_15XX_PKTS,
371 EFX_MAC_TX_GE_15XX_PKTS,
372 EFX_MAC_TX_ERRORS,
373 EFX_MAC_TX_SGL_COL_PKTS,
374 EFX_MAC_TX_MULT_COL_PKTS,
375 EFX_MAC_TX_EX_COL_PKTS,
376 EFX_MAC_TX_LATE_COL_PKTS,
377 EFX_MAC_TX_DEF_PKTS,
378 EFX_MAC_TX_EX_DEF_PKTS,
379 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
380 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
381 EFX_MAC_PM_TRUNC_VFIFO_FULL,
382 EFX_MAC_PM_DISCARD_VFIFO_FULL,
383 EFX_MAC_PM_TRUNC_QBB,
384 EFX_MAC_PM_DISCARD_QBB,
385 EFX_MAC_PM_DISCARD_MAPPING,
386 EFX_MAC_RXDP_Q_DISABLED_PKTS,
387 EFX_MAC_RXDP_DI_DROPPED_PKTS,
388 EFX_MAC_RXDP_STREAMING_PKTS,
389 EFX_MAC_RXDP_HLB_FETCH,
390 EFX_MAC_RXDP_HLB_WAIT,
391 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
392 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
393 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
394 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
395 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
396 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
397 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
398 EFX_MAC_VADAPTER_RX_BAD_BYTES,
399 EFX_MAC_VADAPTER_RX_OVERFLOW,
400 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
401 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
402 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
403 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
404 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
405 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
406 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
407 EFX_MAC_VADAPTER_TX_BAD_BYTES,
408 EFX_MAC_VADAPTER_TX_OVERFLOW,
409 EFX_MAC_NSTATS
410} efx_mac_stat_t;
411
412/* END MKCONFIG GENERATED EfxHeaderMacBlock */
413
414#endif /* EFSYS_OPT_MAC_STATS */
415
416typedef enum efx_link_mode_e {
417 EFX_LINK_UNKNOWN = 0,
418 EFX_LINK_DOWN,
419 EFX_LINK_10HDX,
420 EFX_LINK_10FDX,
421 EFX_LINK_100HDX,
422 EFX_LINK_100FDX,
423 EFX_LINK_1000HDX,
424 EFX_LINK_1000FDX,
425 EFX_LINK_10000FDX,
426 EFX_LINK_40000FDX,
427 EFX_LINK_NMODES
428} efx_link_mode_t;
429
430#define EFX_MAC_ADDR_LEN 6
431
432#define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01)
433
434#define EFX_MAC_MULTICAST_LIST_MAX 256
435
436#define EFX_MAC_SDU_MAX 9202
437
438#define EFX_MAC_PDU(_sdu) \
439 P2ROUNDUP(((_sdu) \
440 + /* EtherII */ 14 \
441 + /* VLAN */ 4 \
442 + /* CRC */ 4 \
443 + /* bug16011 */ 16), \
444 (1 << 3))
445
446#define EFX_MAC_PDU_MIN 60
447#define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
448
449extern __checkReturn efx_rc_t
450efx_mac_pdu_set(
451 __in efx_nic_t *enp,
452 __in size_t pdu);
453
454extern __checkReturn efx_rc_t
455efx_mac_addr_set(
456 __in efx_nic_t *enp,
457 __in uint8_t *addr);
458
459extern __checkReturn efx_rc_t
460efx_mac_filter_set(
461 __in efx_nic_t *enp,
462 __in boolean_t all_unicst,
463 __in boolean_t mulcst,
464 __in boolean_t all_mulcst,
465 __in boolean_t brdcst);
466
467extern __checkReturn efx_rc_t
468efx_mac_multicast_list_set(
469 __in efx_nic_t *enp,
470 __in_ecount(6*count) uint8_t const *addrs,
471 __in int count);
472
473extern __checkReturn efx_rc_t
474efx_mac_filter_default_rxq_set(
475 __in efx_nic_t *enp,
476 __in efx_rxq_t *erp,
477 __in boolean_t using_rss);
478
479extern void
480efx_mac_filter_default_rxq_clear(
481 __in efx_nic_t *enp);
482
483extern __checkReturn efx_rc_t
484efx_mac_drain(
485 __in efx_nic_t *enp,
486 __in boolean_t enabled);
487
488extern __checkReturn efx_rc_t
489efx_mac_up(
490 __in efx_nic_t *enp,
491 __out boolean_t *mac_upp);
492
493#define EFX_FCNTL_RESPOND 0x00000001
494#define EFX_FCNTL_GENERATE 0x00000002
495
496extern __checkReturn efx_rc_t
497efx_mac_fcntl_set(
498 __in efx_nic_t *enp,
499 __in unsigned int fcntl,
500 __in boolean_t autoneg);
501
502extern void
503efx_mac_fcntl_get(
504 __in efx_nic_t *enp,
505 __out unsigned int *fcntl_wantedp,
506 __out unsigned int *fcntl_linkp);
507
508
509#if EFSYS_OPT_MAC_STATS
510
511#if EFSYS_OPT_NAMES
512
513extern __checkReturn const char *
514efx_mac_stat_name(
515 __in efx_nic_t *enp,
516 __in unsigned int id);
517
518#endif /* EFSYS_OPT_NAMES */
519
520#define EFX_MAC_STATS_SIZE 0x400
521
522/*
523 * Upload mac statistics supported by the hardware into the given buffer.
524 *
525 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
526 * and page aligned.
527 *
528 * The hardware will only DMA statistics that it understands (of course).
529 * Drivers should not make any assumptions about which statistics are
530 * supported, especially when the statistics are generated by firmware.
531 *
532 * Thus, drivers should zero this buffer before use, so that not-understood
533 * statistics read back as zero.
534 */
535extern __checkReturn efx_rc_t
536efx_mac_stats_upload(
537 __in efx_nic_t *enp,
538 __in efsys_mem_t *esmp);
539
540extern __checkReturn efx_rc_t
541efx_mac_stats_periodic(
542 __in efx_nic_t *enp,
543 __in efsys_mem_t *esmp,
544 __in uint16_t period_ms,
545 __in boolean_t events);
546
547extern __checkReturn efx_rc_t
548efx_mac_stats_update(
549 __in efx_nic_t *enp,
550 __in efsys_mem_t *esmp,
551 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
552 __inout_opt uint32_t *generationp);
553
554#endif /* EFSYS_OPT_MAC_STATS */
555
556/* MON */
557
558typedef enum efx_mon_type_e {
559 EFX_MON_INVALID = 0,
560 EFX_MON_NULL,
561 EFX_MON_LM87,
562 EFX_MON_MAX6647,
563 EFX_MON_SFC90X0,
564 EFX_MON_SFC91X0,
565 EFX_MON_SFC92X0,
566 EFX_MON_NTYPES
567} efx_mon_type_t;
568
569#if EFSYS_OPT_NAMES
570
571extern const char *
572efx_mon_name(
573 __in efx_nic_t *enp);
574
575#endif /* EFSYS_OPT_NAMES */
576
577extern __checkReturn efx_rc_t
578efx_mon_init(
579 __in efx_nic_t *enp);
580
581#if EFSYS_OPT_MON_STATS
582
583#define EFX_MON_STATS_PAGE_SIZE 0x100
584#define EFX_MON_MASK_ELEMENT_SIZE 32
585
586/* START MKCONFIG GENERATED MonitorHeaderStatsBlock c09b13f732431f23 */
587typedef enum efx_mon_stat_e {
588 EFX_MON_STAT_2_5V,
589 EFX_MON_STAT_VCCP1,
590 EFX_MON_STAT_VCC,
591 EFX_MON_STAT_5V,
592 EFX_MON_STAT_12V,
593 EFX_MON_STAT_VCCP2,
594 EFX_MON_STAT_EXT_TEMP,
595 EFX_MON_STAT_INT_TEMP,
596 EFX_MON_STAT_AIN1,
597 EFX_MON_STAT_AIN2,
598 EFX_MON_STAT_INT_COOLING,
599 EFX_MON_STAT_EXT_COOLING,
600 EFX_MON_STAT_1V,
601 EFX_MON_STAT_1_2V,
602 EFX_MON_STAT_1_8V,
603 EFX_MON_STAT_3_3V,
604 EFX_MON_STAT_1_2VA,
605 EFX_MON_STAT_VREF,
606 EFX_MON_STAT_VAOE,
607 EFX_MON_STAT_AOE_TEMP,
608 EFX_MON_STAT_PSU_AOE_TEMP,
609 EFX_MON_STAT_PSU_TEMP,
610 EFX_MON_STAT_FAN0,
611 EFX_MON_STAT_FAN1,
612 EFX_MON_STAT_FAN2,
613 EFX_MON_STAT_FAN3,
614 EFX_MON_STAT_FAN4,
615 EFX_MON_STAT_VAOE_IN,
616 EFX_MON_STAT_IAOE,
617 EFX_MON_STAT_IAOE_IN,
618 EFX_MON_STAT_NIC_POWER,
619 EFX_MON_STAT_0_9V,
620 EFX_MON_STAT_I0_9V,
621 EFX_MON_STAT_I1_2V,
622 EFX_MON_STAT_0_9V_ADC,
623 EFX_MON_STAT_INT_TEMP2,
624 EFX_MON_STAT_VREG_TEMP,
625 EFX_MON_STAT_VREG_0_9V_TEMP,
626 EFX_MON_STAT_VREG_1_2V_TEMP,
627 EFX_MON_STAT_INT_VPTAT,
628 EFX_MON_STAT_INT_ADC_TEMP,
629 EFX_MON_STAT_EXT_VPTAT,
630 EFX_MON_STAT_EXT_ADC_TEMP,
631 EFX_MON_STAT_AMBIENT_TEMP,
632 EFX_MON_STAT_AIRFLOW,
633 EFX_MON_STAT_VDD08D_VSS08D_CSR,
634 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
635 EFX_MON_STAT_HOTPOINT_TEMP,
636 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
637 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
638 EFX_MON_STAT_MUM_VCC,
639 EFX_MON_STAT_0V9_A,
640 EFX_MON_STAT_I0V9_A,
641 EFX_MON_STAT_0V9_A_TEMP,
642 EFX_MON_STAT_0V9_B,
643 EFX_MON_STAT_I0V9_B,
644 EFX_MON_STAT_0V9_B_TEMP,
645 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
646 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
647 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
648 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
649 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
650 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
651 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
652 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
653 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
654 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
655 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
656 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
657 EFX_MON_STAT_SODIMM_VOUT,
658 EFX_MON_STAT_SODIMM_0_TEMP,
659 EFX_MON_STAT_SODIMM_1_TEMP,
660 EFX_MON_STAT_PHY0_VCC,
661 EFX_MON_STAT_PHY1_VCC,
662 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
663 EFX_MON_NSTATS
664} efx_mon_stat_t;
665
666/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
667
668typedef enum efx_mon_stat_state_e {
669 EFX_MON_STAT_STATE_OK = 0,
670 EFX_MON_STAT_STATE_WARNING = 1,
671 EFX_MON_STAT_STATE_FATAL = 2,
672 EFX_MON_STAT_STATE_BROKEN = 3,
673 EFX_MON_STAT_STATE_NO_READING = 4,
674} efx_mon_stat_state_t;
675
676typedef struct efx_mon_stat_value_s {
677 uint16_t emsv_value;
678 uint16_t emsv_state;
679} efx_mon_stat_value_t;
680
681#if EFSYS_OPT_NAMES
682
683extern const char *
684efx_mon_stat_name(
685 __in efx_nic_t *enp,
686 __in efx_mon_stat_t id);
687
688#endif /* EFSYS_OPT_NAMES */
689
690extern __checkReturn efx_rc_t
691efx_mon_stats_update(
692 __in efx_nic_t *enp,
693 __in efsys_mem_t *esmp,
694 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
695
696#endif /* EFSYS_OPT_MON_STATS */
697
698extern void
699efx_mon_fini(
700 __in efx_nic_t *enp);
701
702/* PHY */
703
704#define PMA_PMD_MMD 1
705#define PCS_MMD 3
706#define PHY_XS_MMD 4
707#define DTE_XS_MMD 5
708#define AN_MMD 7
709#define CL22EXT_MMD 29
710
711#define MAXMMD ((1 << 5) - 1)
712
713extern __checkReturn efx_rc_t
714efx_phy_verify(
715 __in efx_nic_t *enp);
716
717#if EFSYS_OPT_PHY_LED_CONTROL
718
719typedef enum efx_phy_led_mode_e {
720 EFX_PHY_LED_DEFAULT = 0,
721 EFX_PHY_LED_OFF,
722 EFX_PHY_LED_ON,
723 EFX_PHY_LED_FLASH,
724 EFX_PHY_LED_NMODES
725} efx_phy_led_mode_t;
726
727extern __checkReturn efx_rc_t
728efx_phy_led_set(
729 __in efx_nic_t *enp,
730 __in efx_phy_led_mode_t mode);
731
732#endif /* EFSYS_OPT_PHY_LED_CONTROL */
733
734extern __checkReturn efx_rc_t
735efx_port_init(
736 __in efx_nic_t *enp);
737
738#if EFSYS_OPT_LOOPBACK
739
740typedef enum efx_loopback_type_e {
741 EFX_LOOPBACK_OFF = 0,
742 EFX_LOOPBACK_DATA = 1,
743 EFX_LOOPBACK_GMAC = 2,
744 EFX_LOOPBACK_XGMII = 3,
745 EFX_LOOPBACK_XGXS = 4,
746 EFX_LOOPBACK_XAUI = 5,
747 EFX_LOOPBACK_GMII = 6,
748 EFX_LOOPBACK_SGMII = 7,
749 EFX_LOOPBACK_XGBR = 8,
750 EFX_LOOPBACK_XFI = 9,
751 EFX_LOOPBACK_XAUI_FAR = 10,
752 EFX_LOOPBACK_GMII_FAR = 11,
753 EFX_LOOPBACK_SGMII_FAR = 12,
754 EFX_LOOPBACK_XFI_FAR = 13,
755 EFX_LOOPBACK_GPHY = 14,
756 EFX_LOOPBACK_PHY_XS = 15,
757 EFX_LOOPBACK_PCS = 16,
758 EFX_LOOPBACK_PMA_PMD = 17,
759 EFX_LOOPBACK_XPORT = 18,
760 EFX_LOOPBACK_XGMII_WS = 19,
761 EFX_LOOPBACK_XAUI_WS = 20,
762 EFX_LOOPBACK_XAUI_WS_FAR = 21,
763 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
764 EFX_LOOPBACK_GMII_WS = 23,
765 EFX_LOOPBACK_XFI_WS = 24,
766 EFX_LOOPBACK_XFI_WS_FAR = 25,
767 EFX_LOOPBACK_PHYXS_WS = 26,
768 EFX_LOOPBACK_PMA_INT = 27,
769 EFX_LOOPBACK_SD_NEAR = 28,
770 EFX_LOOPBACK_SD_FAR = 29,
771 EFX_LOOPBACK_PMA_INT_WS = 30,
772 EFX_LOOPBACK_SD_FEP2_WS = 31,
773 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
774 EFX_LOOPBACK_SD_FEP_WS = 33,
775 EFX_LOOPBACK_SD_FES_WS = 34,
776 EFX_LOOPBACK_NTYPES
777} efx_loopback_type_t;
778
779typedef enum efx_loopback_kind_e {
780 EFX_LOOPBACK_KIND_OFF = 0,
781 EFX_LOOPBACK_KIND_ALL,
782 EFX_LOOPBACK_KIND_MAC,
783 EFX_LOOPBACK_KIND_PHY,
784 EFX_LOOPBACK_NKINDS
785} efx_loopback_kind_t;
786
787extern void
788efx_loopback_mask(
789 __in efx_loopback_kind_t loopback_kind,
790 __out efx_qword_t *maskp);
791
792extern __checkReturn efx_rc_t
793efx_port_loopback_set(
794 __in efx_nic_t *enp,
795 __in efx_link_mode_t link_mode,
796 __in efx_loopback_type_t type);
797
798#if EFSYS_OPT_NAMES
799
800extern __checkReturn const char *
801efx_loopback_type_name(
802 __in efx_nic_t *enp,
803 __in efx_loopback_type_t type);
804
805#endif /* EFSYS_OPT_NAMES */
806
807#endif /* EFSYS_OPT_LOOPBACK */
808
809extern __checkReturn efx_rc_t
810efx_port_poll(
811 __in efx_nic_t *enp,
812 __out_opt efx_link_mode_t *link_modep);
813
814extern void
815efx_port_fini(
816 __in efx_nic_t *enp);
817
818typedef enum efx_phy_cap_type_e {
819 EFX_PHY_CAP_INVALID = 0,
820 EFX_PHY_CAP_10HDX,
821 EFX_PHY_CAP_10FDX,
822 EFX_PHY_CAP_100HDX,
823 EFX_PHY_CAP_100FDX,
824 EFX_PHY_CAP_1000HDX,
825 EFX_PHY_CAP_1000FDX,
826 EFX_PHY_CAP_10000FDX,
827 EFX_PHY_CAP_PAUSE,
828 EFX_PHY_CAP_ASYM,
829 EFX_PHY_CAP_AN,
830 EFX_PHY_CAP_40000FDX,
831 EFX_PHY_CAP_NTYPES
832} efx_phy_cap_type_t;
833
834
835#define EFX_PHY_CAP_CURRENT 0x00000000
836#define EFX_PHY_CAP_DEFAULT 0x00000001
837#define EFX_PHY_CAP_PERM 0x00000002
838
839extern void
840efx_phy_adv_cap_get(
841 __in efx_nic_t *enp,
842 __in uint32_t flag,
843 __out uint32_t *maskp);
844
845extern __checkReturn efx_rc_t
846efx_phy_adv_cap_set(
847 __in efx_nic_t *enp,
848 __in uint32_t mask);
849
850extern void
851efx_phy_lp_cap_get(
852 __in efx_nic_t *enp,
853 __out uint32_t *maskp);
854
855extern __checkReturn efx_rc_t
856efx_phy_oui_get(
857 __in efx_nic_t *enp,
858 __out uint32_t *ouip);
859
860typedef enum efx_phy_media_type_e {
861 EFX_PHY_MEDIA_INVALID = 0,
862 EFX_PHY_MEDIA_XAUI,
863 EFX_PHY_MEDIA_CX4,
864 EFX_PHY_MEDIA_KX4,
865 EFX_PHY_MEDIA_XFP,
866 EFX_PHY_MEDIA_SFP_PLUS,
867 EFX_PHY_MEDIA_BASE_T,
868 EFX_PHY_MEDIA_QSFP_PLUS,
869 EFX_PHY_MEDIA_NTYPES
870} efx_phy_media_type_t;
871
872/* Get the type of medium currently used. If the board has ports for
873 * modules, a module is present, and we recognise the media type of
874 * the module, then this will be the media type of the module.
875 * Otherwise it will be the media type of the port.
876 */
877extern void
878efx_phy_media_type_get(
879 __in efx_nic_t *enp,
880 __out efx_phy_media_type_t *typep);
881
882#if EFSYS_OPT_PHY_STATS
883
884/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
885typedef enum efx_phy_stat_e {
886 EFX_PHY_STAT_OUI,
887 EFX_PHY_STAT_PMA_PMD_LINK_UP,
888 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
889 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
890 EFX_PHY_STAT_PMA_PMD_REV_A,
891 EFX_PHY_STAT_PMA_PMD_REV_B,
892 EFX_PHY_STAT_PMA_PMD_REV_C,
893 EFX_PHY_STAT_PMA_PMD_REV_D,
894 EFX_PHY_STAT_PCS_LINK_UP,
895 EFX_PHY_STAT_PCS_RX_FAULT,
896 EFX_PHY_STAT_PCS_TX_FAULT,
897 EFX_PHY_STAT_PCS_BER,
898 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
899 EFX_PHY_STAT_PHY_XS_LINK_UP,
900 EFX_PHY_STAT_PHY_XS_RX_FAULT,
901 EFX_PHY_STAT_PHY_XS_TX_FAULT,
902 EFX_PHY_STAT_PHY_XS_ALIGN,
903 EFX_PHY_STAT_PHY_XS_SYNC_A,
904 EFX_PHY_STAT_PHY_XS_SYNC_B,
905 EFX_PHY_STAT_PHY_XS_SYNC_C,
906 EFX_PHY_STAT_PHY_XS_SYNC_D,
907 EFX_PHY_STAT_AN_LINK_UP,
908 EFX_PHY_STAT_AN_MASTER,
909 EFX_PHY_STAT_AN_LOCAL_RX_OK,
910 EFX_PHY_STAT_AN_REMOTE_RX_OK,
911 EFX_PHY_STAT_CL22EXT_LINK_UP,
912 EFX_PHY_STAT_SNR_A,
913 EFX_PHY_STAT_SNR_B,
914 EFX_PHY_STAT_SNR_C,
915 EFX_PHY_STAT_SNR_D,
916 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
917 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
918 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
919 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
920 EFX_PHY_STAT_AN_COMPLETE,
921 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
922 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
923 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
924 EFX_PHY_STAT_PCS_FW_VERSION_0,
925 EFX_PHY_STAT_PCS_FW_VERSION_1,
926 EFX_PHY_STAT_PCS_FW_VERSION_2,
927 EFX_PHY_STAT_PCS_FW_VERSION_3,
928 EFX_PHY_STAT_PCS_FW_BUILD_YY,
929 EFX_PHY_STAT_PCS_FW_BUILD_MM,
930 EFX_PHY_STAT_PCS_FW_BUILD_DD,
931 EFX_PHY_STAT_PCS_OP_MODE,
932 EFX_PHY_NSTATS
933} efx_phy_stat_t;
934
935/* END MKCONFIG GENERATED PhyHeaderStatsBlock */
936
937#if EFSYS_OPT_NAMES
938
939extern const char *
940efx_phy_stat_name(
941 __in efx_nic_t *enp,
942 __in efx_phy_stat_t stat);
943
944#endif /* EFSYS_OPT_NAMES */
945
946#define EFX_PHY_STATS_SIZE 0x100
947
948extern __checkReturn efx_rc_t
949efx_phy_stats_update(
950 __in efx_nic_t *enp,
951 __in efsys_mem_t *esmp,
952 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
953
954#endif /* EFSYS_OPT_PHY_STATS */
955
956#if EFSYS_OPT_PHY_PROPS
957
958#if EFSYS_OPT_NAMES
959
960extern const char *
961efx_phy_prop_name(
962 __in efx_nic_t *enp,
963 __in unsigned int id);
964
965#endif /* EFSYS_OPT_NAMES */
966
967#define EFX_PHY_PROP_DEFAULT 0x00000001
968
969extern __checkReturn efx_rc_t
970efx_phy_prop_get(
971 __in efx_nic_t *enp,
972 __in unsigned int id,
973 __in uint32_t flags,
974 __out uint32_t *valp);
975
976extern __checkReturn efx_rc_t
977efx_phy_prop_set(
978 __in efx_nic_t *enp,
979 __in unsigned int id,
980 __in uint32_t val);
981
982#endif /* EFSYS_OPT_PHY_PROPS */
983
984#if EFSYS_OPT_BIST
985
986typedef enum efx_bist_type_e {
987 EFX_BIST_TYPE_UNKNOWN,
988 EFX_BIST_TYPE_PHY_NORMAL,
989 EFX_BIST_TYPE_PHY_CABLE_SHORT,
990 EFX_BIST_TYPE_PHY_CABLE_LONG,
991 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
992 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
993 EFX_BIST_TYPE_REG, /* Test the register memories */
994 EFX_BIST_TYPE_NTYPES,
995} efx_bist_type_t;
996
997typedef enum efx_bist_result_e {
998 EFX_BIST_RESULT_UNKNOWN,
999 EFX_BIST_RESULT_RUNNING,
1000 EFX_BIST_RESULT_PASSED,
1001 EFX_BIST_RESULT_FAILED,
1002} efx_bist_result_t;
1003
1004typedef enum efx_phy_cable_status_e {
1005 EFX_PHY_CABLE_STATUS_OK,
1006 EFX_PHY_CABLE_STATUS_INVALID,
1007 EFX_PHY_CABLE_STATUS_OPEN,
1008 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1009 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1010 EFX_PHY_CABLE_STATUS_BUSY,
1011} efx_phy_cable_status_t;
1012
1013typedef enum efx_bist_value_e {
1014 EFX_BIST_PHY_CABLE_LENGTH_A,
1015 EFX_BIST_PHY_CABLE_LENGTH_B,
1016 EFX_BIST_PHY_CABLE_LENGTH_C,
1017 EFX_BIST_PHY_CABLE_LENGTH_D,
1018 EFX_BIST_PHY_CABLE_STATUS_A,
1019 EFX_BIST_PHY_CABLE_STATUS_B,
1020 EFX_BIST_PHY_CABLE_STATUS_C,
1021 EFX_BIST_PHY_CABLE_STATUS_D,
1022 EFX_BIST_FAULT_CODE,
1023 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1024 * response. */
1025 EFX_BIST_MEM_TEST,
1026 EFX_BIST_MEM_ADDR,
1027 EFX_BIST_MEM_BUS,
1028 EFX_BIST_MEM_EXPECT,
1029 EFX_BIST_MEM_ACTUAL,
1030 EFX_BIST_MEM_ECC,
1031 EFX_BIST_MEM_ECC_PARITY,
1032 EFX_BIST_MEM_ECC_FATAL,
1033 EFX_BIST_NVALUES,
1034} efx_bist_value_t;
1035
1036extern __checkReturn efx_rc_t
1037efx_bist_enable_offline(
1038 __in efx_nic_t *enp);
1039
1040extern __checkReturn efx_rc_t
1041efx_bist_start(
1042 __in efx_nic_t *enp,
1043 __in efx_bist_type_t type);
1044
1045extern __checkReturn efx_rc_t
1046efx_bist_poll(
1047 __in efx_nic_t *enp,
1048 __in efx_bist_type_t type,
1049 __out efx_bist_result_t *resultp,
1050 __out_opt uint32_t *value_maskp,
1051 __out_ecount_opt(count) unsigned long *valuesp,
1052 __in size_t count);
1053
1054extern void
1055efx_bist_stop(
1056 __in efx_nic_t *enp,
1057 __in efx_bist_type_t type);
1058
1059#endif /* EFSYS_OPT_BIST */
1060
1061#define EFX_FEATURE_IPV6 0x00000001
1062#define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1063#define EFX_FEATURE_LINK_EVENTS 0x00000004
1064#define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1065#define EFX_FEATURE_WOL 0x00000010
1066#define EFX_FEATURE_MCDI 0x00000020
1067#define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1068#define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1069#define EFX_FEATURE_TURBO 0x00000100
1070#define EFX_FEATURE_MCDI_DMA 0x00000200
1071#define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1072#define EFX_FEATURE_PIO_BUFFERS 0x00000800
1073#define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1074#define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1075
1076typedef struct efx_nic_cfg_s {
1077 uint32_t enc_board_type;
1078 uint32_t enc_phy_type;
1079#if EFSYS_OPT_NAMES
1080 char enc_phy_name[21];
1081#endif
1082 char enc_phy_revision[21];
1083 efx_mon_type_t enc_mon_type;
1084#if EFSYS_OPT_MON_STATS
1085 uint32_t enc_mon_stat_dma_buf_size;
1086 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1087#endif
1088 unsigned int enc_features;
1089 uint8_t enc_mac_addr[6];
1090 uint8_t enc_port; /* PHY port number */
1091 uint32_t enc_func_flags;
1092 uint32_t enc_intr_vec_base;
1093 uint32_t enc_intr_limit;
1094 uint32_t enc_evq_limit;
1095 uint32_t enc_txq_limit;
1096 uint32_t enc_rxq_limit;
1097 uint32_t enc_buftbl_limit;
1098 uint32_t enc_piobuf_limit;
1099 uint32_t enc_piobuf_size;
1100 uint32_t enc_piobuf_min_alloc_size;
1101 uint32_t enc_evq_timer_quantum_ns;
1102 uint32_t enc_evq_timer_max_us;
1103 uint32_t enc_clk_mult;
1104 uint32_t enc_rx_prefix_size;
1105 uint32_t enc_rx_buf_align_start;
1106 uint32_t enc_rx_buf_align_end;
1107#if EFSYS_OPT_LOOPBACK
1108 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1109#endif /* EFSYS_OPT_LOOPBACK */
1110#if EFSYS_OPT_PHY_FLAGS
1111 uint32_t enc_phy_flags_mask;
1112#endif /* EFSYS_OPT_PHY_FLAGS */
1113#if EFSYS_OPT_PHY_LED_CONTROL
1114 uint32_t enc_led_mask;
1115#endif /* EFSYS_OPT_PHY_LED_CONTROL */
1116#if EFSYS_OPT_PHY_STATS
1117 uint64_t enc_phy_stat_mask;
1118#endif /* EFSYS_OPT_PHY_STATS */
1119#if EFSYS_OPT_PHY_PROPS
1120 unsigned int enc_phy_nprops;
1121#endif /* EFSYS_OPT_PHY_PROPS */
1122#if EFSYS_OPT_SIENA
1123 uint8_t enc_mcdi_mdio_channel;
1124#if EFSYS_OPT_PHY_STATS
1125 uint32_t enc_mcdi_phy_stat_mask;
1126#endif /* EFSYS_OPT_PHY_STATS */
1127#endif /* EFSYS_OPT_SIENA */
1128#if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
1129#if EFSYS_OPT_MON_STATS
1130 uint32_t *enc_mcdi_sensor_maskp;
1131 uint32_t enc_mcdi_sensor_mask_size;
1132#endif /* EFSYS_OPT_MON_STATS */
1133#endif /* (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
1134#if EFSYS_OPT_BIST
1135 uint32_t enc_bist_mask;
1136#endif /* EFSYS_OPT_BIST */
1137#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1138 uint32_t enc_pf;
1139 uint32_t enc_vf;
1140 uint32_t enc_privilege_mask;
1141#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1142 boolean_t enc_bug26807_workaround;
1143 boolean_t enc_bug35388_workaround;
1144 boolean_t enc_bug41750_workaround;
1145 boolean_t enc_rx_batching_enabled;
1146 /* Maximum number of descriptors completed in an rx event. */
1147 uint32_t enc_rx_batch_max;
1148 /* Number of rx descriptors the hardware requires for a push. */
1149 uint32_t enc_rx_push_align;
1150 /*
1151 * Maximum number of bytes into the packet the TCP header can start for
1152 * the hardware to apply TSO packet edits.
1153 */
1154 uint32_t enc_tx_tso_tcp_header_offset_limit;
1155 boolean_t enc_fw_assisted_tso_enabled;
1156 boolean_t enc_fw_assisted_tso_v2_enabled;
1157 boolean_t enc_hw_tx_insert_vlan_enabled;
1158 /* Datapath firmware vadapter/vport/vswitch support */
1159 boolean_t enc_datapath_cap_evb;
1160 boolean_t enc_rx_disable_scatter_supported;
1161 boolean_t enc_allow_set_mac_with_installed_filters;
1162 /* External port identifier */
1163 uint8_t enc_external_port;
1164 uint32_t enc_mcdi_max_payload_length;
1165} efx_nic_cfg_t;
1166
1167#define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1168#define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1169
1170#define EFX_PCI_FUNCTION(_encp) \
1171 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1172
1173#define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1174
1175extern const efx_nic_cfg_t *
1176efx_nic_cfg_get(
1177 __in efx_nic_t *enp);
1178
1179/* Driver resource limits (minimum required/maximum usable). */
1180typedef struct efx_drv_limits_s
1181{
1182 uint32_t edl_min_evq_count;
1183 uint32_t edl_max_evq_count;
1184
1185 uint32_t edl_min_rxq_count;
1186 uint32_t edl_max_rxq_count;
1187
1188 uint32_t edl_min_txq_count;
1189 uint32_t edl_max_txq_count;
1190
1191 /* PIO blocks (sub-allocated from piobuf) */
1192 uint32_t edl_min_pio_alloc_size;
1193 uint32_t edl_max_pio_alloc_count;
1194} efx_drv_limits_t;
1195
1196extern __checkReturn efx_rc_t
1197efx_nic_set_drv_limits(
1198 __inout efx_nic_t *enp,
1199 __in efx_drv_limits_t *edlp);
1200
1201typedef enum efx_nic_region_e {
1202 EFX_REGION_VI, /* Memory BAR UC mapping */
1203 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1204} efx_nic_region_t;
1205
1206extern __checkReturn efx_rc_t
1207efx_nic_get_bar_region(
1208 __in efx_nic_t *enp,
1209 __in efx_nic_region_t region,
1210 __out uint32_t *offsetp,
1211 __out size_t *sizep);
1212
1213extern __checkReturn efx_rc_t
1214efx_nic_get_vi_pool(
1215 __in efx_nic_t *enp,
1216 __out uint32_t *evq_countp,
1217 __out uint32_t *rxq_countp,
1218 __out uint32_t *txq_countp);
1219
1220
1221#if EFSYS_OPT_VPD
1222
1223typedef enum efx_vpd_tag_e {
1224 EFX_VPD_ID = 0x02,
1225 EFX_VPD_END = 0x0f,
1226 EFX_VPD_RO = 0x10,
1227 EFX_VPD_RW = 0x11,
1228} efx_vpd_tag_t;
1229
1230typedef uint16_t efx_vpd_keyword_t;
1231
1232typedef struct efx_vpd_value_s {
1233 efx_vpd_tag_t evv_tag;
1234 efx_vpd_keyword_t evv_keyword;
1235 uint8_t evv_length;
1236 uint8_t evv_value[0x100];
1237} efx_vpd_value_t;
1238
1239
1240#define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1241
1242extern __checkReturn efx_rc_t
1243efx_vpd_init(
1244 __in efx_nic_t *enp);
1245
1246extern __checkReturn efx_rc_t
1247efx_vpd_size(
1248 __in efx_nic_t *enp,
1249 __out size_t *sizep);
1250
1251extern __checkReturn efx_rc_t
1252efx_vpd_read(
1253 __in efx_nic_t *enp,
1254 __out_bcount(size) caddr_t data,
1255 __in size_t size);
1256
1257extern __checkReturn efx_rc_t
1258efx_vpd_verify(
1259 __in efx_nic_t *enp,
1260 __in_bcount(size) caddr_t data,
1261 __in size_t size);
1262
1263extern __checkReturn efx_rc_t
1264efx_vpd_reinit(
1265 __in efx_nic_t *enp,
1266 __in_bcount(size) caddr_t data,
1267 __in size_t size);
1268
1269extern __checkReturn efx_rc_t
1270efx_vpd_get(
1271 __in efx_nic_t *enp,
1272 __in_bcount(size) caddr_t data,
1273 __in size_t size,
1274 __inout efx_vpd_value_t *evvp);
1275
1276extern __checkReturn efx_rc_t
1277efx_vpd_set(
1278 __in efx_nic_t *enp,
1279 __inout_bcount(size) caddr_t data,
1280 __in size_t size,
1281 __in efx_vpd_value_t *evvp);
1282
1283extern __checkReturn efx_rc_t
1284efx_vpd_next(
1285 __in efx_nic_t *enp,
1286 __inout_bcount(size) caddr_t data,
1287 __in size_t size,
1288 __out efx_vpd_value_t *evvp,
1289 __inout unsigned int *contp);
1290
1291extern __checkReturn efx_rc_t
1292efx_vpd_write(
1293 __in efx_nic_t *enp,
1294 __in_bcount(size) caddr_t data,
1295 __in size_t size);
1296
1297extern void
1298efx_vpd_fini(
1299 __in efx_nic_t *enp);
1300
1301#endif /* EFSYS_OPT_VPD */
1302
1303/* NVRAM */
1304
1305#if EFSYS_OPT_NVRAM
1306
1307typedef enum efx_nvram_type_e {
1308 EFX_NVRAM_INVALID = 0,
1309 EFX_NVRAM_BOOTROM,
1310 EFX_NVRAM_BOOTROM_CFG,
1311 EFX_NVRAM_MC_FIRMWARE,
1312 EFX_NVRAM_MC_GOLDEN,
1313 EFX_NVRAM_PHY,
1314 EFX_NVRAM_NULLPHY,
1315 EFX_NVRAM_FPGA,
1316 EFX_NVRAM_FCFW,
1317 EFX_NVRAM_CPLD,
1318 EFX_NVRAM_FPGA_BACKUP,
1319 EFX_NVRAM_DYNAMIC_CFG,
1320 EFX_NVRAM_NTYPES,
1321} efx_nvram_type_t;
1322
1323extern __checkReturn efx_rc_t
1324efx_nvram_init(
1325 __in efx_nic_t *enp);
1326
1327#if EFSYS_OPT_DIAG
1328
1329extern __checkReturn efx_rc_t
1330efx_nvram_test(
1331 __in efx_nic_t *enp);
1332
1333#endif /* EFSYS_OPT_DIAG */
1334
1335extern __checkReturn efx_rc_t
1336efx_nvram_size(
1337 __in efx_nic_t *enp,
1338 __in efx_nvram_type_t type,
1339 __out size_t *sizep);
1340
1341extern __checkReturn efx_rc_t
1342efx_nvram_rw_start(
1343 __in efx_nic_t *enp,
1344 __in efx_nvram_type_t type,
1345 __out_opt size_t *pref_chunkp);
1346
1347extern void
1348efx_nvram_rw_finish(
1349 __in efx_nic_t *enp,
1350 __in efx_nvram_type_t type);
1351
1352extern __checkReturn efx_rc_t
1353efx_nvram_get_version(
1354 __in efx_nic_t *enp,
1355 __in efx_nvram_type_t type,
1356 __out uint32_t *subtypep,
1357 __out_ecount(4) uint16_t version[4]);
1358
1359extern __checkReturn efx_rc_t
1360efx_nvram_read_chunk(
1361 __in efx_nic_t *enp,
1362 __in efx_nvram_type_t type,
1363 __in unsigned int offset,
1364 __out_bcount(size) caddr_t data,
1365 __in size_t size);
1366
1367extern __checkReturn efx_rc_t
1368efx_nvram_set_version(
1369 __in efx_nic_t *enp,
1370 __in efx_nvram_type_t type,
1371 __in_ecount(4) uint16_t version[4]);
1372
1373/* Validate contents of TLV formatted partition */
1374extern __checkReturn efx_rc_t
1375efx_nvram_tlv_validate(
1376 __in efx_nic_t *enp,
1377 __in uint32_t partn,
1378 __in_bcount(partn_size) caddr_t partn_data,
1379 __in size_t partn_size);
1380
1381extern __checkReturn efx_rc_t
1382efx_nvram_erase(
1383 __in efx_nic_t *enp,
1384 __in efx_nvram_type_t type);
1385
1386extern __checkReturn efx_rc_t
1387efx_nvram_write_chunk(
1388 __in efx_nic_t *enp,
1389 __in efx_nvram_type_t type,
1390 __in unsigned int offset,
1391 __in_bcount(size) caddr_t data,
1392 __in size_t size);
1393
1394extern void
1395efx_nvram_fini(
1396 __in efx_nic_t *enp);
1397
1398#endif /* EFSYS_OPT_NVRAM */
1399
1400#if EFSYS_OPT_BOOTCFG
1401
1402extern efx_rc_t
1403efx_bootcfg_read(
1404 __in efx_nic_t *enp,
1405 __out_bcount(size) caddr_t data,
1406 __in size_t size);
1407
1408extern efx_rc_t
1409efx_bootcfg_write(
1410 __in efx_nic_t *enp,
1411 __in_bcount(size) caddr_t data,
1412 __in size_t size);
1413
1414#endif /* EFSYS_OPT_BOOTCFG */
1415
1416#if EFSYS_OPT_WOL
1417
1418typedef enum efx_wol_type_e {
1419 EFX_WOL_TYPE_INVALID,
1420 EFX_WOL_TYPE_MAGIC,
1421 EFX_WOL_TYPE_BITMAP,
1422 EFX_WOL_TYPE_LINK,
1423 EFX_WOL_NTYPES,
1424} efx_wol_type_t;
1425
1426typedef enum efx_lightsout_offload_type_e {
1427 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1428 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1429 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1430} efx_lightsout_offload_type_t;
1431
1432#define EFX_WOL_BITMAP_MASK_SIZE (48)
1433#define EFX_WOL_BITMAP_VALUE_SIZE (128)
1434
1435typedef union efx_wol_param_u {
1436 struct {
1437 uint8_t mac_addr[6];
1438 } ewp_magic;
1439 struct {
1440 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */
1441 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1442 uint8_t value_len;
1443 } ewp_bitmap;
1444} efx_wol_param_t;
1445
1446typedef union efx_lightsout_offload_param_u {
1447 struct {
1448 uint8_t mac_addr[6];
1449 uint32_t ip;
1450 } elop_arp;
1451 struct {
1452 uint8_t mac_addr[6];
1453 uint32_t solicited_node[4];
1454 uint32_t ip[4];
1455 } elop_ns;
1456} efx_lightsout_offload_param_t;
1457
1458extern __checkReturn efx_rc_t
1459efx_wol_init(
1460 __in efx_nic_t *enp);
1461
1462extern __checkReturn efx_rc_t
1463efx_wol_filter_clear(
1464 __in efx_nic_t *enp);
1465
1466extern __checkReturn efx_rc_t
1467efx_wol_filter_add(
1468 __in efx_nic_t *enp,
1469 __in efx_wol_type_t type,
1470 __in efx_wol_param_t *paramp,
1471 __out uint32_t *filter_idp);
1472
1473extern __checkReturn efx_rc_t
1474efx_wol_filter_remove(
1475 __in efx_nic_t *enp,
1476 __in uint32_t filter_id);
1477
1478extern __checkReturn efx_rc_t
1479efx_lightsout_offload_add(
1480 __in efx_nic_t *enp,
1481 __in efx_lightsout_offload_type_t type,
1482 __in efx_lightsout_offload_param_t *paramp,
1483 __out uint32_t *filter_idp);
1484
1485extern __checkReturn efx_rc_t
1486efx_lightsout_offload_remove(
1487 __in efx_nic_t *enp,
1488 __in efx_lightsout_offload_type_t type,
1489 __in uint32_t filter_id);
1490
1491extern void
1492efx_wol_fini(
1493 __in efx_nic_t *enp);
1494
1495#endif /* EFSYS_OPT_WOL */
1496
1497#if EFSYS_OPT_DIAG
1498
1499typedef enum efx_pattern_type_t {
1500 EFX_PATTERN_BYTE_INCREMENT = 0,
1501 EFX_PATTERN_ALL_THE_SAME,
1502 EFX_PATTERN_BIT_ALTERNATE,
1503 EFX_PATTERN_BYTE_ALTERNATE,
1504 EFX_PATTERN_BYTE_CHANGING,
1505 EFX_PATTERN_BIT_SWEEP,
1506 EFX_PATTERN_NTYPES
1507} efx_pattern_type_t;
1508
1509typedef void
1510(*efx_sram_pattern_fn_t)(
1511 __in size_t row,
1512 __in boolean_t negate,
1513 __out efx_qword_t *eqp);
1514
1515extern __checkReturn efx_rc_t
1516efx_sram_test(
1517 __in efx_nic_t *enp,
1518 __in efx_pattern_type_t type);
1519
1520#endif /* EFSYS_OPT_DIAG */
1521
1522extern __checkReturn efx_rc_t
1523efx_sram_buf_tbl_set(
1524 __in efx_nic_t *enp,
1525 __in uint32_t id,
1526 __in efsys_mem_t *esmp,
1527 __in size_t n);
1528
1529extern void
1530efx_sram_buf_tbl_clear(
1531 __in efx_nic_t *enp,
1532 __in uint32_t id,
1533 __in size_t n);
1534
1535#define EFX_BUF_TBL_SIZE 0x20000
1536
1537#define EFX_BUF_SIZE 4096
1538
1539/* EV */
1540
1541typedef struct efx_evq_s efx_evq_t;
1542
1543#if EFSYS_OPT_QSTATS
1544
1545/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1546typedef enum efx_ev_qstat_e {
1547 EV_ALL,
1548 EV_RX,
1549 EV_RX_OK,
1550 EV_RX_FRM_TRUNC,
1551 EV_RX_TOBE_DISC,
1552 EV_RX_PAUSE_FRM_ERR,
1553 EV_RX_BUF_OWNER_ID_ERR,
1554 EV_RX_IPV4_HDR_CHKSUM_ERR,
1555 EV_RX_TCP_UDP_CHKSUM_ERR,
1556 EV_RX_ETH_CRC_ERR,
1557 EV_RX_IP_FRAG_ERR,
1558 EV_RX_MCAST_PKT,
1559 EV_RX_MCAST_HASH_MATCH,
1560 EV_RX_TCP_IPV4,
1561 EV_RX_TCP_IPV6,
1562 EV_RX_UDP_IPV4,
1563 EV_RX_UDP_IPV6,
1564 EV_RX_OTHER_IPV4,
1565 EV_RX_OTHER_IPV6,
1566 EV_RX_NON_IP,
1567 EV_RX_BATCH,
1568 EV_TX,
1569 EV_TX_WQ_FF_FULL,
1570 EV_TX_PKT_ERR,
1571 EV_TX_PKT_TOO_BIG,
1572 EV_TX_UNEXPECTED,
1573 EV_GLOBAL,
1574 EV_GLOBAL_MNT,
1575 EV_DRIVER,
1576 EV_DRIVER_SRM_UPD_DONE,
1577 EV_DRIVER_TX_DESCQ_FLS_DONE,
1578 EV_DRIVER_RX_DESCQ_FLS_DONE,
1579 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1580 EV_DRIVER_RX_DSC_ERROR,
1581 EV_DRIVER_TX_DSC_ERROR,
1582 EV_DRV_GEN,
1583 EV_MCDI_RESPONSE,
1584 EV_NQSTATS
1585} efx_ev_qstat_t;
1586
1587/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1588
1589#endif /* EFSYS_OPT_QSTATS */
1590
1591extern __checkReturn efx_rc_t
1592efx_ev_init(
1593 __in efx_nic_t *enp);
1594
1595extern void
1596efx_ev_fini(
1597 __in efx_nic_t *enp);
1598
1599#define EFX_EVQ_MAXNEVS 32768
1600#define EFX_EVQ_MINNEVS 512
1601
1602#define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1603#define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1604
1605extern __checkReturn efx_rc_t
1606efx_ev_qcreate(
1607 __in efx_nic_t *enp,
1608 __in unsigned int index,
1609 __in efsys_mem_t *esmp,
1610 __in size_t n,
1611 __in uint32_t id,
1612 __deref_out efx_evq_t **eepp);
1613
1614extern void
1615efx_ev_qpost(
1616 __in efx_evq_t *eep,
1617 __in uint16_t data);
1618
1619typedef __checkReturn boolean_t
1620(*efx_initialized_ev_t)(
1621 __in_opt void *arg);
1622
1623#define EFX_PKT_UNICAST 0x0004
1624#define EFX_PKT_START 0x0008
1625
1626#define EFX_PKT_VLAN_TAGGED 0x0010
1627#define EFX_CKSUM_TCPUDP 0x0020
1628#define EFX_CKSUM_IPV4 0x0040
1629#define EFX_PKT_CONT 0x0080
1630
1631#define EFX_CHECK_VLAN 0x0100
1632#define EFX_PKT_TCP 0x0200
1633#define EFX_PKT_UDP 0x0400
1634#define EFX_PKT_IPV4 0x0800
1635
1636#define EFX_PKT_IPV6 0x1000
1637#define EFX_PKT_PREFIX_LEN 0x2000
1638#define EFX_ADDR_MISMATCH 0x4000
1639#define EFX_DISCARD 0x8000
1640
1641#define EFX_EV_RX_NLABELS 32
1642#define EFX_EV_TX_NLABELS 32
1643
1644typedef __checkReturn boolean_t
1645(*efx_rx_ev_t)(
1646 __in_opt void *arg,
1647 __in uint32_t label,
1648 __in uint32_t id,
1649 __in uint32_t size,
1650 __in uint16_t flags);
1651
1652typedef __checkReturn boolean_t
1653(*efx_tx_ev_t)(
1654 __in_opt void *arg,
1655 __in uint32_t label,
1656 __in uint32_t id);
1657
1658#define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1659#define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1660#define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1661#define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1662#define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1663#define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1664#define EFX_EXCEPTION_RX_ERROR 0x00000007
1665#define EFX_EXCEPTION_TX_ERROR 0x00000008
1666#define EFX_EXCEPTION_EV_ERROR 0x00000009
1667
1668typedef __checkReturn boolean_t
1669(*efx_exception_ev_t)(
1670 __in_opt void *arg,
1671 __in uint32_t label,
1672 __in uint32_t data);
1673
1674typedef __checkReturn boolean_t
1675(*efx_rxq_flush_done_ev_t)(
1676 __in_opt void *arg,
1677 __in uint32_t rxq_index);
1678
1679typedef __checkReturn boolean_t
1680(*efx_rxq_flush_failed_ev_t)(
1681 __in_opt void *arg,
1682 __in uint32_t rxq_index);
1683
1684typedef __checkReturn boolean_t
1685(*efx_txq_flush_done_ev_t)(
1686 __in_opt void *arg,
1687 __in uint32_t txq_index);
1688
1689typedef __checkReturn boolean_t
1690(*efx_software_ev_t)(
1691 __in_opt void *arg,
1692 __in uint16_t magic);
1693
1694typedef __checkReturn boolean_t
1695(*efx_sram_ev_t)(
1696 __in_opt void *arg,
1697 __in uint32_t code);
1698
1699#define EFX_SRAM_CLEAR 0
1700#define EFX_SRAM_UPDATE 1
1701#define EFX_SRAM_ILLEGAL_CLEAR 2
1702
1703typedef __checkReturn boolean_t
1704(*efx_wake_up_ev_t)(
1705 __in_opt void *arg,
1706 __in uint32_t label);
1707
1708typedef __checkReturn boolean_t
1709(*efx_timer_ev_t)(
1710 __in_opt void *arg,
1711 __in uint32_t label);
1712
1713typedef __checkReturn boolean_t
1714(*efx_link_change_ev_t)(
1715 __in_opt void *arg,
1716 __in efx_link_mode_t link_mode);
1717
1718#if EFSYS_OPT_MON_STATS
1719
1720typedef __checkReturn boolean_t
1721(*efx_monitor_ev_t)(
1722 __in_opt void *arg,
1723 __in efx_mon_stat_t id,
1724 __in efx_mon_stat_value_t value);
1725
1726#endif /* EFSYS_OPT_MON_STATS */
1727
1728#if EFSYS_OPT_MAC_STATS
1729
1730typedef __checkReturn boolean_t
1731(*efx_mac_stats_ev_t)(
1732 __in_opt void *arg,
1733 __in uint32_t generation
1734 );
1735
1736#endif /* EFSYS_OPT_MAC_STATS */
1737
1738typedef struct efx_ev_callbacks_s {
1739 efx_initialized_ev_t eec_initialized;
1740 efx_rx_ev_t eec_rx;
1741 efx_tx_ev_t eec_tx;
1742 efx_exception_ev_t eec_exception;
1743 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1744 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1745 efx_txq_flush_done_ev_t eec_txq_flush_done;
1746 efx_software_ev_t eec_software;
1747 efx_sram_ev_t eec_sram;
1748 efx_wake_up_ev_t eec_wake_up;
1749 efx_timer_ev_t eec_timer;
1750 efx_link_change_ev_t eec_link_change;
1751#if EFSYS_OPT_MON_STATS
1752 efx_monitor_ev_t eec_monitor;
1753#endif /* EFSYS_OPT_MON_STATS */
1754#if EFSYS_OPT_MAC_STATS
1755 efx_mac_stats_ev_t eec_mac_stats;
1756#endif /* EFSYS_OPT_MAC_STATS */
1757} efx_ev_callbacks_t;
1758
1759extern __checkReturn boolean_t
1760efx_ev_qpending(
1761 __in efx_evq_t *eep,
1762 __in unsigned int count);
1763
1764#if EFSYS_OPT_EV_PREFETCH
1765
1766extern void
1767efx_ev_qprefetch(
1768 __in efx_evq_t *eep,
1769 __in unsigned int count);
1770
1771#endif /* EFSYS_OPT_EV_PREFETCH */
1772
1773extern void
1774efx_ev_qpoll(
1775 __in efx_evq_t *eep,
1776 __inout unsigned int *countp,
1777 __in const efx_ev_callbacks_t *eecp,
1778 __in_opt void *arg);
1779
1780extern __checkReturn efx_rc_t
1781efx_ev_qmoderate(
1782 __in efx_evq_t *eep,
1783 __in unsigned int us);
1784
1785extern __checkReturn efx_rc_t
1786efx_ev_qprime(
1787 __in efx_evq_t *eep,
1788 __in unsigned int count);
1789
1790#if EFSYS_OPT_QSTATS
1791
1792#if EFSYS_OPT_NAMES
1793
1794extern const char *
1795efx_ev_qstat_name(
1796 __in efx_nic_t *enp,
1797 __in unsigned int id);
1798
1799#endif /* EFSYS_OPT_NAMES */
1800
1801extern void
1802efx_ev_qstats_update(
1803 __in efx_evq_t *eep,
1804 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1805
1806#endif /* EFSYS_OPT_QSTATS */
1807
1808extern void
1809efx_ev_qdestroy(
1810 __in efx_evq_t *eep);
1811
1812/* RX */
1813
1814extern __checkReturn efx_rc_t
1815efx_rx_init(
1816 __inout efx_nic_t *enp);
1817
1818extern void
1819efx_rx_fini(
1820 __in efx_nic_t *enp);
1821
1822#if EFSYS_OPT_RX_SCATTER
1823 __checkReturn efx_rc_t
1824efx_rx_scatter_enable(
1825 __in efx_nic_t *enp,
1826 __in unsigned int buf_size);
1827#endif /* EFSYS_OPT_RX_SCATTER */
1828
1829#if EFSYS_OPT_RX_SCALE
1830
1831typedef enum efx_rx_hash_alg_e {
1832 EFX_RX_HASHALG_LFSR = 0,
1833 EFX_RX_HASHALG_TOEPLITZ
1834} efx_rx_hash_alg_t;
1835
1836typedef enum efx_rx_hash_type_e {
1837 EFX_RX_HASH_IPV4 = 0,
1838 EFX_RX_HASH_TCPIPV4,
1839 EFX_RX_HASH_IPV6,
1840 EFX_RX_HASH_TCPIPV6,
1841} efx_rx_hash_type_t;
1842
1843typedef enum efx_rx_hash_support_e {
1844 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1845 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1846} efx_rx_hash_support_t;
1847
1848#define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1849#define EFX_MAXRSS 64 /* RX indirection entry range */
1850#define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1851
1852typedef enum efx_rx_scale_support_e {
1853 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */
1854 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1855 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1856} efx_rx_scale_support_t;
1857
1858extern __checkReturn efx_rc_t
1859efx_rx_hash_support_get(
1860 __in efx_nic_t *enp,
1861 __out efx_rx_hash_support_t *supportp);
1862
1863
1864extern __checkReturn efx_rc_t
1865efx_rx_scale_support_get(
1866 __in efx_nic_t *enp,
1867 __out efx_rx_scale_support_t *supportp);
1868
1869extern __checkReturn efx_rc_t
1870efx_rx_scale_mode_set(
1871 __in efx_nic_t *enp,
1872 __in efx_rx_hash_alg_t alg,
1873 __in efx_rx_hash_type_t type,
1874 __in boolean_t insert);
1875
1876extern __checkReturn efx_rc_t
1877efx_rx_scale_tbl_set(
1878 __in efx_nic_t *enp,
1879 __in_ecount(n) unsigned int *table,
1880 __in size_t n);
1881
1882extern __checkReturn efx_rc_t
1883efx_rx_scale_key_set(
1884 __in efx_nic_t *enp,
1885 __in_ecount(n) uint8_t *key,
1886 __in size_t n);
1887
1888extern __checkReturn uint32_t
1889efx_psuedo_hdr_hash_get(
1890 __in efx_nic_t *enp,
1891 __in efx_rx_hash_alg_t func,
1892 __in uint8_t *buffer);
1893
1894#endif /* EFSYS_OPT_RX_SCALE */
1895
1896extern __checkReturn efx_rc_t
1897efx_psuedo_hdr_pkt_length_get(
1898 __in efx_nic_t *enp,
1899 __in uint8_t *buffer,
1900 __out uint16_t *pkt_lengthp);
1901
1902#define EFX_RXQ_MAXNDESCS 4096
1903#define EFX_RXQ_MINNDESCS 512
1904
1905#define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1906#define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1907#define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1908#define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1909
1910typedef enum efx_rxq_type_e {
1911 EFX_RXQ_TYPE_DEFAULT,
1912 EFX_RXQ_TYPE_SCATTER,
1913 EFX_RXQ_NTYPES
1914} efx_rxq_type_t;
1915
1916extern __checkReturn efx_rc_t
1917efx_rx_qcreate(
1918 __in efx_nic_t *enp,
1919 __in unsigned int index,
1920 __in unsigned int label,
1921 __in efx_rxq_type_t type,
1922 __in efsys_mem_t *esmp,
1923 __in size_t n,
1924 __in uint32_t id,
1925 __in efx_evq_t *eep,
1926 __deref_out efx_rxq_t **erpp);
1927
1928typedef struct efx_buffer_s {
1929 efsys_dma_addr_t eb_addr;
1930 size_t eb_size;
1931 boolean_t eb_eop;
1932} efx_buffer_t;
1933
1934typedef struct efx_desc_s {
1935 efx_qword_t ed_eq;
1936} efx_desc_t;
1937
1938extern void
1939efx_rx_qpost(
1940 __in efx_rxq_t *erp,
1941 __in_ecount(n) efsys_dma_addr_t *addrp,
1942 __in size_t size,
1943 __in unsigned int n,
1944 __in unsigned int completed,
1945 __in unsigned int added);
1946
1947extern void
1948efx_rx_qpush(
1949 __in efx_rxq_t *erp,
1950 __in unsigned int added,
1951 __inout unsigned int *pushedp);
1952
1953extern __checkReturn efx_rc_t
1954efx_rx_qflush(
1955 __in efx_rxq_t *erp);
1956
1957extern void
1958efx_rx_qenable(
1959 __in efx_rxq_t *erp);
1960
1961extern void
1962efx_rx_qdestroy(
1963 __in efx_rxq_t *erp);
1964
1965/* TX */
1966
1967typedef struct efx_txq_s efx_txq_t;
1968
1969#if EFSYS_OPT_QSTATS
1970
1971/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1972typedef enum efx_tx_qstat_e {
1973 TX_POST,
1974 TX_POST_PIO,
1975 TX_NQSTATS
1976} efx_tx_qstat_t;
1977
1978/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1979
1980#endif /* EFSYS_OPT_QSTATS */
1981
1982extern __checkReturn efx_rc_t
1983efx_tx_init(
1984 __in efx_nic_t *enp);
1985
1986extern void
1987efx_tx_fini(
1988 __in efx_nic_t *enp);
1989
1990#define EFX_BUG35388_WORKAROUND(_encp) \
1991 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
1992
1993#define EFX_TXQ_MAXNDESCS(_encp) \
1994 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
1995
1996#define EFX_TXQ_MINNDESCS 512
1997
1998#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1999#define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2000#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2001#define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2002
2003#define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2004
2005#define EFX_TXQ_CKSUM_IPV4 0x0001
2006#define EFX_TXQ_CKSUM_TCPUDP 0x0002
2007#define EFX_TXQ_FATSOV2 0x0004
2008
2009extern __checkReturn efx_rc_t
2010efx_tx_qcreate(
2011 __in efx_nic_t *enp,
2012 __in unsigned int index,
2013 __in unsigned int label,
2014 __in efsys_mem_t *esmp,
2015 __in size_t n,
2016 __in uint32_t id,
2017 __in uint16_t flags,
2018 __in efx_evq_t *eep,
2019 __deref_out efx_txq_t **etpp,
2020 __out unsigned int *addedp);
2021
2022extern __checkReturn efx_rc_t
2023efx_tx_qpost(
2024 __in efx_txq_t *etp,
2025 __in_ecount(n) efx_buffer_t *eb,
2026 __in unsigned int n,
2027 __in unsigned int completed,
2028 __inout unsigned int *addedp);
2029
2030extern __checkReturn efx_rc_t
2031efx_tx_qpace(
2032 __in efx_txq_t *etp,
2033 __in unsigned int ns);
2034
2035extern void
2036efx_tx_qpush(
2037 __in efx_txq_t *etp,
2038 __in unsigned int added,
2039 __in unsigned int pushed);
2040
2041extern __checkReturn efx_rc_t
2042efx_tx_qflush(
2043 __in efx_txq_t *etp);
2044
2045extern void
2046efx_tx_qenable(
2047 __in efx_txq_t *etp);
2048
2049extern __checkReturn efx_rc_t
2050efx_tx_qpio_enable(
2051 __in efx_txq_t *etp);
2052
2053extern void
2054efx_tx_qpio_disable(
2055 __in efx_txq_t *etp);
2056
2057extern __checkReturn efx_rc_t
2058efx_tx_qpio_write(
2059 __in efx_txq_t *etp,
2060 __in_ecount(buf_length) uint8_t *buffer,
2061 __in size_t buf_length,
2062 __in size_t pio_buf_offset);
2063
2064extern __checkReturn efx_rc_t
2065efx_tx_qpio_post(
2066 __in efx_txq_t *etp,
2067 __in size_t pkt_length,
2068 __in unsigned int completed,
2069 __inout unsigned int *addedp);
2070
2071extern __checkReturn efx_rc_t
2072efx_tx_qdesc_post(
2073 __in efx_txq_t *etp,
2074 __in_ecount(n) efx_desc_t *ed,
2075 __in unsigned int n,
2076 __in unsigned int completed,
2077 __inout unsigned int *addedp);
2078
2079extern void
2080efx_tx_qdesc_dma_create(
2081 __in efx_txq_t *etp,
2082 __in efsys_dma_addr_t addr,
2083 __in size_t size,
2084 __in boolean_t eop,
2085 __out efx_desc_t *edp);
2086
2087extern void
2088efx_tx_qdesc_tso_create(
2089 __in efx_txq_t *etp,
2090 __in uint16_t ipv4_id,
2091 __in uint32_t tcp_seq,
2092 __in uint8_t tcp_flags,
2093 __out efx_desc_t *edp);
2094
2095/* Number of FATSOv2 option descriptors */
2096#define EFX_TX_FATSOV2_OPT_NDESCS 2
2097
2098/* Maximum number of DMA segments per TSO packet (not superframe) */
2099#define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2100
2101extern void
2102efx_tx_qdesc_tso2_create(
2103 __in efx_txq_t *etp,
2104 __in uint16_t ipv4_id,
2105 __in uint32_t tcp_seq,
2106 __in uint16_t tcp_mss,
2107 __out_ecount(count) efx_desc_t *edp,
2108 __in int count);
2109
2110extern void
2111efx_tx_qdesc_vlantci_create(
2112 __in efx_txq_t *etp,
2113 __in uint16_t tci,
2114 __out efx_desc_t *edp);
2115
2116#if EFSYS_OPT_QSTATS
2117
2118#if EFSYS_OPT_NAMES
2119
2120extern const char *
2121efx_tx_qstat_name(
2122 __in efx_nic_t *etp,
2123 __in unsigned int id);
2124
2125#endif /* EFSYS_OPT_NAMES */
2126
2127extern void
2128efx_tx_qstats_update(
2129 __in efx_txq_t *etp,
2130 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2131
2132#endif /* EFSYS_OPT_QSTATS */
2133
2134extern void
2135efx_tx_qdestroy(
2136 __in efx_txq_t *etp);
2137
2138
2139/* FILTER */
2140
2141#if EFSYS_OPT_FILTER
2142
2143#define EFX_ETHER_TYPE_IPV4 0x0800
2144#define EFX_ETHER_TYPE_IPV6 0x86DD
2145
2146#define EFX_IPPROTO_TCP 6
2147#define EFX_IPPROTO_UDP 17
2148
2149typedef enum efx_filter_flag_e {
2150 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across
2151 * multiple queues */
2152 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */
2153 EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04, /* Override an automatic filter
2154 * (priority EFX_FILTER_PRI_AUTO).
2155 * May only be set by the filter
2156 * implementation for each type.
2157 * A removal request will
2158 * restore the automatic filter
2159 * in its place. */
2160 EFX_FILTER_FLAG_RX = 0x08, /* Filter is for RX */
2161 EFX_FILTER_FLAG_TX = 0x10, /* Filter is for TX */
2162} efx_filter_flag_t;
2163
2164typedef enum efx_filter_match_flags_e {
2165 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
2166 * address */
2167 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
2168 * address */
2169 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
2170 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
2171 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
2172 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
2173 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
2174 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
2175 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
2176 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
2177 * protocol */
2178 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
2179 * I/G bit. Used for RX default
2180 * unicast and multicast/
2181 * broadcast filters. */
2182} efx_filter_match_flags_t;
2183
2184typedef enum efx_filter_priority_s {
2185 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2186 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2187 * address list or hardware
2188 * requirements. This may only be used
2189 * by the filter implementation for
2190 * each NIC type. */
2191 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2192 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2193 * client (e.g. SR-IOV, HyperV VMQ etc.)
2194 */
2195} efx_filter_priority_t;
2196
2197/*
2198 * FIXME: All these fields are assumed to be in little-endian byte order.
2199 * It may be better for some to be big-endian. See bug42804.
2200 */
2201
2202typedef struct efx_filter_spec_s {
2203 uint32_t efs_match_flags:12;
2204 uint32_t efs_priority:2;
2205 uint32_t efs_flags:6;
2206 uint32_t efs_dmaq_id:12;
2207 uint32_t efs_rss_context;
2208 uint16_t efs_outer_vid;
2209 uint16_t efs_inner_vid;
2210 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2211 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2212 uint16_t efs_ether_type;
2213 uint8_t efs_ip_proto;
2214 uint16_t efs_loc_port;
2215 uint16_t efs_rem_port;
2216 efx_oword_t efs_rem_host;
2217 efx_oword_t efs_loc_host;
2218} efx_filter_spec_t;
2219
2220
2221/* Default values for use in filter specifications */
2222#define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
2223#define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2224#define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2225
2226extern __checkReturn efx_rc_t
2227efx_filter_init(
2228 __in efx_nic_t *enp);
2229
2230extern void
2231efx_filter_fini(
2232 __in efx_nic_t *enp);
2233
2234extern __checkReturn efx_rc_t
2235efx_filter_insert(
2236 __in efx_nic_t *enp,
2237 __inout efx_filter_spec_t *spec);
2238
2239extern __checkReturn efx_rc_t
2240efx_filter_remove(
2241 __in efx_nic_t *enp,
2242 __inout efx_filter_spec_t *spec);
2243
2244extern __checkReturn efx_rc_t
2245efx_filter_restore(
2246 __in efx_nic_t *enp);
2247
2248extern __checkReturn efx_rc_t
2249efx_filter_supported_filters(
2250 __in efx_nic_t *enp,
2251 __out uint32_t *list,
2252 __out size_t *length);
2253
2254extern void
2255efx_filter_spec_init_rx(
2256 __out efx_filter_spec_t *spec,
2257 __in efx_filter_priority_t priority,
2258 __in efx_filter_flag_t flags,
2259 __in efx_rxq_t *erp);
2260
2261extern void
2262efx_filter_spec_init_tx(
2263 __out efx_filter_spec_t *spec,
2264 __in efx_txq_t *etp);
2265
2266extern __checkReturn efx_rc_t
2267efx_filter_spec_set_ipv4_local(
2268 __inout efx_filter_spec_t *spec,
2269 __in uint8_t proto,
2270 __in uint32_t host,
2271 __in uint16_t port);
2272
2273extern __checkReturn efx_rc_t
2274efx_filter_spec_set_ipv4_full(
2275 __inout efx_filter_spec_t *spec,
2276 __in uint8_t proto,
2277 __in uint32_t lhost,
2278 __in uint16_t lport,
2279 __in uint32_t rhost,
2280 __in uint16_t rport);
2281
2282extern __checkReturn efx_rc_t
2283efx_filter_spec_set_eth_local(
2284 __inout efx_filter_spec_t *spec,
2285 __in uint16_t vid,
2286 __in const uint8_t *addr);
2287
2288extern __checkReturn efx_rc_t
2289efx_filter_spec_set_uc_def(
2290 __inout efx_filter_spec_t *spec);
2291
2292extern __checkReturn efx_rc_t
2293efx_filter_spec_set_mc_def(
2294 __inout efx_filter_spec_t *spec);
2295
2296#endif /* EFSYS_OPT_FILTER */
2297
2298/* HASH */
2299
2300extern __checkReturn uint32_t
2301efx_hash_dwords(
2302 __in_ecount(count) uint32_t const *input,
2303 __in size_t count,
2304 __in uint32_t init);
2305
2306extern __checkReturn uint32_t
2307efx_hash_bytes(
2308 __in_ecount(length) uint8_t const *input,
2309 __in size_t length,
2310 __in uint32_t init);
2311
2312
2313#ifdef __cplusplus
2314}
2315#endif
2316
2317#endif /* _SYS_EFX_H */
2 * Copyright (c) 2006-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: head/sys/dev/sfxge/common/efx.h 293891 2016-01-14 09:05:51Z arybchik $
31 */
32
33#ifndef _SYS_EFX_H
34#define _SYS_EFX_H
35
36#include "efsys.h"
37#include "efx_phy_ids.h"
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43#define EFX_STATIC_ASSERT(_cond) \
44 ((void)sizeof(char[(_cond) ? 1 : -1]))
45
46#define EFX_ARRAY_SIZE(_array) \
47 (sizeof(_array) / sizeof((_array)[0]))
48
49#define EFX_FIELD_OFFSET(_type, _field) \
50 ((size_t) &(((_type *)0)->_field))
51
52/* Return codes */
53
54typedef __success(return == 0) int efx_rc_t;
55
56
57/* Chip families */
58
59typedef enum efx_family_e {
60 EFX_FAMILY_INVALID,
61 EFX_FAMILY_FALCON,
62 EFX_FAMILY_SIENA,
63 EFX_FAMILY_HUNTINGTON,
64 EFX_FAMILY_MEDFORD,
65 EFX_FAMILY_NTYPES
66} efx_family_t;
67
68extern __checkReturn efx_rc_t
69efx_family(
70 __in uint16_t venid,
71 __in uint16_t devid,
72 __out efx_family_t *efp);
73
74extern __checkReturn efx_rc_t
75efx_infer_family(
76 __in efsys_bar_t *esbp,
77 __out efx_family_t *efp);
78
79#define EFX_PCI_VENID_SFC 0x1924
80
81#define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
82
83#define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
84#define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
85#define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
86
87#define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
88#define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
89#define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
90
91#define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
92#define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
93
94#define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
95#define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
96#define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
97
98#define EFX_MEM_BAR 2
99
100/* Error codes */
101
102enum {
103 EFX_ERR_INVALID,
104 EFX_ERR_SRAM_OOB,
105 EFX_ERR_BUFID_DC_OOB,
106 EFX_ERR_MEM_PERR,
107 EFX_ERR_RBUF_OWN,
108 EFX_ERR_TBUF_OWN,
109 EFX_ERR_RDESQ_OWN,
110 EFX_ERR_TDESQ_OWN,
111 EFX_ERR_EVQ_OWN,
112 EFX_ERR_EVFF_OFLO,
113 EFX_ERR_ILL_ADDR,
114 EFX_ERR_SRAM_PERR,
115 EFX_ERR_NCODES
116};
117
118/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
119extern __checkReturn uint32_t
120efx_crc32_calculate(
121 __in uint32_t crc_init,
122 __in_ecount(length) uint8_t const *input,
123 __in int length);
124
125
126/* Type prototypes */
127
128typedef struct efx_rxq_s efx_rxq_t;
129
130/* NIC */
131
132typedef struct efx_nic_s efx_nic_t;
133
134#define EFX_NIC_FUNC_PRIMARY 0x00000001
135#define EFX_NIC_FUNC_LINKCTRL 0x00000002
136#define EFX_NIC_FUNC_TRUSTED 0x00000004
137
138
139extern __checkReturn efx_rc_t
140efx_nic_create(
141 __in efx_family_t family,
142 __in efsys_identifier_t *esip,
143 __in efsys_bar_t *esbp,
144 __in efsys_lock_t *eslp,
145 __deref_out efx_nic_t **enpp);
146
147extern __checkReturn efx_rc_t
148efx_nic_probe(
149 __in efx_nic_t *enp);
150
151#if EFSYS_OPT_PCIE_TUNE
152
153extern __checkReturn efx_rc_t
154efx_nic_pcie_tune(
155 __in efx_nic_t *enp,
156 unsigned int nlanes);
157
158extern __checkReturn efx_rc_t
159efx_nic_pcie_extended_sync(
160 __in efx_nic_t *enp);
161
162#endif /* EFSYS_OPT_PCIE_TUNE */
163
164extern __checkReturn efx_rc_t
165efx_nic_init(
166 __in efx_nic_t *enp);
167
168extern __checkReturn efx_rc_t
169efx_nic_reset(
170 __in efx_nic_t *enp);
171
172#if EFSYS_OPT_DIAG
173
174extern __checkReturn efx_rc_t
175efx_nic_register_test(
176 __in efx_nic_t *enp);
177
178#endif /* EFSYS_OPT_DIAG */
179
180extern void
181efx_nic_fini(
182 __in efx_nic_t *enp);
183
184extern void
185efx_nic_unprobe(
186 __in efx_nic_t *enp);
187
188extern void
189efx_nic_destroy(
190 __in efx_nic_t *enp);
191
192#if EFSYS_OPT_MCDI
193
194#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
195/* Huntington and Medford require MCDIv2 commands */
196#define WITH_MCDI_V2 1
197#endif
198
199typedef struct efx_mcdi_req_s efx_mcdi_req_t;
200
201typedef enum efx_mcdi_exception_e {
202 EFX_MCDI_EXCEPTION_MC_REBOOT,
203 EFX_MCDI_EXCEPTION_MC_BADASSERT,
204} efx_mcdi_exception_t;
205
206#if EFSYS_OPT_MCDI_LOGGING
207typedef enum efx_log_msg_e
208{
209 EFX_LOG_INVALID,
210 EFX_LOG_MCDI_REQUEST,
211 EFX_LOG_MCDI_RESPONSE,
212} efx_log_msg_t;
213#endif /* EFSYS_OPT_MCDI_LOGGING */
214
215typedef struct efx_mcdi_transport_s {
216 void *emt_context;
217 efsys_mem_t *emt_dma_mem;
218 void (*emt_execute)(void *, efx_mcdi_req_t *);
219 void (*emt_ev_cpl)(void *);
220 void (*emt_exception)(void *, efx_mcdi_exception_t);
221#if EFSYS_OPT_MCDI_LOGGING
222 void (*emt_logger)(void *, efx_log_msg_t,
223 void *, size_t, void *, size_t);
224#endif /* EFSYS_OPT_MCDI_LOGGING */
225#if EFSYS_OPT_MCDI_PROXY_AUTH
226 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
227#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
228} efx_mcdi_transport_t;
229
230extern __checkReturn efx_rc_t
231efx_mcdi_init(
232 __in efx_nic_t *enp,
233 __in const efx_mcdi_transport_t *mtp);
234
235extern __checkReturn efx_rc_t
236efx_mcdi_reboot(
237 __in efx_nic_t *enp);
238
239 void
240efx_mcdi_new_epoch(
241 __in efx_nic_t *enp);
242
243extern void
244efx_mcdi_request_start(
245 __in efx_nic_t *enp,
246 __in efx_mcdi_req_t *emrp,
247 __in boolean_t ev_cpl);
248
249extern __checkReturn boolean_t
250efx_mcdi_request_poll(
251 __in efx_nic_t *enp);
252
253extern __checkReturn boolean_t
254efx_mcdi_request_abort(
255 __in efx_nic_t *enp);
256
257extern void
258efx_mcdi_fini(
259 __in efx_nic_t *enp);
260
261#endif /* EFSYS_OPT_MCDI */
262
263/* INTR */
264
265#define EFX_NINTR_FALCON 64
266#define EFX_NINTR_SIENA 1024
267
268typedef enum efx_intr_type_e {
269 EFX_INTR_INVALID = 0,
270 EFX_INTR_LINE,
271 EFX_INTR_MESSAGE,
272 EFX_INTR_NTYPES
273} efx_intr_type_t;
274
275#define EFX_INTR_SIZE (sizeof (efx_oword_t))
276
277extern __checkReturn efx_rc_t
278efx_intr_init(
279 __in efx_nic_t *enp,
280 __in efx_intr_type_t type,
281 __in efsys_mem_t *esmp);
282
283extern void
284efx_intr_enable(
285 __in efx_nic_t *enp);
286
287extern void
288efx_intr_disable(
289 __in efx_nic_t *enp);
290
291extern void
292efx_intr_disable_unlocked(
293 __in efx_nic_t *enp);
294
295#define EFX_INTR_NEVQS 32
296
297extern __checkReturn efx_rc_t
298efx_intr_trigger(
299 __in efx_nic_t *enp,
300 __in unsigned int level);
301
302extern void
303efx_intr_status_line(
304 __in efx_nic_t *enp,
305 __out boolean_t *fatalp,
306 __out uint32_t *maskp);
307
308extern void
309efx_intr_status_message(
310 __in efx_nic_t *enp,
311 __in unsigned int message,
312 __out boolean_t *fatalp);
313
314extern void
315efx_intr_fatal(
316 __in efx_nic_t *enp);
317
318extern void
319efx_intr_fini(
320 __in efx_nic_t *enp);
321
322/* MAC */
323
324#if EFSYS_OPT_MAC_STATS
325
326/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
327typedef enum efx_mac_stat_e {
328 EFX_MAC_RX_OCTETS,
329 EFX_MAC_RX_PKTS,
330 EFX_MAC_RX_UNICST_PKTS,
331 EFX_MAC_RX_MULTICST_PKTS,
332 EFX_MAC_RX_BRDCST_PKTS,
333 EFX_MAC_RX_PAUSE_PKTS,
334 EFX_MAC_RX_LE_64_PKTS,
335 EFX_MAC_RX_65_TO_127_PKTS,
336 EFX_MAC_RX_128_TO_255_PKTS,
337 EFX_MAC_RX_256_TO_511_PKTS,
338 EFX_MAC_RX_512_TO_1023_PKTS,
339 EFX_MAC_RX_1024_TO_15XX_PKTS,
340 EFX_MAC_RX_GE_15XX_PKTS,
341 EFX_MAC_RX_ERRORS,
342 EFX_MAC_RX_FCS_ERRORS,
343 EFX_MAC_RX_DROP_EVENTS,
344 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
345 EFX_MAC_RX_SYMBOL_ERRORS,
346 EFX_MAC_RX_ALIGN_ERRORS,
347 EFX_MAC_RX_INTERNAL_ERRORS,
348 EFX_MAC_RX_JABBER_PKTS,
349 EFX_MAC_RX_LANE0_CHAR_ERR,
350 EFX_MAC_RX_LANE1_CHAR_ERR,
351 EFX_MAC_RX_LANE2_CHAR_ERR,
352 EFX_MAC_RX_LANE3_CHAR_ERR,
353 EFX_MAC_RX_LANE0_DISP_ERR,
354 EFX_MAC_RX_LANE1_DISP_ERR,
355 EFX_MAC_RX_LANE2_DISP_ERR,
356 EFX_MAC_RX_LANE3_DISP_ERR,
357 EFX_MAC_RX_MATCH_FAULT,
358 EFX_MAC_RX_NODESC_DROP_CNT,
359 EFX_MAC_TX_OCTETS,
360 EFX_MAC_TX_PKTS,
361 EFX_MAC_TX_UNICST_PKTS,
362 EFX_MAC_TX_MULTICST_PKTS,
363 EFX_MAC_TX_BRDCST_PKTS,
364 EFX_MAC_TX_PAUSE_PKTS,
365 EFX_MAC_TX_LE_64_PKTS,
366 EFX_MAC_TX_65_TO_127_PKTS,
367 EFX_MAC_TX_128_TO_255_PKTS,
368 EFX_MAC_TX_256_TO_511_PKTS,
369 EFX_MAC_TX_512_TO_1023_PKTS,
370 EFX_MAC_TX_1024_TO_15XX_PKTS,
371 EFX_MAC_TX_GE_15XX_PKTS,
372 EFX_MAC_TX_ERRORS,
373 EFX_MAC_TX_SGL_COL_PKTS,
374 EFX_MAC_TX_MULT_COL_PKTS,
375 EFX_MAC_TX_EX_COL_PKTS,
376 EFX_MAC_TX_LATE_COL_PKTS,
377 EFX_MAC_TX_DEF_PKTS,
378 EFX_MAC_TX_EX_DEF_PKTS,
379 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
380 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
381 EFX_MAC_PM_TRUNC_VFIFO_FULL,
382 EFX_MAC_PM_DISCARD_VFIFO_FULL,
383 EFX_MAC_PM_TRUNC_QBB,
384 EFX_MAC_PM_DISCARD_QBB,
385 EFX_MAC_PM_DISCARD_MAPPING,
386 EFX_MAC_RXDP_Q_DISABLED_PKTS,
387 EFX_MAC_RXDP_DI_DROPPED_PKTS,
388 EFX_MAC_RXDP_STREAMING_PKTS,
389 EFX_MAC_RXDP_HLB_FETCH,
390 EFX_MAC_RXDP_HLB_WAIT,
391 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
392 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
393 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
394 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
395 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
396 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
397 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
398 EFX_MAC_VADAPTER_RX_BAD_BYTES,
399 EFX_MAC_VADAPTER_RX_OVERFLOW,
400 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
401 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
402 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
403 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
404 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
405 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
406 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
407 EFX_MAC_VADAPTER_TX_BAD_BYTES,
408 EFX_MAC_VADAPTER_TX_OVERFLOW,
409 EFX_MAC_NSTATS
410} efx_mac_stat_t;
411
412/* END MKCONFIG GENERATED EfxHeaderMacBlock */
413
414#endif /* EFSYS_OPT_MAC_STATS */
415
416typedef enum efx_link_mode_e {
417 EFX_LINK_UNKNOWN = 0,
418 EFX_LINK_DOWN,
419 EFX_LINK_10HDX,
420 EFX_LINK_10FDX,
421 EFX_LINK_100HDX,
422 EFX_LINK_100FDX,
423 EFX_LINK_1000HDX,
424 EFX_LINK_1000FDX,
425 EFX_LINK_10000FDX,
426 EFX_LINK_40000FDX,
427 EFX_LINK_NMODES
428} efx_link_mode_t;
429
430#define EFX_MAC_ADDR_LEN 6
431
432#define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01)
433
434#define EFX_MAC_MULTICAST_LIST_MAX 256
435
436#define EFX_MAC_SDU_MAX 9202
437
438#define EFX_MAC_PDU(_sdu) \
439 P2ROUNDUP(((_sdu) \
440 + /* EtherII */ 14 \
441 + /* VLAN */ 4 \
442 + /* CRC */ 4 \
443 + /* bug16011 */ 16), \
444 (1 << 3))
445
446#define EFX_MAC_PDU_MIN 60
447#define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
448
449extern __checkReturn efx_rc_t
450efx_mac_pdu_set(
451 __in efx_nic_t *enp,
452 __in size_t pdu);
453
454extern __checkReturn efx_rc_t
455efx_mac_addr_set(
456 __in efx_nic_t *enp,
457 __in uint8_t *addr);
458
459extern __checkReturn efx_rc_t
460efx_mac_filter_set(
461 __in efx_nic_t *enp,
462 __in boolean_t all_unicst,
463 __in boolean_t mulcst,
464 __in boolean_t all_mulcst,
465 __in boolean_t brdcst);
466
467extern __checkReturn efx_rc_t
468efx_mac_multicast_list_set(
469 __in efx_nic_t *enp,
470 __in_ecount(6*count) uint8_t const *addrs,
471 __in int count);
472
473extern __checkReturn efx_rc_t
474efx_mac_filter_default_rxq_set(
475 __in efx_nic_t *enp,
476 __in efx_rxq_t *erp,
477 __in boolean_t using_rss);
478
479extern void
480efx_mac_filter_default_rxq_clear(
481 __in efx_nic_t *enp);
482
483extern __checkReturn efx_rc_t
484efx_mac_drain(
485 __in efx_nic_t *enp,
486 __in boolean_t enabled);
487
488extern __checkReturn efx_rc_t
489efx_mac_up(
490 __in efx_nic_t *enp,
491 __out boolean_t *mac_upp);
492
493#define EFX_FCNTL_RESPOND 0x00000001
494#define EFX_FCNTL_GENERATE 0x00000002
495
496extern __checkReturn efx_rc_t
497efx_mac_fcntl_set(
498 __in efx_nic_t *enp,
499 __in unsigned int fcntl,
500 __in boolean_t autoneg);
501
502extern void
503efx_mac_fcntl_get(
504 __in efx_nic_t *enp,
505 __out unsigned int *fcntl_wantedp,
506 __out unsigned int *fcntl_linkp);
507
508
509#if EFSYS_OPT_MAC_STATS
510
511#if EFSYS_OPT_NAMES
512
513extern __checkReturn const char *
514efx_mac_stat_name(
515 __in efx_nic_t *enp,
516 __in unsigned int id);
517
518#endif /* EFSYS_OPT_NAMES */
519
520#define EFX_MAC_STATS_SIZE 0x400
521
522/*
523 * Upload mac statistics supported by the hardware into the given buffer.
524 *
525 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
526 * and page aligned.
527 *
528 * The hardware will only DMA statistics that it understands (of course).
529 * Drivers should not make any assumptions about which statistics are
530 * supported, especially when the statistics are generated by firmware.
531 *
532 * Thus, drivers should zero this buffer before use, so that not-understood
533 * statistics read back as zero.
534 */
535extern __checkReturn efx_rc_t
536efx_mac_stats_upload(
537 __in efx_nic_t *enp,
538 __in efsys_mem_t *esmp);
539
540extern __checkReturn efx_rc_t
541efx_mac_stats_periodic(
542 __in efx_nic_t *enp,
543 __in efsys_mem_t *esmp,
544 __in uint16_t period_ms,
545 __in boolean_t events);
546
547extern __checkReturn efx_rc_t
548efx_mac_stats_update(
549 __in efx_nic_t *enp,
550 __in efsys_mem_t *esmp,
551 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
552 __inout_opt uint32_t *generationp);
553
554#endif /* EFSYS_OPT_MAC_STATS */
555
556/* MON */
557
558typedef enum efx_mon_type_e {
559 EFX_MON_INVALID = 0,
560 EFX_MON_NULL,
561 EFX_MON_LM87,
562 EFX_MON_MAX6647,
563 EFX_MON_SFC90X0,
564 EFX_MON_SFC91X0,
565 EFX_MON_SFC92X0,
566 EFX_MON_NTYPES
567} efx_mon_type_t;
568
569#if EFSYS_OPT_NAMES
570
571extern const char *
572efx_mon_name(
573 __in efx_nic_t *enp);
574
575#endif /* EFSYS_OPT_NAMES */
576
577extern __checkReturn efx_rc_t
578efx_mon_init(
579 __in efx_nic_t *enp);
580
581#if EFSYS_OPT_MON_STATS
582
583#define EFX_MON_STATS_PAGE_SIZE 0x100
584#define EFX_MON_MASK_ELEMENT_SIZE 32
585
586/* START MKCONFIG GENERATED MonitorHeaderStatsBlock c09b13f732431f23 */
587typedef enum efx_mon_stat_e {
588 EFX_MON_STAT_2_5V,
589 EFX_MON_STAT_VCCP1,
590 EFX_MON_STAT_VCC,
591 EFX_MON_STAT_5V,
592 EFX_MON_STAT_12V,
593 EFX_MON_STAT_VCCP2,
594 EFX_MON_STAT_EXT_TEMP,
595 EFX_MON_STAT_INT_TEMP,
596 EFX_MON_STAT_AIN1,
597 EFX_MON_STAT_AIN2,
598 EFX_MON_STAT_INT_COOLING,
599 EFX_MON_STAT_EXT_COOLING,
600 EFX_MON_STAT_1V,
601 EFX_MON_STAT_1_2V,
602 EFX_MON_STAT_1_8V,
603 EFX_MON_STAT_3_3V,
604 EFX_MON_STAT_1_2VA,
605 EFX_MON_STAT_VREF,
606 EFX_MON_STAT_VAOE,
607 EFX_MON_STAT_AOE_TEMP,
608 EFX_MON_STAT_PSU_AOE_TEMP,
609 EFX_MON_STAT_PSU_TEMP,
610 EFX_MON_STAT_FAN0,
611 EFX_MON_STAT_FAN1,
612 EFX_MON_STAT_FAN2,
613 EFX_MON_STAT_FAN3,
614 EFX_MON_STAT_FAN4,
615 EFX_MON_STAT_VAOE_IN,
616 EFX_MON_STAT_IAOE,
617 EFX_MON_STAT_IAOE_IN,
618 EFX_MON_STAT_NIC_POWER,
619 EFX_MON_STAT_0_9V,
620 EFX_MON_STAT_I0_9V,
621 EFX_MON_STAT_I1_2V,
622 EFX_MON_STAT_0_9V_ADC,
623 EFX_MON_STAT_INT_TEMP2,
624 EFX_MON_STAT_VREG_TEMP,
625 EFX_MON_STAT_VREG_0_9V_TEMP,
626 EFX_MON_STAT_VREG_1_2V_TEMP,
627 EFX_MON_STAT_INT_VPTAT,
628 EFX_MON_STAT_INT_ADC_TEMP,
629 EFX_MON_STAT_EXT_VPTAT,
630 EFX_MON_STAT_EXT_ADC_TEMP,
631 EFX_MON_STAT_AMBIENT_TEMP,
632 EFX_MON_STAT_AIRFLOW,
633 EFX_MON_STAT_VDD08D_VSS08D_CSR,
634 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
635 EFX_MON_STAT_HOTPOINT_TEMP,
636 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
637 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
638 EFX_MON_STAT_MUM_VCC,
639 EFX_MON_STAT_0V9_A,
640 EFX_MON_STAT_I0V9_A,
641 EFX_MON_STAT_0V9_A_TEMP,
642 EFX_MON_STAT_0V9_B,
643 EFX_MON_STAT_I0V9_B,
644 EFX_MON_STAT_0V9_B_TEMP,
645 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
646 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
647 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
648 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
649 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
650 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
651 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
652 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
653 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
654 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
655 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
656 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
657 EFX_MON_STAT_SODIMM_VOUT,
658 EFX_MON_STAT_SODIMM_0_TEMP,
659 EFX_MON_STAT_SODIMM_1_TEMP,
660 EFX_MON_STAT_PHY0_VCC,
661 EFX_MON_STAT_PHY1_VCC,
662 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
663 EFX_MON_NSTATS
664} efx_mon_stat_t;
665
666/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
667
668typedef enum efx_mon_stat_state_e {
669 EFX_MON_STAT_STATE_OK = 0,
670 EFX_MON_STAT_STATE_WARNING = 1,
671 EFX_MON_STAT_STATE_FATAL = 2,
672 EFX_MON_STAT_STATE_BROKEN = 3,
673 EFX_MON_STAT_STATE_NO_READING = 4,
674} efx_mon_stat_state_t;
675
676typedef struct efx_mon_stat_value_s {
677 uint16_t emsv_value;
678 uint16_t emsv_state;
679} efx_mon_stat_value_t;
680
681#if EFSYS_OPT_NAMES
682
683extern const char *
684efx_mon_stat_name(
685 __in efx_nic_t *enp,
686 __in efx_mon_stat_t id);
687
688#endif /* EFSYS_OPT_NAMES */
689
690extern __checkReturn efx_rc_t
691efx_mon_stats_update(
692 __in efx_nic_t *enp,
693 __in efsys_mem_t *esmp,
694 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
695
696#endif /* EFSYS_OPT_MON_STATS */
697
698extern void
699efx_mon_fini(
700 __in efx_nic_t *enp);
701
702/* PHY */
703
704#define PMA_PMD_MMD 1
705#define PCS_MMD 3
706#define PHY_XS_MMD 4
707#define DTE_XS_MMD 5
708#define AN_MMD 7
709#define CL22EXT_MMD 29
710
711#define MAXMMD ((1 << 5) - 1)
712
713extern __checkReturn efx_rc_t
714efx_phy_verify(
715 __in efx_nic_t *enp);
716
717#if EFSYS_OPT_PHY_LED_CONTROL
718
719typedef enum efx_phy_led_mode_e {
720 EFX_PHY_LED_DEFAULT = 0,
721 EFX_PHY_LED_OFF,
722 EFX_PHY_LED_ON,
723 EFX_PHY_LED_FLASH,
724 EFX_PHY_LED_NMODES
725} efx_phy_led_mode_t;
726
727extern __checkReturn efx_rc_t
728efx_phy_led_set(
729 __in efx_nic_t *enp,
730 __in efx_phy_led_mode_t mode);
731
732#endif /* EFSYS_OPT_PHY_LED_CONTROL */
733
734extern __checkReturn efx_rc_t
735efx_port_init(
736 __in efx_nic_t *enp);
737
738#if EFSYS_OPT_LOOPBACK
739
740typedef enum efx_loopback_type_e {
741 EFX_LOOPBACK_OFF = 0,
742 EFX_LOOPBACK_DATA = 1,
743 EFX_LOOPBACK_GMAC = 2,
744 EFX_LOOPBACK_XGMII = 3,
745 EFX_LOOPBACK_XGXS = 4,
746 EFX_LOOPBACK_XAUI = 5,
747 EFX_LOOPBACK_GMII = 6,
748 EFX_LOOPBACK_SGMII = 7,
749 EFX_LOOPBACK_XGBR = 8,
750 EFX_LOOPBACK_XFI = 9,
751 EFX_LOOPBACK_XAUI_FAR = 10,
752 EFX_LOOPBACK_GMII_FAR = 11,
753 EFX_LOOPBACK_SGMII_FAR = 12,
754 EFX_LOOPBACK_XFI_FAR = 13,
755 EFX_LOOPBACK_GPHY = 14,
756 EFX_LOOPBACK_PHY_XS = 15,
757 EFX_LOOPBACK_PCS = 16,
758 EFX_LOOPBACK_PMA_PMD = 17,
759 EFX_LOOPBACK_XPORT = 18,
760 EFX_LOOPBACK_XGMII_WS = 19,
761 EFX_LOOPBACK_XAUI_WS = 20,
762 EFX_LOOPBACK_XAUI_WS_FAR = 21,
763 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
764 EFX_LOOPBACK_GMII_WS = 23,
765 EFX_LOOPBACK_XFI_WS = 24,
766 EFX_LOOPBACK_XFI_WS_FAR = 25,
767 EFX_LOOPBACK_PHYXS_WS = 26,
768 EFX_LOOPBACK_PMA_INT = 27,
769 EFX_LOOPBACK_SD_NEAR = 28,
770 EFX_LOOPBACK_SD_FAR = 29,
771 EFX_LOOPBACK_PMA_INT_WS = 30,
772 EFX_LOOPBACK_SD_FEP2_WS = 31,
773 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
774 EFX_LOOPBACK_SD_FEP_WS = 33,
775 EFX_LOOPBACK_SD_FES_WS = 34,
776 EFX_LOOPBACK_NTYPES
777} efx_loopback_type_t;
778
779typedef enum efx_loopback_kind_e {
780 EFX_LOOPBACK_KIND_OFF = 0,
781 EFX_LOOPBACK_KIND_ALL,
782 EFX_LOOPBACK_KIND_MAC,
783 EFX_LOOPBACK_KIND_PHY,
784 EFX_LOOPBACK_NKINDS
785} efx_loopback_kind_t;
786
787extern void
788efx_loopback_mask(
789 __in efx_loopback_kind_t loopback_kind,
790 __out efx_qword_t *maskp);
791
792extern __checkReturn efx_rc_t
793efx_port_loopback_set(
794 __in efx_nic_t *enp,
795 __in efx_link_mode_t link_mode,
796 __in efx_loopback_type_t type);
797
798#if EFSYS_OPT_NAMES
799
800extern __checkReturn const char *
801efx_loopback_type_name(
802 __in efx_nic_t *enp,
803 __in efx_loopback_type_t type);
804
805#endif /* EFSYS_OPT_NAMES */
806
807#endif /* EFSYS_OPT_LOOPBACK */
808
809extern __checkReturn efx_rc_t
810efx_port_poll(
811 __in efx_nic_t *enp,
812 __out_opt efx_link_mode_t *link_modep);
813
814extern void
815efx_port_fini(
816 __in efx_nic_t *enp);
817
818typedef enum efx_phy_cap_type_e {
819 EFX_PHY_CAP_INVALID = 0,
820 EFX_PHY_CAP_10HDX,
821 EFX_PHY_CAP_10FDX,
822 EFX_PHY_CAP_100HDX,
823 EFX_PHY_CAP_100FDX,
824 EFX_PHY_CAP_1000HDX,
825 EFX_PHY_CAP_1000FDX,
826 EFX_PHY_CAP_10000FDX,
827 EFX_PHY_CAP_PAUSE,
828 EFX_PHY_CAP_ASYM,
829 EFX_PHY_CAP_AN,
830 EFX_PHY_CAP_40000FDX,
831 EFX_PHY_CAP_NTYPES
832} efx_phy_cap_type_t;
833
834
835#define EFX_PHY_CAP_CURRENT 0x00000000
836#define EFX_PHY_CAP_DEFAULT 0x00000001
837#define EFX_PHY_CAP_PERM 0x00000002
838
839extern void
840efx_phy_adv_cap_get(
841 __in efx_nic_t *enp,
842 __in uint32_t flag,
843 __out uint32_t *maskp);
844
845extern __checkReturn efx_rc_t
846efx_phy_adv_cap_set(
847 __in efx_nic_t *enp,
848 __in uint32_t mask);
849
850extern void
851efx_phy_lp_cap_get(
852 __in efx_nic_t *enp,
853 __out uint32_t *maskp);
854
855extern __checkReturn efx_rc_t
856efx_phy_oui_get(
857 __in efx_nic_t *enp,
858 __out uint32_t *ouip);
859
860typedef enum efx_phy_media_type_e {
861 EFX_PHY_MEDIA_INVALID = 0,
862 EFX_PHY_MEDIA_XAUI,
863 EFX_PHY_MEDIA_CX4,
864 EFX_PHY_MEDIA_KX4,
865 EFX_PHY_MEDIA_XFP,
866 EFX_PHY_MEDIA_SFP_PLUS,
867 EFX_PHY_MEDIA_BASE_T,
868 EFX_PHY_MEDIA_QSFP_PLUS,
869 EFX_PHY_MEDIA_NTYPES
870} efx_phy_media_type_t;
871
872/* Get the type of medium currently used. If the board has ports for
873 * modules, a module is present, and we recognise the media type of
874 * the module, then this will be the media type of the module.
875 * Otherwise it will be the media type of the port.
876 */
877extern void
878efx_phy_media_type_get(
879 __in efx_nic_t *enp,
880 __out efx_phy_media_type_t *typep);
881
882#if EFSYS_OPT_PHY_STATS
883
884/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
885typedef enum efx_phy_stat_e {
886 EFX_PHY_STAT_OUI,
887 EFX_PHY_STAT_PMA_PMD_LINK_UP,
888 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
889 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
890 EFX_PHY_STAT_PMA_PMD_REV_A,
891 EFX_PHY_STAT_PMA_PMD_REV_B,
892 EFX_PHY_STAT_PMA_PMD_REV_C,
893 EFX_PHY_STAT_PMA_PMD_REV_D,
894 EFX_PHY_STAT_PCS_LINK_UP,
895 EFX_PHY_STAT_PCS_RX_FAULT,
896 EFX_PHY_STAT_PCS_TX_FAULT,
897 EFX_PHY_STAT_PCS_BER,
898 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
899 EFX_PHY_STAT_PHY_XS_LINK_UP,
900 EFX_PHY_STAT_PHY_XS_RX_FAULT,
901 EFX_PHY_STAT_PHY_XS_TX_FAULT,
902 EFX_PHY_STAT_PHY_XS_ALIGN,
903 EFX_PHY_STAT_PHY_XS_SYNC_A,
904 EFX_PHY_STAT_PHY_XS_SYNC_B,
905 EFX_PHY_STAT_PHY_XS_SYNC_C,
906 EFX_PHY_STAT_PHY_XS_SYNC_D,
907 EFX_PHY_STAT_AN_LINK_UP,
908 EFX_PHY_STAT_AN_MASTER,
909 EFX_PHY_STAT_AN_LOCAL_RX_OK,
910 EFX_PHY_STAT_AN_REMOTE_RX_OK,
911 EFX_PHY_STAT_CL22EXT_LINK_UP,
912 EFX_PHY_STAT_SNR_A,
913 EFX_PHY_STAT_SNR_B,
914 EFX_PHY_STAT_SNR_C,
915 EFX_PHY_STAT_SNR_D,
916 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
917 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
918 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
919 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
920 EFX_PHY_STAT_AN_COMPLETE,
921 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
922 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
923 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
924 EFX_PHY_STAT_PCS_FW_VERSION_0,
925 EFX_PHY_STAT_PCS_FW_VERSION_1,
926 EFX_PHY_STAT_PCS_FW_VERSION_2,
927 EFX_PHY_STAT_PCS_FW_VERSION_3,
928 EFX_PHY_STAT_PCS_FW_BUILD_YY,
929 EFX_PHY_STAT_PCS_FW_BUILD_MM,
930 EFX_PHY_STAT_PCS_FW_BUILD_DD,
931 EFX_PHY_STAT_PCS_OP_MODE,
932 EFX_PHY_NSTATS
933} efx_phy_stat_t;
934
935/* END MKCONFIG GENERATED PhyHeaderStatsBlock */
936
937#if EFSYS_OPT_NAMES
938
939extern const char *
940efx_phy_stat_name(
941 __in efx_nic_t *enp,
942 __in efx_phy_stat_t stat);
943
944#endif /* EFSYS_OPT_NAMES */
945
946#define EFX_PHY_STATS_SIZE 0x100
947
948extern __checkReturn efx_rc_t
949efx_phy_stats_update(
950 __in efx_nic_t *enp,
951 __in efsys_mem_t *esmp,
952 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
953
954#endif /* EFSYS_OPT_PHY_STATS */
955
956#if EFSYS_OPT_PHY_PROPS
957
958#if EFSYS_OPT_NAMES
959
960extern const char *
961efx_phy_prop_name(
962 __in efx_nic_t *enp,
963 __in unsigned int id);
964
965#endif /* EFSYS_OPT_NAMES */
966
967#define EFX_PHY_PROP_DEFAULT 0x00000001
968
969extern __checkReturn efx_rc_t
970efx_phy_prop_get(
971 __in efx_nic_t *enp,
972 __in unsigned int id,
973 __in uint32_t flags,
974 __out uint32_t *valp);
975
976extern __checkReturn efx_rc_t
977efx_phy_prop_set(
978 __in efx_nic_t *enp,
979 __in unsigned int id,
980 __in uint32_t val);
981
982#endif /* EFSYS_OPT_PHY_PROPS */
983
984#if EFSYS_OPT_BIST
985
986typedef enum efx_bist_type_e {
987 EFX_BIST_TYPE_UNKNOWN,
988 EFX_BIST_TYPE_PHY_NORMAL,
989 EFX_BIST_TYPE_PHY_CABLE_SHORT,
990 EFX_BIST_TYPE_PHY_CABLE_LONG,
991 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
992 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
993 EFX_BIST_TYPE_REG, /* Test the register memories */
994 EFX_BIST_TYPE_NTYPES,
995} efx_bist_type_t;
996
997typedef enum efx_bist_result_e {
998 EFX_BIST_RESULT_UNKNOWN,
999 EFX_BIST_RESULT_RUNNING,
1000 EFX_BIST_RESULT_PASSED,
1001 EFX_BIST_RESULT_FAILED,
1002} efx_bist_result_t;
1003
1004typedef enum efx_phy_cable_status_e {
1005 EFX_PHY_CABLE_STATUS_OK,
1006 EFX_PHY_CABLE_STATUS_INVALID,
1007 EFX_PHY_CABLE_STATUS_OPEN,
1008 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1009 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1010 EFX_PHY_CABLE_STATUS_BUSY,
1011} efx_phy_cable_status_t;
1012
1013typedef enum efx_bist_value_e {
1014 EFX_BIST_PHY_CABLE_LENGTH_A,
1015 EFX_BIST_PHY_CABLE_LENGTH_B,
1016 EFX_BIST_PHY_CABLE_LENGTH_C,
1017 EFX_BIST_PHY_CABLE_LENGTH_D,
1018 EFX_BIST_PHY_CABLE_STATUS_A,
1019 EFX_BIST_PHY_CABLE_STATUS_B,
1020 EFX_BIST_PHY_CABLE_STATUS_C,
1021 EFX_BIST_PHY_CABLE_STATUS_D,
1022 EFX_BIST_FAULT_CODE,
1023 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1024 * response. */
1025 EFX_BIST_MEM_TEST,
1026 EFX_BIST_MEM_ADDR,
1027 EFX_BIST_MEM_BUS,
1028 EFX_BIST_MEM_EXPECT,
1029 EFX_BIST_MEM_ACTUAL,
1030 EFX_BIST_MEM_ECC,
1031 EFX_BIST_MEM_ECC_PARITY,
1032 EFX_BIST_MEM_ECC_FATAL,
1033 EFX_BIST_NVALUES,
1034} efx_bist_value_t;
1035
1036extern __checkReturn efx_rc_t
1037efx_bist_enable_offline(
1038 __in efx_nic_t *enp);
1039
1040extern __checkReturn efx_rc_t
1041efx_bist_start(
1042 __in efx_nic_t *enp,
1043 __in efx_bist_type_t type);
1044
1045extern __checkReturn efx_rc_t
1046efx_bist_poll(
1047 __in efx_nic_t *enp,
1048 __in efx_bist_type_t type,
1049 __out efx_bist_result_t *resultp,
1050 __out_opt uint32_t *value_maskp,
1051 __out_ecount_opt(count) unsigned long *valuesp,
1052 __in size_t count);
1053
1054extern void
1055efx_bist_stop(
1056 __in efx_nic_t *enp,
1057 __in efx_bist_type_t type);
1058
1059#endif /* EFSYS_OPT_BIST */
1060
1061#define EFX_FEATURE_IPV6 0x00000001
1062#define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1063#define EFX_FEATURE_LINK_EVENTS 0x00000004
1064#define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1065#define EFX_FEATURE_WOL 0x00000010
1066#define EFX_FEATURE_MCDI 0x00000020
1067#define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1068#define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1069#define EFX_FEATURE_TURBO 0x00000100
1070#define EFX_FEATURE_MCDI_DMA 0x00000200
1071#define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1072#define EFX_FEATURE_PIO_BUFFERS 0x00000800
1073#define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1074#define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1075
1076typedef struct efx_nic_cfg_s {
1077 uint32_t enc_board_type;
1078 uint32_t enc_phy_type;
1079#if EFSYS_OPT_NAMES
1080 char enc_phy_name[21];
1081#endif
1082 char enc_phy_revision[21];
1083 efx_mon_type_t enc_mon_type;
1084#if EFSYS_OPT_MON_STATS
1085 uint32_t enc_mon_stat_dma_buf_size;
1086 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1087#endif
1088 unsigned int enc_features;
1089 uint8_t enc_mac_addr[6];
1090 uint8_t enc_port; /* PHY port number */
1091 uint32_t enc_func_flags;
1092 uint32_t enc_intr_vec_base;
1093 uint32_t enc_intr_limit;
1094 uint32_t enc_evq_limit;
1095 uint32_t enc_txq_limit;
1096 uint32_t enc_rxq_limit;
1097 uint32_t enc_buftbl_limit;
1098 uint32_t enc_piobuf_limit;
1099 uint32_t enc_piobuf_size;
1100 uint32_t enc_piobuf_min_alloc_size;
1101 uint32_t enc_evq_timer_quantum_ns;
1102 uint32_t enc_evq_timer_max_us;
1103 uint32_t enc_clk_mult;
1104 uint32_t enc_rx_prefix_size;
1105 uint32_t enc_rx_buf_align_start;
1106 uint32_t enc_rx_buf_align_end;
1107#if EFSYS_OPT_LOOPBACK
1108 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1109#endif /* EFSYS_OPT_LOOPBACK */
1110#if EFSYS_OPT_PHY_FLAGS
1111 uint32_t enc_phy_flags_mask;
1112#endif /* EFSYS_OPT_PHY_FLAGS */
1113#if EFSYS_OPT_PHY_LED_CONTROL
1114 uint32_t enc_led_mask;
1115#endif /* EFSYS_OPT_PHY_LED_CONTROL */
1116#if EFSYS_OPT_PHY_STATS
1117 uint64_t enc_phy_stat_mask;
1118#endif /* EFSYS_OPT_PHY_STATS */
1119#if EFSYS_OPT_PHY_PROPS
1120 unsigned int enc_phy_nprops;
1121#endif /* EFSYS_OPT_PHY_PROPS */
1122#if EFSYS_OPT_SIENA
1123 uint8_t enc_mcdi_mdio_channel;
1124#if EFSYS_OPT_PHY_STATS
1125 uint32_t enc_mcdi_phy_stat_mask;
1126#endif /* EFSYS_OPT_PHY_STATS */
1127#endif /* EFSYS_OPT_SIENA */
1128#if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
1129#if EFSYS_OPT_MON_STATS
1130 uint32_t *enc_mcdi_sensor_maskp;
1131 uint32_t enc_mcdi_sensor_mask_size;
1132#endif /* EFSYS_OPT_MON_STATS */
1133#endif /* (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
1134#if EFSYS_OPT_BIST
1135 uint32_t enc_bist_mask;
1136#endif /* EFSYS_OPT_BIST */
1137#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1138 uint32_t enc_pf;
1139 uint32_t enc_vf;
1140 uint32_t enc_privilege_mask;
1141#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1142 boolean_t enc_bug26807_workaround;
1143 boolean_t enc_bug35388_workaround;
1144 boolean_t enc_bug41750_workaround;
1145 boolean_t enc_rx_batching_enabled;
1146 /* Maximum number of descriptors completed in an rx event. */
1147 uint32_t enc_rx_batch_max;
1148 /* Number of rx descriptors the hardware requires for a push. */
1149 uint32_t enc_rx_push_align;
1150 /*
1151 * Maximum number of bytes into the packet the TCP header can start for
1152 * the hardware to apply TSO packet edits.
1153 */
1154 uint32_t enc_tx_tso_tcp_header_offset_limit;
1155 boolean_t enc_fw_assisted_tso_enabled;
1156 boolean_t enc_fw_assisted_tso_v2_enabled;
1157 boolean_t enc_hw_tx_insert_vlan_enabled;
1158 /* Datapath firmware vadapter/vport/vswitch support */
1159 boolean_t enc_datapath_cap_evb;
1160 boolean_t enc_rx_disable_scatter_supported;
1161 boolean_t enc_allow_set_mac_with_installed_filters;
1162 /* External port identifier */
1163 uint8_t enc_external_port;
1164 uint32_t enc_mcdi_max_payload_length;
1165} efx_nic_cfg_t;
1166
1167#define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1168#define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1169
1170#define EFX_PCI_FUNCTION(_encp) \
1171 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1172
1173#define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1174
1175extern const efx_nic_cfg_t *
1176efx_nic_cfg_get(
1177 __in efx_nic_t *enp);
1178
1179/* Driver resource limits (minimum required/maximum usable). */
1180typedef struct efx_drv_limits_s
1181{
1182 uint32_t edl_min_evq_count;
1183 uint32_t edl_max_evq_count;
1184
1185 uint32_t edl_min_rxq_count;
1186 uint32_t edl_max_rxq_count;
1187
1188 uint32_t edl_min_txq_count;
1189 uint32_t edl_max_txq_count;
1190
1191 /* PIO blocks (sub-allocated from piobuf) */
1192 uint32_t edl_min_pio_alloc_size;
1193 uint32_t edl_max_pio_alloc_count;
1194} efx_drv_limits_t;
1195
1196extern __checkReturn efx_rc_t
1197efx_nic_set_drv_limits(
1198 __inout efx_nic_t *enp,
1199 __in efx_drv_limits_t *edlp);
1200
1201typedef enum efx_nic_region_e {
1202 EFX_REGION_VI, /* Memory BAR UC mapping */
1203 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1204} efx_nic_region_t;
1205
1206extern __checkReturn efx_rc_t
1207efx_nic_get_bar_region(
1208 __in efx_nic_t *enp,
1209 __in efx_nic_region_t region,
1210 __out uint32_t *offsetp,
1211 __out size_t *sizep);
1212
1213extern __checkReturn efx_rc_t
1214efx_nic_get_vi_pool(
1215 __in efx_nic_t *enp,
1216 __out uint32_t *evq_countp,
1217 __out uint32_t *rxq_countp,
1218 __out uint32_t *txq_countp);
1219
1220
1221#if EFSYS_OPT_VPD
1222
1223typedef enum efx_vpd_tag_e {
1224 EFX_VPD_ID = 0x02,
1225 EFX_VPD_END = 0x0f,
1226 EFX_VPD_RO = 0x10,
1227 EFX_VPD_RW = 0x11,
1228} efx_vpd_tag_t;
1229
1230typedef uint16_t efx_vpd_keyword_t;
1231
1232typedef struct efx_vpd_value_s {
1233 efx_vpd_tag_t evv_tag;
1234 efx_vpd_keyword_t evv_keyword;
1235 uint8_t evv_length;
1236 uint8_t evv_value[0x100];
1237} efx_vpd_value_t;
1238
1239
1240#define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1241
1242extern __checkReturn efx_rc_t
1243efx_vpd_init(
1244 __in efx_nic_t *enp);
1245
1246extern __checkReturn efx_rc_t
1247efx_vpd_size(
1248 __in efx_nic_t *enp,
1249 __out size_t *sizep);
1250
1251extern __checkReturn efx_rc_t
1252efx_vpd_read(
1253 __in efx_nic_t *enp,
1254 __out_bcount(size) caddr_t data,
1255 __in size_t size);
1256
1257extern __checkReturn efx_rc_t
1258efx_vpd_verify(
1259 __in efx_nic_t *enp,
1260 __in_bcount(size) caddr_t data,
1261 __in size_t size);
1262
1263extern __checkReturn efx_rc_t
1264efx_vpd_reinit(
1265 __in efx_nic_t *enp,
1266 __in_bcount(size) caddr_t data,
1267 __in size_t size);
1268
1269extern __checkReturn efx_rc_t
1270efx_vpd_get(
1271 __in efx_nic_t *enp,
1272 __in_bcount(size) caddr_t data,
1273 __in size_t size,
1274 __inout efx_vpd_value_t *evvp);
1275
1276extern __checkReturn efx_rc_t
1277efx_vpd_set(
1278 __in efx_nic_t *enp,
1279 __inout_bcount(size) caddr_t data,
1280 __in size_t size,
1281 __in efx_vpd_value_t *evvp);
1282
1283extern __checkReturn efx_rc_t
1284efx_vpd_next(
1285 __in efx_nic_t *enp,
1286 __inout_bcount(size) caddr_t data,
1287 __in size_t size,
1288 __out efx_vpd_value_t *evvp,
1289 __inout unsigned int *contp);
1290
1291extern __checkReturn efx_rc_t
1292efx_vpd_write(
1293 __in efx_nic_t *enp,
1294 __in_bcount(size) caddr_t data,
1295 __in size_t size);
1296
1297extern void
1298efx_vpd_fini(
1299 __in efx_nic_t *enp);
1300
1301#endif /* EFSYS_OPT_VPD */
1302
1303/* NVRAM */
1304
1305#if EFSYS_OPT_NVRAM
1306
1307typedef enum efx_nvram_type_e {
1308 EFX_NVRAM_INVALID = 0,
1309 EFX_NVRAM_BOOTROM,
1310 EFX_NVRAM_BOOTROM_CFG,
1311 EFX_NVRAM_MC_FIRMWARE,
1312 EFX_NVRAM_MC_GOLDEN,
1313 EFX_NVRAM_PHY,
1314 EFX_NVRAM_NULLPHY,
1315 EFX_NVRAM_FPGA,
1316 EFX_NVRAM_FCFW,
1317 EFX_NVRAM_CPLD,
1318 EFX_NVRAM_FPGA_BACKUP,
1319 EFX_NVRAM_DYNAMIC_CFG,
1320 EFX_NVRAM_NTYPES,
1321} efx_nvram_type_t;
1322
1323extern __checkReturn efx_rc_t
1324efx_nvram_init(
1325 __in efx_nic_t *enp);
1326
1327#if EFSYS_OPT_DIAG
1328
1329extern __checkReturn efx_rc_t
1330efx_nvram_test(
1331 __in efx_nic_t *enp);
1332
1333#endif /* EFSYS_OPT_DIAG */
1334
1335extern __checkReturn efx_rc_t
1336efx_nvram_size(
1337 __in efx_nic_t *enp,
1338 __in efx_nvram_type_t type,
1339 __out size_t *sizep);
1340
1341extern __checkReturn efx_rc_t
1342efx_nvram_rw_start(
1343 __in efx_nic_t *enp,
1344 __in efx_nvram_type_t type,
1345 __out_opt size_t *pref_chunkp);
1346
1347extern void
1348efx_nvram_rw_finish(
1349 __in efx_nic_t *enp,
1350 __in efx_nvram_type_t type);
1351
1352extern __checkReturn efx_rc_t
1353efx_nvram_get_version(
1354 __in efx_nic_t *enp,
1355 __in efx_nvram_type_t type,
1356 __out uint32_t *subtypep,
1357 __out_ecount(4) uint16_t version[4]);
1358
1359extern __checkReturn efx_rc_t
1360efx_nvram_read_chunk(
1361 __in efx_nic_t *enp,
1362 __in efx_nvram_type_t type,
1363 __in unsigned int offset,
1364 __out_bcount(size) caddr_t data,
1365 __in size_t size);
1366
1367extern __checkReturn efx_rc_t
1368efx_nvram_set_version(
1369 __in efx_nic_t *enp,
1370 __in efx_nvram_type_t type,
1371 __in_ecount(4) uint16_t version[4]);
1372
1373/* Validate contents of TLV formatted partition */
1374extern __checkReturn efx_rc_t
1375efx_nvram_tlv_validate(
1376 __in efx_nic_t *enp,
1377 __in uint32_t partn,
1378 __in_bcount(partn_size) caddr_t partn_data,
1379 __in size_t partn_size);
1380
1381extern __checkReturn efx_rc_t
1382efx_nvram_erase(
1383 __in efx_nic_t *enp,
1384 __in efx_nvram_type_t type);
1385
1386extern __checkReturn efx_rc_t
1387efx_nvram_write_chunk(
1388 __in efx_nic_t *enp,
1389 __in efx_nvram_type_t type,
1390 __in unsigned int offset,
1391 __in_bcount(size) caddr_t data,
1392 __in size_t size);
1393
1394extern void
1395efx_nvram_fini(
1396 __in efx_nic_t *enp);
1397
1398#endif /* EFSYS_OPT_NVRAM */
1399
1400#if EFSYS_OPT_BOOTCFG
1401
1402extern efx_rc_t
1403efx_bootcfg_read(
1404 __in efx_nic_t *enp,
1405 __out_bcount(size) caddr_t data,
1406 __in size_t size);
1407
1408extern efx_rc_t
1409efx_bootcfg_write(
1410 __in efx_nic_t *enp,
1411 __in_bcount(size) caddr_t data,
1412 __in size_t size);
1413
1414#endif /* EFSYS_OPT_BOOTCFG */
1415
1416#if EFSYS_OPT_WOL
1417
1418typedef enum efx_wol_type_e {
1419 EFX_WOL_TYPE_INVALID,
1420 EFX_WOL_TYPE_MAGIC,
1421 EFX_WOL_TYPE_BITMAP,
1422 EFX_WOL_TYPE_LINK,
1423 EFX_WOL_NTYPES,
1424} efx_wol_type_t;
1425
1426typedef enum efx_lightsout_offload_type_e {
1427 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1428 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1429 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1430} efx_lightsout_offload_type_t;
1431
1432#define EFX_WOL_BITMAP_MASK_SIZE (48)
1433#define EFX_WOL_BITMAP_VALUE_SIZE (128)
1434
1435typedef union efx_wol_param_u {
1436 struct {
1437 uint8_t mac_addr[6];
1438 } ewp_magic;
1439 struct {
1440 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */
1441 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1442 uint8_t value_len;
1443 } ewp_bitmap;
1444} efx_wol_param_t;
1445
1446typedef union efx_lightsout_offload_param_u {
1447 struct {
1448 uint8_t mac_addr[6];
1449 uint32_t ip;
1450 } elop_arp;
1451 struct {
1452 uint8_t mac_addr[6];
1453 uint32_t solicited_node[4];
1454 uint32_t ip[4];
1455 } elop_ns;
1456} efx_lightsout_offload_param_t;
1457
1458extern __checkReturn efx_rc_t
1459efx_wol_init(
1460 __in efx_nic_t *enp);
1461
1462extern __checkReturn efx_rc_t
1463efx_wol_filter_clear(
1464 __in efx_nic_t *enp);
1465
1466extern __checkReturn efx_rc_t
1467efx_wol_filter_add(
1468 __in efx_nic_t *enp,
1469 __in efx_wol_type_t type,
1470 __in efx_wol_param_t *paramp,
1471 __out uint32_t *filter_idp);
1472
1473extern __checkReturn efx_rc_t
1474efx_wol_filter_remove(
1475 __in efx_nic_t *enp,
1476 __in uint32_t filter_id);
1477
1478extern __checkReturn efx_rc_t
1479efx_lightsout_offload_add(
1480 __in efx_nic_t *enp,
1481 __in efx_lightsout_offload_type_t type,
1482 __in efx_lightsout_offload_param_t *paramp,
1483 __out uint32_t *filter_idp);
1484
1485extern __checkReturn efx_rc_t
1486efx_lightsout_offload_remove(
1487 __in efx_nic_t *enp,
1488 __in efx_lightsout_offload_type_t type,
1489 __in uint32_t filter_id);
1490
1491extern void
1492efx_wol_fini(
1493 __in efx_nic_t *enp);
1494
1495#endif /* EFSYS_OPT_WOL */
1496
1497#if EFSYS_OPT_DIAG
1498
1499typedef enum efx_pattern_type_t {
1500 EFX_PATTERN_BYTE_INCREMENT = 0,
1501 EFX_PATTERN_ALL_THE_SAME,
1502 EFX_PATTERN_BIT_ALTERNATE,
1503 EFX_PATTERN_BYTE_ALTERNATE,
1504 EFX_PATTERN_BYTE_CHANGING,
1505 EFX_PATTERN_BIT_SWEEP,
1506 EFX_PATTERN_NTYPES
1507} efx_pattern_type_t;
1508
1509typedef void
1510(*efx_sram_pattern_fn_t)(
1511 __in size_t row,
1512 __in boolean_t negate,
1513 __out efx_qword_t *eqp);
1514
1515extern __checkReturn efx_rc_t
1516efx_sram_test(
1517 __in efx_nic_t *enp,
1518 __in efx_pattern_type_t type);
1519
1520#endif /* EFSYS_OPT_DIAG */
1521
1522extern __checkReturn efx_rc_t
1523efx_sram_buf_tbl_set(
1524 __in efx_nic_t *enp,
1525 __in uint32_t id,
1526 __in efsys_mem_t *esmp,
1527 __in size_t n);
1528
1529extern void
1530efx_sram_buf_tbl_clear(
1531 __in efx_nic_t *enp,
1532 __in uint32_t id,
1533 __in size_t n);
1534
1535#define EFX_BUF_TBL_SIZE 0x20000
1536
1537#define EFX_BUF_SIZE 4096
1538
1539/* EV */
1540
1541typedef struct efx_evq_s efx_evq_t;
1542
1543#if EFSYS_OPT_QSTATS
1544
1545/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1546typedef enum efx_ev_qstat_e {
1547 EV_ALL,
1548 EV_RX,
1549 EV_RX_OK,
1550 EV_RX_FRM_TRUNC,
1551 EV_RX_TOBE_DISC,
1552 EV_RX_PAUSE_FRM_ERR,
1553 EV_RX_BUF_OWNER_ID_ERR,
1554 EV_RX_IPV4_HDR_CHKSUM_ERR,
1555 EV_RX_TCP_UDP_CHKSUM_ERR,
1556 EV_RX_ETH_CRC_ERR,
1557 EV_RX_IP_FRAG_ERR,
1558 EV_RX_MCAST_PKT,
1559 EV_RX_MCAST_HASH_MATCH,
1560 EV_RX_TCP_IPV4,
1561 EV_RX_TCP_IPV6,
1562 EV_RX_UDP_IPV4,
1563 EV_RX_UDP_IPV6,
1564 EV_RX_OTHER_IPV4,
1565 EV_RX_OTHER_IPV6,
1566 EV_RX_NON_IP,
1567 EV_RX_BATCH,
1568 EV_TX,
1569 EV_TX_WQ_FF_FULL,
1570 EV_TX_PKT_ERR,
1571 EV_TX_PKT_TOO_BIG,
1572 EV_TX_UNEXPECTED,
1573 EV_GLOBAL,
1574 EV_GLOBAL_MNT,
1575 EV_DRIVER,
1576 EV_DRIVER_SRM_UPD_DONE,
1577 EV_DRIVER_TX_DESCQ_FLS_DONE,
1578 EV_DRIVER_RX_DESCQ_FLS_DONE,
1579 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1580 EV_DRIVER_RX_DSC_ERROR,
1581 EV_DRIVER_TX_DSC_ERROR,
1582 EV_DRV_GEN,
1583 EV_MCDI_RESPONSE,
1584 EV_NQSTATS
1585} efx_ev_qstat_t;
1586
1587/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1588
1589#endif /* EFSYS_OPT_QSTATS */
1590
1591extern __checkReturn efx_rc_t
1592efx_ev_init(
1593 __in efx_nic_t *enp);
1594
1595extern void
1596efx_ev_fini(
1597 __in efx_nic_t *enp);
1598
1599#define EFX_EVQ_MAXNEVS 32768
1600#define EFX_EVQ_MINNEVS 512
1601
1602#define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1603#define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1604
1605extern __checkReturn efx_rc_t
1606efx_ev_qcreate(
1607 __in efx_nic_t *enp,
1608 __in unsigned int index,
1609 __in efsys_mem_t *esmp,
1610 __in size_t n,
1611 __in uint32_t id,
1612 __deref_out efx_evq_t **eepp);
1613
1614extern void
1615efx_ev_qpost(
1616 __in efx_evq_t *eep,
1617 __in uint16_t data);
1618
1619typedef __checkReturn boolean_t
1620(*efx_initialized_ev_t)(
1621 __in_opt void *arg);
1622
1623#define EFX_PKT_UNICAST 0x0004
1624#define EFX_PKT_START 0x0008
1625
1626#define EFX_PKT_VLAN_TAGGED 0x0010
1627#define EFX_CKSUM_TCPUDP 0x0020
1628#define EFX_CKSUM_IPV4 0x0040
1629#define EFX_PKT_CONT 0x0080
1630
1631#define EFX_CHECK_VLAN 0x0100
1632#define EFX_PKT_TCP 0x0200
1633#define EFX_PKT_UDP 0x0400
1634#define EFX_PKT_IPV4 0x0800
1635
1636#define EFX_PKT_IPV6 0x1000
1637#define EFX_PKT_PREFIX_LEN 0x2000
1638#define EFX_ADDR_MISMATCH 0x4000
1639#define EFX_DISCARD 0x8000
1640
1641#define EFX_EV_RX_NLABELS 32
1642#define EFX_EV_TX_NLABELS 32
1643
1644typedef __checkReturn boolean_t
1645(*efx_rx_ev_t)(
1646 __in_opt void *arg,
1647 __in uint32_t label,
1648 __in uint32_t id,
1649 __in uint32_t size,
1650 __in uint16_t flags);
1651
1652typedef __checkReturn boolean_t
1653(*efx_tx_ev_t)(
1654 __in_opt void *arg,
1655 __in uint32_t label,
1656 __in uint32_t id);
1657
1658#define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1659#define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1660#define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1661#define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1662#define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1663#define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1664#define EFX_EXCEPTION_RX_ERROR 0x00000007
1665#define EFX_EXCEPTION_TX_ERROR 0x00000008
1666#define EFX_EXCEPTION_EV_ERROR 0x00000009
1667
1668typedef __checkReturn boolean_t
1669(*efx_exception_ev_t)(
1670 __in_opt void *arg,
1671 __in uint32_t label,
1672 __in uint32_t data);
1673
1674typedef __checkReturn boolean_t
1675(*efx_rxq_flush_done_ev_t)(
1676 __in_opt void *arg,
1677 __in uint32_t rxq_index);
1678
1679typedef __checkReturn boolean_t
1680(*efx_rxq_flush_failed_ev_t)(
1681 __in_opt void *arg,
1682 __in uint32_t rxq_index);
1683
1684typedef __checkReturn boolean_t
1685(*efx_txq_flush_done_ev_t)(
1686 __in_opt void *arg,
1687 __in uint32_t txq_index);
1688
1689typedef __checkReturn boolean_t
1690(*efx_software_ev_t)(
1691 __in_opt void *arg,
1692 __in uint16_t magic);
1693
1694typedef __checkReturn boolean_t
1695(*efx_sram_ev_t)(
1696 __in_opt void *arg,
1697 __in uint32_t code);
1698
1699#define EFX_SRAM_CLEAR 0
1700#define EFX_SRAM_UPDATE 1
1701#define EFX_SRAM_ILLEGAL_CLEAR 2
1702
1703typedef __checkReturn boolean_t
1704(*efx_wake_up_ev_t)(
1705 __in_opt void *arg,
1706 __in uint32_t label);
1707
1708typedef __checkReturn boolean_t
1709(*efx_timer_ev_t)(
1710 __in_opt void *arg,
1711 __in uint32_t label);
1712
1713typedef __checkReturn boolean_t
1714(*efx_link_change_ev_t)(
1715 __in_opt void *arg,
1716 __in efx_link_mode_t link_mode);
1717
1718#if EFSYS_OPT_MON_STATS
1719
1720typedef __checkReturn boolean_t
1721(*efx_monitor_ev_t)(
1722 __in_opt void *arg,
1723 __in efx_mon_stat_t id,
1724 __in efx_mon_stat_value_t value);
1725
1726#endif /* EFSYS_OPT_MON_STATS */
1727
1728#if EFSYS_OPT_MAC_STATS
1729
1730typedef __checkReturn boolean_t
1731(*efx_mac_stats_ev_t)(
1732 __in_opt void *arg,
1733 __in uint32_t generation
1734 );
1735
1736#endif /* EFSYS_OPT_MAC_STATS */
1737
1738typedef struct efx_ev_callbacks_s {
1739 efx_initialized_ev_t eec_initialized;
1740 efx_rx_ev_t eec_rx;
1741 efx_tx_ev_t eec_tx;
1742 efx_exception_ev_t eec_exception;
1743 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1744 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1745 efx_txq_flush_done_ev_t eec_txq_flush_done;
1746 efx_software_ev_t eec_software;
1747 efx_sram_ev_t eec_sram;
1748 efx_wake_up_ev_t eec_wake_up;
1749 efx_timer_ev_t eec_timer;
1750 efx_link_change_ev_t eec_link_change;
1751#if EFSYS_OPT_MON_STATS
1752 efx_monitor_ev_t eec_monitor;
1753#endif /* EFSYS_OPT_MON_STATS */
1754#if EFSYS_OPT_MAC_STATS
1755 efx_mac_stats_ev_t eec_mac_stats;
1756#endif /* EFSYS_OPT_MAC_STATS */
1757} efx_ev_callbacks_t;
1758
1759extern __checkReturn boolean_t
1760efx_ev_qpending(
1761 __in efx_evq_t *eep,
1762 __in unsigned int count);
1763
1764#if EFSYS_OPT_EV_PREFETCH
1765
1766extern void
1767efx_ev_qprefetch(
1768 __in efx_evq_t *eep,
1769 __in unsigned int count);
1770
1771#endif /* EFSYS_OPT_EV_PREFETCH */
1772
1773extern void
1774efx_ev_qpoll(
1775 __in efx_evq_t *eep,
1776 __inout unsigned int *countp,
1777 __in const efx_ev_callbacks_t *eecp,
1778 __in_opt void *arg);
1779
1780extern __checkReturn efx_rc_t
1781efx_ev_qmoderate(
1782 __in efx_evq_t *eep,
1783 __in unsigned int us);
1784
1785extern __checkReturn efx_rc_t
1786efx_ev_qprime(
1787 __in efx_evq_t *eep,
1788 __in unsigned int count);
1789
1790#if EFSYS_OPT_QSTATS
1791
1792#if EFSYS_OPT_NAMES
1793
1794extern const char *
1795efx_ev_qstat_name(
1796 __in efx_nic_t *enp,
1797 __in unsigned int id);
1798
1799#endif /* EFSYS_OPT_NAMES */
1800
1801extern void
1802efx_ev_qstats_update(
1803 __in efx_evq_t *eep,
1804 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1805
1806#endif /* EFSYS_OPT_QSTATS */
1807
1808extern void
1809efx_ev_qdestroy(
1810 __in efx_evq_t *eep);
1811
1812/* RX */
1813
1814extern __checkReturn efx_rc_t
1815efx_rx_init(
1816 __inout efx_nic_t *enp);
1817
1818extern void
1819efx_rx_fini(
1820 __in efx_nic_t *enp);
1821
1822#if EFSYS_OPT_RX_SCATTER
1823 __checkReturn efx_rc_t
1824efx_rx_scatter_enable(
1825 __in efx_nic_t *enp,
1826 __in unsigned int buf_size);
1827#endif /* EFSYS_OPT_RX_SCATTER */
1828
1829#if EFSYS_OPT_RX_SCALE
1830
1831typedef enum efx_rx_hash_alg_e {
1832 EFX_RX_HASHALG_LFSR = 0,
1833 EFX_RX_HASHALG_TOEPLITZ
1834} efx_rx_hash_alg_t;
1835
1836typedef enum efx_rx_hash_type_e {
1837 EFX_RX_HASH_IPV4 = 0,
1838 EFX_RX_HASH_TCPIPV4,
1839 EFX_RX_HASH_IPV6,
1840 EFX_RX_HASH_TCPIPV6,
1841} efx_rx_hash_type_t;
1842
1843typedef enum efx_rx_hash_support_e {
1844 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1845 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1846} efx_rx_hash_support_t;
1847
1848#define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1849#define EFX_MAXRSS 64 /* RX indirection entry range */
1850#define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1851
1852typedef enum efx_rx_scale_support_e {
1853 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */
1854 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1855 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1856} efx_rx_scale_support_t;
1857
1858extern __checkReturn efx_rc_t
1859efx_rx_hash_support_get(
1860 __in efx_nic_t *enp,
1861 __out efx_rx_hash_support_t *supportp);
1862
1863
1864extern __checkReturn efx_rc_t
1865efx_rx_scale_support_get(
1866 __in efx_nic_t *enp,
1867 __out efx_rx_scale_support_t *supportp);
1868
1869extern __checkReturn efx_rc_t
1870efx_rx_scale_mode_set(
1871 __in efx_nic_t *enp,
1872 __in efx_rx_hash_alg_t alg,
1873 __in efx_rx_hash_type_t type,
1874 __in boolean_t insert);
1875
1876extern __checkReturn efx_rc_t
1877efx_rx_scale_tbl_set(
1878 __in efx_nic_t *enp,
1879 __in_ecount(n) unsigned int *table,
1880 __in size_t n);
1881
1882extern __checkReturn efx_rc_t
1883efx_rx_scale_key_set(
1884 __in efx_nic_t *enp,
1885 __in_ecount(n) uint8_t *key,
1886 __in size_t n);
1887
1888extern __checkReturn uint32_t
1889efx_psuedo_hdr_hash_get(
1890 __in efx_nic_t *enp,
1891 __in efx_rx_hash_alg_t func,
1892 __in uint8_t *buffer);
1893
1894#endif /* EFSYS_OPT_RX_SCALE */
1895
1896extern __checkReturn efx_rc_t
1897efx_psuedo_hdr_pkt_length_get(
1898 __in efx_nic_t *enp,
1899 __in uint8_t *buffer,
1900 __out uint16_t *pkt_lengthp);
1901
1902#define EFX_RXQ_MAXNDESCS 4096
1903#define EFX_RXQ_MINNDESCS 512
1904
1905#define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1906#define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1907#define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1908#define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1909
1910typedef enum efx_rxq_type_e {
1911 EFX_RXQ_TYPE_DEFAULT,
1912 EFX_RXQ_TYPE_SCATTER,
1913 EFX_RXQ_NTYPES
1914} efx_rxq_type_t;
1915
1916extern __checkReturn efx_rc_t
1917efx_rx_qcreate(
1918 __in efx_nic_t *enp,
1919 __in unsigned int index,
1920 __in unsigned int label,
1921 __in efx_rxq_type_t type,
1922 __in efsys_mem_t *esmp,
1923 __in size_t n,
1924 __in uint32_t id,
1925 __in efx_evq_t *eep,
1926 __deref_out efx_rxq_t **erpp);
1927
1928typedef struct efx_buffer_s {
1929 efsys_dma_addr_t eb_addr;
1930 size_t eb_size;
1931 boolean_t eb_eop;
1932} efx_buffer_t;
1933
1934typedef struct efx_desc_s {
1935 efx_qword_t ed_eq;
1936} efx_desc_t;
1937
1938extern void
1939efx_rx_qpost(
1940 __in efx_rxq_t *erp,
1941 __in_ecount(n) efsys_dma_addr_t *addrp,
1942 __in size_t size,
1943 __in unsigned int n,
1944 __in unsigned int completed,
1945 __in unsigned int added);
1946
1947extern void
1948efx_rx_qpush(
1949 __in efx_rxq_t *erp,
1950 __in unsigned int added,
1951 __inout unsigned int *pushedp);
1952
1953extern __checkReturn efx_rc_t
1954efx_rx_qflush(
1955 __in efx_rxq_t *erp);
1956
1957extern void
1958efx_rx_qenable(
1959 __in efx_rxq_t *erp);
1960
1961extern void
1962efx_rx_qdestroy(
1963 __in efx_rxq_t *erp);
1964
1965/* TX */
1966
1967typedef struct efx_txq_s efx_txq_t;
1968
1969#if EFSYS_OPT_QSTATS
1970
1971/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1972typedef enum efx_tx_qstat_e {
1973 TX_POST,
1974 TX_POST_PIO,
1975 TX_NQSTATS
1976} efx_tx_qstat_t;
1977
1978/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1979
1980#endif /* EFSYS_OPT_QSTATS */
1981
1982extern __checkReturn efx_rc_t
1983efx_tx_init(
1984 __in efx_nic_t *enp);
1985
1986extern void
1987efx_tx_fini(
1988 __in efx_nic_t *enp);
1989
1990#define EFX_BUG35388_WORKAROUND(_encp) \
1991 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
1992
1993#define EFX_TXQ_MAXNDESCS(_encp) \
1994 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
1995
1996#define EFX_TXQ_MINNDESCS 512
1997
1998#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1999#define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2000#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2001#define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2002
2003#define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2004
2005#define EFX_TXQ_CKSUM_IPV4 0x0001
2006#define EFX_TXQ_CKSUM_TCPUDP 0x0002
2007#define EFX_TXQ_FATSOV2 0x0004
2008
2009extern __checkReturn efx_rc_t
2010efx_tx_qcreate(
2011 __in efx_nic_t *enp,
2012 __in unsigned int index,
2013 __in unsigned int label,
2014 __in efsys_mem_t *esmp,
2015 __in size_t n,
2016 __in uint32_t id,
2017 __in uint16_t flags,
2018 __in efx_evq_t *eep,
2019 __deref_out efx_txq_t **etpp,
2020 __out unsigned int *addedp);
2021
2022extern __checkReturn efx_rc_t
2023efx_tx_qpost(
2024 __in efx_txq_t *etp,
2025 __in_ecount(n) efx_buffer_t *eb,
2026 __in unsigned int n,
2027 __in unsigned int completed,
2028 __inout unsigned int *addedp);
2029
2030extern __checkReturn efx_rc_t
2031efx_tx_qpace(
2032 __in efx_txq_t *etp,
2033 __in unsigned int ns);
2034
2035extern void
2036efx_tx_qpush(
2037 __in efx_txq_t *etp,
2038 __in unsigned int added,
2039 __in unsigned int pushed);
2040
2041extern __checkReturn efx_rc_t
2042efx_tx_qflush(
2043 __in efx_txq_t *etp);
2044
2045extern void
2046efx_tx_qenable(
2047 __in efx_txq_t *etp);
2048
2049extern __checkReturn efx_rc_t
2050efx_tx_qpio_enable(
2051 __in efx_txq_t *etp);
2052
2053extern void
2054efx_tx_qpio_disable(
2055 __in efx_txq_t *etp);
2056
2057extern __checkReturn efx_rc_t
2058efx_tx_qpio_write(
2059 __in efx_txq_t *etp,
2060 __in_ecount(buf_length) uint8_t *buffer,
2061 __in size_t buf_length,
2062 __in size_t pio_buf_offset);
2063
2064extern __checkReturn efx_rc_t
2065efx_tx_qpio_post(
2066 __in efx_txq_t *etp,
2067 __in size_t pkt_length,
2068 __in unsigned int completed,
2069 __inout unsigned int *addedp);
2070
2071extern __checkReturn efx_rc_t
2072efx_tx_qdesc_post(
2073 __in efx_txq_t *etp,
2074 __in_ecount(n) efx_desc_t *ed,
2075 __in unsigned int n,
2076 __in unsigned int completed,
2077 __inout unsigned int *addedp);
2078
2079extern void
2080efx_tx_qdesc_dma_create(
2081 __in efx_txq_t *etp,
2082 __in efsys_dma_addr_t addr,
2083 __in size_t size,
2084 __in boolean_t eop,
2085 __out efx_desc_t *edp);
2086
2087extern void
2088efx_tx_qdesc_tso_create(
2089 __in efx_txq_t *etp,
2090 __in uint16_t ipv4_id,
2091 __in uint32_t tcp_seq,
2092 __in uint8_t tcp_flags,
2093 __out efx_desc_t *edp);
2094
2095/* Number of FATSOv2 option descriptors */
2096#define EFX_TX_FATSOV2_OPT_NDESCS 2
2097
2098/* Maximum number of DMA segments per TSO packet (not superframe) */
2099#define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2100
2101extern void
2102efx_tx_qdesc_tso2_create(
2103 __in efx_txq_t *etp,
2104 __in uint16_t ipv4_id,
2105 __in uint32_t tcp_seq,
2106 __in uint16_t tcp_mss,
2107 __out_ecount(count) efx_desc_t *edp,
2108 __in int count);
2109
2110extern void
2111efx_tx_qdesc_vlantci_create(
2112 __in efx_txq_t *etp,
2113 __in uint16_t tci,
2114 __out efx_desc_t *edp);
2115
2116#if EFSYS_OPT_QSTATS
2117
2118#if EFSYS_OPT_NAMES
2119
2120extern const char *
2121efx_tx_qstat_name(
2122 __in efx_nic_t *etp,
2123 __in unsigned int id);
2124
2125#endif /* EFSYS_OPT_NAMES */
2126
2127extern void
2128efx_tx_qstats_update(
2129 __in efx_txq_t *etp,
2130 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2131
2132#endif /* EFSYS_OPT_QSTATS */
2133
2134extern void
2135efx_tx_qdestroy(
2136 __in efx_txq_t *etp);
2137
2138
2139/* FILTER */
2140
2141#if EFSYS_OPT_FILTER
2142
2143#define EFX_ETHER_TYPE_IPV4 0x0800
2144#define EFX_ETHER_TYPE_IPV6 0x86DD
2145
2146#define EFX_IPPROTO_TCP 6
2147#define EFX_IPPROTO_UDP 17
2148
2149typedef enum efx_filter_flag_e {
2150 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across
2151 * multiple queues */
2152 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */
2153 EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04, /* Override an automatic filter
2154 * (priority EFX_FILTER_PRI_AUTO).
2155 * May only be set by the filter
2156 * implementation for each type.
2157 * A removal request will
2158 * restore the automatic filter
2159 * in its place. */
2160 EFX_FILTER_FLAG_RX = 0x08, /* Filter is for RX */
2161 EFX_FILTER_FLAG_TX = 0x10, /* Filter is for TX */
2162} efx_filter_flag_t;
2163
2164typedef enum efx_filter_match_flags_e {
2165 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
2166 * address */
2167 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
2168 * address */
2169 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
2170 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
2171 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
2172 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
2173 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
2174 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
2175 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
2176 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
2177 * protocol */
2178 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
2179 * I/G bit. Used for RX default
2180 * unicast and multicast/
2181 * broadcast filters. */
2182} efx_filter_match_flags_t;
2183
2184typedef enum efx_filter_priority_s {
2185 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2186 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2187 * address list or hardware
2188 * requirements. This may only be used
2189 * by the filter implementation for
2190 * each NIC type. */
2191 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2192 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2193 * client (e.g. SR-IOV, HyperV VMQ etc.)
2194 */
2195} efx_filter_priority_t;
2196
2197/*
2198 * FIXME: All these fields are assumed to be in little-endian byte order.
2199 * It may be better for some to be big-endian. See bug42804.
2200 */
2201
2202typedef struct efx_filter_spec_s {
2203 uint32_t efs_match_flags:12;
2204 uint32_t efs_priority:2;
2205 uint32_t efs_flags:6;
2206 uint32_t efs_dmaq_id:12;
2207 uint32_t efs_rss_context;
2208 uint16_t efs_outer_vid;
2209 uint16_t efs_inner_vid;
2210 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2211 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2212 uint16_t efs_ether_type;
2213 uint8_t efs_ip_proto;
2214 uint16_t efs_loc_port;
2215 uint16_t efs_rem_port;
2216 efx_oword_t efs_rem_host;
2217 efx_oword_t efs_loc_host;
2218} efx_filter_spec_t;
2219
2220
2221/* Default values for use in filter specifications */
2222#define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
2223#define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2224#define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2225
2226extern __checkReturn efx_rc_t
2227efx_filter_init(
2228 __in efx_nic_t *enp);
2229
2230extern void
2231efx_filter_fini(
2232 __in efx_nic_t *enp);
2233
2234extern __checkReturn efx_rc_t
2235efx_filter_insert(
2236 __in efx_nic_t *enp,
2237 __inout efx_filter_spec_t *spec);
2238
2239extern __checkReturn efx_rc_t
2240efx_filter_remove(
2241 __in efx_nic_t *enp,
2242 __inout efx_filter_spec_t *spec);
2243
2244extern __checkReturn efx_rc_t
2245efx_filter_restore(
2246 __in efx_nic_t *enp);
2247
2248extern __checkReturn efx_rc_t
2249efx_filter_supported_filters(
2250 __in efx_nic_t *enp,
2251 __out uint32_t *list,
2252 __out size_t *length);
2253
2254extern void
2255efx_filter_spec_init_rx(
2256 __out efx_filter_spec_t *spec,
2257 __in efx_filter_priority_t priority,
2258 __in efx_filter_flag_t flags,
2259 __in efx_rxq_t *erp);
2260
2261extern void
2262efx_filter_spec_init_tx(
2263 __out efx_filter_spec_t *spec,
2264 __in efx_txq_t *etp);
2265
2266extern __checkReturn efx_rc_t
2267efx_filter_spec_set_ipv4_local(
2268 __inout efx_filter_spec_t *spec,
2269 __in uint8_t proto,
2270 __in uint32_t host,
2271 __in uint16_t port);
2272
2273extern __checkReturn efx_rc_t
2274efx_filter_spec_set_ipv4_full(
2275 __inout efx_filter_spec_t *spec,
2276 __in uint8_t proto,
2277 __in uint32_t lhost,
2278 __in uint16_t lport,
2279 __in uint32_t rhost,
2280 __in uint16_t rport);
2281
2282extern __checkReturn efx_rc_t
2283efx_filter_spec_set_eth_local(
2284 __inout efx_filter_spec_t *spec,
2285 __in uint16_t vid,
2286 __in const uint8_t *addr);
2287
2288extern __checkReturn efx_rc_t
2289efx_filter_spec_set_uc_def(
2290 __inout efx_filter_spec_t *spec);
2291
2292extern __checkReturn efx_rc_t
2293efx_filter_spec_set_mc_def(
2294 __inout efx_filter_spec_t *spec);
2295
2296#endif /* EFSYS_OPT_FILTER */
2297
2298/* HASH */
2299
2300extern __checkReturn uint32_t
2301efx_hash_dwords(
2302 __in_ecount(count) uint32_t const *input,
2303 __in size_t count,
2304 __in uint32_t init);
2305
2306extern __checkReturn uint32_t
2307efx_hash_bytes(
2308 __in_ecount(length) uint8_t const *input,
2309 __in size_t length,
2310 __in uint32_t init);
2311
2312
2313#ifdef __cplusplus
2314}
2315#endif
2316
2317#endif /* _SYS_EFX_H */