1/*-
2 * Copyright (c) 2012-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/sfxge/common/hunt_tx.c 293814 2016-01-13 07:25:51Z arybchik $");
33
34#include "efx.h"
35#include "efx_impl.h"
36
37
38#if EFSYS_OPT_HUNTINGTON
39
40#if EFSYS_OPT_QSTATS
41#define EFX_TX_QSTAT_INCR(_etp, _stat) \
42 do { \
43 (_etp)->et_stat[_stat]++; \
44 _NOTE(CONSTANTCONDITION) \
45 } while (B_FALSE)
46#else
47#define EFX_TX_QSTAT_INCR(_etp, _stat)
48#endif
49
50static __checkReturn efx_rc_t
51efx_mcdi_init_txq(
52 __in efx_nic_t *enp,
53 __in uint32_t size,
54 __in uint32_t target_evq,
55 __in uint32_t label,
56 __in uint32_t instance,
57 __in uint16_t flags,
58 __in efsys_mem_t *esmp)
59{
60 efx_mcdi_req_t req;
61 uint8_t payload[MAX(MC_CMD_INIT_TXQ_IN_LEN(EFX_TXQ_MAX_BUFS),
62 MC_CMD_INIT_TXQ_OUT_LEN)];
63 efx_qword_t *dma_addr;
64 uint64_t addr;
65 int npages;
66 int i;
67 efx_rc_t rc;
68
69 EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >=
70 EFX_TXQ_NBUFS(EFX_TXQ_MAXNDESCS(&enp->en_nic_cfg)));
71
72 npages = EFX_TXQ_NBUFS(size);
73 if (npages > MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM) {
74 rc = EINVAL;
75 goto fail1;
76 }
77
78 (void) memset(payload, 0, sizeof (payload));
79 req.emr_cmd = MC_CMD_INIT_TXQ;
80 req.emr_in_buf = payload;
81 req.emr_in_length = MC_CMD_INIT_TXQ_IN_LEN(npages);
82 req.emr_out_buf = payload;
83 req.emr_out_length = MC_CMD_INIT_TXQ_OUT_LEN;
84
85 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, size);
86 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_TARGET_EVQ, target_evq);
87 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label);
88 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance);
89
90 MCDI_IN_POPULATE_DWORD_6(req, INIT_TXQ_IN_FLAGS,
91 INIT_TXQ_IN_FLAG_BUFF_MODE, 0,
92 INIT_TXQ_IN_FLAG_IP_CSUM_DIS,
93 (flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1,
94 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS,
95 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1,
96 INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0,
97 INIT_TXQ_IN_CRC_MODE, 0,
98 INIT_TXQ_IN_FLAG_TIMESTAMP, 0);
99
100 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0);
101 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
102
103 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR);
104 addr = EFSYS_MEM_ADDR(esmp);
105
106 for (i = 0; i < npages; i++) {
107 EFX_POPULATE_QWORD_2(*dma_addr,
108 EFX_DWORD_1, (uint32_t)(addr >> 32),
109 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
110
111 dma_addr++;
112 addr += EFX_BUF_SIZE;
113 }
114
115 efx_mcdi_execute(enp, &req);
116
117 if (req.emr_rc != 0) {
118 rc = req.emr_rc;
119 goto fail2;
120 }
121
122 return (0);
123
124fail2:
125 EFSYS_PROBE(fail2);
126fail1:
127 EFSYS_PROBE1(fail1, efx_rc_t, rc);
128
129 return (rc);
130}
131
132static __checkReturn efx_rc_t
133efx_mcdi_fini_txq(
134 __in efx_nic_t *enp,
135 __in uint32_t instance)
136{
137 efx_mcdi_req_t req;
138 uint8_t payload[MAX(MC_CMD_FINI_TXQ_IN_LEN,
139 MC_CMD_FINI_TXQ_OUT_LEN)];
140 efx_rc_t rc;
141
142 (void) memset(payload, 0, sizeof (payload));
143 req.emr_cmd = MC_CMD_FINI_TXQ;
144 req.emr_in_buf = payload;
145 req.emr_in_length = MC_CMD_FINI_TXQ_IN_LEN;
146 req.emr_out_buf = payload;
147 req.emr_out_length = MC_CMD_FINI_TXQ_OUT_LEN;
148
149 MCDI_IN_SET_DWORD(req, FINI_TXQ_IN_INSTANCE, instance);
150
151 efx_mcdi_execute(enp, &req);
152
153 if ((req.emr_rc != 0) && (req.emr_rc != MC_CMD_ERR_EALREADY)) {
154 rc = req.emr_rc;
155 goto fail1;
156 }
157
158 return (0);
159
160fail1:
161 EFSYS_PROBE1(fail1, efx_rc_t, rc);
162
163 return (rc);
164}
165
166 __checkReturn efx_rc_t
167ef10_tx_init(
168 __in efx_nic_t *enp)
169{
170 _NOTE(ARGUNUSED(enp))
171 return (0);
172}
173
174 void
175ef10_tx_fini(
176 __in efx_nic_t *enp)
177{
178 _NOTE(ARGUNUSED(enp))
179}
180
181 __checkReturn efx_rc_t
182ef10_tx_qcreate(
183 __in efx_nic_t *enp,
184 __in unsigned int index,
185 __in unsigned int label,
186 __in efsys_mem_t *esmp,
187 __in size_t n,
188 __in uint32_t id,
189 __in uint16_t flags,
190 __in efx_evq_t *eep,
191 __in efx_txq_t *etp,
192 __out unsigned int *addedp)
193{
194 efx_qword_t desc;
195 efx_rc_t rc;
196
197
198 if ((rc = efx_mcdi_init_txq(enp, n, eep->ee_index, label, index, flags,
199 esmp)) != 0)
200 goto fail1;
201
202 /*
203 * A previous user of this TX queue may have written a descriptor to the
204 * TX push collector, but not pushed the doorbell (e.g. after a crash).
205 * The next doorbell write would then push the stale descriptor.
206 *
207 * Ensure the (per network port) TX push collector is cleared by writing
208 * a no-op TX option descriptor. See bug29981 for details.
209 */
210 *addedp = 1;
211 EFX_POPULATE_QWORD_4(desc,
212 ESF_DZ_TX_DESC_IS_OPT, 1,
213 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
214 ESF_DZ_TX_OPTION_UDP_TCP_CSUM,
215 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 1 : 0,
216 ESF_DZ_TX_OPTION_IP_CSUM,
217 (flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0);
218
219 EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc);
220 ef10_tx_qpush(etp, *addedp, 0);
221
222 return (0);
223
224fail1:
225 EFSYS_PROBE1(fail1, efx_rc_t, rc);
226
227 return (rc);
228}
229
230 void
231ef10_tx_qdestroy(
232 __in efx_txq_t *etp)
233{
234 /* FIXME */
235 _NOTE(ARGUNUSED(etp))
236 /* FIXME */
237}
238
239 __checkReturn efx_rc_t
240ef10_tx_qpio_enable(
241 __in efx_txq_t *etp)
242{
243 efx_nic_t *enp = etp->et_enp;
244 efx_piobuf_handle_t handle;
245 efx_rc_t rc;
246
247 if (etp->et_pio_size != 0) {
248 rc = EALREADY;
249 goto fail1;
250 }
251
252 /* Sub-allocate a PIO block from a piobuf */
253 if ((rc = ef10_nic_pio_alloc(enp,
254 &etp->et_pio_bufnum,
255 &handle,
256 &etp->et_pio_blknum,
257 &etp->et_pio_offset,
258 &etp->et_pio_size)) != 0) {
259 goto fail2;
260 }
261 EFSYS_ASSERT3U(etp->et_pio_size, !=, 0);
262
263 /* Link the piobuf to this TXQ */
264 if ((rc = ef10_nic_pio_link(enp, etp->et_index, handle)) != 0) {
265 goto fail3;
266 }
267
268 /*
269 * et_pio_offset is the offset of the sub-allocated block within the
270 * hardware PIO buffer. It is used as the buffer address in the PIO
271 * option descriptor.
272 *
273 * et_pio_write_offset is the offset of the sub-allocated block from the
274 * start of the write-combined memory mapping, and is used for writing
275 * data into the PIO buffer.
276 */
277 etp->et_pio_write_offset =
278 (etp->et_pio_bufnum * ER_DZ_TX_PIOBUF_STEP) +
279 ER_DZ_TX_PIOBUF_OFST + etp->et_pio_offset;
280
281 return (0);
282
283fail3:
284 EFSYS_PROBE(fail3);
285 ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
286 etp->et_pio_size = 0;
287fail2:
288 EFSYS_PROBE(fail2);
289fail1:
290 EFSYS_PROBE1(fail1, efx_rc_t, rc);
291
292 return (rc);
293}
294
295 void
296ef10_tx_qpio_disable(
297 __in efx_txq_t *etp)
298{
299 efx_nic_t *enp = etp->et_enp;
300
301 if (etp->et_pio_size != 0) {
302 /* Unlink the piobuf from this TXQ */
303 ef10_nic_pio_unlink(enp, etp->et_index);
304
305 /* Free the sub-allocated PIO block */
306 ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
307 etp->et_pio_size = 0;
308 etp->et_pio_write_offset = 0;
309 }
310}
311
312 __checkReturn efx_rc_t
313ef10_tx_qpio_write(
314 __in efx_txq_t *etp,
315 __in_ecount(length) uint8_t *buffer,
316 __in size_t length,
317 __in size_t offset)
318{
319 efx_nic_t *enp = etp->et_enp;
320 efsys_bar_t *esbp = enp->en_esbp;
321 uint32_t write_offset;
322 uint32_t write_offset_limit;
323 efx_qword_t *eqp;
324 efx_rc_t rc;
325
326 EFSYS_ASSERT(length % sizeof (efx_qword_t) == 0);
327
328 if (etp->et_pio_size == 0) {
329 rc = ENOENT;
330 goto fail1;
331 }
332 if (offset + length > etp->et_pio_size) {
333 rc = ENOSPC;
334 goto fail2;
335 }
336
337 /*
338 * Writes to PIO buffers must be 64 bit aligned, and multiples of
339 * 64 bits.
340 */
341 write_offset = etp->et_pio_write_offset + offset;
342 write_offset_limit = write_offset + length;
343 eqp = (efx_qword_t *)buffer;
344 while (write_offset < write_offset_limit) {
345 EFSYS_BAR_WC_WRITEQ(esbp, write_offset, eqp);
346 eqp++;
347 write_offset += sizeof (efx_qword_t);
348 }
349
350 return (0);
351
352fail2:
353 EFSYS_PROBE(fail2);
354fail1:
355 EFSYS_PROBE1(fail1, efx_rc_t, rc);
356
357 return (rc);
358}
359
360 __checkReturn efx_rc_t
361ef10_tx_qpio_post(
362 __in efx_txq_t *etp,
363 __in size_t pkt_length,
364 __in unsigned int completed,
365 __inout unsigned int *addedp)
366{
367 efx_qword_t pio_desc;
368 unsigned int id;
369 size_t offset;
370 unsigned int added = *addedp;
371 efx_rc_t rc;
372
373
374 if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
375 rc = ENOSPC;
376 goto fail1;
377 }
378
379 if (etp->et_pio_size == 0) {
380 rc = ENOENT;
381 goto fail2;
382 }
383
384 id = added++ & etp->et_mask;
385 offset = id * sizeof (efx_qword_t);
386
387 EFSYS_PROBE4(tx_pio_post, unsigned int, etp->et_index,
388 unsigned int, id, uint32_t, etp->et_pio_offset,
389 size_t, pkt_length);
390
391 EFX_POPULATE_QWORD_5(pio_desc,
392 ESF_DZ_TX_DESC_IS_OPT, 1,
393 ESF_DZ_TX_OPTION_TYPE, 1,
394 ESF_DZ_TX_PIO_CONT, 0,
395 ESF_DZ_TX_PIO_BYTE_CNT, pkt_length,
396 ESF_DZ_TX_PIO_BUF_ADDR, etp->et_pio_offset);
397
398 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &pio_desc);
399
400 EFX_TX_QSTAT_INCR(etp, TX_POST_PIO);
401
402 *addedp = added;
403 return (0);
404
405fail2:
406 EFSYS_PROBE(fail2);
407fail1:
408 EFSYS_PROBE1(fail1, efx_rc_t, rc);
409
410 return (rc);
411}
412
413 __checkReturn efx_rc_t
414ef10_tx_qpost(
415 __in efx_txq_t *etp,
416 __in_ecount(n) efx_buffer_t *eb,
417 __in unsigned int n,
418 __in unsigned int completed,
419 __inout unsigned int *addedp)
420{
421 unsigned int added = *addedp;
422 unsigned int i;
423 efx_rc_t rc;
424
425 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
426 rc = ENOSPC;
427 goto fail1;
428 }
429
430 for (i = 0; i < n; i++) {
431 efx_buffer_t *ebp = &eb[i];
432 efsys_dma_addr_t addr = ebp->eb_addr;
433 size_t size = ebp->eb_size;
434 boolean_t eop = ebp->eb_eop;
435 unsigned int id;
436 size_t offset;
437 efx_qword_t qword;
438
439 /* Fragments must not span 4k boundaries. */
440 EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= (addr + size));
441
442 id = added++ & etp->et_mask;
443 offset = id * sizeof (efx_qword_t);
444
445 EFSYS_PROBE5(tx_post, unsigned int, etp->et_index,
446 unsigned int, id, efsys_dma_addr_t, addr,
447 size_t, size, boolean_t, eop);
448
449 EFX_POPULATE_QWORD_5(qword,
450 ESF_DZ_TX_KER_TYPE, 0,
451 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
452 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
453 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
454 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
455
456 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &qword);
457 }
458
459 EFX_TX_QSTAT_INCR(etp, TX_POST);
460
461 *addedp = added;
462 return (0);
463
464fail1:
465 EFSYS_PROBE1(fail1, efx_rc_t, rc);
466
467 return (rc);
468}
469
470/*
471 * This improves performance by pushing a TX descriptor at the same time as the
472 * doorbell. The descriptor must be added to the TXQ, so that can be used if the
473 * hardware decides not to use the pushed descriptor.
474 */
475 void
476ef10_tx_qpush(
477 __in efx_txq_t *etp,
478 __in unsigned int added,
479 __in unsigned int pushed)
480{
481 efx_nic_t *enp = etp->et_enp;
482 unsigned int wptr;
483 unsigned int id;
484 size_t offset;
485 efx_qword_t desc;
486 efx_oword_t oword;
487
488 wptr = added & etp->et_mask;
489 id = pushed & etp->et_mask;
490 offset = id * sizeof (efx_qword_t);
491
492 EFSYS_MEM_READQ(etp->et_esmp, offset, &desc);
493 EFX_POPULATE_OWORD_3(oword,
494 ERF_DZ_TX_DESC_WPTR, wptr,
495 ERF_DZ_TX_DESC_HWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_1),
496 ERF_DZ_TX_DESC_LWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_0));
497
498 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
499 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1, wptr, id);
500 EFSYS_PIO_WRITE_BARRIER();
501 EFX_BAR_TBL_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG, etp->et_index,
502 &oword);
503}
504
505 __checkReturn efx_rc_t
506ef10_tx_qdesc_post(
507 __in efx_txq_t *etp,
508 __in_ecount(n) efx_desc_t *ed,
509 __in unsigned int n,
510 __in unsigned int completed,
511 __inout unsigned int *addedp)
512{
513 unsigned int added = *addedp;
514 unsigned int i;
515 efx_rc_t rc;
516
517 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
518 rc = ENOSPC;
519 goto fail1;
520 }
521
522 for (i = 0; i < n; i++) {
523 efx_desc_t *edp = &ed[i];
524 unsigned int id;
525 size_t offset;
526
527 id = added++ & etp->et_mask;
528 offset = id * sizeof (efx_desc_t);
529
530 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq);
531 }
532
533 EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
534 unsigned int, added, unsigned int, n);
535
536 EFX_TX_QSTAT_INCR(etp, TX_POST);
537
538 *addedp = added;
539 return (0);
540
541fail1:
542 EFSYS_PROBE1(fail1, efx_rc_t, rc);
543
544 return (rc);
545}
546
547 void
548ef10_tx_qdesc_dma_create(
549 __in efx_txq_t *etp,
550 __in efsys_dma_addr_t addr,
551 __in size_t size,
552 __in boolean_t eop,
553 __out efx_desc_t *edp)
554{
555 /* Fragments must not span 4k boundaries. */
556 EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= addr + size);
557
558 EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
559 efsys_dma_addr_t, addr,
560 size_t, size, boolean_t, eop);
561
562 EFX_POPULATE_QWORD_5(edp->ed_eq,
563 ESF_DZ_TX_KER_TYPE, 0,
564 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
565 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
566 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
567 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
568}
569
570 void
571hunt_tx_qdesc_tso_create(
572 __in efx_txq_t *etp,
573 __in uint16_t ipv4_id,
574 __in uint32_t tcp_seq,
575 __in uint8_t tcp_flags,
576 __out efx_desc_t *edp)
577{
578 EFSYS_PROBE4(tx_desc_tso_create, unsigned int, etp->et_index,
579 uint16_t, ipv4_id, uint32_t, tcp_seq,
580 uint8_t, tcp_flags);
581
582 EFX_POPULATE_QWORD_5(edp->ed_eq,
583 ESF_DZ_TX_DESC_IS_OPT, 1,
584 ESF_DZ_TX_OPTION_TYPE,
585 ESE_DZ_TX_OPTION_DESC_TSO,
586 ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
587 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
588 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
589}
590
591 void
592ef10_tx_qdesc_vlantci_create(
593 __in efx_txq_t *etp,
594 __in uint16_t tci,
595 __out efx_desc_t *edp)
596{
597 EFSYS_PROBE2(tx_desc_vlantci_create, unsigned int, etp->et_index,
598 uint16_t, tci);
599
600 EFX_POPULATE_QWORD_4(edp->ed_eq,
601 ESF_DZ_TX_DESC_IS_OPT, 1,
602 ESF_DZ_TX_OPTION_TYPE,
603 ESE_DZ_TX_OPTION_DESC_VLAN,
604 ESF_DZ_TX_VLAN_OP, tci ? 1 : 0,
605 ESF_DZ_TX_VLAN_TAG1, tci);
606}
607
608
609 __checkReturn efx_rc_t
610ef10_tx_qpace(
611 __in efx_txq_t *etp,
612 __in unsigned int ns)
613{
614 efx_rc_t rc;
615
616 /* FIXME */
617 _NOTE(ARGUNUSED(etp, ns))
618 if (B_FALSE) {
619 rc = ENOTSUP;
620 goto fail1;
621 }
622 /* FIXME */
623
624 return (0);
625
626fail1:
627 EFSYS_PROBE1(fail1, efx_rc_t, rc);
628
629 return (rc);
630}
631
632 __checkReturn efx_rc_t
633ef10_tx_qflush(
634 __in efx_txq_t *etp)
635{
636 efx_nic_t *enp = etp->et_enp;
637 efx_rc_t rc;
638
639 if ((rc = efx_mcdi_fini_txq(enp, etp->et_index)) != 0)
640 goto fail1;
641
642 return (0);
643
644fail1:
645 EFSYS_PROBE1(fail1, efx_rc_t, rc);
646
647 return (rc);
648}
649
650 void
651ef10_tx_qenable(
652 __in efx_txq_t *etp)
653{
654 /* FIXME */
655 _NOTE(ARGUNUSED(etp))
656 /* FIXME */
657}
658
659#if EFSYS_OPT_QSTATS
660 void
661ef10_tx_qstats_update(
662 __in efx_txq_t *etp,
663 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
664{
665 unsigned int id;
666
667 for (id = 0; id < TX_NQSTATS; id++) {
668 efsys_stat_t *essp = &stat[id];
669
670 EFSYS_STAT_INCR(essp, etp->et_stat[id]);
671 etp->et_stat[id] = 0;
672 }
673}
674
675#endif /* EFSYS_OPT_QSTATS */
676
677#endif /* EFSYS_OPT_HUNTINGTON */
2 * Copyright (c) 2012-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/sfxge/common/hunt_tx.c 293814 2016-01-13 07:25:51Z arybchik $");
33
34#include "efx.h"
35#include "efx_impl.h"
36
37
38#if EFSYS_OPT_HUNTINGTON
39
40#if EFSYS_OPT_QSTATS
41#define EFX_TX_QSTAT_INCR(_etp, _stat) \
42 do { \
43 (_etp)->et_stat[_stat]++; \
44 _NOTE(CONSTANTCONDITION) \
45 } while (B_FALSE)
46#else
47#define EFX_TX_QSTAT_INCR(_etp, _stat)
48#endif
49
50static __checkReturn efx_rc_t
51efx_mcdi_init_txq(
52 __in efx_nic_t *enp,
53 __in uint32_t size,
54 __in uint32_t target_evq,
55 __in uint32_t label,
56 __in uint32_t instance,
57 __in uint16_t flags,
58 __in efsys_mem_t *esmp)
59{
60 efx_mcdi_req_t req;
61 uint8_t payload[MAX(MC_CMD_INIT_TXQ_IN_LEN(EFX_TXQ_MAX_BUFS),
62 MC_CMD_INIT_TXQ_OUT_LEN)];
63 efx_qword_t *dma_addr;
64 uint64_t addr;
65 int npages;
66 int i;
67 efx_rc_t rc;
68
69 EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >=
70 EFX_TXQ_NBUFS(EFX_TXQ_MAXNDESCS(&enp->en_nic_cfg)));
71
72 npages = EFX_TXQ_NBUFS(size);
73 if (npages > MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM) {
74 rc = EINVAL;
75 goto fail1;
76 }
77
78 (void) memset(payload, 0, sizeof (payload));
79 req.emr_cmd = MC_CMD_INIT_TXQ;
80 req.emr_in_buf = payload;
81 req.emr_in_length = MC_CMD_INIT_TXQ_IN_LEN(npages);
82 req.emr_out_buf = payload;
83 req.emr_out_length = MC_CMD_INIT_TXQ_OUT_LEN;
84
85 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, size);
86 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_TARGET_EVQ, target_evq);
87 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label);
88 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance);
89
90 MCDI_IN_POPULATE_DWORD_6(req, INIT_TXQ_IN_FLAGS,
91 INIT_TXQ_IN_FLAG_BUFF_MODE, 0,
92 INIT_TXQ_IN_FLAG_IP_CSUM_DIS,
93 (flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1,
94 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS,
95 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1,
96 INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0,
97 INIT_TXQ_IN_CRC_MODE, 0,
98 INIT_TXQ_IN_FLAG_TIMESTAMP, 0);
99
100 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0);
101 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
102
103 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR);
104 addr = EFSYS_MEM_ADDR(esmp);
105
106 for (i = 0; i < npages; i++) {
107 EFX_POPULATE_QWORD_2(*dma_addr,
108 EFX_DWORD_1, (uint32_t)(addr >> 32),
109 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
110
111 dma_addr++;
112 addr += EFX_BUF_SIZE;
113 }
114
115 efx_mcdi_execute(enp, &req);
116
117 if (req.emr_rc != 0) {
118 rc = req.emr_rc;
119 goto fail2;
120 }
121
122 return (0);
123
124fail2:
125 EFSYS_PROBE(fail2);
126fail1:
127 EFSYS_PROBE1(fail1, efx_rc_t, rc);
128
129 return (rc);
130}
131
132static __checkReturn efx_rc_t
133efx_mcdi_fini_txq(
134 __in efx_nic_t *enp,
135 __in uint32_t instance)
136{
137 efx_mcdi_req_t req;
138 uint8_t payload[MAX(MC_CMD_FINI_TXQ_IN_LEN,
139 MC_CMD_FINI_TXQ_OUT_LEN)];
140 efx_rc_t rc;
141
142 (void) memset(payload, 0, sizeof (payload));
143 req.emr_cmd = MC_CMD_FINI_TXQ;
144 req.emr_in_buf = payload;
145 req.emr_in_length = MC_CMD_FINI_TXQ_IN_LEN;
146 req.emr_out_buf = payload;
147 req.emr_out_length = MC_CMD_FINI_TXQ_OUT_LEN;
148
149 MCDI_IN_SET_DWORD(req, FINI_TXQ_IN_INSTANCE, instance);
150
151 efx_mcdi_execute(enp, &req);
152
153 if ((req.emr_rc != 0) && (req.emr_rc != MC_CMD_ERR_EALREADY)) {
154 rc = req.emr_rc;
155 goto fail1;
156 }
157
158 return (0);
159
160fail1:
161 EFSYS_PROBE1(fail1, efx_rc_t, rc);
162
163 return (rc);
164}
165
166 __checkReturn efx_rc_t
167ef10_tx_init(
168 __in efx_nic_t *enp)
169{
170 _NOTE(ARGUNUSED(enp))
171 return (0);
172}
173
174 void
175ef10_tx_fini(
176 __in efx_nic_t *enp)
177{
178 _NOTE(ARGUNUSED(enp))
179}
180
181 __checkReturn efx_rc_t
182ef10_tx_qcreate(
183 __in efx_nic_t *enp,
184 __in unsigned int index,
185 __in unsigned int label,
186 __in efsys_mem_t *esmp,
187 __in size_t n,
188 __in uint32_t id,
189 __in uint16_t flags,
190 __in efx_evq_t *eep,
191 __in efx_txq_t *etp,
192 __out unsigned int *addedp)
193{
194 efx_qword_t desc;
195 efx_rc_t rc;
196
197
198 if ((rc = efx_mcdi_init_txq(enp, n, eep->ee_index, label, index, flags,
199 esmp)) != 0)
200 goto fail1;
201
202 /*
203 * A previous user of this TX queue may have written a descriptor to the
204 * TX push collector, but not pushed the doorbell (e.g. after a crash).
205 * The next doorbell write would then push the stale descriptor.
206 *
207 * Ensure the (per network port) TX push collector is cleared by writing
208 * a no-op TX option descriptor. See bug29981 for details.
209 */
210 *addedp = 1;
211 EFX_POPULATE_QWORD_4(desc,
212 ESF_DZ_TX_DESC_IS_OPT, 1,
213 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
214 ESF_DZ_TX_OPTION_UDP_TCP_CSUM,
215 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 1 : 0,
216 ESF_DZ_TX_OPTION_IP_CSUM,
217 (flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0);
218
219 EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc);
220 ef10_tx_qpush(etp, *addedp, 0);
221
222 return (0);
223
224fail1:
225 EFSYS_PROBE1(fail1, efx_rc_t, rc);
226
227 return (rc);
228}
229
230 void
231ef10_tx_qdestroy(
232 __in efx_txq_t *etp)
233{
234 /* FIXME */
235 _NOTE(ARGUNUSED(etp))
236 /* FIXME */
237}
238
239 __checkReturn efx_rc_t
240ef10_tx_qpio_enable(
241 __in efx_txq_t *etp)
242{
243 efx_nic_t *enp = etp->et_enp;
244 efx_piobuf_handle_t handle;
245 efx_rc_t rc;
246
247 if (etp->et_pio_size != 0) {
248 rc = EALREADY;
249 goto fail1;
250 }
251
252 /* Sub-allocate a PIO block from a piobuf */
253 if ((rc = ef10_nic_pio_alloc(enp,
254 &etp->et_pio_bufnum,
255 &handle,
256 &etp->et_pio_blknum,
257 &etp->et_pio_offset,
258 &etp->et_pio_size)) != 0) {
259 goto fail2;
260 }
261 EFSYS_ASSERT3U(etp->et_pio_size, !=, 0);
262
263 /* Link the piobuf to this TXQ */
264 if ((rc = ef10_nic_pio_link(enp, etp->et_index, handle)) != 0) {
265 goto fail3;
266 }
267
268 /*
269 * et_pio_offset is the offset of the sub-allocated block within the
270 * hardware PIO buffer. It is used as the buffer address in the PIO
271 * option descriptor.
272 *
273 * et_pio_write_offset is the offset of the sub-allocated block from the
274 * start of the write-combined memory mapping, and is used for writing
275 * data into the PIO buffer.
276 */
277 etp->et_pio_write_offset =
278 (etp->et_pio_bufnum * ER_DZ_TX_PIOBUF_STEP) +
279 ER_DZ_TX_PIOBUF_OFST + etp->et_pio_offset;
280
281 return (0);
282
283fail3:
284 EFSYS_PROBE(fail3);
285 ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
286 etp->et_pio_size = 0;
287fail2:
288 EFSYS_PROBE(fail2);
289fail1:
290 EFSYS_PROBE1(fail1, efx_rc_t, rc);
291
292 return (rc);
293}
294
295 void
296ef10_tx_qpio_disable(
297 __in efx_txq_t *etp)
298{
299 efx_nic_t *enp = etp->et_enp;
300
301 if (etp->et_pio_size != 0) {
302 /* Unlink the piobuf from this TXQ */
303 ef10_nic_pio_unlink(enp, etp->et_index);
304
305 /* Free the sub-allocated PIO block */
306 ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
307 etp->et_pio_size = 0;
308 etp->et_pio_write_offset = 0;
309 }
310}
311
312 __checkReturn efx_rc_t
313ef10_tx_qpio_write(
314 __in efx_txq_t *etp,
315 __in_ecount(length) uint8_t *buffer,
316 __in size_t length,
317 __in size_t offset)
318{
319 efx_nic_t *enp = etp->et_enp;
320 efsys_bar_t *esbp = enp->en_esbp;
321 uint32_t write_offset;
322 uint32_t write_offset_limit;
323 efx_qword_t *eqp;
324 efx_rc_t rc;
325
326 EFSYS_ASSERT(length % sizeof (efx_qword_t) == 0);
327
328 if (etp->et_pio_size == 0) {
329 rc = ENOENT;
330 goto fail1;
331 }
332 if (offset + length > etp->et_pio_size) {
333 rc = ENOSPC;
334 goto fail2;
335 }
336
337 /*
338 * Writes to PIO buffers must be 64 bit aligned, and multiples of
339 * 64 bits.
340 */
341 write_offset = etp->et_pio_write_offset + offset;
342 write_offset_limit = write_offset + length;
343 eqp = (efx_qword_t *)buffer;
344 while (write_offset < write_offset_limit) {
345 EFSYS_BAR_WC_WRITEQ(esbp, write_offset, eqp);
346 eqp++;
347 write_offset += sizeof (efx_qword_t);
348 }
349
350 return (0);
351
352fail2:
353 EFSYS_PROBE(fail2);
354fail1:
355 EFSYS_PROBE1(fail1, efx_rc_t, rc);
356
357 return (rc);
358}
359
360 __checkReturn efx_rc_t
361ef10_tx_qpio_post(
362 __in efx_txq_t *etp,
363 __in size_t pkt_length,
364 __in unsigned int completed,
365 __inout unsigned int *addedp)
366{
367 efx_qword_t pio_desc;
368 unsigned int id;
369 size_t offset;
370 unsigned int added = *addedp;
371 efx_rc_t rc;
372
373
374 if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
375 rc = ENOSPC;
376 goto fail1;
377 }
378
379 if (etp->et_pio_size == 0) {
380 rc = ENOENT;
381 goto fail2;
382 }
383
384 id = added++ & etp->et_mask;
385 offset = id * sizeof (efx_qword_t);
386
387 EFSYS_PROBE4(tx_pio_post, unsigned int, etp->et_index,
388 unsigned int, id, uint32_t, etp->et_pio_offset,
389 size_t, pkt_length);
390
391 EFX_POPULATE_QWORD_5(pio_desc,
392 ESF_DZ_TX_DESC_IS_OPT, 1,
393 ESF_DZ_TX_OPTION_TYPE, 1,
394 ESF_DZ_TX_PIO_CONT, 0,
395 ESF_DZ_TX_PIO_BYTE_CNT, pkt_length,
396 ESF_DZ_TX_PIO_BUF_ADDR, etp->et_pio_offset);
397
398 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &pio_desc);
399
400 EFX_TX_QSTAT_INCR(etp, TX_POST_PIO);
401
402 *addedp = added;
403 return (0);
404
405fail2:
406 EFSYS_PROBE(fail2);
407fail1:
408 EFSYS_PROBE1(fail1, efx_rc_t, rc);
409
410 return (rc);
411}
412
413 __checkReturn efx_rc_t
414ef10_tx_qpost(
415 __in efx_txq_t *etp,
416 __in_ecount(n) efx_buffer_t *eb,
417 __in unsigned int n,
418 __in unsigned int completed,
419 __inout unsigned int *addedp)
420{
421 unsigned int added = *addedp;
422 unsigned int i;
423 efx_rc_t rc;
424
425 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
426 rc = ENOSPC;
427 goto fail1;
428 }
429
430 for (i = 0; i < n; i++) {
431 efx_buffer_t *ebp = &eb[i];
432 efsys_dma_addr_t addr = ebp->eb_addr;
433 size_t size = ebp->eb_size;
434 boolean_t eop = ebp->eb_eop;
435 unsigned int id;
436 size_t offset;
437 efx_qword_t qword;
438
439 /* Fragments must not span 4k boundaries. */
440 EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= (addr + size));
441
442 id = added++ & etp->et_mask;
443 offset = id * sizeof (efx_qword_t);
444
445 EFSYS_PROBE5(tx_post, unsigned int, etp->et_index,
446 unsigned int, id, efsys_dma_addr_t, addr,
447 size_t, size, boolean_t, eop);
448
449 EFX_POPULATE_QWORD_5(qword,
450 ESF_DZ_TX_KER_TYPE, 0,
451 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
452 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
453 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
454 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
455
456 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &qword);
457 }
458
459 EFX_TX_QSTAT_INCR(etp, TX_POST);
460
461 *addedp = added;
462 return (0);
463
464fail1:
465 EFSYS_PROBE1(fail1, efx_rc_t, rc);
466
467 return (rc);
468}
469
470/*
471 * This improves performance by pushing a TX descriptor at the same time as the
472 * doorbell. The descriptor must be added to the TXQ, so that can be used if the
473 * hardware decides not to use the pushed descriptor.
474 */
475 void
476ef10_tx_qpush(
477 __in efx_txq_t *etp,
478 __in unsigned int added,
479 __in unsigned int pushed)
480{
481 efx_nic_t *enp = etp->et_enp;
482 unsigned int wptr;
483 unsigned int id;
484 size_t offset;
485 efx_qword_t desc;
486 efx_oword_t oword;
487
488 wptr = added & etp->et_mask;
489 id = pushed & etp->et_mask;
490 offset = id * sizeof (efx_qword_t);
491
492 EFSYS_MEM_READQ(etp->et_esmp, offset, &desc);
493 EFX_POPULATE_OWORD_3(oword,
494 ERF_DZ_TX_DESC_WPTR, wptr,
495 ERF_DZ_TX_DESC_HWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_1),
496 ERF_DZ_TX_DESC_LWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_0));
497
498 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
499 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1, wptr, id);
500 EFSYS_PIO_WRITE_BARRIER();
501 EFX_BAR_TBL_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG, etp->et_index,
502 &oword);
503}
504
505 __checkReturn efx_rc_t
506ef10_tx_qdesc_post(
507 __in efx_txq_t *etp,
508 __in_ecount(n) efx_desc_t *ed,
509 __in unsigned int n,
510 __in unsigned int completed,
511 __inout unsigned int *addedp)
512{
513 unsigned int added = *addedp;
514 unsigned int i;
515 efx_rc_t rc;
516
517 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
518 rc = ENOSPC;
519 goto fail1;
520 }
521
522 for (i = 0; i < n; i++) {
523 efx_desc_t *edp = &ed[i];
524 unsigned int id;
525 size_t offset;
526
527 id = added++ & etp->et_mask;
528 offset = id * sizeof (efx_desc_t);
529
530 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq);
531 }
532
533 EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
534 unsigned int, added, unsigned int, n);
535
536 EFX_TX_QSTAT_INCR(etp, TX_POST);
537
538 *addedp = added;
539 return (0);
540
541fail1:
542 EFSYS_PROBE1(fail1, efx_rc_t, rc);
543
544 return (rc);
545}
546
547 void
548ef10_tx_qdesc_dma_create(
549 __in efx_txq_t *etp,
550 __in efsys_dma_addr_t addr,
551 __in size_t size,
552 __in boolean_t eop,
553 __out efx_desc_t *edp)
554{
555 /* Fragments must not span 4k boundaries. */
556 EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= addr + size);
557
558 EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
559 efsys_dma_addr_t, addr,
560 size_t, size, boolean_t, eop);
561
562 EFX_POPULATE_QWORD_5(edp->ed_eq,
563 ESF_DZ_TX_KER_TYPE, 0,
564 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
565 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
566 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
567 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
568}
569
570 void
571hunt_tx_qdesc_tso_create(
572 __in efx_txq_t *etp,
573 __in uint16_t ipv4_id,
574 __in uint32_t tcp_seq,
575 __in uint8_t tcp_flags,
576 __out efx_desc_t *edp)
577{
578 EFSYS_PROBE4(tx_desc_tso_create, unsigned int, etp->et_index,
579 uint16_t, ipv4_id, uint32_t, tcp_seq,
580 uint8_t, tcp_flags);
581
582 EFX_POPULATE_QWORD_5(edp->ed_eq,
583 ESF_DZ_TX_DESC_IS_OPT, 1,
584 ESF_DZ_TX_OPTION_TYPE,
585 ESE_DZ_TX_OPTION_DESC_TSO,
586 ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
587 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
588 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
589}
590
591 void
592ef10_tx_qdesc_vlantci_create(
593 __in efx_txq_t *etp,
594 __in uint16_t tci,
595 __out efx_desc_t *edp)
596{
597 EFSYS_PROBE2(tx_desc_vlantci_create, unsigned int, etp->et_index,
598 uint16_t, tci);
599
600 EFX_POPULATE_QWORD_4(edp->ed_eq,
601 ESF_DZ_TX_DESC_IS_OPT, 1,
602 ESF_DZ_TX_OPTION_TYPE,
603 ESE_DZ_TX_OPTION_DESC_VLAN,
604 ESF_DZ_TX_VLAN_OP, tci ? 1 : 0,
605 ESF_DZ_TX_VLAN_TAG1, tci);
606}
607
608
609 __checkReturn efx_rc_t
610ef10_tx_qpace(
611 __in efx_txq_t *etp,
612 __in unsigned int ns)
613{
614 efx_rc_t rc;
615
616 /* FIXME */
617 _NOTE(ARGUNUSED(etp, ns))
618 if (B_FALSE) {
619 rc = ENOTSUP;
620 goto fail1;
621 }
622 /* FIXME */
623
624 return (0);
625
626fail1:
627 EFSYS_PROBE1(fail1, efx_rc_t, rc);
628
629 return (rc);
630}
631
632 __checkReturn efx_rc_t
633ef10_tx_qflush(
634 __in efx_txq_t *etp)
635{
636 efx_nic_t *enp = etp->et_enp;
637 efx_rc_t rc;
638
639 if ((rc = efx_mcdi_fini_txq(enp, etp->et_index)) != 0)
640 goto fail1;
641
642 return (0);
643
644fail1:
645 EFSYS_PROBE1(fail1, efx_rc_t, rc);
646
647 return (rc);
648}
649
650 void
651ef10_tx_qenable(
652 __in efx_txq_t *etp)
653{
654 /* FIXME */
655 _NOTE(ARGUNUSED(etp))
656 /* FIXME */
657}
658
659#if EFSYS_OPT_QSTATS
660 void
661ef10_tx_qstats_update(
662 __in efx_txq_t *etp,
663 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
664{
665 unsigned int id;
666
667 for (id = 0; id < TX_NQSTATS; id++) {
668 efsys_stat_t *essp = &stat[id];
669
670 EFSYS_STAT_INCR(essp, etp->et_stat[id]);
671 etp->et_stat[id] = 0;
672 }
673}
674
675#endif /* EFSYS_OPT_QSTATS */
676
677#endif /* EFSYS_OPT_HUNTINGTON */