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rpreg.h (59874) rpreg.h (61541)
1/*
2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted prodived that the follwoing conditions
7 * are met.
8 * 1. Redistributions of source code must retain the above copyright

--- 15 unchanged lines hidden (view full) ---

24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
1/*
2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted prodived that the follwoing conditions
7 * are met.
8 * 1. Redistributions of source code must retain the above copyright

--- 15 unchanged lines hidden (view full) ---

24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/dev/rp/rpreg.h 59874 2000-05-01 20:32:07Z peter $
32 * $FreeBSD: head/sys/dev/rp/rpreg.h 61541 2000-06-11 06:43:16Z tanimura $
33 */
34
35/*
36 * Begin OS-specific defines - rpreg.h - for RocketPort FreeBSD
37 */
38
39typedef unsigned char Byte_t;
40typedef unsigned int ByteIO_t;
41
42typedef unsigned int Word_t;
43typedef unsigned int WordIO_t;
44
45typedef unsigned long DWord_t;
46typedef unsigned int DWordIO_t;
47
33 */
34
35/*
36 * Begin OS-specific defines - rpreg.h - for RocketPort FreeBSD
37 */
38
39typedef unsigned char Byte_t;
40typedef unsigned int ByteIO_t;
41
42typedef unsigned int Word_t;
43typedef unsigned int WordIO_t;
44
45typedef unsigned long DWord_t;
46typedef unsigned int DWordIO_t;
47
48#define sOutB(a, b) outb(a, b)
49#define sOutW(a, b) outw(a, b)
50#define sOutDW(a, b) outl(a, b)
51#define sInB(a) (inb(a))
52#define sInW(a) (inw(a))
53#define sOutStrW(port, addr, count) outsw(port, addr, count)
54#define sInStrW(port, addr, count) insw(port, addr, count)
48#define rp_readio(size, ctlp, rid, offset) \
49 (bus_space_read_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset))
50#define rp_readmultiio(size, ctlp, rid, offset, addr, count) \
51 (bus_space_read_multi_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset, addr, count))
52#define rp_writeio(size, ctlp, rid, offset, data) \
53 (bus_space_write_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset, data))
54#define rp_writemultiio(size, ctlp, rid, offset, addr, count) \
55 (bus_space_write_multi_##size(rman_get_bustag(ctlp->io[rid]), rman_get_bushandle(ctlp->io[rid]), offset, addr, count))
55
56
57#define rp_readio1(ctlp, rid, offset) rp_readio(1, ctlp, rid, offset)
58#define rp_readio2(ctlp, rid, offset) rp_readio(2, ctlp, rid, offset)
59#define rp_readio4(ctlp, rid, offset) rp_readio(4, ctlp, rid, offset)
60#define rp_writeio1(ctlp, rid, offset, data) rp_writeio(1, ctlp, rid, offset, data)
61#define rp_writeio2(ctlp, rid, offset, data) rp_writeio(2, ctlp, rid, offset, data)
62#define rp_writeio4(ctlp, rid, offset, data) rp_writeio(4, ctlp, rid, offset, data)
63#define rp_readmultiio1(ctlp, rid, offset, addr, count) rp_readmultiio(1, ctlp, rid, offset, addr, count)
64#define rp_readmultiio2(ctlp, rid, offset, addr, count) rp_readmultiio(2, ctlp, rid, offset, addr, count)
65#define rp_readmultiio4(ctlp, rid, offset, addr, count) rp_readmultiio(4, ctlp, rid, offset, addr, count)
66#define rp_writemultiio1(ctlp, rid, offset, addr, count) rp_writemultiio(1, ctlp, rid, offset, addr, count)
67#define rp_writemultiio2(ctlp, rid, offset, addr, count) rp_writemultiio(2, ctlp, rid, offset, addr, count)
68#define rp_writemultiio4(ctlp, rid, offset, addr, count) rp_writemultiio(4, ctlp, rid, offset, addr, count)
69
70#define rp_readaiop1(ctlp, aiop, offset) \
71 (rp_readio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
72#define rp_readaiop2(ctlp, aiop, offset) \
73 (rp_readio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
74#define rp_readaiop4(ctlp, aiop, offset) \
75 (rp_readio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
76#define rp_readmultiaiop1(ctlp, aiop, offset, addr, count) \
77 (rp_readmultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
78#define rp_readmultiaiop2(ctlp, aiop, offset, addr, count) \
79 (rp_readmultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
80#define rp_readmultiaiop4(ctlp, aiop, offset, addr, count) \
81 (rp_readmultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
82#define rp_writeaiop1(ctlp, aiop, offset, data) \
83 (rp_writeio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
84#define rp_writeaiop2(ctlp, aiop, offset, data) \
85 (rp_writeio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
86#define rp_writeaiop4(ctlp, aiop, offset, data) \
87 (rp_writeio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
88#define rp_writemultiaiop1(ctlp, aiop, offset, addr, count) \
89 (rp_writemultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
90#define rp_writemultiaiop2(ctlp, aiop, offset, addr, count) \
91 (rp_writemultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
92#define rp_writemultiaiop4(ctlp, aiop, offset, addr, count) \
93 (rp_writemultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
94
95#define rp_readch1(chp, offset) \
96 (rp_readaiop1((chp)->CtlP, (chp)->AiopNum, offset))
97#define rp_readch2(chp, offset) \
98 (rp_readaiop2((chp)->CtlP, (chp)->AiopNum, offset))
99#define rp_readch4(chp, offset) \
100 (rp_readaiop4((chp)->CtlP, (chp)->AiopNum, offset))
101#define rp_readmultich1(chp, offset, addr, count) \
102 (rp_readmultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
103#define rp_readmultich2(chp, offset, addr, count) \
104 (rp_readmultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
105#define rp_readmultich4(chp, offset, addr, count) \
106 (rp_readmultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
107#define rp_writech1(chp, offset, data) \
108 (rp_writeaiop1((chp)->CtlP, (chp)->AiopNum, offset, data))
109#define rp_writech2(chp, offset, data) \
110 (rp_writeaiop2((chp)->CtlP, (chp)->AiopNum, offset, data))
111#define rp_writech4(chp, offset, data) \
112 (rp_writeaiop4((chp)->CtlP, (chp)->AiopNum, offset, data))
113#define rp_writemultich1(chp, offset, addr, count) \
114 (rp_writemultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
115#define rp_writemultich2(chp, offset, addr, count) \
116 (rp_writemultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
117#define rp_writemultich4(chp, offset, addr, count) \
118 (rp_writemultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
119
56/*
57 * End of OS-specific defines
58 */
59
60#define ROCKET_H
61
62#define CTL_SIZE 4
63#define AIOP_CTL_SIZE 4
64#define CHAN_AIOP_SIZE 8
65#define MAX_PORTS_PER_AIOP 8
66#define MAX_AIOPS_PER_BOARD 4
67#define MAX_PORTS_PER_BOARD 32
68
120/*
121 * End of OS-specific defines
122 */
123
124#define ROCKET_H
125
126#define CTL_SIZE 4
127#define AIOP_CTL_SIZE 4
128#define CHAN_AIOP_SIZE 8
129#define MAX_PORTS_PER_AIOP 8
130#define MAX_AIOPS_PER_BOARD 4
131#define MAX_PORTS_PER_BOARD 32
132
69/* Bus Type ID */
70#define isISA 0
71#define isPCI 1
72#define isMC 2
73
74/* Controller ID numbers */
75#define CTLID_NULL -1 /* no controller exists */
76#define CTLID_0001 0x0001 /* controller release 1 */
77
133/* Controller ID numbers */
134#define CTLID_NULL -1 /* no controller exists */
135#define CTLID_0001 0x0001 /* controller release 1 */
136
78/* PCI IDs */
79#define RP_VENDOR_ID 0x11FE
80#define RP_DEVICE_ID_8OCTA 0x0001
81#define RP_DEVICE_ID_8INTF 0x0002
82#define RP_DEVICE_ID_16INTF 0x0003
83#define RP_DEVICE_ID_32INTF 0x0004
84
85/* AIOP ID numbers, identifies AIOP type implementing channel */
86#define AIOPID_NULL -1 /* no AIOP or channel exists */
87#define AIOPID_0001 0x0001 /* AIOP release 1 */
88
89#define NULLDEV -1 /* identifies non-existant device */
90#define NULLCTL -1 /* identifies non-existant controller */
91#define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */
92#define NULLAIOP -1 /* identifies non-existant AIOP */

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262#define INTSTAT0 0x01 /* AIOP 0 interrupt status */
263#define INTSTAT1 0x02 /* AIOP 1 interrupt status */
264#define INTSTAT2 0x04 /* AIOP 2 interrupt status */
265#define INTSTAT3 0x08 /* AIOP 3 interrupt status */
266
267#define INTR_EN 0x08 /* allow interrupts to host */
268#define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */
269
137/* AIOP ID numbers, identifies AIOP type implementing channel */
138#define AIOPID_NULL -1 /* no AIOP or channel exists */
139#define AIOPID_0001 0x0001 /* AIOP release 1 */
140
141#define NULLDEV -1 /* identifies non-existant device */
142#define NULLCTL -1 /* identifies non-existant controller */
143#define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */
144#define NULLAIOP -1 /* identifies non-existant AIOP */

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314#define INTSTAT0 0x01 /* AIOP 0 interrupt status */
315#define INTSTAT1 0x02 /* AIOP 1 interrupt status */
316#define INTSTAT2 0x04 /* AIOP 2 interrupt status */
317#define INTSTAT3 0x08 /* AIOP 3 interrupt status */
318
319#define INTR_EN 0x08 /* allow interrupts to host */
320#define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */
321
270/**************************************************************************
271 MUDBAC remapped for PCI
272**************************************************************************/
273
274#define _CFG_INT_PCI 0x40
275#define _PCI_INT_FUNC 0x3A
276
277#define PCI_STROB 0x2000
278#define INTR_EN_PCI 0x0010
279
280#define CHAN3_EN 0x08 /* enable AIOP 3 */
281#define CHAN2_EN 0x04 /* enable AIOP 2 */
282#define CHAN1_EN 0x02 /* enable AIOP 1 */
283#define CHAN0_EN 0x01 /* enable AIOP 0 */
284#define FREQ_DIS 0x00
285#define FREQ_274HZ 0x60
286#define FREQ_137HZ 0x50
287#define FREQ_69HZ 0x40
288#define FREQ_34HZ 0x30
289#define FREQ_17HZ 0x20
290#define FREQ_9HZ 0x10
291#define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */
292
293#define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
294
295#define RDATASIZE 72
296#define RREGDATASIZE 52
297
322#define CHAN3_EN 0x08 /* enable AIOP 3 */
323#define CHAN2_EN 0x04 /* enable AIOP 2 */
324#define CHAN1_EN 0x02 /* enable AIOP 1 */
325#define CHAN0_EN 0x01 /* enable AIOP 0 */
326#define FREQ_DIS 0x00
327#define FREQ_274HZ 0x60
328#define FREQ_137HZ 0x50
329#define FREQ_69HZ 0x40
330#define FREQ_34HZ 0x30
331#define FREQ_17HZ 0x20
332#define FREQ_9HZ 0x10
333#define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */
334
335#define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
336
337#define RDATASIZE 72
338#define RREGDATASIZE 52
339
340#ifndef TRUE
341#define TRUE 1
342#endif
343
344#ifndef FALSE
345#define FALSE 0
346#endif
347
348struct CONTROLLER_str;
349struct CHANNEL_str;
350
351/* The types of bus-specific methods */
352typedef int rp_aiop2rid_t(int, int);
353typedef int rp_aiop2off_t(int, int);
354typedef unsigned char rp_ctlmask_t(struct CONTROLLER_str *);
355
298/* Controller level information structure */
356/* Controller level information structure */
299typedef struct
357struct CONTROLLER_str
300{
301 int CtlID;
358{
359 int CtlID;
302 int CtlNum;
303 int BusType;
304 WordIO_t PCIIO;
305 ByteIO_t MBaseIO;
306 ByteIO_t MReg1IO;
307 ByteIO_t MReg2IO;
308 ByteIO_t MReg3IO;
309 Byte_t MReg2;
310 Byte_t MReg3;
311 int NumAiop;
360 int NumAiop;
312 WordIO_t AiopIO[AIOP_CTL_SIZE];
313 ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE];
314 int AiopID[AIOP_CTL_SIZE];
315 int AiopNumChan[AIOP_CTL_SIZE];
361 int AiopID[AIOP_CTL_SIZE];
362 int AiopNumChan[AIOP_CTL_SIZE];
316} CONTROLLER_T;
317
363
364 /* Device and resource management */
365 device_t dev; /* device */
366 int io_num; /* Number of IO resources */
367 int *io_rid; /* IO resource IDs */
368 struct resource **io; /* IO resources */
369
370 struct rp_port *rp; /* port */
371 struct tty *tty; /* tty */
372
373 /* Device nodes */
374 dev_t *dev_nodes;
375
376 /* Bus-specific properties */
377 void *bus_ctlp;
378
379 /* Bus-specific methods */
380 rp_aiop2rid_t *aiop2rid; /* (aiop, offset) -> rid */
381 rp_aiop2off_t *aiop2off; /* (aiop, offset) -> off */
382 rp_ctlmask_t *ctlmask; /* Int status */
383};
384typedef struct CONTROLLER_str CONTROLLER_T;
318typedef CONTROLLER_T CONTROLLER_t;
319
320/* Channel level information structure */
385typedef CONTROLLER_T CONTROLLER_t;
386
387/* Channel level information structure */
321typedef struct
388struct CHANNEL_str
322{
389{
323 CONTROLLER_T *CtlP;
390 CONTROLLER_t *CtlP;
324 int AiopNum;
325 int ChanID;
326 int ChanNum;
327
391 int AiopNum;
392 int ChanID;
393 int ChanNum;
394
328 ByteIO_t Cmd;
329 ByteIO_t IntChan;
330 ByteIO_t IntMask;
331 DWordIO_t IndexAddr;
332 WordIO_t IndexData;
333
334 WordIO_t TxRxData;
335 WordIO_t ChanStat;
336 WordIO_t TxRxCount;
337 ByteIO_t IntID;
338
339 Word_t TxFIFO;
340 Word_t TxFIFOPtrs;
341 Word_t RxFIFO;
342 Word_t RxFIFOPtrs;
343 Word_t TxPrioCnt;
344 Word_t TxPrioPtr;
345 Word_t TxPrioBuf;
346
347 Byte_t R[RREGDATASIZE];
348
349 Byte_t BaudDiv[4];
350 Byte_t TxControl[4];
351 Byte_t RxControl[4];
352 Byte_t TxEnables[4];
353 Byte_t TxCompare[4];
354 Byte_t TxReplace1[4];
355 Byte_t TxReplace2[4];
395 Word_t TxFIFO;
396 Word_t TxFIFOPtrs;
397 Word_t RxFIFO;
398 Word_t RxFIFOPtrs;
399 Word_t TxPrioCnt;
400 Word_t TxPrioPtr;
401 Word_t TxPrioBuf;
402
403 Byte_t R[RREGDATASIZE];
404
405 Byte_t BaudDiv[4];
406 Byte_t TxControl[4];
407 Byte_t RxControl[4];
408 Byte_t TxEnables[4];
409 Byte_t TxCompare[4];
410 Byte_t TxReplace1[4];
411 Byte_t TxReplace2[4];
356} CHANNEL_T;
412};
357
413
414typedef struct CHANNEL_str CHANNEL_T;
358typedef CHANNEL_T CHANNEL_t;
359typedef CHANNEL_T * CHANPTR_T;
360
415typedef CHANNEL_T CHANNEL_t;
416typedef CHANNEL_T * CHANPTR_T;
417
418#define CHNOFF_TXRXDATA(chp) ((chp)->ChanNum * 2 + _TD0)
419#define CHNOFF_CHANSTAT(chp) ((chp)->ChanNum * 2 + _CHN_STAT0)
420#define CHNOFF_TXRXCOUNT(chp) ((chp)->ChanNum * 2 + _FIFO_CNT0)
421#define CHNOFF_INTID(chp) ((chp)->ChanNum + _INT_ID0)
422
361/***************************************************************************
362Function: sClrBreak
363Purpose: Stop sending a transmit BREAK signal
364Call: sClrBreak(ChP)
365 CHANNEL_T *ChP; Ptr to channel structure
366*/
367#define sClrBreak(ChP) \
368{ \
369 (ChP)->TxControl[3] &= ~SETBREAK; \
423/***************************************************************************
424Function: sClrBreak
425Purpose: Stop sending a transmit BREAK signal
426Call: sClrBreak(ChP)
427 CHANNEL_T *ChP; Ptr to channel structure
428*/
429#define sClrBreak(ChP) \
430{ \
431 (ChP)->TxControl[3] &= ~SETBREAK; \
370 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
432 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
371}
372
373/***************************************************************************
374Function: sClrDTR
375Purpose: Clr the DTR output
376Call: sClrDTR(ChP)
377 CHANNEL_T *ChP; Ptr to channel structure
378*/
379#define sClrDTR(ChP) \
380{ \
381 (ChP)->TxControl[3] &= ~SET_DTR; \
433}
434
435/***************************************************************************
436Function: sClrDTR
437Purpose: Clr the DTR output
438Call: sClrDTR(ChP)
439 CHANNEL_T *ChP; Ptr to channel structure
440*/
441#define sClrDTR(ChP) \
442{ \
443 (ChP)->TxControl[3] &= ~SET_DTR; \
382 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
444 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
383}
384
385/***************************************************************************
386Function: sClrRTS
387Purpose: Clr the RTS output
388Call: sClrRTS(ChP)
389 CHANNEL_T *ChP; Ptr to channel structure
390*/
391#define sClrRTS(ChP) \
392{ \
393 (ChP)->TxControl[3] &= ~SET_RTS; \
445}
446
447/***************************************************************************
448Function: sClrRTS
449Purpose: Clr the RTS output
450Call: sClrRTS(ChP)
451 CHANNEL_T *ChP; Ptr to channel structure
452*/
453#define sClrRTS(ChP) \
454{ \
455 (ChP)->TxControl[3] &= ~SET_RTS; \
394 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
456 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
395}
396
397/***************************************************************************
398Function: sClrTxXOFF
399Purpose: Clear any existing transmit software flow control off condition
400Call: sClrTxXOFF(ChP)
401 CHANNEL_T *ChP; Ptr to channel structure
402*/
403#define sClrTxXOFF(ChP) \
404{ \
457}
458
459/***************************************************************************
460Function: sClrTxXOFF
461Purpose: Clear any existing transmit software flow control off condition
462Call: sClrTxXOFF(ChP)
463 CHANNEL_T *ChP; Ptr to channel structure
464*/
465#define sClrTxXOFF(ChP) \
466{ \
405 sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
406 sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \
467 rp_writech1(ChP,_CMD_REG,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
468 rp_writech1(ChP,_CMD_REG,(Byte_t)(ChP)->ChanNum); \
407}
408
409/***************************************************************************
469}
470
471/***************************************************************************
410Function: sCtlNumToCtlPtr
411Purpose: Convert a controller number to controller structure pointer
412Call: sCtlNumToCtlPtr(CtlNum)
413 int CtlNum; Controller number
414Return: CONTROLLER_T *: Ptr to controller structure
415*/
416#define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM]
417
418/***************************************************************************
419Function: sControllerEOI
420Purpose: Strobe the MUDBAC's End Of Interrupt bit.
421Call: sControllerEOI(CtlP)
422 CONTROLLER_T *CtlP; Ptr to controller structure
423*/
424#define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB)
425
426
427/***************************************************************************
428Function: sPCIControllerEOI
429Purpose: Strobe the MUDBAC's End Of Interrupt bit.
430Call: sPCIControllerEOI(CtlP)
431 CONTROLLER_T *CtlP; Ptr to controller structure
432*/
433#define sPCIControllerEOI(CTLP) sOutW((CTLP)->PCIIO, PCI_STROB)
434
435/***************************************************************************
436Function: sDisAiop
437Purpose: Disable I/O access to an AIOP
438Call: sDisAiop(CltP)
439 CONTROLLER_T *CtlP; Ptr to controller structure
440 int AiopNum; Number of AIOP on controller
441*/
442#define sDisAiop(CTLP,AIOPNUM) \
443{ \
444 (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \
445 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
446}
447
448/***************************************************************************
449Function: sDisCTSFlowCtl
450Purpose: Disable output flow control using CTS
451Call: sDisCTSFlowCtl(ChP)
452 CHANNEL_T *ChP; Ptr to channel structure
453*/
454#define sDisCTSFlowCtl(ChP) \
455{ \
456 (ChP)->TxControl[2] &= ~CTSFC_EN; \
472Function: sDisCTSFlowCtl
473Purpose: Disable output flow control using CTS
474Call: sDisCTSFlowCtl(ChP)
475 CHANNEL_T *ChP; Ptr to channel structure
476*/
477#define sDisCTSFlowCtl(ChP) \
478{ \
479 (ChP)->TxControl[2] &= ~CTSFC_EN; \
457 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
480 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
458}
459
460/***************************************************************************
461Function: DisParity
462Purpose: Disable parity
463Call: sDisParity(ChP)
464 CHANNEL_T *ChP; Ptr to channel structure
465Comments: Function sSetParity() can be used in place of functions sEnParity(),
466 sDisParity(), sSetOddParity(), and sSetEvenParity().
467*/
468#define sDisParity(ChP) \
469{ \
470 (ChP)->TxControl[2] &= ~PARITY_EN; \
481}
482
483/***************************************************************************
484Function: DisParity
485Purpose: Disable parity
486Call: sDisParity(ChP)
487 CHANNEL_T *ChP; Ptr to channel structure
488Comments: Function sSetParity() can be used in place of functions sEnParity(),
489 sDisParity(), sSetOddParity(), and sSetEvenParity().
490*/
491#define sDisParity(ChP) \
492{ \
493 (ChP)->TxControl[2] &= ~PARITY_EN; \
471 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
494 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
472}
473
474/***************************************************************************
475Function: sDisRxFIFO
476Purpose: Disable Rx FIFO
477Call: sDisRxFIFO(ChP)
478 CHANNEL_T *ChP; Ptr to channel structure
479*/
480#define sDisRxFIFO(ChP) \
481{ \
482 (ChP)->R[0x32] = 0x0a; \
495}
496
497/***************************************************************************
498Function: sDisRxFIFO
499Purpose: Disable Rx FIFO
500Call: sDisRxFIFO(ChP)
501 CHANNEL_T *ChP; Ptr to channel structure
502*/
503#define sDisRxFIFO(ChP) \
504{ \
505 (ChP)->R[0x32] = 0x0a; \
483 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
506 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0x30]); \
484}
485
486/***************************************************************************
487Function: sDisRxStatusMode
488Purpose: Disable the Rx status mode
489Call: sDisRxStatusMode(ChP)
490 CHANNEL_T *ChP; Ptr to channel structure
491Comments: This takes the channel out of the receive status mode. All
492 subsequent reads of receive data using sReadRxWord() will return
493 two data bytes.
494*/
507}
508
509/***************************************************************************
510Function: sDisRxStatusMode
511Purpose: Disable the Rx status mode
512Call: sDisRxStatusMode(ChP)
513 CHANNEL_T *ChP; Ptr to channel structure
514Comments: This takes the channel out of the receive status mode. All
515 subsequent reads of receive data using sReadRxWord() will return
516 two data bytes.
517*/
495#define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0)
518#define sDisRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),0)
496
497/***************************************************************************
498Function: sDisTransmit
499Purpose: Disable transmit
500Call: sDisTransmit(ChP)
501 CHANNEL_T *ChP; Ptr to channel structure
502 This disables movement of Tx data from the Tx FIFO into the 1 byte
503 Tx buffer. Therefore there could be up to a 2 byte latency
504 between the time sDisTransmit() is called and the transmit buffer
505 and transmit shift register going completely empty.
506*/
507#define sDisTransmit(ChP) \
508{ \
509 (ChP)->TxControl[3] &= ~TX_ENABLE; \
519
520/***************************************************************************
521Function: sDisTransmit
522Purpose: Disable transmit
523Call: sDisTransmit(ChP)
524 CHANNEL_T *ChP; Ptr to channel structure
525 This disables movement of Tx data from the Tx FIFO into the 1 byte
526 Tx buffer. Therefore there could be up to a 2 byte latency
527 between the time sDisTransmit() is called and the transmit buffer
528 and transmit shift register going completely empty.
529*/
530#define sDisTransmit(ChP) \
531{ \
532 (ChP)->TxControl[3] &= ~TX_ENABLE; \
510 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
533 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
511}
512
513/***************************************************************************
514Function: sDisTxSoftFlowCtl
515Purpose: Disable Tx Software Flow Control
516Call: sDisTxSoftFlowCtl(ChP)
517 CHANNEL_T *ChP; Ptr to channel structure
518*/
519#define sDisTxSoftFlowCtl(ChP) \
520{ \
521 (ChP)->R[0x06] = 0x8a; \
534}
535
536/***************************************************************************
537Function: sDisTxSoftFlowCtl
538Purpose: Disable Tx Software Flow Control
539Call: sDisTxSoftFlowCtl(ChP)
540 CHANNEL_T *ChP; Ptr to channel structure
541*/
542#define sDisTxSoftFlowCtl(ChP) \
543{ \
544 (ChP)->R[0x06] = 0x8a; \
522 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
545 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0x04]); \
523}
524
525/***************************************************************************
546}
547
548/***************************************************************************
526Function: sEnAiop
527Purpose: Enable I/O access to an AIOP
528Call: sEnAiop(CltP)
529 CONTROLLER_T *CtlP; Ptr to controller structure
530 int AiopNum; Number of AIOP on controller
531*/
532#define sEnAiop(CTLP,AIOPNUM) \
533{ \
534 (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \
535 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
536}
537
538/***************************************************************************
539Function: sEnCTSFlowCtl
540Purpose: Enable output flow control using CTS
541Call: sEnCTSFlowCtl(ChP)
542 CHANNEL_T *ChP; Ptr to channel structure
543*/
544#define sEnCTSFlowCtl(ChP) \
545{ \
546 (ChP)->TxControl[2] |= CTSFC_EN; \
549Function: sEnCTSFlowCtl
550Purpose: Enable output flow control using CTS
551Call: sEnCTSFlowCtl(ChP)
552 CHANNEL_T *ChP; Ptr to channel structure
553*/
554#define sEnCTSFlowCtl(ChP) \
555{ \
556 (ChP)->TxControl[2] |= CTSFC_EN; \
547 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
557 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
548}
549
550/***************************************************************************
551Function: EnParity
552Purpose: Enable parity
553Call: sEnParity(ChP)
554 CHANNEL_T *ChP; Ptr to channel structure
555Comments: Function sSetParity() can be used in place of functions sEnParity(),
556 sDisParity(), sSetOddParity(), and sSetEvenParity().
557
558Warnings: Before enabling parity odd or even parity should be chosen using
559 functions sSetOddParity() or sSetEvenParity().
560*/
561#define sEnParity(ChP) \
562{ \
563 (ChP)->TxControl[2] |= PARITY_EN; \
558}
559
560/***************************************************************************
561Function: EnParity
562Purpose: Enable parity
563Call: sEnParity(ChP)
564 CHANNEL_T *ChP; Ptr to channel structure
565Comments: Function sSetParity() can be used in place of functions sEnParity(),
566 sDisParity(), sSetOddParity(), and sSetEvenParity().
567
568Warnings: Before enabling parity odd or even parity should be chosen using
569 functions sSetOddParity() or sSetEvenParity().
570*/
571#define sEnParity(ChP) \
572{ \
573 (ChP)->TxControl[2] |= PARITY_EN; \
564 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
574 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
565}
566
567/***************************************************************************
568Function: sEnRTSFlowCtl
569Return: void
570*/
571#define sEnRTSFlowCtl(ChP) \
572{ \
573 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
574 (ChP)->TxControl[3] &= ~SET_RTS; \
575}
576
577/***************************************************************************
578Function: sEnRTSFlowCtl
579Return: void
580*/
581#define sEnRTSFlowCtl(ChP) \
582{ \
583 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
584 (ChP)->TxControl[3] &= ~SET_RTS; \
575 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
585 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
576 (ChP)->RxControl[2] |= RTSFC_EN; \
586 (ChP)->RxControl[2] |= RTSFC_EN; \
577 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
587 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
578}
579
580/***************************************************************************
581Function: sDisRTSFlowCtl
582Return: void
583*/
584#define sDisRTSFlowCtl(ChP) \
585{ \
586 (ChP)->RxControl[2] &= ~RTSFC_EN; \
588}
589
590/***************************************************************************
591Function: sDisRTSFlowCtl
592Return: void
593*/
594#define sDisRTSFlowCtl(ChP) \
595{ \
596 (ChP)->RxControl[2] &= ~RTSFC_EN; \
587 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
597 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
588}
589
590/***************************************************************************
591Function: sEnRxFIFO
592Purpose: Enable Rx FIFO
593Call: sEnRxFIFO(ChP)
594 CHANNEL_T *ChP; Ptr to channel structure
595*/
596#define sEnRxFIFO(ChP) \
597{ \
598 (ChP)->R[0x32] = 0x08; \
598}
599
600/***************************************************************************
601Function: sEnRxFIFO
602Purpose: Enable Rx FIFO
603Call: sEnRxFIFO(ChP)
604 CHANNEL_T *ChP; Ptr to channel structure
605*/
606#define sEnRxFIFO(ChP) \
607{ \
608 (ChP)->R[0x32] = 0x08; \
599 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
609 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0x30]); \
600}
601
602/***************************************************************************
603Function: sEnRxProcessor
604Purpose: Enable the receive processor
605Call: sEnRxProcessor(ChP)
606 CHANNEL_T *ChP; Ptr to channel structure
607Comments: This function is used to start the receive processor. When

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612
613Warnings: This function must be called after valid microcode has been
614 downloaded to the AIOP, and it must not be called before the
615 microcode has been downloaded.
616*/
617#define sEnRxProcessor(ChP) \
618{ \
619 (ChP)->RxControl[2] |= RXPROC_EN; \
610}
611
612/***************************************************************************
613Function: sEnRxProcessor
614Purpose: Enable the receive processor
615Call: sEnRxProcessor(ChP)
616 CHANNEL_T *ChP; Ptr to channel structure
617Comments: This function is used to start the receive processor. When

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622
623Warnings: This function must be called after valid microcode has been
624 downloaded to the AIOP, and it must not be called before the
625 microcode has been downloaded.
626*/
627#define sEnRxProcessor(ChP) \
628{ \
629 (ChP)->RxControl[2] |= RXPROC_EN; \
620 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
630 rp_writech2(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
621}
622
623/***************************************************************************
624Function: sEnRxStatusMode
625Purpose: Enable the Rx status mode
626Call: sEnRxStatusMode(ChP)
627 CHANNEL_T *ChP; Ptr to channel structure
628Comments: This places the channel in the receive status mode. All subsequent
629 reads of receive data using sReadRxWord() will return a data byte
630 in the low word and a status byte in the high word.
631
632*/
631}
632
633/***************************************************************************
634Function: sEnRxStatusMode
635Purpose: Enable the Rx status mode
636Call: sEnRxStatusMode(ChP)
637 CHANNEL_T *ChP; Ptr to channel structure
638Comments: This places the channel in the receive status mode. All subsequent
639 reads of receive data using sReadRxWord() will return a data byte
640 in the low word and a status byte in the high word.
641
642*/
633#define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE)
643#define sEnRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),STATMODE)
634
635/***************************************************************************
636Function: sEnTransmit
637Purpose: Enable transmit
638Call: sEnTransmit(ChP)
639 CHANNEL_T *ChP; Ptr to channel structure
640*/
641#define sEnTransmit(ChP) \
642{ \
643 (ChP)->TxControl[3] |= TX_ENABLE; \
644
645/***************************************************************************
646Function: sEnTransmit
647Purpose: Enable transmit
648Call: sEnTransmit(ChP)
649 CHANNEL_T *ChP; Ptr to channel structure
650*/
651#define sEnTransmit(ChP) \
652{ \
653 (ChP)->TxControl[3] |= TX_ENABLE; \
644 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
654 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
645}
646
647/***************************************************************************
648Function: sGetAiopIntStatus
649Purpose: Get the AIOP interrupt status
650Call: sGetAiopIntStatus(CtlP,AiopNum)
651 CONTROLLER_T *CtlP; Ptr to controller structure
652 int AiopNum; AIOP number
653Return: Byte_t: The AIOP interrupt status. Bits 0 through 7
654 represent channels 0 through 7 respectively. If a
655 bit is set that channel is interrupting.
656*/
655}
656
657/***************************************************************************
658Function: sGetAiopIntStatus
659Purpose: Get the AIOP interrupt status
660Call: sGetAiopIntStatus(CtlP,AiopNum)
661 CONTROLLER_T *CtlP; Ptr to controller structure
662 int AiopNum; AIOP number
663Return: Byte_t: The AIOP interrupt status. Bits 0 through 7
664 represent channels 0 through 7 respectively. If a
665 bit is set that channel is interrupting.
666*/
657#define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM])
667#define sGetAiopIntStatus(CtlP,AIOPNUM) rp_readaiop1(CtlP,AIOPNUM,_INT_CHAN)
658
659/***************************************************************************
660Function: sGetAiopNumChan
661Purpose: Get the number of channels supported by an AIOP
662Call: sGetAiopNumChan(CtlP,AiopNum)
663 CONTROLLER_T *CtlP; Ptr to controller structure
664 int AiopNum; AIOP number
665Return: int: The number of channels supported by the AIOP
666*/
668
669/***************************************************************************
670Function: sGetAiopNumChan
671Purpose: Get the number of channels supported by an AIOP
672Call: sGetAiopNumChan(CtlP,AiopNum)
673 CONTROLLER_T *CtlP; Ptr to controller structure
674 int AiopNum; AIOP number
675Return: int: The number of channels supported by the AIOP
676*/
667#define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM]
677#define sGetAiopNumChan(CtlP,AIOPNUM) CtlP->AiopNumChan[AIOPNUM]
668
669/***************************************************************************
670Function: sGetChanIntID
671Purpose: Get a channel's interrupt identification byte
672Call: sGetChanIntID(ChP)
673 CHANNEL_T *ChP; Ptr to channel structure
674Return: Byte_t: The channel interrupt ID. Can be any
675 combination of the following flags:
676 RXF_TRIG: Rx FIFO trigger level interrupt
677 TXFIFO_MT: Tx FIFO empty interrupt
678 SRC_INT: Special receive condition interrupt
679 DELTA_CD: CD change interrupt
680 DELTA_CTS: CTS change interrupt
681 DELTA_DSR: DSR change interrupt
682*/
678
679/***************************************************************************
680Function: sGetChanIntID
681Purpose: Get a channel's interrupt identification byte
682Call: sGetChanIntID(ChP)
683 CHANNEL_T *ChP; Ptr to channel structure
684Return: Byte_t: The channel interrupt ID. Can be any
685 combination of the following flags:
686 RXF_TRIG: Rx FIFO trigger level interrupt
687 TXFIFO_MT: Tx FIFO empty interrupt
688 SRC_INT: Special receive condition interrupt
689 DELTA_CD: CD change interrupt
690 DELTA_CTS: CTS change interrupt
691 DELTA_DSR: DSR change interrupt
692*/
683#define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
693#define sGetChanIntID(ChP) (rp_readch1(ChP,(ChP)->ChanNum+_INT_ID0) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
684
685/***************************************************************************
686Function: sGetChanNum
687Purpose: Get the number of a channel within an AIOP
688Call: sGetChanNum(ChP)
689 CHANNEL_T *ChP; Ptr to channel structure
690Return: int: Channel number within AIOP, or NULLCHAN if channel does
691 not exist.

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713 RX2MATCH: receive compare byte 2 match
714 RX1MATCH: receive compare byte 1 match
715 RXBREAK: received BREAK
716 RXFRAME: received framing error
717 RXPARITY: received parity error
718Warnings: This function will clear the high byte flags in the Channel
719 Status Register.
720*/
694
695/***************************************************************************
696Function: sGetChanNum
697Purpose: Get the number of a channel within an AIOP
698Call: sGetChanNum(ChP)
699 CHANNEL_T *ChP; Ptr to channel structure
700Return: int: Channel number within AIOP, or NULLCHAN if channel does
701 not exist.

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723 RX2MATCH: receive compare byte 2 match
724 RX1MATCH: receive compare byte 1 match
725 RXBREAK: received BREAK
726 RXFRAME: received framing error
727 RXPARITY: received parity error
728Warnings: This function will clear the high byte flags in the Channel
729 Status Register.
730*/
721#define sGetChanStatus(ChP) sInW((ChP)->ChanStat)
731#define sGetChanStatus(ChP) rp_readch2(ChP,CHNOFF_CHANSTAT(ChP))
722
723/***************************************************************************
724Function: sGetChanStatusLo
725Purpose: Get the low byte only of the channel status
726Call: sGetChanStatusLo(ChP)
727 CHANNEL_T *ChP; Ptr to channel structure
728Return: Byte_t: The channel status low byte. Can be any combination
729 of the following flags:
730 CTS_ACT: CTS input asserted
731 DSR_ACT: DSR input asserted
732 CD_ACT: CD input asserted
733 TXFIFOMT: Tx FIFO is empty
734 TXSHRMT: Tx shift register is empty
735 RDA: Rx data available
736*/
732
733/***************************************************************************
734Function: sGetChanStatusLo
735Purpose: Get the low byte only of the channel status
736Call: sGetChanStatusLo(ChP)
737 CHANNEL_T *ChP; Ptr to channel structure
738Return: Byte_t: The channel status low byte. Can be any combination
739 of the following flags:
740 CTS_ACT: CTS input asserted
741 DSR_ACT: DSR input asserted
742 CD_ACT: CD input asserted
743 TXFIFOMT: Tx FIFO is empty
744 TXSHRMT: Tx shift register is empty
745 RDA: Rx data available
746*/
737#define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat)
747#define sGetChanStatusLo(ChP) rp_readch1(ChP,CHNOFF_CHANSTAT(ChP))
738
739/***************************************************************************
748
749/***************************************************************************
740Function: sGetControllerIntStatus
741Purpose: Get the controller interrupt status
742Call: sGetControllerIntStatus(CtlP)
743 CONTROLLER_T *CtlP; Ptr to controller structure
744Return: Byte_t: The controller interrupt status in the lower 4
745 bits. Bits 0 through 3 represent AIOP's 0
746 through 3 respectively. If a bit is set that
747 AIOP is interrupting. Bits 4 through 7 will
748 always be cleared.
749*/
750#define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f)
751
752/***************************************************************************
753Function: sPCIGetControllerIntStatus
754Purpose: Get the controller interrupt status
755Call: sPCIGetControllerIntStatus(CtlP)
756 CONTROLLER_T *CtlP; Ptr to controller structure
757Return: Byte_t: The controller interrupt status in the lower 4
758 bits. Bits 0 through 3 represent AIOP's 0
759 through 3 respectively. If a bit is set that
760 AIOP is interrupting. Bits 4 through 7 will
761 always be cleared.
762*/
763#define sPCIGetControllerIntStatus(CTLP) ((sInW((CTLP)->PCIIO) >> 8) & 0x1f)
764
765/***************************************************************************
766Function: sGetRxCnt
767Purpose: Get the number of data bytes in the Rx FIFO
768Call: sGetRxCnt(ChP)
769 CHANNEL_T *ChP; Ptr to channel structure
770Return: int: The number of data bytes in the Rx FIFO.
771Comments: Byte read of count register is required to obtain Rx count.
772
773*/
750Function: sGetRxCnt
751Purpose: Get the number of data bytes in the Rx FIFO
752Call: sGetRxCnt(ChP)
753 CHANNEL_T *ChP; Ptr to channel structure
754Return: int: The number of data bytes in the Rx FIFO.
755Comments: Byte read of count register is required to obtain Rx count.
756
757*/
774#define sGetRxCnt(ChP) sInW((ChP)->TxRxCount)
758#define sGetRxCnt(ChP) rp_readch2(ChP,CHNOFF_TXRXCOUNT(ChP))
775
776/***************************************************************************
777Function: sGetTxCnt
778Purpose: Get the number of data bytes in the Tx FIFO
779Call: sGetTxCnt(ChP)
780 CHANNEL_T *ChP; Ptr to channel structure
781Return: Byte_t: The number of data bytes in the Tx FIFO.
782Comments: Byte read of count register is required to obtain Tx count.
783
784*/
759
760/***************************************************************************
761Function: sGetTxCnt
762Purpose: Get the number of data bytes in the Tx FIFO
763Call: sGetTxCnt(ChP)
764 CHANNEL_T *ChP; Ptr to channel structure
765Return: Byte_t: The number of data bytes in the Tx FIFO.
766Comments: Byte read of count register is required to obtain Tx count.
767
768*/
785#define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount)
769#define sGetTxCnt(ChP) rp_readch1(ChP,CHNOFF_TXRXCOUNT(ChP))
786
787/*****************************************************************************
788Function: sGetTxRxDataIO
770
771/*****************************************************************************
772Function: sGetTxRxDataIO
789Purpose: Get the I/O address of a channel's TxRx Data register
773Purpose: Get the offset of a channel's TxRx Data register
790Call: sGetTxRxDataIO(ChP)
791 CHANNEL_T *ChP; Ptr to channel structure
774Call: sGetTxRxDataIO(ChP)
775 CHANNEL_T *ChP; Ptr to channel structure
792Return: WordIO_t: I/O address of a channel's TxRx Data register
776Return: WordIO_t: offset of a channel's TxRx Data register
793*/
777*/
794#define sGetTxRxDataIO(ChP) (ChP)->TxRxData
778#define sGetTxRxDataIO(ChP) CHNOFF_TXRXDATA(ChP)
795
796/***************************************************************************
797Function: sInitChanDefaults
798Purpose: Initialize a channel structure to its default state.
799Call: sInitChanDefaults(ChP)
800 CHANNEL_T *ChP; Ptr to the channel structure
801Comments: This function must be called once for every channel structure
802 that exists before any other SSCI calls can be made.

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814Function: sResetAiopByNum
815Purpose: Reset the AIOP by number
816Call: sResetAiopByNum(CTLP,AIOPNUM)
817 CONTROLLER_T CTLP; Ptr to controller structure
818 AIOPNUM; AIOP index
819*/
820#define sResetAiopByNum(CTLP,AIOPNUM) \
821{ \
779
780/***************************************************************************
781Function: sInitChanDefaults
782Purpose: Initialize a channel structure to its default state.
783Call: sInitChanDefaults(ChP)
784 CHANNEL_T *ChP; Ptr to the channel structure
785Comments: This function must be called once for every channel structure
786 that exists before any other SSCI calls can be made.

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798Function: sResetAiopByNum
799Purpose: Reset the AIOP by number
800Call: sResetAiopByNum(CTLP,AIOPNUM)
801 CONTROLLER_T CTLP; Ptr to controller structure
802 AIOPNUM; AIOP index
803*/
804#define sResetAiopByNum(CTLP,AIOPNUM) \
805{ \
822 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \
823 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \
806 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,RESET_ALL); \
807 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,0x0); \
824}
825
826/***************************************************************************
827Function: sSendBreak
828Purpose: Send a transmit BREAK signal
829Call: sSendBreak(ChP)
830 CHANNEL_T *ChP; Ptr to channel structure
831*/
832#define sSendBreak(ChP) \
833{ \
834 (ChP)->TxControl[3] |= SETBREAK; \
808}
809
810/***************************************************************************
811Function: sSendBreak
812Purpose: Send a transmit BREAK signal
813Call: sSendBreak(ChP)
814 CHANNEL_T *ChP; Ptr to channel structure
815*/
816#define sSendBreak(ChP) \
817{ \
818 (ChP)->TxControl[3] |= SETBREAK; \
835 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
819 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
836}
837
838/***************************************************************************
839Function: sSetBaud
840Purpose: Set baud rate
841Call: sSetBaud(ChP,Divisor)
842 CHANNEL_T *ChP; Ptr to channel structure
843 Word_t Divisor; 16 bit baud rate divisor for channel
844*/
845#define sSetBaud(ChP,DIVISOR) \
846{ \
847 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
848 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
820}
821
822/***************************************************************************
823Function: sSetBaud
824Purpose: Set baud rate
825Call: sSetBaud(ChP,Divisor)
826 CHANNEL_T *ChP; Ptr to channel structure
827 Word_t Divisor; 16 bit baud rate divisor for channel
828*/
829#define sSetBaud(ChP,DIVISOR) \
830{ \
831 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
832 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
849 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \
833 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->BaudDiv[0]); \
850}
851
852/***************************************************************************
853Function: sSetData7
854Purpose: Set data bits to 7
855Call: sSetData7(ChP)
856 CHANNEL_T *ChP; Ptr to channel structure
857*/
858#define sSetData7(ChP) \
859{ \
860 (ChP)->TxControl[2] &= ~DATA8BIT; \
834}
835
836/***************************************************************************
837Function: sSetData7
838Purpose: Set data bits to 7
839Call: sSetData7(ChP)
840 CHANNEL_T *ChP; Ptr to channel structure
841*/
842#define sSetData7(ChP) \
843{ \
844 (ChP)->TxControl[2] &= ~DATA8BIT; \
861 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
845 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
862}
863
864/***************************************************************************
865Function: sSetData8
866Purpose: Set data bits to 8
867Call: sSetData8(ChP)
868 CHANNEL_T *ChP; Ptr to channel structure
869*/
870#define sSetData8(ChP) \
871{ \
872 (ChP)->TxControl[2] |= DATA8BIT; \
846}
847
848/***************************************************************************
849Function: sSetData8
850Purpose: Set data bits to 8
851Call: sSetData8(ChP)
852 CHANNEL_T *ChP; Ptr to channel structure
853*/
854#define sSetData8(ChP) \
855{ \
856 (ChP)->TxControl[2] |= DATA8BIT; \
873 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
857 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
874}
875
876/***************************************************************************
877Function: sSetDTR
878Purpose: Set the DTR output
879Call: sSetDTR(ChP)
880 CHANNEL_T *ChP; Ptr to channel structure
881*/
882#define sSetDTR(ChP) \
883{ \
884 (ChP)->TxControl[3] |= SET_DTR; \
858}
859
860/***************************************************************************
861Function: sSetDTR
862Purpose: Set the DTR output
863Call: sSetDTR(ChP)
864 CHANNEL_T *ChP; Ptr to channel structure
865*/
866#define sSetDTR(ChP) \
867{ \
868 (ChP)->TxControl[3] |= SET_DTR; \
885 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
869 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
886}
887
888/***************************************************************************
889Function: sSetEvenParity
890Purpose: Set even parity
891Call: sSetEvenParity(ChP)
892 CHANNEL_T *ChP; Ptr to channel structure
893Comments: Function sSetParity() can be used in place of functions sEnParity(),
894 sDisParity(), sSetOddParity(), and sSetEvenParity().
895
896Warnings: This function has no effect unless parity is enabled with function
897 sEnParity().
898*/
899#define sSetEvenParity(ChP) \
900{ \
901 (ChP)->TxControl[2] |= EVEN_PAR; \
870}
871
872/***************************************************************************
873Function: sSetEvenParity
874Purpose: Set even parity
875Call: sSetEvenParity(ChP)
876 CHANNEL_T *ChP; Ptr to channel structure
877Comments: Function sSetParity() can be used in place of functions sEnParity(),
878 sDisParity(), sSetOddParity(), and sSetEvenParity().
879
880Warnings: This function has no effect unless parity is enabled with function
881 sEnParity().
882*/
883#define sSetEvenParity(ChP) \
884{ \
885 (ChP)->TxControl[2] |= EVEN_PAR; \
902 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
886 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
903}
904
905/***************************************************************************
906Function: sSetOddParity
907Purpose: Set odd parity
908Call: sSetOddParity(ChP)
909 CHANNEL_T *ChP; Ptr to channel structure
910Comments: Function sSetParity() can be used in place of functions sEnParity(),
911 sDisParity(), sSetOddParity(), and sSetEvenParity().
912
913Warnings: This function has no effect unless parity is enabled with function
914 sEnParity().
915*/
916#define sSetOddParity(ChP) \
917{ \
918 (ChP)->TxControl[2] &= ~EVEN_PAR; \
887}
888
889/***************************************************************************
890Function: sSetOddParity
891Purpose: Set odd parity
892Call: sSetOddParity(ChP)
893 CHANNEL_T *ChP; Ptr to channel structure
894Comments: Function sSetParity() can be used in place of functions sEnParity(),
895 sDisParity(), sSetOddParity(), and sSetEvenParity().
896
897Warnings: This function has no effect unless parity is enabled with function
898 sEnParity().
899*/
900#define sSetOddParity(ChP) \
901{ \
902 (ChP)->TxControl[2] &= ~EVEN_PAR; \
919 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
903 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
920}
921
922/***************************************************************************
923Function: sSetRTS
924Purpose: Set the RTS output
925Call: sSetRTS(ChP)
926 CHANNEL_T *ChP; Ptr to channel structure
927*/
928#define sSetRTS(ChP) \
929{ \
930 (ChP)->TxControl[3] |= SET_RTS; \
904}
905
906/***************************************************************************
907Function: sSetRTS
908Purpose: Set the RTS output
909Call: sSetRTS(ChP)
910 CHANNEL_T *ChP; Ptr to channel structure
911*/
912#define sSetRTS(ChP) \
913{ \
914 (ChP)->TxControl[3] |= SET_RTS; \
931 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
915 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
932}
933
934/***************************************************************************
935Function: sSetRxTrigger
936Purpose: Set the Rx FIFO trigger level
937Call: sSetRxProcessor(ChP,Level)
938 CHANNEL_T *ChP; Ptr to channel structure
939 Byte_t Level; Number of characters in Rx FIFO at which the

--- 9 unchanged lines hidden (view full) ---

949 register will be set whenever the trigger level is reached
950 regardless of the setting of RXINT_EN.
951
952*/
953#define sSetRxTrigger(ChP,LEVEL) \
954{ \
955 (ChP)->RxControl[2] &= ~TRIG_MASK; \
956 (ChP)->RxControl[2] |= LEVEL; \
916}
917
918/***************************************************************************
919Function: sSetRxTrigger
920Purpose: Set the Rx FIFO trigger level
921Call: sSetRxProcessor(ChP,Level)
922 CHANNEL_T *ChP; Ptr to channel structure
923 Byte_t Level; Number of characters in Rx FIFO at which the

--- 9 unchanged lines hidden (view full) ---

933 register will be set whenever the trigger level is reached
934 regardless of the setting of RXINT_EN.
935
936*/
937#define sSetRxTrigger(ChP,LEVEL) \
938{ \
939 (ChP)->RxControl[2] &= ~TRIG_MASK; \
940 (ChP)->RxControl[2] |= LEVEL; \
957 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
941 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->RxControl[0]); \
958}
959
960/***************************************************************************
961Function: sSetStop1
962Purpose: Set stop bits to 1
963Call: sSetStop1(ChP)
964 CHANNEL_T *ChP; Ptr to channel structure
965*/
966#define sSetStop1(ChP) \
967{ \
968 (ChP)->TxControl[2] &= ~STOP2; \
942}
943
944/***************************************************************************
945Function: sSetStop1
946Purpose: Set stop bits to 1
947Call: sSetStop1(ChP)
948 CHANNEL_T *ChP; Ptr to channel structure
949*/
950#define sSetStop1(ChP) \
951{ \
952 (ChP)->TxControl[2] &= ~STOP2; \
969 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
953 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
970}
971
972/***************************************************************************
973Function: sSetStop2
974Purpose: Set stop bits to 2
975Call: sSetStop2(ChP)
976 CHANNEL_T *ChP; Ptr to channel structure
977*/
978#define sSetStop2(ChP) \
979{ \
980 (ChP)->TxControl[2] |= STOP2; \
954}
955
956/***************************************************************************
957Function: sSetStop2
958Purpose: Set stop bits to 2
959Call: sSetStop2(ChP)
960 CHANNEL_T *ChP; Ptr to channel structure
961*/
962#define sSetStop2(ChP) \
963{ \
964 (ChP)->TxControl[2] |= STOP2; \
981 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
965 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->TxControl[0]); \
982}
983
984/***************************************************************************
985Function: sStartRxProcessor
986Purpose: Start a channel's receive processor
987Call: sStartRxProcessor(ChP)
988 CHANNEL_T *ChP; Ptr to channel structure
989Comments: This function is used to start a Rx processor after it was
990 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It
991 will restart both the Rx processor and software input flow control.
992
993*/
966}
967
968/***************************************************************************
969Function: sStartRxProcessor
970Purpose: Start a channel's receive processor
971Call: sStartRxProcessor(ChP)
972 CHANNEL_T *ChP; Ptr to channel structure
973Comments: This function is used to start a Rx processor after it was
974 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It
975 will restart both the Rx processor and software input flow control.
976
977*/
994#define sStartRxProcessor(ChP) sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0])
978#define sStartRxProcessor(ChP) rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&(ChP)->R[0])
995
996/***************************************************************************
997Function: sWriteTxByte
998Purpose: Write a transmit data byte to a channel.
979
980/***************************************************************************
981Function: sWriteTxByte
982Purpose: Write a transmit data byte to a channel.
983 CHANNEL_T *ChP; Ptr to channel structure
999 ByteIO_t io: Channel transmit register I/O address. This can
1000 be obtained with sGetTxRxDataIO().
1001 Byte_t Data; The transmit data byte.
1002Warnings: This function writes the data byte without checking to see if
1003 sMaxTxSize is exceeded in the Tx FIFO.
1004*/
984 ByteIO_t io: Channel transmit register I/O address. This can
985 be obtained with sGetTxRxDataIO().
986 Byte_t Data; The transmit data byte.
987Warnings: This function writes the data byte without checking to see if
988 sMaxTxSize is exceeded in the Tx FIFO.
989*/
1005#define sWriteTxByte(IO,DATA) sOutB(IO,DATA)
990#define sWriteTxByte(ChP,IO,DATA) rp_writech1(ChP,IO,DATA)
1006
991
1007int sInitController( CONTROLLER_T *CtlP,
1008 int CtlNum,
1009 ByteIO_t MudbacIO,
1010 ByteIO_t *AiopIOList,
1011 int AiopIOListSize,
1012 int IRQNum,
1013 Byte_t Frequency,
1014 int PeriodicOnly);
1015
1016int sPCIInitController( CONTROLLER_T *CtlP,
1017 int CtlNum,
1018 ByteIO_t *AiopIOList,
1019 int AiopIOListSize,
1020 int IRQNum,
1021 Byte_t Frequency,
1022 int PeriodicOnly);
1023
1024int sReadAiopID(ByteIO_t io);
1025int sReadAiopNumChan(WordIO_t io);
992int sReadAiopID(CONTROLLER_T *CtlP, int aiop);
993int sReadAiopNumChan(CONTROLLER_T *CtlP, int aiop);
1026int sInitChan( CONTROLLER_T *CtlP,
1027 CHANNEL_T *ChP,
1028 int AiopNum,
1029 int ChanNum);
1030Byte_t sGetRxErrStatus(CHANNEL_T *ChP);
1031void sStopRxProcessor(CHANNEL_T *ChP);
1032void sStopSWInFlowCtl(CHANNEL_T *ChP);
1033void sFlushRxFIFO(CHANNEL_T *ChP);
1034void sFlushTxFIFO(CHANNEL_T *ChP);
1035int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data);
1036void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags);
1037void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags);
994int sInitChan( CONTROLLER_T *CtlP,
995 CHANNEL_T *ChP,
996 int AiopNum,
997 int ChanNum);
998Byte_t sGetRxErrStatus(CHANNEL_T *ChP);
999void sStopRxProcessor(CHANNEL_T *ChP);
1000void sStopSWInFlowCtl(CHANNEL_T *ChP);
1001void sFlushRxFIFO(CHANNEL_T *ChP);
1002void sFlushTxFIFO(CHANNEL_T *ChP);
1003int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data);
1004void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags);
1005void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags);
1006int rp_attachcommon(CONTROLLER_T *ctlp, int num_aiops, int num_ports);
1007void rp_releaseresource(CONTROLLER_t *ctlp);
1038
1039#ifndef ROCKET_C
1040extern Byte_t R[RDATASIZE];
1041extern CONTROLLER_T sController[CTL_SIZE];
1042extern Byte_t sIRQMap[16];
1008
1009#ifndef ROCKET_C
1010extern Byte_t R[RDATASIZE];
1011extern CONTROLLER_T sController[CTL_SIZE];
1012extern Byte_t sIRQMap[16];
1043extern Byte_t sBitMapClrTbl[8];
1044extern Byte_t sBitMapSetTbl[8];
1045#endif
1013#endif
1014extern Byte_t rp_sBitMapClrTbl[8];
1015extern Byte_t rp_sBitMapSetTbl[8];