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rp.c (61011) rp.c (61541)
1/*
2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted prodived that the follwoing conditions
7 * are met.
8 * 1. Redistributions of source code must retain the above copyright

--- 15 unchanged lines hidden (view full) ---

24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
1/*
2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted prodived that the follwoing conditions
7 * are met.
8 * 1. Redistributions of source code must retain the above copyright

--- 15 unchanged lines hidden (view full) ---

24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/dev/rp/rp.c 61011 2000-05-28 13:40:48Z peter $
32 * $FreeBSD: head/sys/dev/rp/rp.c 61541 2000-06-11 06:43:16Z tanimura $
33 */
34
35/*
36 * rp.c - for RocketPort FreeBSD
37 */
38
33 */
34
35/*
36 * rp.c - for RocketPort FreeBSD
37 */
38
39#include "opt_compat.h"
40
41#include <sys/param.h>
42#include <sys/systm.h>
39#include <sys/param.h>
40#include <sys/systm.h>
43#include <sys/kernel.h>
44#include <sys/fcntl.h>
45#include <sys/malloc.h>
46#include <sys/tty.h>
47#include <sys/proc.h>
41#include <sys/fcntl.h>
42#include <sys/malloc.h>
43#include <sys/tty.h>
44#include <sys/proc.h>
45#include <sys/dkstat.h>
48#include <sys/conf.h>
46#include <sys/conf.h>
47#include <sys/kernel.h>
48#include <machine/resource.h>
49#include <machine/bus.h>
49#include <sys/bus.h>
50#include <sys/bus.h>
51#include <sys/rman.h>
50
52
51#include <i386/isa/isa_device.h>
52
53#include <pci/pcivar.h>
54
55#define ROCKET_C
53#define ROCKET_C
56#include <i386/isa/rpreg.h>
57#include <i386/isa/rpvar.h>
54#include <dev/rp/rpreg.h>
55#include <dev/rp/rpvar.h>
58
56
59#ifndef TRUE
60#define TRUE 1
61#endif
57static const char RocketPortVersion[] = "3.02";
62
58
63#ifndef FALSE
64#define FALSE 0
65#endif
66
67static Byte_t RData[RDATASIZE] =
68{
69 0x00, 0x09, 0xf6, 0x82,
70 0x02, 0x09, 0x86, 0xfb,
71 0x04, 0x09, 0x00, 0x0a,
72 0x06, 0x09, 0x01, 0x0a,
73 0x08, 0x09, 0x8a, 0x13,
74 0x0a, 0x09, 0xc5, 0x11,

--- 23 unchanged lines hidden (view full) ---

98 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
99 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
100 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
101 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
102 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
103 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
104};
105
59static Byte_t RData[RDATASIZE] =
60{
61 0x00, 0x09, 0xf6, 0x82,
62 0x02, 0x09, 0x86, 0xfb,
63 0x04, 0x09, 0x00, 0x0a,
64 0x06, 0x09, 0x01, 0x0a,
65 0x08, 0x09, 0x8a, 0x13,
66 0x0a, 0x09, 0xc5, 0x11,

--- 23 unchanged lines hidden (view full) ---

90 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
91 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
92 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
93 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
94 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
95 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
96};
97
106static CONTROLLER_T sController[CTL_SIZE] =
107{
108 {-1,-1,0,0,0,0,0,0,0,0,0,{0,0,0,0},{0,0,0,0},{-1,-1,-1,-1},{0,0,0,0}},
109 {-1,-1,0,0,0,0,0,0,0,0,0,{0,0,0,0},{0,0,0,0},{-1,-1,-1,-1},{0,0,0,0}},
110 {-1,-1,0,0,0,0,0,0,0,0,0,{0,0,0,0},{0,0,0,0},{-1,-1,-1,-1},{0,0,0,0}},
111 {-1,-1,0,0,0,0,0,0,0,0,0,{0,0,0,0},{0,0,0,0},{-1,-1,-1,-1},{0,0,0,0}}
112};
113
114#if 0
115/* IRQ number to MUDBAC register 2 mapping */
116Byte_t sIRQMap[16] =
117{
118 0,0,0,0x10,0x20,0x30,0,0,0,0x40,0x50,0x60,0x70,0,0,0x80
119};
120#endif
121
98#if 0
99/* IRQ number to MUDBAC register 2 mapping */
100Byte_t sIRQMap[16] =
101{
102 0,0,0,0x10,0x20,0x30,0,0,0,0x40,0x50,0x60,0x70,0,0,0x80
103};
104#endif
105
122static Byte_t sBitMapClrTbl[8] =
106Byte_t rp_sBitMapClrTbl[8] =
123{
124 0xfe,0xfd,0xfb,0xf7,0xef,0xdf,0xbf,0x7f
125};
126
107{
108 0xfe,0xfd,0xfb,0xf7,0xef,0xdf,0xbf,0x7f
109};
110
127static Byte_t sBitMapSetTbl[8] =
111Byte_t rp_sBitMapSetTbl[8] =
128{
129 0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80
130};
131
112{
113 0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80
114};
115
132/***************************************************************************
133Function: sInitController
134Purpose: Initialization of controller global registers and controller
135 structure.
136Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
137 IRQNum,Frequency,PeriodicOnly)
138 CONTROLLER_T *CtlP; Ptr to controller structure
139 int CtlNum; Controller number
140 ByteIO_t MudbacIO; Mudbac base I/O address.
141 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
142 This list must be in the order the AIOPs will be found on the
143 controller. Once an AIOP in the list is not found, it is
144 assumed that there are no more AIOPs on the controller.
145 int AiopIOListSize; Number of addresses in AiopIOList
146 int IRQNum; Interrupt Request number. Can be any of the following:
147 0: Disable global interrupts
148 3: IRQ 3
149 4: IRQ 4
150 5: IRQ 5
151 9: IRQ 9
152 10: IRQ 10
153 11: IRQ 11
154 12: IRQ 12
155 15: IRQ 15
156 Byte_t Frequency: A flag identifying the frequency
157 of the periodic interrupt, can be any one of the following:
158 FREQ_DIS - periodic interrupt disabled
159 FREQ_137HZ - 137 Hertz
160 FREQ_69HZ - 69 Hertz
161 FREQ_34HZ - 34 Hertz
162 FREQ_17HZ - 17 Hertz
163 FREQ_9HZ - 9 Hertz
164 FREQ_4HZ - 4 Hertz
165 If IRQNum is set to 0 the Frequency parameter is
166 overidden, it is forced to a value of FREQ_DIS.
167 int PeriodicOnly: TRUE if all interrupts except the periodic
168 interrupt are to be blocked.
169 FALSE is both the periodic interrupt and
170 other channel interrupts are allowed.
171 If IRQNum is set to 0 the PeriodicOnly parameter is
172 overidden, it is forced to a value of FALSE.
173Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
174 initialization failed.
116struct termios deftermios = {
117 TTYDEF_IFLAG,
118 TTYDEF_OFLAG,
119 TTYDEF_CFLAG,
120 TTYDEF_LFLAG,
121 { CEOF, CEOL, CEOL, CERASE, CWERASE, CKILL, CREPRINT,
122 _POSIX_VDISABLE, CINTR, CQUIT, CSUSP, CDSUSP, CSTART, CSTOP, CLNEXT,
123 CDISCARD, CMIN, CTIME, CSTATUS, _POSIX_VDISABLE },
124 TTYDEF_SPEED,
125 TTYDEF_SPEED
126};
175
127
176Comments:
177 If periodic interrupts are to be disabled but AIOP interrupts
178 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to FALSE.
179
180 If interrupts are to be completely disabled set IRQNum to 0.
181
182 Setting Frequency to FREQ_DIS and PeriodicOnly to TRUE is an
183 invalid combination.
184
185 This function performs initialization of global interrupt modes,
186 but it does not actually enable global interrupts. To enable
187 and disable global interrupts use functions sEnGlobalInt() and
188 sDisGlobalInt(). Enabling of global interrupts is normally not
189 done until all other initializations are complete.
190
191 Even if interrupts are globally enabled, they must also be
192 individually enabled for each channel that is to generate
193 interrupts.
194
195Warnings: No range checking on any of the parameters is done.
196
197 No context switches are allowed while executing this function.
198
199 After this function all AIOPs on the controller are disabled,
200 they can be enabled with sEnAiop().
201*/
202int sInitController( CONTROLLER_T *CtlP,
203 int CtlNum,
204 ByteIO_t MudbacIO,
205 ByteIO_t *AiopIOList,
206 int AiopIOListSize,
207 int IRQNum,
208 Byte_t Frequency,
209 int PeriodicOnly)
210{
211 int i;
212 ByteIO_t io;
213
214 CtlP->CtlNum = CtlNum;
215 CtlP->BusType = isISA;
216 CtlP->CtlID = CTLID_0001; /* controller release 1 */
217
218 CtlP->MBaseIO = MudbacIO;
219 CtlP->MReg1IO = MudbacIO + 1;
220 CtlP->MReg2IO = MudbacIO + 2;
221 CtlP->MReg3IO = MudbacIO + 3;
222#if 1
223 CtlP->MReg2 = 0; /* interrupt disable */
224 CtlP->MReg3 = 0; /* no periodic interrupts */
225#else
226 if(sIRQMap[IRQNum] == 0) /* interrupts globally disabled */
227 {
228 CtlP->MReg2 = 0; /* interrupt disable */
229 CtlP->MReg3 = 0; /* no periodic interrupts */
230 }
231 else
232 {
233 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
234 CtlP->MReg3 = Frequency; /* set frequency */
235 if(PeriodicOnly) /* periodic interrupt only */
236 {
237 CtlP->MReg3 |= PERIODIC_ONLY;
238 }
239 }
240#endif
241 sOutB(CtlP->MReg2IO,CtlP->MReg2);
242 sOutB(CtlP->MReg3IO,CtlP->MReg3);
243 sControllerEOI(CtlP); /* clear EOI if warm init */
244
245 /* Init AIOPs */
246 CtlP->NumAiop = 0;
247 for(i=0; i < AiopIOListSize; i++)
248 {
249 io = AiopIOList[i];
250 CtlP->AiopIO[i] = (WordIO_t)io;
251 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
252 sOutB(CtlP->MReg2IO,CtlP->MReg2 | (i & 0x03)); /* AIOP index */
253 sOutB(MudbacIO,(Byte_t)(io >> 6)); /* set up AIOP I/O in MUDBAC */
254 sEnAiop(CtlP,i); /* enable the AIOP */
255
256 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
257 if(CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
258 {
259 sDisAiop(CtlP,i); /* disable AIOP */
260 break; /* done looking for AIOPs */
261 }
262
263 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t)io); /* num channels in AIOP */
264 sOutW((WordIO_t)io + _INDX_ADDR,_CLK_PRE); /* clock prescaler */
265 sOutB(io + _INDX_DATA,CLOCK_PRESC);
266 CtlP->NumAiop++; /* bump count of AIOPs */
267 sDisAiop(CtlP,i); /* disable AIOP */
268 }
269
270 if(CtlP->NumAiop == 0)
271 return(-1);
272 else
273 return(CtlP->NumAiop);
274}
275
276int sPCIInitController( CONTROLLER_T *CtlP,
277 int CtlNum,
278 ByteIO_t *AiopIOList,
279 int AiopIOListSize,
280 int IRQNum,
281 Byte_t Frequency,
282 int PeriodicOnly)
283{
284 int i;
285 ByteIO_t io;
286
287 CtlP->CtlNum = CtlNum;
288 CtlP->BusType = isPCI;
289 CtlP->CtlID = CTLID_0001; /* controller release 1 */
290 CtlP->PCIIO = (WordIO_t)((ByteIO_t)AiopIOList[0] + _PCI_INT_FUNC);
291
292 sPCIControllerEOI(CtlP);
293
294 /* Init AIOPs */
295 CtlP->NumAiop = 0;
296 for(i=0; i < AiopIOListSize; i++)
297 {
298 io = AiopIOList[i];
299 CtlP->AiopIO[i] = (WordIO_t)io;
300 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
301
302 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
303 if(CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
304 {
305 break; /* done looking for AIOPs */
306 }
307
308 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t)io); /* num channels in AIOP */
309 sOutW((WordIO_t)io + _INDX_ADDR,_CLK_PRE); /* clock prescaler */
310 sOutB(io + _INDX_DATA,CLOCK_PRESC);
311 CtlP->NumAiop++; /* bump count of AIOPs */
312 }
313
314 if(CtlP->NumAiop == 0)
315 return(-1);
316 else
317 return(CtlP->NumAiop);
318}
319
320/***************************************************************************
321Function: sReadAiopID
322Purpose: Read the AIOP idenfication number directly from an AIOP.
128/***************************************************************************
129Function: sReadAiopID
130Purpose: Read the AIOP idenfication number directly from an AIOP.
323Call: sReadAiopID(io)
324 ByteIO_t io: AIOP base I/O address
131Call: sReadAiopID(CtlP, aiop)
132 CONTROLLER_T *CtlP; Ptr to controller structure
133 int aiop: AIOP index
325Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
326 is replace by an identifying number.
327 Flag AIOPID_NULL if no valid AIOP is found
328Warnings: No context switches are allowed while executing this function.
329
330*/
134Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
135 is replace by an identifying number.
136 Flag AIOPID_NULL if no valid AIOP is found
137Warnings: No context switches are allowed while executing this function.
138
139*/
331int sReadAiopID(ByteIO_t io)
140int sReadAiopID(CONTROLLER_T *CtlP, int aiop)
332{
333 Byte_t AiopID; /* ID byte from AIOP */
334
141{
142 Byte_t AiopID; /* ID byte from AIOP */
143
335 sOutB(io + _CMD_REG,RESET_ALL); /* reset AIOP */
336 sOutB(io + _CMD_REG,0x0);
337 AiopID = sInB(io + _CHN_STAT0) & 0x07;
144 rp_writeaiop1(CtlP, aiop, _CMD_REG, RESET_ALL); /* reset AIOP */
145 rp_writeaiop1(CtlP, aiop, _CMD_REG, 0x0);
146 AiopID = rp_readaiop1(CtlP, aiop, _CHN_STAT0) & 0x07;
338 if(AiopID == 0x06)
339 return(1);
340 else /* AIOP does not exist */
341 return(-1);
342}
343
344/***************************************************************************
345Function: sReadAiopNumChan
346Purpose: Read the number of channels available in an AIOP directly from
347 an AIOP.
147 if(AiopID == 0x06)
148 return(1);
149 else /* AIOP does not exist */
150 return(-1);
151}
152
153/***************************************************************************
154Function: sReadAiopNumChan
155Purpose: Read the number of channels available in an AIOP directly from
156 an AIOP.
348Call: sReadAiopNumChan(io)
349 WordIO_t io: AIOP base I/O address
157Call: sReadAiopNumChan(CtlP, aiop)
158 CONTROLLER_T *CtlP; Ptr to controller structure
159 int aiop: AIOP index
350Return: int: The number of channels available
351Comments: The number of channels is determined by write/reads from identical
352 offsets within the SRAM address spaces for channels 0 and 4.
353 If the channel 4 space is mirrored to channel 0 it is a 4 channel
354 AIOP, otherwise it is an 8 channel.
355Warnings: No context switches are allowed while executing this function.
356*/
160Return: int: The number of channels available
161Comments: The number of channels is determined by write/reads from identical
162 offsets within the SRAM address spaces for channels 0 and 4.
163 If the channel 4 space is mirrored to channel 0 it is a 4 channel
164 AIOP, otherwise it is an 8 channel.
165Warnings: No context switches are allowed while executing this function.
166*/
357int sReadAiopNumChan(WordIO_t io)
167int sReadAiopNumChan(CONTROLLER_T *CtlP, int aiop)
358{
168{
359 Word_t x;
169 Word_t x, y;
360
170
361 sOutDW((DWordIO_t)io + _INDX_ADDR,0x12340000L); /* write to chan 0 SRAM */
362 sOutW(io + _INDX_ADDR,0); /* read from SRAM, chan 0 */
363 x = sInW(io + _INDX_DATA);
364 sOutW(io + _INDX_ADDR,0x4000); /* read from SRAM, chan 4 */
365 if(x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
171 rp_writeaiop4(CtlP, aiop, _INDX_ADDR,0x12340000L); /* write to chan 0 SRAM */
172 rp_writeaiop2(CtlP, aiop, _INDX_ADDR,0); /* read from SRAM, chan 0 */
173 x = rp_readaiop2(CtlP, aiop, _INDX_DATA);
174 rp_writeaiop2(CtlP, aiop, _INDX_ADDR,0x4000); /* read from SRAM, chan 4 */
175 y = rp_readaiop2(CtlP, aiop, _INDX_DATA);
176 if(x != y) /* if different must be 8 chan */
366 return(8);
367 else
368 return(4);
369}
370
371/***************************************************************************
372Function: sInitChan
373Purpose: Initialization of a channel and channel structure

--- 9 unchanged lines hidden (view full) ---

383
384 No context switches are allowed while executing this function.
385*/
386int sInitChan( CONTROLLER_T *CtlP,
387 CHANNEL_T *ChP,
388 int AiopNum,
389 int ChanNum)
390{
177 return(8);
178 else
179 return(4);
180}
181
182/***************************************************************************
183Function: sInitChan
184Purpose: Initialization of a channel and channel structure

--- 9 unchanged lines hidden (view full) ---

194
195 No context switches are allowed while executing this function.
196*/
197int sInitChan( CONTROLLER_T *CtlP,
198 CHANNEL_T *ChP,
199 int AiopNum,
200 int ChanNum)
201{
391 int i;
392 WordIO_t AiopIO;
393 WordIO_t ChIOOff;
202 int i, ChOff;
394 Byte_t *ChR;
203 Byte_t *ChR;
395 Word_t ChOff;
396 static Byte_t R[4];
397
398 if(ChanNum >= CtlP->AiopNumChan[AiopNum])
399 return(FALSE); /* exceeds num chans in AIOP */
400
401 /* Channel, AIOP, and controller identifiers */
402 ChP->CtlP = CtlP;
403 ChP->ChanID = CtlP->AiopID[AiopNum];
404 ChP->AiopNum = AiopNum;
405 ChP->ChanNum = ChanNum;
406
204 static Byte_t R[4];
205
206 if(ChanNum >= CtlP->AiopNumChan[AiopNum])
207 return(FALSE); /* exceeds num chans in AIOP */
208
209 /* Channel, AIOP, and controller identifiers */
210 ChP->CtlP = CtlP;
211 ChP->ChanID = CtlP->AiopID[AiopNum];
212 ChP->AiopNum = AiopNum;
213 ChP->ChanNum = ChanNum;
214
407 /* Global direct addresses */
408 AiopIO = CtlP->AiopIO[AiopNum];
409 ChP->Cmd = (ByteIO_t)AiopIO + _CMD_REG;
410 ChP->IntChan = (ByteIO_t)AiopIO + _INT_CHAN;
411 ChP->IntMask = (ByteIO_t)AiopIO + _INT_MASK;
412 ChP->IndexAddr = (DWordIO_t)AiopIO + _INDX_ADDR;
413 ChP->IndexData = AiopIO + _INDX_DATA;
414
415 /* Channel direct addresses */
416 ChIOOff = AiopIO + ChP->ChanNum * 2;
417 ChP->TxRxData = ChIOOff + _TD0;
418 ChP->ChanStat = ChIOOff + _CHN_STAT0;
419 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
420 ChP->IntID = (ByteIO_t)AiopIO + ChP->ChanNum + _INT_ID0;
421
422 /* Initialize the channel from the RData array */
423 for(i=0; i < RDATASIZE; i+=4)
424 {
425 R[0] = RData[i];
426 R[1] = RData[i+1] + 0x10 * ChanNum;
427 R[2] = RData[i+2];
428 R[3] = RData[i+3];
215 /* Initialize the channel from the RData array */
216 for(i=0; i < RDATASIZE; i+=4)
217 {
218 R[0] = RData[i];
219 R[1] = RData[i+1] + 0x10 * ChanNum;
220 R[2] = RData[i+2];
221 R[3] = RData[i+3];
429 sOutDW(ChP->IndexAddr,*((DWord_t *)&R[0]));
222 rp_writech4(ChP,_INDX_ADDR,*((DWord_t *)&R[0]));
430 }
431
432 ChR = ChP->R;
433 for(i=0; i < RREGDATASIZE; i+=4)
434 {
435 ChR[i] = RRegData[i];
436 ChR[i+1] = RRegData[i+1] + 0x10 * ChanNum;
437 ChR[i+2] = RRegData[i+2];
438 ChR[i+3] = RRegData[i+3];
439 }
440
441 /* Indexed registers */
442 ChOff = (Word_t)ChanNum * 0x1000;
443
444 ChP->BaudDiv[0] = (Byte_t)(ChOff + _BAUD);
445 ChP->BaudDiv[1] = (Byte_t)((ChOff + _BAUD) >> 8);
446 ChP->BaudDiv[2] = (Byte_t)BRD9600;
447 ChP->BaudDiv[3] = (Byte_t)(BRD9600 >> 8);
223 }
224
225 ChR = ChP->R;
226 for(i=0; i < RREGDATASIZE; i+=4)
227 {
228 ChR[i] = RRegData[i];
229 ChR[i+1] = RRegData[i+1] + 0x10 * ChanNum;
230 ChR[i+2] = RRegData[i+2];
231 ChR[i+3] = RRegData[i+3];
232 }
233
234 /* Indexed registers */
235 ChOff = (Word_t)ChanNum * 0x1000;
236
237 ChP->BaudDiv[0] = (Byte_t)(ChOff + _BAUD);
238 ChP->BaudDiv[1] = (Byte_t)((ChOff + _BAUD) >> 8);
239 ChP->BaudDiv[2] = (Byte_t)BRD9600;
240 ChP->BaudDiv[3] = (Byte_t)(BRD9600 >> 8);
448 sOutDW(ChP->IndexAddr,*(DWord_t *)&ChP->BaudDiv[0]);
241 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->BaudDiv[0]);
449
450 ChP->TxControl[0] = (Byte_t)(ChOff + _TX_CTRL);
451 ChP->TxControl[1] = (Byte_t)((ChOff + _TX_CTRL) >> 8);
452 ChP->TxControl[2] = 0;
453 ChP->TxControl[3] = 0;
242
243 ChP->TxControl[0] = (Byte_t)(ChOff + _TX_CTRL);
244 ChP->TxControl[1] = (Byte_t)((ChOff + _TX_CTRL) >> 8);
245 ChP->TxControl[2] = 0;
246 ChP->TxControl[3] = 0;
454 sOutDW(ChP->IndexAddr,*(DWord_t *)&ChP->TxControl[0]);
247 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxControl[0]);
455
456 ChP->RxControl[0] = (Byte_t)(ChOff + _RX_CTRL);
457 ChP->RxControl[1] = (Byte_t)((ChOff + _RX_CTRL) >> 8);
458 ChP->RxControl[2] = 0;
459 ChP->RxControl[3] = 0;
248
249 ChP->RxControl[0] = (Byte_t)(ChOff + _RX_CTRL);
250 ChP->RxControl[1] = (Byte_t)((ChOff + _RX_CTRL) >> 8);
251 ChP->RxControl[2] = 0;
252 ChP->RxControl[3] = 0;
460 sOutDW(ChP->IndexAddr,*(DWord_t *)&ChP->RxControl[0]);
253 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->RxControl[0]);
461
462 ChP->TxEnables[0] = (Byte_t)(ChOff + _TX_ENBLS);
463 ChP->TxEnables[1] = (Byte_t)((ChOff + _TX_ENBLS) >> 8);
464 ChP->TxEnables[2] = 0;
465 ChP->TxEnables[3] = 0;
254
255 ChP->TxEnables[0] = (Byte_t)(ChOff + _TX_ENBLS);
256 ChP->TxEnables[1] = (Byte_t)((ChOff + _TX_ENBLS) >> 8);
257 ChP->TxEnables[2] = 0;
258 ChP->TxEnables[3] = 0;
466 sOutDW(ChP->IndexAddr,*(DWord_t *)&ChP->TxEnables[0]);
259 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxEnables[0]);
467
468 ChP->TxCompare[0] = (Byte_t)(ChOff + _TXCMP1);
469 ChP->TxCompare[1] = (Byte_t)((ChOff + _TXCMP1) >> 8);
470 ChP->TxCompare[2] = 0;
471 ChP->TxCompare[3] = 0;
260
261 ChP->TxCompare[0] = (Byte_t)(ChOff + _TXCMP1);
262 ChP->TxCompare[1] = (Byte_t)((ChOff + _TXCMP1) >> 8);
263 ChP->TxCompare[2] = 0;
264 ChP->TxCompare[3] = 0;
472 sOutDW(ChP->IndexAddr,*(DWord_t *)&ChP->TxCompare[0]);
265 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxCompare[0]);
473
474 ChP->TxReplace1[0] = (Byte_t)(ChOff + _TXREP1B1);
475 ChP->TxReplace1[1] = (Byte_t)((ChOff + _TXREP1B1) >> 8);
476 ChP->TxReplace1[2] = 0;
477 ChP->TxReplace1[3] = 0;
266
267 ChP->TxReplace1[0] = (Byte_t)(ChOff + _TXREP1B1);
268 ChP->TxReplace1[1] = (Byte_t)((ChOff + _TXREP1B1) >> 8);
269 ChP->TxReplace1[2] = 0;
270 ChP->TxReplace1[3] = 0;
478 sOutDW(ChP->IndexAddr,*(DWord_t *)&ChP->TxReplace1[0]);
271 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxReplace1[0]);
479
480 ChP->TxReplace2[0] = (Byte_t)(ChOff + _TXREP2);
481 ChP->TxReplace2[1] = (Byte_t)((ChOff + _TXREP2) >> 8);
482 ChP->TxReplace2[2] = 0;
483 ChP->TxReplace2[3] = 0;
272
273 ChP->TxReplace2[0] = (Byte_t)(ChOff + _TXREP2);
274 ChP->TxReplace2[1] = (Byte_t)((ChOff + _TXREP2) >> 8);
275 ChP->TxReplace2[2] = 0;
276 ChP->TxReplace2[3] = 0;
484 sOutDW(ChP->IndexAddr,*(DWord_t *)&ChP->TxReplace2[0]);
277 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxReplace2[0]);
485
486 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
487 ChP->TxFIFO = ChOff + _TX_FIFO;
488
278
279 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
280 ChP->TxFIFO = ChOff + _TX_FIFO;
281
489 sOutB(ChP->Cmd,(Byte_t)ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
490 sOutB(ChP->Cmd,(Byte_t)ChanNum); /* remove reset Tx FIFO count */
491 sOutW((WordIO_t)ChP->IndexAddr,ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
492 sOutW(ChP->IndexData,0);
282 rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
283 rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum); /* remove reset Tx FIFO count */
284 rp_writech2(ChP,_INDX_ADDR,ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
285 rp_writech2(ChP,_INDX_DATA,0);
493 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
494 ChP->RxFIFO = ChOff + _RX_FIFO;
495
286 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
287 ChP->RxFIFO = ChOff + _RX_FIFO;
288
496 sOutB(ChP->Cmd,(Byte_t)ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
497 sOutB(ChP->Cmd,(Byte_t)ChanNum); /* remove reset Rx FIFO count */
498 sOutW((WordIO_t)ChP->IndexAddr,ChP->RxFIFOPtrs); /* clear Rx out ptr */
499 sOutW(ChP->IndexData,0);
500 sOutW((WordIO_t)ChP->IndexAddr,ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
501 sOutW(ChP->IndexData,0);
289 rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
290 rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum); /* remove reset Rx FIFO count */
291 rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs); /* clear Rx out ptr */
292 rp_writech2(ChP,_INDX_ADDR,0);
293 rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
294 rp_writech2(ChP,_INDX_ADDR,0);
502 ChP->TxPrioCnt = ChOff + _TXP_CNT;
295 ChP->TxPrioCnt = ChOff + _TXP_CNT;
503 sOutW((WordIO_t)ChP->IndexAddr,ChP->TxPrioCnt);
504 sOutB(ChP->IndexData,0);
296 rp_writech2(ChP,_INDX_ADDR,ChP->TxPrioCnt);
297 rp_writech1(ChP,_INDX_ADDR,0);
505 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
298 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
506 sOutW((WordIO_t)ChP->IndexAddr,ChP->TxPrioPtr);
507 sOutB(ChP->IndexData,0);
299 rp_writech2(ChP,_INDX_ADDR,ChP->TxPrioPtr);
300 rp_writech1(ChP,_INDX_ADDR,0);
508 ChP->TxPrioBuf = ChOff + _TXP_BUF;
509 sEnRxProcessor(ChP); /* start the Rx processor */
510
511 return(TRUE);
512}
513
514/***************************************************************************
515Function: sStopRxProcessor

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532void sStopRxProcessor(CHANNEL_T *ChP)
533{
534 Byte_t R[4];
535
536 R[0] = ChP->R[0];
537 R[1] = ChP->R[1];
538 R[2] = 0x0a;
539 R[3] = ChP->R[3];
301 ChP->TxPrioBuf = ChOff + _TXP_BUF;
302 sEnRxProcessor(ChP); /* start the Rx processor */
303
304 return(TRUE);
305}
306
307/***************************************************************************
308Function: sStopRxProcessor

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325void sStopRxProcessor(CHANNEL_T *ChP)
326{
327 Byte_t R[4];
328
329 R[0] = ChP->R[0];
330 R[1] = ChP->R[1];
331 R[2] = 0x0a;
332 R[3] = ChP->R[3];
540 sOutDW(ChP->IndexAddr,*(DWord_t *)&R[0]);
333 rp_writech4(ChP, _INDX_ADDR,*(DWord_t *)&R[0]);
541}
542
543/***************************************************************************
544Function: sFlushRxFIFO
545Purpose: Flush the Rx FIFO
546Call: sFlushRxFIFO(ChP)
547 CHANNEL_T *ChP; Ptr to channel structure
548Return: void

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564 return; /* don't need to flush */
565
566 RxFIFOEnabled = FALSE;
567 if(ChP->R[0x32] == 0x08) /* Rx FIFO is enabled */
568 {
569 RxFIFOEnabled = TRUE;
570 sDisRxFIFO(ChP); /* disable it */
571 for(i=0; i < 2000/200; i++) /* delay 2 uS to allow proc to disable FIFO*/
334}
335
336/***************************************************************************
337Function: sFlushRxFIFO
338Purpose: Flush the Rx FIFO
339Call: sFlushRxFIFO(ChP)
340 CHANNEL_T *ChP; Ptr to channel structure
341Return: void

--- 15 unchanged lines hidden (view full) ---

357 return; /* don't need to flush */
358
359 RxFIFOEnabled = FALSE;
360 if(ChP->R[0x32] == 0x08) /* Rx FIFO is enabled */
361 {
362 RxFIFOEnabled = TRUE;
363 sDisRxFIFO(ChP); /* disable it */
364 for(i=0; i < 2000/200; i++) /* delay 2 uS to allow proc to disable FIFO*/
572 sInB(ChP->IntChan); /* depends on bus i/o timing */
365 rp_readch1(ChP,_INT_CHAN); /* depends on bus i/o timing */
573 }
574 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
575 Ch = (Byte_t)sGetChanNum(ChP);
366 }
367 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
368 Ch = (Byte_t)sGetChanNum(ChP);
576 sOutB(ChP->Cmd,Ch | RESRXFCNT); /* apply reset Rx FIFO count */
577 sOutB(ChP->Cmd,Ch); /* remove reset Rx FIFO count */
578 sOutW((WordIO_t)ChP->IndexAddr,ChP->RxFIFOPtrs); /* clear Rx out ptr */
579 sOutW(ChP->IndexData,0);
580 sOutW((WordIO_t)ChP->IndexAddr,ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
581 sOutW(ChP->IndexData,0);
369 rp_writech1(ChP,_CMD_REG,Ch | RESRXFCNT); /* apply reset Rx FIFO count */
370 rp_writech1(ChP,_CMD_REG,Ch); /* remove reset Rx FIFO count */
371 rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs); /* clear Rx out ptr */
372 rp_writech2(ChP,_INDX_DATA,0);
373 rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
374 rp_writech2(ChP,_INDX_DATA,0);
582 if(RxFIFOEnabled)
583 sEnRxFIFO(ChP); /* enable Rx FIFO */
584}
585
586/***************************************************************************
587Function: sFlushTxFIFO
588Purpose: Flush the Tx FIFO
589Call: sFlushTxFIFO(ChP)

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609 TxEnabled = FALSE;
610 if(ChP->TxControl[3] & TX_ENABLE)
611 {
612 TxEnabled = TRUE;
613 sDisTransmit(ChP); /* disable transmitter */
614 }
615 sStopRxProcessor(ChP); /* stop Rx processor */
616 for(i = 0; i < 4000/200; i++) /* delay 4 uS to allow proc to stop */
375 if(RxFIFOEnabled)
376 sEnRxFIFO(ChP); /* enable Rx FIFO */
377}
378
379/***************************************************************************
380Function: sFlushTxFIFO
381Purpose: Flush the Tx FIFO
382Call: sFlushTxFIFO(ChP)

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402 TxEnabled = FALSE;
403 if(ChP->TxControl[3] & TX_ENABLE)
404 {
405 TxEnabled = TRUE;
406 sDisTransmit(ChP); /* disable transmitter */
407 }
408 sStopRxProcessor(ChP); /* stop Rx processor */
409 for(i = 0; i < 4000/200; i++) /* delay 4 uS to allow proc to stop */
617 sInB(ChP->IntChan); /* depends on bus i/o timing */
410 rp_readch1(ChP,_INT_CHAN); /* depends on bus i/o timing */
618 Ch = (Byte_t)sGetChanNum(ChP);
411 Ch = (Byte_t)sGetChanNum(ChP);
619 sOutB(ChP->Cmd,Ch | RESTXFCNT); /* apply reset Tx FIFO count */
620 sOutB(ChP->Cmd,Ch); /* remove reset Tx FIFO count */
621 sOutW((WordIO_t)ChP->IndexAddr,ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
622 sOutW(ChP->IndexData,0);
412 rp_writech1(ChP,_CMD_REG,Ch | RESTXFCNT); /* apply reset Tx FIFO count */
413 rp_writech1(ChP,_CMD_REG,Ch); /* remove reset Tx FIFO count */
414 rp_writech2(ChP,_INDX_ADDR,ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
415 rp_writech2(ChP,_INDX_DATA,0);
623 if(TxEnabled)
624 sEnTransmit(ChP); /* enable transmitter */
625 sStartRxProcessor(ChP); /* restart Rx processor */
626}
627
628/***************************************************************************
629Function: sWriteTxPrioByte
630Purpose: Write a byte of priority transmit data to a channel

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637Comments: The priority byte is transmitted before any data in the Tx FIFO.
638
639Warnings: No context switches are allowed while executing this function.
640*/
641int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data)
642{
643 Byte_t DWBuf[4]; /* buffer for double word writes */
644 Word_t *WordPtr; /* must be far because Win SS != DS */
416 if(TxEnabled)
417 sEnTransmit(ChP); /* enable transmitter */
418 sStartRxProcessor(ChP); /* restart Rx processor */
419}
420
421/***************************************************************************
422Function: sWriteTxPrioByte
423Purpose: Write a byte of priority transmit data to a channel

--- 6 unchanged lines hidden (view full) ---

430Comments: The priority byte is transmitted before any data in the Tx FIFO.
431
432Warnings: No context switches are allowed while executing this function.
433*/
434int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data)
435{
436 Byte_t DWBuf[4]; /* buffer for double word writes */
437 Word_t *WordPtr; /* must be far because Win SS != DS */
645 register DWordIO_t IndexAddr;
646
647 if(sGetTxCnt(ChP) > 1) /* write it to Tx priority buffer */
648 {
438
439 if(sGetTxCnt(ChP) > 1) /* write it to Tx priority buffer */
440 {
649 IndexAddr = ChP->IndexAddr;
650 sOutW((WordIO_t)IndexAddr,ChP->TxPrioCnt); /* get priority buffer status */
651 if(sInB((ByteIO_t)ChP->IndexData) & PRI_PEND) /* priority buffer busy */
441 rp_writech2(ChP,_INDX_ADDR,ChP->TxPrioCnt); /* get priority buffer status */
442 if(rp_readch1(ChP,_INDX_DATA) & PRI_PEND) /* priority buffer busy */
652 return(0); /* nothing sent */
653
654 WordPtr = (Word_t *)(&DWBuf[0]);
655 *WordPtr = ChP->TxPrioBuf; /* data byte address */
656
657 DWBuf[2] = Data; /* data byte value */
443 return(0); /* nothing sent */
444
445 WordPtr = (Word_t *)(&DWBuf[0]);
446 *WordPtr = ChP->TxPrioBuf; /* data byte address */
447
448 DWBuf[2] = Data; /* data byte value */
658 sOutDW(IndexAddr,*((DWord_t *)(&DWBuf[0]))); /* write it out */
449 rp_writech4(ChP,_INDX_ADDR,*((DWord_t *)(&DWBuf[0]))); /* write it out */
659
660 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
661
662 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
663 DWBuf[3] = 0; /* priority buffer pointer */
450
451 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
452
453 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
454 DWBuf[3] = 0; /* priority buffer pointer */
664 sOutDW(IndexAddr,*((DWord_t *)(&DWBuf[0]))); /* write it out */
455 rp_writech4(ChP,_INDX_ADDR,*((DWord_t *)(&DWBuf[0]))); /* write it out */
665 }
666 else /* write it to Tx FIFO */
667 {
456 }
457 else /* write it to Tx FIFO */
458 {
668 sWriteTxByte(sGetTxRxDataIO(ChP),Data);
459 sWriteTxByte(ChP,sGetTxRxDataIO(ChP),Data);
669 }
670 return(1); /* 1 byte sent */
671}
672
673/***************************************************************************
674Function: sEnInterrupts
675Purpose: Enable one or more interrupts for a channel
676Call: sEnInterrupts(ChP,Flags)

--- 27 unchanged lines hidden (view full) ---

704*/
705void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags)
706{
707 Byte_t Mask; /* Interrupt Mask Register */
708
709 ChP->RxControl[2] |=
710 ((Byte_t)Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
711
460 }
461 return(1); /* 1 byte sent */
462}
463
464/***************************************************************************
465Function: sEnInterrupts
466Purpose: Enable one or more interrupts for a channel
467Call: sEnInterrupts(ChP,Flags)

--- 27 unchanged lines hidden (view full) ---

495*/
496void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags)
497{
498 Byte_t Mask; /* Interrupt Mask Register */
499
500 ChP->RxControl[2] |=
501 ((Byte_t)Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
502
712 sOutDW(ChP->IndexAddr,*(DWord_t *)&ChP->RxControl[0]);
503 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->RxControl[0]);
713
714 ChP->TxControl[2] |= ((Byte_t)Flags & TXINT_EN);
715
504
505 ChP->TxControl[2] |= ((Byte_t)Flags & TXINT_EN);
506
716 sOutDW(ChP->IndexAddr,*(DWord_t *)&ChP->TxControl[0]);
507 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxControl[0]);
717
718 if(Flags & CHANINT_EN)
719 {
508
509 if(Flags & CHANINT_EN)
510 {
720 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
721 sOutB(ChP->IntMask,Mask);
511 Mask = rp_readch1(ChP,_INT_MASK) | rp_sBitMapSetTbl[ChP->ChanNum];
512 rp_writech1(ChP,_INT_MASK,Mask);
722 }
723}
724
725/***************************************************************************
726Function: sDisInterrupts
727Purpose: Disable one or more interrupts for a channel
728Call: sDisInterrupts(ChP,Flags)
729 CHANNEL_T *ChP; Ptr to channel structure

--- 18 unchanged lines hidden (view full) ---

748 Register.
749*/
750void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags)
751{
752 Byte_t Mask; /* Interrupt Mask Register */
753
754 ChP->RxControl[2] &=
755 ~((Byte_t)Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
513 }
514}
515
516/***************************************************************************
517Function: sDisInterrupts
518Purpose: Disable one or more interrupts for a channel
519Call: sDisInterrupts(ChP,Flags)
520 CHANNEL_T *ChP; Ptr to channel structure

--- 18 unchanged lines hidden (view full) ---

539 Register.
540*/
541void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags)
542{
543 Byte_t Mask; /* Interrupt Mask Register */
544
545 ChP->RxControl[2] &=
546 ~((Byte_t)Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
756 sOutDW(ChP->IndexAddr,*(DWord_t *)&ChP->RxControl[0]);
547 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->RxControl[0]);
757 ChP->TxControl[2] &= ~((Byte_t)Flags & TXINT_EN);
548 ChP->TxControl[2] &= ~((Byte_t)Flags & TXINT_EN);
758 sOutDW(ChP->IndexAddr,*(DWord_t *)&ChP->TxControl[0]);
549 rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxControl[0]);
759
760 if(Flags & CHANINT_EN)
761 {
550
551 if(Flags & CHANINT_EN)
552 {
762 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
763 sOutB(ChP->IntMask,Mask);
553 Mask = rp_readch1(ChP,_INT_MASK) & rp_sBitMapClrTbl[ChP->ChanNum];
554 rp_writech1(ChP,_INT_MASK,Mask);
764 }
765}
766
767/*********************************************************************
768 Begin FreeBsd-specific driver code
769**********************************************************************/
770
555 }
556}
557
558/*********************************************************************
559 Begin FreeBsd-specific driver code
560**********************************************************************/
561
771static int rpprobe __P((struct isa_device *));
772static int rpattach __P((struct isa_device *));
773
774static const char* rp_pciprobe(pcici_t tag, pcidi_t type);
775static void rp_pciattach(pcici_t tag, int unit);
776static u_long rp_pcicount;
777
778static struct pci_device rp_pcidevice = {
779 "rp",
780 rp_pciprobe,
781 rp_pciattach,
782 &rp_pcicount,
783 NULL
784};
785
786COMPAT_PCI_DRIVER (rp_pci, rp_pcidevice);
787
788static timeout_t rpdtrwakeup;
789
562static timeout_t rpdtrwakeup;
563
790struct isa_driver rpdriver = {
791 INTR_TYPE_TTY,
792 rpprobe,
793 rpattach,
794 "rp"
795};
796COMPAT_ISA_DRIVER(rp, rpdriver);
797
798static char driver_name[] = "rp";
799
800static d_open_t rpopen;
801static d_close_t rpclose;
564static d_open_t rpopen;
565static d_close_t rpclose;
566static d_read_t rpread;
802static d_write_t rpwrite;
803static d_ioctl_t rpioctl;
804
805#define CDEV_MAJOR 81
567static d_write_t rpwrite;
568static d_ioctl_t rpioctl;
569
570#define CDEV_MAJOR 81
806static struct cdevsw rp_cdevsw = {
571struct cdevsw rp_cdevsw = {
807 /* open */ rpopen,
808 /* close */ rpclose,
572 /* open */ rpopen,
573 /* close */ rpclose,
809 /* read */ ttyread,
574 /* read */ rpread,
810 /* write */ rpwrite,
811 /* ioctl */ rpioctl,
812 /* poll */ ttypoll,
813 /* mmap */ nommap,
814 /* strategy */ nostrategy,
575 /* write */ rpwrite,
576 /* ioctl */ rpioctl,
577 /* poll */ ttypoll,
578 /* mmap */ nommap,
579 /* strategy */ nostrategy,
815 /* name */ driver_name,
580 /* name */ "rp",
816 /* maj */ CDEV_MAJOR,
817 /* dump */ nodump,
818 /* psize */ nopsize,
819 /* flags */ D_TTY,
820 /* bmaj */ -1
821};
822
581 /* maj */ CDEV_MAJOR,
582 /* dump */ nodump,
583 /* psize */ nopsize,
584 /* flags */ D_TTY,
585 /* bmaj */ -1
586};
587
823static int rp_controller_port = 0;
824static int rp_num_ports_open = 0;
825static int ndevs = 0;
588static int rp_num_ports_open = 0;
589static int rp_ndevs = 0;
826static int minor_to_unit[128];
590static int minor_to_unit[128];
827#if 0
828static struct tty rp_tty[128];
829#endif
830
831static int rp_num_ports[4]; /* Number of ports on each controller */
832
833#define _INLINE_ __inline
834#define POLL_INTERVAL 1
835
836#define CALLOUT_MASK 0x80
837#define CONTROL_MASK 0x60

--- 17 unchanged lines hidden (view full) ---

855/*
856 * The top-level routines begin here
857 */
858
859static int rpparam __P((struct tty *, struct termios *));
860static void rpstart __P((struct tty *));
861static void rpstop __P((struct tty *, int));
862static void rphardclose __P((struct rp_port *));
591
592static int rp_num_ports[4]; /* Number of ports on each controller */
593
594#define _INLINE_ __inline
595#define POLL_INTERVAL 1
596
597#define CALLOUT_MASK 0x80
598#define CONTROL_MASK 0x60

--- 17 unchanged lines hidden (view full) ---

616/*
617 * The top-level routines begin here
618 */
619
620static int rpparam __P((struct tty *, struct termios *));
621static void rpstart __P((struct tty *));
622static void rpstop __P((struct tty *, int));
623static void rphardclose __P((struct rp_port *));
863static void rp_disc_optim __P((struct tty *tp, struct termios *t,
864 struct rp_port *rp));
624static void rp_disc_optim __P((struct tty *tp, struct termios *t));
865
866static _INLINE_ void rp_do_receive(struct rp_port *rp, struct tty *tp,
867 CHANNEL_t *cp, unsigned int ChanStatus)
868{
869 int spl;
870 unsigned int CharNStat;
625
626static _INLINE_ void rp_do_receive(struct rp_port *rp, struct tty *tp,
627 CHANNEL_t *cp, unsigned int ChanStatus)
628{
629 int spl;
630 unsigned int CharNStat;
871 int ToRecv, ch;
631 int ToRecv, wRecv, ch, ttynocopy;
872
873 ToRecv = sGetRxCnt(cp);
874 if(ToRecv == 0)
875 return;
876
877/* If status indicates there are errored characters in the
878 FIFO, then enter status mode (a word in FIFO holds
879 characters and status)

--- 10 unchanged lines hidden (view full) ---

890 FIFO one word at a time, pulling apart the character and
891 the status. Update error counters depending on status.
892*/
893 if(ChanStatus & STATMODE) {
894 while(ToRecv) {
895 if(tp->t_state & TS_TBLOCK) {
896 break;
897 }
632
633 ToRecv = sGetRxCnt(cp);
634 if(ToRecv == 0)
635 return;
636
637/* If status indicates there are errored characters in the
638 FIFO, then enter status mode (a word in FIFO holds
639 characters and status)

--- 10 unchanged lines hidden (view full) ---

650 FIFO one word at a time, pulling apart the character and
651 the status. Update error counters depending on status.
652*/
653 if(ChanStatus & STATMODE) {
654 while(ToRecv) {
655 if(tp->t_state & TS_TBLOCK) {
656 break;
657 }
898 CharNStat = sInW(sGetTxRxDataIO(cp));
658 CharNStat = rp_readch2(cp,sGetTxRxDataIO(cp));
899 ch = CharNStat & 0xff;
900
901 if((CharNStat & STMBREAK) || (CharNStat & STMFRAMEH))
902 ch |= TTY_FE;
903 else if (CharNStat & STMPARITYH)
904 ch |= TTY_PE;
905 else if (CharNStat & STMRCVROVRH)
906 rp->rp_overflows++;
907
908 (*linesw[tp->t_line].l_rint)(ch, tp);
909 ToRecv--;
910 }
911/*
912 After emtying FIFO in status mode, turn off status mode
913*/
914
659 ch = CharNStat & 0xff;
660
661 if((CharNStat & STMBREAK) || (CharNStat & STMFRAMEH))
662 ch |= TTY_FE;
663 else if (CharNStat & STMPARITYH)
664 ch |= TTY_PE;
665 else if (CharNStat & STMRCVROVRH)
666 rp->rp_overflows++;
667
668 (*linesw[tp->t_line].l_rint)(ch, tp);
669 ToRecv--;
670 }
671/*
672 After emtying FIFO in status mode, turn off status mode
673*/
674
915 if(sGetRxCnt(cp) == 0)
916 sDisRxStatusMode(cp);
917 }
918 else {
919 while (ToRecv) {
920 if(tp->t_state & TS_TBLOCK) {
921 break;
675 if(sGetRxCnt(cp) == 0)
676 sDisRxStatusMode(cp);
677 } else {
678 /*
679 * Avoid the grotesquely inefficient lineswitch routine
680 * (ttyinput) in "raw" mode. It usually takes about 450
681 * instructions (that's without canonical processing or echo!).
682 * slinput is reasonably fast (usually 40 instructions plus
683 * call overhead).
684 */
685 ToRecv = sGetRxCnt(cp);
686 if ( tp->t_state & TS_CAN_BYPASS_L_RINT ) {
687 if ( ToRecv > RXFIFO_SIZE ) {
688 ToRecv = RXFIFO_SIZE;
922 }
689 }
923 ch = (u_char) sInB(sGetTxRxDataIO(cp));
924 spl = spltty();
925 (*linesw[tp->t_line].l_rint)(ch, tp);
926 splx(spl);
927 ToRecv--;
690 wRecv = ToRecv >> 1;
691 if ( wRecv ) {
692 rp_readmultich2(cp,sGetTxRxDataIO(cp),(u_int16_t *)rp->RxBuf,wRecv);
693 }
694 if ( ToRecv & 1 ) {
695 rp->RxBuf[(ToRecv-1)] = (u_char) rp_readch1(cp,sGetTxRxDataIO(cp));
696 }
697 tk_nin += ToRecv;
698 tk_rawcc += ToRecv;
699 tp->t_rawcc += ToRecv;
700 ttynocopy = b_to_q((char *)rp->RxBuf, ToRecv, &tp->t_rawq);
701 ttwakeup(tp);
702 } else {
703 while (ToRecv) {
704 if(tp->t_state & TS_TBLOCK) {
705 break;
706 }
707 ch = (u_char) rp_readch1(cp,sGetTxRxDataIO(cp));
708 spl = spltty();
709 (*linesw[tp->t_line].l_rint)(ch, tp);
710 splx(spl);
711 ToRecv--;
712 }
928 }
929 }
930}
931
932static _INLINE_ void rp_handle_port(struct rp_port *rp)
933{
934 CHANNEL_t *cp;
935 struct tty *tp;
936 unsigned int IntMask, ChanStatus;
713 }
714 }
715}
716
717static _INLINE_ void rp_handle_port(struct rp_port *rp)
718{
719 CHANNEL_t *cp;
720 struct tty *tp;
721 unsigned int IntMask, ChanStatus;
937 /* int oldcts; */
938
939 if(!rp)
940 return;
941
942 cp = &rp->rp_channel;
943 tp = rp->rp_tty;
944 IntMask = sGetChanIntID(cp);
945 IntMask = IntMask & rp->rp_intmask;

--- 27 unchanged lines hidden (view full) ---

973static void rp_do_poll(void *not_used)
974{
975 CONTROLLER_t *ctl;
976 struct rp_port *rp;
977 struct tty *tp;
978 int unit, aiop, ch, line, count;
979 unsigned char CtlMask, AiopMask;
980
722
723 if(!rp)
724 return;
725
726 cp = &rp->rp_channel;
727 tp = rp->rp_tty;
728 IntMask = sGetChanIntID(cp);
729 IntMask = IntMask & rp->rp_intmask;

--- 27 unchanged lines hidden (view full) ---

757static void rp_do_poll(void *not_used)
758{
759 CONTROLLER_t *ctl;
760 struct rp_port *rp;
761 struct tty *tp;
762 int unit, aiop, ch, line, count;
763 unsigned char CtlMask, AiopMask;
764
981 for(unit = 0; unit <= ndevs; unit++) {
765 for(unit = 0; unit < rp_ndevs; unit++) {
982 rp = rp_addr(unit);
983 ctl = rp->rp_ctlp;
766 rp = rp_addr(unit);
767 ctl = rp->rp_ctlp;
984 if(ctl->BusType == isPCI)
985 CtlMask = sPCIGetControllerIntStatus(ctl);
986 else
987 CtlMask = sGetControllerIntStatus(ctl);
768 CtlMask = ctl->ctlmask(ctl);
988 for(aiop=0; CtlMask; CtlMask >>=1, aiop++) {
989 if(CtlMask & 1) {
990 AiopMask = sGetAiopIntStatus(ctl, aiop);
991 for(ch = 0; AiopMask; AiopMask >>=1, ch++) {
992 if(AiopMask & 1) {
993 line = (unit << 5) | (aiop << 3) | ch;
994 rp = rp_table(line);
995 rp_handle_port(rp);

--- 15 unchanged lines hidden (view full) ---

1011 }
1012 }
1013 }
1014 }
1015 if(rp_num_ports_open)
1016 timeout(rp_do_poll, (void *)NULL, POLL_INTERVAL);
1017}
1018
769 for(aiop=0; CtlMask; CtlMask >>=1, aiop++) {
770 if(CtlMask & 1) {
771 AiopMask = sGetAiopIntStatus(ctl, aiop);
772 for(ch = 0; AiopMask; AiopMask >>=1, ch++) {
773 if(AiopMask & 1) {
774 line = (unit << 5) | (aiop << 3) | ch;
775 rp = rp_table(line);
776 rp_handle_port(rp);

--- 15 unchanged lines hidden (view full) ---

792 }
793 }
794 }
795 }
796 if(rp_num_ports_open)
797 timeout(rp_do_poll, (void *)NULL, POLL_INTERVAL);
798}
799
1019static const char*
1020rp_pciprobe(pcici_t tag, pcidi_t type)
1021{
1022 int vendor_id;
1023
1024 vendor_id = type & 0xffff;
1025 switch(vendor_id)
1026 case 0x11fe:
1027 return("rp");
1028 return(NULL);
1029}
1030
1031static
1032int
800int
1033rpprobe(dev)
1034struct isa_device *dev;
801rp_attachcommon(CONTROLLER_T *ctlp, int num_aiops, int num_ports)
1035{
802{
1036 int controller, unit;
1037 int aiop, num_aiops;
1038 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1039 CONTROLLER_t *ctlp;
1040
1041 unit = dev->id_unit;
1042 if (dev->id_unit >= 4) {
1043 printf("rpprobe: unit number %d invalid.\n", dev->id_unit);
1044 return 1;
1045 }
1046 printf("probing for RocketPort(ISA) unit %d\n", unit);
1047 if (rp_controller_port)
1048 controller = rp_controller_port;
1049 else {
1050 controller = dev->id_iobase + 0x40;
1051 }
1052
1053 for (aiop=0; aiop<MAX_AIOPS_PER_BOARD; aiop++)
1054 aiopio[aiop]= dev->id_iobase + (aiop * 0x400);
1055
1056 ctlp = sCtlNumToCtlPtr(dev->id_unit);
1057 num_aiops = sInitController(ctlp, dev->id_unit,
1058 controller + ((unit-rp_pcicount)*0x400),
1059 aiopio, MAX_AIOPS_PER_BOARD, 0,
1060 FREQ_DIS, 0);
1061 if (num_aiops <= 0) {
1062 printf("board%d init failed\n", unit);
1063 return 0;
1064 }
1065
1066 if (rp_controller_port) {
1067 dev->id_msize = 64;
1068 } else {
1069 dev->id_msize = 68;
1070 rp_controller_port = controller;
1071 }
1072
1073 dev->id_irq = 0;
1074
1075 return 1;
1076}
1077
1078static void
1079rp_pciattach(pcici_t tag, int unit)
1080{
1081 int success, oldspl;
1082 u_short iobase;
1083 int num_ports, num_chan, num_aiops;
803 int oldspl, unit;
804 int num_chan;
1084 int aiop, chan, port;
1085 int ChanStatus, line, i, count;
805 int aiop, chan, port;
806 int ChanStatus, line, i, count;
1086 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
807 int retval;
1087 struct rp_port *rp;
1088 struct tty *tty;
808 struct rp_port *rp;
809 struct tty *tty;
1089 CONTROLLER_t *ctlp;
810 dev_t *dev_nodes;
1090
811
1091 success = pci_map_port(tag, 0x10, &iobase);
1092 if(!success)
1093 printf("ioaddr mapping failed for RocketPort(PCI)\n");
812 unit = device_get_unit(ctlp->dev);
1094
813
1095 for(aiop=0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
1096 aiopio[aiop] = iobase + (aiop * 0x40);
1097
1098 ctlp = sCtlNumToCtlPtr(unit);
1099 num_aiops = sPCIInitController(ctlp, unit,
1100 aiopio, MAX_AIOPS_PER_BOARD, 0,
1101 FREQ_DIS, 0);
1102
1103 num_ports = 0;
1104 for(aiop=0; aiop < num_aiops; aiop++) {
1105 sResetAiopByNum(ctlp, aiop);
1106 num_ports += sGetAiopNumChan(ctlp, aiop);
1107 }
1108 printf("RocketPort%d = %d ports\n", unit, num_ports);
814 printf("RocketPort%d (Version %s) %d ports.\n", unit,
815 RocketPortVersion, num_ports);
1109 rp_num_ports[unit] = num_ports;
1110
816 rp_num_ports[unit] = num_ports;
817
1111 rp = (struct rp_port *)
818 ctlp->rp = rp = (struct rp_port *)
1112 malloc(sizeof(struct rp_port) * num_ports, M_TTYS, M_NOWAIT);
819 malloc(sizeof(struct rp_port) * num_ports, M_TTYS, M_NOWAIT);
1113 if(rp == 0) {
1114 printf("rp_attach: Could not malloc rp_ports structures\n");
1115 return;
820 if (rp == NULL) {
821 device_printf(ctlp->dev, "rp_attachcommon: Could not malloc rp_ports structures.\n");
822 retval = ENOMEM;
823 goto nogo;
1116 }
1117
1118 count = unit * 32; /* board times max ports per card SG */
1119 for(i=count;i < (count + rp_num_ports[unit]);i++)
1120 minor_to_unit[i] = unit;
1121
1122 bzero(rp, sizeof(struct rp_port) * num_ports);
824 }
825
826 count = unit * 32; /* board times max ports per card SG */
827 for(i=count;i < (count + rp_num_ports[unit]);i++)
828 minor_to_unit[i] = unit;
829
830 bzero(rp, sizeof(struct rp_port) * num_ports);
1123 tty = (struct tty *)
831 ctlp->tty = tty = (struct tty *)
1124 malloc(sizeof(struct tty) * num_ports, M_TTYS, M_NOWAIT);
832 malloc(sizeof(struct tty) * num_ports, M_TTYS, M_NOWAIT);
1125 if(tty == 0) {
1126 printf("rp_attach: Could not malloc tty structures\n");
1127 return;
833 if(tty == NULL) {
834 device_printf(ctlp->dev, "rp_attachcommon: Could not malloc tty structures.\n");
835 retval = ENOMEM;
836 goto nogo;
1128 }
1129 bzero(tty, sizeof(struct tty) * num_ports);
1130
1131 oldspl = spltty();
1132 rp_addr(unit) = rp;
1133 splx(oldspl);
1134
837 }
838 bzero(tty, sizeof(struct tty) * num_ports);
839
840 oldspl = spltty();
841 rp_addr(unit) = rp;
842 splx(oldspl);
843
1135 cdevsw_add(&rp_cdevsw);
844 dev_nodes = ctlp->dev_nodes = malloc(sizeof(*(ctlp->dev_nodes)) * rp_num_ports[unit] * 6, M_DEVBUF, M_NOWAIT);
845 if(ctlp->dev_nodes == NULL) {
846 device_printf(ctlp->dev, "rp_attachcommon: Could not malloc device node structures.\n");
847 retval = ENOMEM;
848 goto nogo;
849 }
850 bzero(dev_nodes, sizeof(*(ctlp->dev_nodes)) * rp_num_ports[unit] * 6);
1136
851
852 for (i = 0 ; i < rp_num_ports[unit] ; i++) {
853 *(dev_nodes++) = make_dev(&rp_cdevsw, ((unit + 1) << 16) | i,
854 UID_ROOT, GID_WHEEL, 0666, "ttyR%c",
855 i <= 9 ? '0' + i : 'a' + i - 10);
856 *(dev_nodes++) = make_dev(&rp_cdevsw, ((unit + 1) << 16) | i | 0x20,
857 UID_ROOT, GID_WHEEL, 0666, "ttyiR%c",
858 i <= 9 ? '0' + i : 'a' + i - 10);
859 *(dev_nodes++) = make_dev(&rp_cdevsw, ((unit + 1) << 16) | i | 0x40,
860 UID_ROOT, GID_WHEEL, 0666, "ttylR%c",
861 i <= 9 ? '0' + i : 'a' + i - 10);
862 *(dev_nodes++) = make_dev(&rp_cdevsw, ((unit + 1) << 16) | i | 0x80,
863 UID_ROOT, GID_WHEEL, 0666, "cuaR%c",
864 i <= 9 ? '0' + i : 'a' + i - 10);
865 *(dev_nodes++) = make_dev(&rp_cdevsw, ((unit + 1) << 16) | i | 0xa0,
866 UID_ROOT, GID_WHEEL, 0666, "cuaiR%c",
867 i <= 9 ? '0' + i : 'a' + i - 10);
868 *(dev_nodes++) = make_dev(&rp_cdevsw, ((unit + 1) << 16) | i | 0xc0,
869 UID_ROOT, GID_WHEEL, 0666, "cualR%c",
870 i <= 9 ? '0' + i : 'a' + i - 10);
871 }
872
1137 port = 0;
1138 for(aiop=0; aiop < num_aiops; aiop++) {
1139 num_chan = sGetAiopNumChan(ctlp, aiop);
1140 for(chan=0; chan < num_chan; chan++, port++, rp++, tty++) {
1141 rp->rp_tty = tty;
1142 rp->rp_port = port;
1143 rp->rp_ctlp = ctlp;
1144 rp->rp_unit = unit;

--- 11 unchanged lines hidden (view full) ---

1156 termioschars(&rp->it_in);
1157 /* termioschars(&tty->t_termios);
1158 */
1159 rp->it_in.c_ispeed = rp->it_in.c_ospeed = TTYDEF_SPEED;
1160 rp->it_out = rp->it_in;
1161
1162 rp->rp_intmask = RXF_TRIG | TXFIFO_MT | SRC_INT |
1163 DELTA_CD | DELTA_CTS | DELTA_DSR;
873 port = 0;
874 for(aiop=0; aiop < num_aiops; aiop++) {
875 num_chan = sGetAiopNumChan(ctlp, aiop);
876 for(chan=0; chan < num_chan; chan++, port++, rp++, tty++) {
877 rp->rp_tty = tty;
878 rp->rp_port = port;
879 rp->rp_ctlp = ctlp;
880 rp->rp_unit = unit;

--- 11 unchanged lines hidden (view full) ---

892 termioschars(&rp->it_in);
893 /* termioschars(&tty->t_termios);
894 */
895 rp->it_in.c_ispeed = rp->it_in.c_ospeed = TTYDEF_SPEED;
896 rp->it_out = rp->it_in;
897
898 rp->rp_intmask = RXF_TRIG | TXFIFO_MT | SRC_INT |
899 DELTA_CD | DELTA_CTS | DELTA_DSR;
900#if notdef
1164 ChanStatus = sGetChanStatus(&rp->rp_channel);
901 ChanStatus = sGetChanStatus(&rp->rp_channel);
902#endif /* notdef */
1165 if(sInitChan(ctlp, &rp->rp_channel, aiop, chan) == 0) {
903 if(sInitChan(ctlp, &rp->rp_channel, aiop, chan) == 0) {
1166 printf("RocketPort sInitChan(%d, %d, %d) failed
1167 \n", unit, aiop, chan);
1168 return;
904 device_printf(ctlp->dev, "RocketPort sInitChan(%d, %d, %d) failed.\n",
905 unit, aiop, chan);
906 retval = ENXIO;
907 goto nogo;
1169 }
1170 ChanStatus = sGetChanStatus(&rp->rp_channel);
1171 rp->rp_cts = (ChanStatus & CTS_ACT) != 0;
1172 line = (unit << 5) | (aiop << 3) | chan;
1173 rp_table(line) = rp;
1174 }
1175 }
908 }
909 ChanStatus = sGetChanStatus(&rp->rp_channel);
910 rp->rp_cts = (ChanStatus & CTS_ACT) != 0;
911 line = (unit << 5) | (aiop << 3) | chan;
912 rp_table(line) = rp;
913 }
914 }
1176}
1177
915
1178static
1179int
1180rpattach(dev)
1181struct isa_device *dev;
1182{
1183 int iobase, unit, /*rpmajor,*/ oldspl;
1184 int num_ports, num_chan, num_aiops;
1185 int aiop, chan, port;
1186 int ChanStatus, line, i, count;
1187 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1188 struct rp_port *rp;
1189 struct tty *tty;
1190 CONTROLLER_t *ctlp;
916 rp_ndevs++;
917 return (0);
1191
918
1192 iobase = dev->id_iobase;
1193 unit = dev->id_unit;
1194 ndevs = unit;
919nogo:
920 rp_releaseresource(ctlp);
1195
921
1196 for(aiop=0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
1197 aiopio[aiop] = iobase + (aiop * 0x400);
922 return (retval);
923}
1198
924
1199 ctlp = sCtlNumToCtlPtr(unit);
1200 num_aiops = sInitController(ctlp, unit,
1201 rp_controller_port + ((unit-rp_pcicount) * 0x400),
1202 aiopio, MAX_AIOPS_PER_BOARD, 0,
1203 FREQ_DIS, 0);
925void
926rp_releaseresource(CONTROLLER_t *ctlp)
927{
928 int i, s, unit;
1204
929
1205 num_ports = 0;
1206 for(aiop=0; aiop < num_aiops; aiop++) {
1207 sResetAiopByNum(ctlp, aiop);
1208 sEnAiop(ctlp, aiop);
1209 num_ports += sGetAiopNumChan(ctlp, aiop);
1210 }
1211 printf("RocketPort%d = %d ports\n", unit, num_ports);
1212 rp_num_ports[unit] = num_ports;
930 unit = device_get_unit(ctlp->dev);
1213
931
1214 rp = (struct rp_port *)
1215 malloc(sizeof(struct rp_port) * num_ports, M_TTYS, M_NOWAIT);
1216 if(rp == 0) {
1217 printf("rp_attach: Could not malloc rp_ports structures\n");
1218 return(0);
932 if (ctlp->rp != NULL) {
933 s = spltty();
934 for (i = 0 ; i < sizeof(p_rp_addr) / sizeof(*p_rp_addr) ; i++)
935 if (p_rp_addr[i] == ctlp->rp)
936 p_rp_addr[i] = NULL;
937 for (i = 0 ; i < sizeof(p_rp_table) / sizeof(*p_rp_table) ; i++)
938 if (p_rp_table[i] == ctlp->rp)
939 p_rp_table[i] = NULL;
940 splx(s);
941 free(ctlp->rp, M_DEVBUF);
942 ctlp->rp = NULL;
1219 }
943 }
1220
1221 count = unit * 32; /* board # times max ports per card SG */
1222 for(i=count;i < (count + rp_num_ports[unit]);i++)
1223 minor_to_unit[i] = unit;
1224
1225 bzero(rp, sizeof(struct rp_port) * num_ports);
1226 tty = (struct tty *)
1227 malloc(sizeof(struct tty) * num_ports, M_TTYS, M_NOWAIT);
1228 if(tty == 0) {
1229 printf("rp_attach: Could not malloc tty structures\n");
1230 return(0);
944 if (ctlp->tty != NULL) {
945 free(ctlp->tty, M_DEVBUF);
946 ctlp->tty = NULL;
1231 }
947 }
1232 bzero(tty, sizeof(struct tty) * num_ports);
1233
1234 oldspl = spltty();
1235 rp_addr(unit) = rp;
1236 splx(oldspl);
1237
1238 cdevsw_add(&rp_cdevsw);
1239
1240 port = 0;
1241 for(aiop=0; aiop < num_aiops; aiop++) {
1242 num_chan = sGetAiopNumChan(ctlp, aiop);
1243 for(chan=0; chan < num_chan; chan++, port++, rp++, tty++) {
1244 rp->rp_tty = tty;
1245 rp->rp_port = port;
1246 rp->rp_ctlp = ctlp;
1247 rp->rp_unit = unit;
1248 rp->rp_chan = chan;
1249 rp->rp_aiop = aiop;
1250
1251 tty->t_line = 0;
1252 /* tty->t_termios = deftermios;
1253 */
1254 rp->dtr_wait = 3 * hz;
1255 rp->it_in.c_iflag = 0;
1256 rp->it_in.c_oflag = 0;
1257 rp->it_in.c_cflag = TTYDEF_CFLAG;
1258 rp->it_in.c_lflag = 0;
1259 termioschars(&rp->it_in);
1260 /* termioschars(&tty->t_termios);
1261 */
1262 rp->it_in.c_ispeed = rp->it_in.c_ospeed = TTYDEF_SPEED;
1263 rp->it_out = rp->it_in;
1264
1265 rp->rp_intmask = RXF_TRIG | TXFIFO_MT | SRC_INT |
1266 DELTA_CD | DELTA_CTS | DELTA_DSR;
1267 ChanStatus = sGetChanStatus(&rp->rp_channel);
1268 if(sInitChan(ctlp, &rp->rp_channel, aiop, chan) == 0) {
1269 printf("RocketPort sInitChan(%d, %d, %d) failed
1270 \n", unit, aiop, chan);
1271 return(0);
1272 }
1273 ChanStatus = sGetChanStatus(&rp->rp_channel);
1274 rp->rp_cts = (ChanStatus & CTS_ACT) != 0;
1275 line = (unit << 5) | (aiop << 3) | chan;
1276 rp_table(line) = rp;
1277 }
948 if (ctlp->dev != NULL) {
949 for (i = 0 ; i < rp_num_ports[unit] * 6 ; i++)
950 destroy_dev(ctlp->dev_nodes[i]);
951 free(ctlp->dev_nodes, M_DEVBUF);
952 ctlp->dev = NULL;
1278 }
953 }
1279
1280 return(1);
1281}
1282
1283int
1284rpopen(dev, flag, mode, p)
1285 dev_t dev;
1286 int flag, mode;
1287 struct proc *p;
1288{
1289 struct rp_port *rp;
1290 int unit, port, mynor, umynor, flags; /* SG */
1291 struct tty *tp;
1292 int oldspl, error;
1293 unsigned int IntMask, ChanStatus;
1294
1295
1296 umynor = (((minor(dev) >> 16) -1) * 32); /* SG */
1297 port = (minor(dev) & 0x1f); /* SG */
1298 mynor = (port + umynor); /* SG */
1299 unit = minor_to_unit[mynor];
954}
955
956int
957rpopen(dev, flag, mode, p)
958 dev_t dev;
959 int flag, mode;
960 struct proc *p;
961{
962 struct rp_port *rp;
963 int unit, port, mynor, umynor, flags; /* SG */
964 struct tty *tp;
965 int oldspl, error;
966 unsigned int IntMask, ChanStatus;
967
968
969 umynor = (((minor(dev) >> 16) -1) * 32); /* SG */
970 port = (minor(dev) & 0x1f); /* SG */
971 mynor = (port + umynor); /* SG */
972 unit = minor_to_unit[mynor];
973 if (rp_addr(unit) == NULL)
974 return (ENXIO);
1300 if(IS_CONTROL(dev))
1301 return(0);
1302 rp = rp_addr(unit) + port;
1303/* rp->rp_tty = &rp_tty[rp->rp_port];
1304*/
1305 tp = rp->rp_tty;
1306 dev->si_tty = tp;
1307

--- 20 unchanged lines hidden (view full) ---

1328 }
1329 error = tsleep(&rp->active_out,
1330 TTIPRI | PCATCH, "rpbi", 0);
1331 if(error != 0)
1332 goto out;
1333 goto open_top;
1334 }
1335 }
975 if(IS_CONTROL(dev))
976 return(0);
977 rp = rp_addr(unit) + port;
978/* rp->rp_tty = &rp_tty[rp->rp_port];
979*/
980 tp = rp->rp_tty;
981 dev->si_tty = tp;
982

--- 20 unchanged lines hidden (view full) ---

1003 }
1004 error = tsleep(&rp->active_out,
1005 TTIPRI | PCATCH, "rpbi", 0);
1006 if(error != 0)
1007 goto out;
1008 goto open_top;
1009 }
1010 }
1336 if(tp->t_state & TS_XCLUDE &&
1337 suser(p)) {
1011 if(tp->t_state & TS_XCLUDE && suser(p) != 0) {
1338 splx(oldspl);
1012 splx(oldspl);
1339 return(EBUSY);
1013 error = EBUSY;
1014 goto out2;
1340 }
1341 }
1342 else {
1343 tp->t_dev = dev;
1344 tp->t_param = rpparam;
1345 tp->t_oproc = rpstart;
1346 tp->t_stop = rpstop;
1347 tp->t_line = 0;
1348 tp->t_termios = IS_CALLOUT(dev) ? rp->it_out : rp->it_in;
1015 }
1016 }
1017 else {
1018 tp->t_dev = dev;
1019 tp->t_param = rpparam;
1020 tp->t_oproc = rpstart;
1021 tp->t_stop = rpstop;
1022 tp->t_line = 0;
1023 tp->t_termios = IS_CALLOUT(dev) ? rp->it_out : rp->it_in;
1024 tp->t_ififosize = 512;
1025 tp->t_ispeedwat = (speed_t)-1;
1026 tp->t_ospeedwat = (speed_t)-1;
1349 flags = 0;
1350 flags |= SET_RTS;
1351 flags |= SET_DTR;
1352 rp->rp_channel.TxControl[3] =
1353 ((rp->rp_channel.TxControl[3]
1354 & ~(SET_RTS | SET_DTR)) | flags);
1027 flags = 0;
1028 flags |= SET_RTS;
1029 flags |= SET_DTR;
1030 rp->rp_channel.TxControl[3] =
1031 ((rp->rp_channel.TxControl[3]
1032 & ~(SET_RTS | SET_DTR)) | flags);
1355 sOutDW(rp->rp_channel.IndexAddr,
1033 rp_writech4(&rp->rp_channel,_INDX_ADDR,
1356 *(DWord_t *) &(rp->rp_channel.TxControl[0]));
1357 sSetRxTrigger(&rp->rp_channel, TRIG_1);
1358 sDisRxStatusMode(&rp->rp_channel);
1359 sFlushRxFIFO(&rp->rp_channel);
1360 sFlushTxFIFO(&rp->rp_channel);
1361
1362 sEnInterrupts(&rp->rp_channel,
1363 (TXINT_EN|MCINT_EN|RXINT_EN|SRCINT_EN|CHANINT_EN));

--- 47 unchanged lines hidden (view full) ---

1411 "rpdcd", 0);
1412 --rp->wopeners;
1413 if(error != 0)
1414 goto out;
1415 goto open_top;
1416 }
1417 error = (*linesw[tp->t_line].l_open)(dev, tp);
1418
1034 *(DWord_t *) &(rp->rp_channel.TxControl[0]));
1035 sSetRxTrigger(&rp->rp_channel, TRIG_1);
1036 sDisRxStatusMode(&rp->rp_channel);
1037 sFlushRxFIFO(&rp->rp_channel);
1038 sFlushTxFIFO(&rp->rp_channel);
1039
1040 sEnInterrupts(&rp->rp_channel,
1041 (TXINT_EN|MCINT_EN|RXINT_EN|SRCINT_EN|CHANINT_EN));

--- 47 unchanged lines hidden (view full) ---

1089 "rpdcd", 0);
1090 --rp->wopeners;
1091 if(error != 0)
1092 goto out;
1093 goto open_top;
1094 }
1095 error = (*linesw[tp->t_line].l_open)(dev, tp);
1096
1419 rp_disc_optim(tp, &tp->t_termios, rp);
1097 rp_disc_optim(tp, &tp->t_termios);
1420 if(tp->t_state & TS_ISOPEN && IS_CALLOUT(dev))
1421 rp->active_out = TRUE;
1422
1423/* if(rp_num_ports_open == 1)
1424 timeout(rp_do_poll, (void *)NULL, POLL_INTERVAL);
1425*/
1426out:
1427 splx(oldspl);
1428 if(!(tp->t_state & TS_ISOPEN) && rp->wopeners == 0) {
1429 rphardclose(rp);
1430 }
1098 if(tp->t_state & TS_ISOPEN && IS_CALLOUT(dev))
1099 rp->active_out = TRUE;
1100
1101/* if(rp_num_ports_open == 1)
1102 timeout(rp_do_poll, (void *)NULL, POLL_INTERVAL);
1103*/
1104out:
1105 splx(oldspl);
1106 if(!(tp->t_state & TS_ISOPEN) && rp->wopeners == 0) {
1107 rphardclose(rp);
1108 }
1109out2:
1110 if (error == 0)
1111 device_busy(rp->rp_ctlp->dev);
1431 return(error);
1432}
1433
1434int
1435rpclose(dev, flag, mode, p)
1436 dev_t dev;
1437 int flag, mode;
1438 struct proc *p;

--- 11 unchanged lines hidden (view full) ---

1450 if(IS_CONTROL(dev))
1451 return(0);
1452 rp = rp_addr(unit) + port;
1453 cp = &rp->rp_channel;
1454 tp = rp->rp_tty;
1455
1456 oldspl = spltty();
1457 (*linesw[tp->t_line].l_close)(tp, flag);
1112 return(error);
1113}
1114
1115int
1116rpclose(dev, flag, mode, p)
1117 dev_t dev;
1118 int flag, mode;
1119 struct proc *p;

--- 11 unchanged lines hidden (view full) ---

1131 if(IS_CONTROL(dev))
1132 return(0);
1133 rp = rp_addr(unit) + port;
1134 cp = &rp->rp_channel;
1135 tp = rp->rp_tty;
1136
1137 oldspl = spltty();
1138 (*linesw[tp->t_line].l_close)(tp, flag);
1458 rp_disc_optim(tp, &tp->t_termios, rp);
1139 rp_disc_optim(tp, &tp->t_termios);
1459 rpstop(tp, FREAD | FWRITE);
1460 rphardclose(rp);
1461
1462 tp->t_state &= ~TS_BUSY;
1463 ttyclose(tp);
1464
1465 splx(oldspl);
1466
1140 rpstop(tp, FREAD | FWRITE);
1141 rphardclose(rp);
1142
1143 tp->t_state &= ~TS_BUSY;
1144 ttyclose(tp);
1145
1146 splx(oldspl);
1147
1148 device_unbusy(rp->rp_ctlp->dev);
1149
1467 return(0);
1468}
1469
1470static void
1471rphardclose(struct rp_port *rp)
1472{
1473 int mynor;
1474 struct tty *tp;

--- 25 unchanged lines hidden (view full) ---

1500
1501 rp->active_out = FALSE;
1502 wakeup(&rp->active_out);
1503 wakeup(TSA_CARR_ON(tp));
1504}
1505
1506static
1507int
1150 return(0);
1151}
1152
1153static void
1154rphardclose(struct rp_port *rp)
1155{
1156 int mynor;
1157 struct tty *tp;

--- 25 unchanged lines hidden (view full) ---

1183
1184 rp->active_out = FALSE;
1185 wakeup(&rp->active_out);
1186 wakeup(TSA_CARR_ON(tp));
1187}
1188
1189static
1190int
1191rpread(dev, uio, flag)
1192 dev_t dev;
1193 struct uio *uio;
1194 int flag;
1195{
1196 struct rp_port *rp;
1197 struct tty *tp;
1198 int unit, mynor, umynor, port, error = 0; /* SG */
1199
1200 umynor = (((minor(dev) >> 16) -1) * 32); /* SG */
1201 port = (minor(dev) & 0x1f); /* SG */
1202 mynor = (port + umynor); /* SG */
1203 unit = minor_to_unit[mynor]; /* SG */
1204
1205 if(IS_CONTROL(dev))
1206 return(ENODEV);
1207 rp = rp_addr(unit) + port;
1208 tp = rp->rp_tty;
1209 error = (*linesw[tp->t_line].l_read)(tp, uio, flag);
1210 return(error);
1211}
1212
1213static
1214int
1508rpwrite(dev, uio, flag)
1509 dev_t dev;
1510 struct uio *uio;
1511 int flag;
1512{
1513 struct rp_port *rp;
1514 struct tty *tp;
1515 int unit, mynor, port, umynor, error = 0; /* SG */

--- 38 unchanged lines hidden (view full) ---

1554{
1555 struct rp_port *rp;
1556 CHANNEL_t *cp;
1557 struct tty *tp;
1558 int unit, mynor, port, umynor; /* SG */
1559 int oldspl;
1560 int error = 0;
1561 int arg, flags, result, ChanStatus;
1215rpwrite(dev, uio, flag)
1216 dev_t dev;
1217 struct uio *uio;
1218 int flag;
1219{
1220 struct rp_port *rp;
1221 struct tty *tp;
1222 int unit, mynor, port, umynor, error = 0; /* SG */

--- 38 unchanged lines hidden (view full) ---

1261{
1262 struct rp_port *rp;
1263 CHANNEL_t *cp;
1264 struct tty *tp;
1265 int unit, mynor, port, umynor; /* SG */
1266 int oldspl;
1267 int error = 0;
1268 int arg, flags, result, ChanStatus;
1562 int oldcmd;
1563 struct termios term, *t;
1269 struct termios *t;
1564
1565 umynor = (((minor(dev) >> 16) -1) * 32); /* SG */
1566 port = (minor(dev) & 0x1f); /* SG */
1567 mynor = (port + umynor); /* SG */
1568 unit = minor_to_unit[mynor];
1569 rp = rp_addr(unit) + port;
1570
1571 if(IS_CONTROL(dev)) {

--- 53 unchanged lines hidden (view full) ---

1625 | (dt->c_iflag & ~lt->c_iflag);
1626 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
1627 | (dt->c_oflag & ~lt->c_oflag);
1628 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
1629 | (dt->c_cflag & ~lt->c_cflag);
1630 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
1631 | (dt->c_lflag & ~lt->c_lflag);
1632 for(cc = 0; cc < NCCS; ++cc)
1270
1271 umynor = (((minor(dev) >> 16) -1) * 32); /* SG */
1272 port = (minor(dev) & 0x1f); /* SG */
1273 mynor = (port + umynor); /* SG */
1274 unit = minor_to_unit[mynor];
1275 rp = rp_addr(unit) + port;
1276
1277 if(IS_CONTROL(dev)) {

--- 53 unchanged lines hidden (view full) ---

1331 | (dt->c_iflag & ~lt->c_iflag);
1332 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
1333 | (dt->c_oflag & ~lt->c_oflag);
1334 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
1335 | (dt->c_cflag & ~lt->c_cflag);
1336 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
1337 | (dt->c_lflag & ~lt->c_lflag);
1338 for(cc = 0; cc < NCCS; ++cc)
1633 if((lt->c_cc[cc] = tp->t_cc[cc]) != 0)
1339 if(lt->c_cc[cc] != 0)
1634 dt->c_cc[cc] = tp->t_cc[cc];
1635 if(lt->c_ispeed != 0)
1636 dt->c_ispeed = tp->t_ispeed;
1637 if(lt->c_ospeed != 0)
1638 dt->c_ospeed = tp->t_ospeed;
1639 }
1640
1641 t = &tp->t_termios;
1642
1643 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
1644 if(error != ENOIOCTL) {
1645 return(error);
1646 }
1647 oldspl = spltty();
1648
1649 flags = rp->rp_channel.TxControl[3];
1650
1651 error = ttioctl(tp, cmd, data, flag);
1652 flags = rp->rp_channel.TxControl[3];
1340 dt->c_cc[cc] = tp->t_cc[cc];
1341 if(lt->c_ispeed != 0)
1342 dt->c_ispeed = tp->t_ispeed;
1343 if(lt->c_ospeed != 0)
1344 dt->c_ospeed = tp->t_ospeed;
1345 }
1346
1347 t = &tp->t_termios;
1348
1349 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
1350 if(error != ENOIOCTL) {
1351 return(error);
1352 }
1353 oldspl = spltty();
1354
1355 flags = rp->rp_channel.TxControl[3];
1356
1357 error = ttioctl(tp, cmd, data, flag);
1358 flags = rp->rp_channel.TxControl[3];
1653 rp_disc_optim(tp, &tp->t_termios, rp);
1359 rp_disc_optim(tp, &tp->t_termios);
1654 if(error != ENOIOCTL) {
1655 splx(oldspl);
1656 return(error);
1657 }
1658 switch(cmd) {
1659 case TIOCSBRK:
1660 sSendBreak(&rp->rp_channel);
1661 break;

--- 16 unchanged lines hidden (view full) ---

1678 flags = 0;
1679 if(arg & TIOCM_RTS)
1680 flags |= SET_RTS;
1681 if(arg & TIOCM_DTR)
1682 flags |= SET_DTR;
1683 rp->rp_channel.TxControl[3] =
1684 ((rp->rp_channel.TxControl[3]
1685 & ~(SET_RTS | SET_DTR)) | flags);
1360 if(error != ENOIOCTL) {
1361 splx(oldspl);
1362 return(error);
1363 }
1364 switch(cmd) {
1365 case TIOCSBRK:
1366 sSendBreak(&rp->rp_channel);
1367 break;

--- 16 unchanged lines hidden (view full) ---

1384 flags = 0;
1385 if(arg & TIOCM_RTS)
1386 flags |= SET_RTS;
1387 if(arg & TIOCM_DTR)
1388 flags |= SET_DTR;
1389 rp->rp_channel.TxControl[3] =
1390 ((rp->rp_channel.TxControl[3]
1391 & ~(SET_RTS | SET_DTR)) | flags);
1686 sOutDW(rp->rp_channel.IndexAddr,
1392 rp_writech4(&rp->rp_channel,_INDX_ADDR,
1687 *(DWord_t *) &(rp->rp_channel.TxControl[0]));
1688 break;
1689 case TIOCMBIS:
1690 arg = *(int *) data;
1691 flags = 0;
1692 if(arg & TIOCM_RTS)
1693 flags |= SET_RTS;
1694 if(arg & TIOCM_DTR)
1695 flags |= SET_DTR;
1696 rp->rp_channel.TxControl[3] |= flags;
1393 *(DWord_t *) &(rp->rp_channel.TxControl[0]));
1394 break;
1395 case TIOCMBIS:
1396 arg = *(int *) data;
1397 flags = 0;
1398 if(arg & TIOCM_RTS)
1399 flags |= SET_RTS;
1400 if(arg & TIOCM_DTR)
1401 flags |= SET_DTR;
1402 rp->rp_channel.TxControl[3] |= flags;
1697 sOutDW(rp->rp_channel.IndexAddr,
1403 rp_writech4(&rp->rp_channel,_INDX_ADDR,
1698 *(DWord_t *) &(rp->rp_channel.TxControl[0]));
1699 break;
1700 case TIOCMBIC:
1701 arg = *(int *) data;
1702 flags = 0;
1703 if(arg & TIOCM_RTS)
1704 flags |= SET_RTS;
1705 if(arg & TIOCM_DTR)
1706 flags |= SET_DTR;
1707 rp->rp_channel.TxControl[3] &= ~flags;
1404 *(DWord_t *) &(rp->rp_channel.TxControl[0]));
1405 break;
1406 case TIOCMBIC:
1407 arg = *(int *) data;
1408 flags = 0;
1409 if(arg & TIOCM_RTS)
1410 flags |= SET_RTS;
1411 if(arg & TIOCM_DTR)
1412 flags |= SET_DTR;
1413 rp->rp_channel.TxControl[3] &= ~flags;
1708 sOutDW(rp->rp_channel.IndexAddr,
1414 rp_writech4(&rp->rp_channel,_INDX_ADDR,
1709 *(DWord_t *) &(rp->rp_channel.TxControl[0]));
1710 break;
1711
1712
1713 case TIOCMGET:
1714 ChanStatus = sGetChanStatusLo(&rp->rp_channel);
1715 flags = rp->rp_channel.TxControl[3];
1716 result = TIOCM_LE; /* always on while open for some reason */

--- 25 unchanged lines hidden (view full) ---

1742 splx(oldspl);
1743 return ENOTTY;
1744 }
1745 splx(oldspl);
1746 return(0);
1747}
1748
1749static struct speedtab baud_table[] = {
1415 *(DWord_t *) &(rp->rp_channel.TxControl[0]));
1416 break;
1417
1418
1419 case TIOCMGET:
1420 ChanStatus = sGetChanStatusLo(&rp->rp_channel);
1421 flags = rp->rp_channel.TxControl[3];
1422 result = TIOCM_LE; /* always on while open for some reason */

--- 25 unchanged lines hidden (view full) ---

1448 splx(oldspl);
1449 return ENOTTY;
1450 }
1451 splx(oldspl);
1452 return(0);
1453}
1454
1455static struct speedtab baud_table[] = {
1750 B0, 0, B50, BRD50, B75, BRD75,
1751 B110, BRD110, B134, BRD134, B150, BRD150,
1752 B200, BRD200, B300, BRD300, B600, BRD600,
1753 B1200, BRD1200, B1800, BRD1800, B2400, BRD2400,
1754 B4800, BRD4800, B9600, BRD9600, B19200, BRD19200,
1755 B38400, BRD38400, B7200, BRD7200, B14400, BRD14400,
1756 B57600, BRD57600, B76800, BRD76800,
1757 B115200, BRD115200, B230400, BRD230400,
1758 -1, -1
1456 {B0, 0}, {B50, BRD50}, {B75, BRD75},
1457 {B110, BRD110}, {B134, BRD134}, {B150, BRD150},
1458 {B200, BRD200}, {B300, BRD300}, {B600, BRD600},
1459 {B1200, BRD1200}, {B1800, BRD1800}, {B2400, BRD2400},
1460 {B4800, BRD4800}, {B9600, BRD9600}, {B19200, BRD19200},
1461 {B38400, BRD38400}, {B7200, BRD7200}, {B14400, BRD14400},
1462 {B57600, BRD57600}, {B76800, BRD76800},
1463 {B115200, BRD115200}, {B230400, BRD230400},
1464 {-1, -1}
1759};
1760
1761static int
1762rpparam(tp, t)
1763 struct tty *tp;
1764 struct termios *t;
1765{
1766 struct rp_port *rp;
1767 CHANNEL_t *cp;
1768 int unit, mynor, port, umynor; /* SG */
1769 int oldspl, cflag, iflag, oflag, lflag;
1770 int ospeed;
1465};
1466
1467static int
1468rpparam(tp, t)
1469 struct tty *tp;
1470 struct termios *t;
1471{
1472 struct rp_port *rp;
1473 CHANNEL_t *cp;
1474 int unit, mynor, port, umynor; /* SG */
1475 int oldspl, cflag, iflag, oflag, lflag;
1476 int ospeed;
1477#ifdef RPCLOCAL
1478 int devshift;
1479#endif
1771
1772
1773 umynor = (((minor(tp->t_dev) >> 16) -1) * 32); /* SG */
1774 port = (minor(tp->t_dev) & 0x1f); /* SG */
1775 mynor = (port + umynor); /* SG */
1776
1777 unit = minor_to_unit[mynor];
1778 rp = rp_addr(unit) + port;
1779 cp = &rp->rp_channel;
1780 oldspl = spltty();
1781
1782 cflag = t->c_cflag;
1480
1481
1482 umynor = (((minor(tp->t_dev) >> 16) -1) * 32); /* SG */
1483 port = (minor(tp->t_dev) & 0x1f); /* SG */
1484 mynor = (port + umynor); /* SG */
1485
1486 unit = minor_to_unit[mynor];
1487 rp = rp_addr(unit) + port;
1488 cp = &rp->rp_channel;
1489 oldspl = spltty();
1490
1491 cflag = t->c_cflag;
1492#ifdef RPCLOCAL
1493 devshift = umynor / 32;
1494 devshift = 1 << devshift;
1495 if ( devshift & RPCLOCAL ) {
1496 cflag |= CLOCAL;
1497 }
1498#endif
1783 iflag = t->c_iflag;
1784 oflag = t->c_oflag;
1785 lflag = t->c_lflag;
1786
1787 ospeed = ttspeedtab(t->c_ispeed, baud_table);
1788 if(ospeed < 0 || t->c_ispeed != t->c_ospeed)
1789 return(EINVAL);
1790

--- 64 unchanged lines hidden (view full) ---

1855 rp->rp_rts_iflow = 0;
1856 }
1857
1858 if(cflag & CRTS_IFLOW) {
1859 sEnRTSFlowCtl(cp);
1860 } else {
1861 sDisRTSFlowCtl(cp);
1862 }
1499 iflag = t->c_iflag;
1500 oflag = t->c_oflag;
1501 lflag = t->c_lflag;
1502
1503 ospeed = ttspeedtab(t->c_ispeed, baud_table);
1504 if(ospeed < 0 || t->c_ispeed != t->c_ospeed)
1505 return(EINVAL);
1506

--- 64 unchanged lines hidden (view full) ---

1571 rp->rp_rts_iflow = 0;
1572 }
1573
1574 if(cflag & CRTS_IFLOW) {
1575 sEnRTSFlowCtl(cp);
1576 } else {
1577 sDisRTSFlowCtl(cp);
1578 }
1863 rp_disc_optim(tp, t, rp);
1579 rp_disc_optim(tp, t);
1864
1865 if((cflag & CLOCAL) || (sGetChanStatusLo(cp) & CD_ACT)) {
1866 tp->t_state |= TS_CARR_ON;
1867 wakeup(TSA_CARR_ON(tp));
1868 }
1869
1870/* tp->t_state |= TS_CAN_BYPASS_L_RINT;
1871 flags = rp->rp_channel.TxControl[3];
1872 if(flags & SET_DTR)
1873 else
1874 if(flags & SET_RTS)
1875 else
1876*/
1877 splx(oldspl);
1878
1879 return(0);
1880}
1881
1882static void
1580
1581 if((cflag & CLOCAL) || (sGetChanStatusLo(cp) & CD_ACT)) {
1582 tp->t_state |= TS_CARR_ON;
1583 wakeup(TSA_CARR_ON(tp));
1584 }
1585
1586/* tp->t_state |= TS_CAN_BYPASS_L_RINT;
1587 flags = rp->rp_channel.TxControl[3];
1588 if(flags & SET_DTR)
1589 else
1590 if(flags & SET_RTS)
1591 else
1592*/
1593 splx(oldspl);
1594
1595 return(0);
1596}
1597
1598static void
1883rp_disc_optim(tp, t, rp)
1599rp_disc_optim(tp, t)
1884struct tty *tp;
1885struct termios *t;
1600struct tty *tp;
1601struct termios *t;
1886struct rp_port *rp;
1887{
1888 if(!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1889 &&(!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1890 &&(!(t->c_iflag & PARMRK)
1891 ||(t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1892 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1893 && linesw[tp->t_line].l_rint == ttyinput)
1894 tp->t_state |= TS_CAN_BYPASS_L_RINT;

--- 4 unchanged lines hidden (view full) ---

1899static void
1900rpstart(tp)
1901 struct tty *tp;
1902{
1903 struct rp_port *rp;
1904 CHANNEL_t *cp;
1905 struct clist *qp;
1906 int unit, mynor, port, umynor; /* SG */
1602{
1603 if(!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1604 &&(!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1605 &&(!(t->c_iflag & PARMRK)
1606 ||(t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1607 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1608 && linesw[tp->t_line].l_rint == ttyinput)
1609 tp->t_state |= TS_CAN_BYPASS_L_RINT;

--- 4 unchanged lines hidden (view full) ---

1614static void
1615rpstart(tp)
1616 struct tty *tp;
1617{
1618 struct rp_port *rp;
1619 CHANNEL_t *cp;
1620 struct clist *qp;
1621 int unit, mynor, port, umynor; /* SG */
1907 char ch, flags;
1622 char flags;
1908 int spl, xmit_fifo_room;
1623 int spl, xmit_fifo_room;
1909 int count;
1624 int count, wcount;
1910
1911
1912 umynor = (((minor(tp->t_dev) >> 16) -1) * 32); /* SG */
1913 port = (minor(tp->t_dev) & 0x1f); /* SG */
1914 mynor = (port + umynor); /* SG */
1915 unit = minor_to_unit[mynor];
1916 rp = rp_addr(unit) + port;
1917 cp = &rp->rp_channel;

--- 16 unchanged lines hidden (view full) ---

1934 tp->t_state &= ~TS_BUSY;
1935 }
1936 ttwwakeup(tp);
1937 splx(spl);
1938 return;
1939 }
1940 xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1941 qp = &tp->t_outq;
1625
1626
1627 umynor = (((minor(tp->t_dev) >> 16) -1) * 32); /* SG */
1628 port = (minor(tp->t_dev) & 0x1f); /* SG */
1629 mynor = (port + umynor); /* SG */
1630 unit = minor_to_unit[mynor];
1631 rp = rp_addr(unit) + port;
1632 cp = &rp->rp_channel;

--- 16 unchanged lines hidden (view full) ---

1649 tp->t_state &= ~TS_BUSY;
1650 }
1651 ttwwakeup(tp);
1652 splx(spl);
1653 return;
1654 }
1655 xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1656 qp = &tp->t_outq;
1942 count = 0;
1943 if(xmit_fifo_room > 0 && qp->c_cc > 0) {
1944 tp->t_state |= TS_BUSY;
1657 if(xmit_fifo_room > 0 && qp->c_cc > 0) {
1658 tp->t_state |= TS_BUSY;
1659 count = q_to_b( qp, rp->TxBuf, xmit_fifo_room );
1660 wcount = count >> 1;
1661 if ( wcount ) {
1662 rp_writemultich2(cp, sGetTxRxDataIO(cp), (u_int16_t *)rp->TxBuf, wcount);
1663 }
1664 if ( count & 1 ) {
1665 rp_writech1(cp, sGetTxRxDataIO(cp), rp->TxBuf[(count-1)]);
1666 }
1945 }
1667 }
1946 while(xmit_fifo_room > 0 && qp->c_cc > 0) {
1947 ch = getc(qp);
1948 sOutB(sGetTxRxDataIO(cp), ch);
1949 xmit_fifo_room--;
1950 count++;
1951 }
1952 rp->rp_restart = (qp->c_cc > 0) ? rp->rp_fifo_lw : 0;
1953
1954 ttwwakeup(tp);
1955 splx(spl);
1956}
1957
1958static
1959void

--- 31 unchanged lines hidden --- 		1668 rp->rp_restart = (qp->c_cc > 0) ? rp->rp_fifo_lw : 0;
1669
1670 ttwwakeup(tp);
1671 splx(spl);
1672}
1673
1674static
1675void

--- 31 unchanged lines hidden ---