| if_rlreg.h (50477) | if_rlreg.h (50703) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_rlreg.h 50477 1999-08-28 01:08:13Z peter $ | 32 * $FreeBSD: head/sys/pci/if_rlreg.h 50703 1999-08-31 14:45:51Z wpaul $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 255 unchanged lines hidden (view full) --- 296 */ 297 298#define RL_RX_BUF_SZ RL_RXBUF_64 299#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 300#define RL_TX_LIST_CNT 4 301#define RL_MIN_FRAMELEN 60 302#define RL_TX_EARLYTHRESH (256 << 11) 303#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 255 unchanged lines hidden (view full) --- 296 */ 297 298#define RL_RX_BUF_SZ RL_RXBUF_64 299#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 300#define RL_TX_LIST_CNT 4 301#define RL_MIN_FRAMELEN 60 302#define RL_TX_EARLYTHRESH (256 << 11) 303#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES |
| 304#define RL_RX_MAXDMA RL_RXDMA_256BYTES 305#define RL_TX_MAXDMA RL_TXDMA_256BYTES | 304#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 305#define RL_TX_MAXDMA RL_TXDMA_2048BYTES |
| 306 307#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 308#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 309 310#define RL_ETHER_ALIGN 2 311 312struct rl_chain_data { 313 u_int16_t cur_rx; --- 31 unchanged lines hidden (view full) --- 345/* 346 * MII constants 347 */ 348#define RL_MII_STARTDELIM 0x01 349#define RL_MII_READOP 0x02 350#define RL_MII_WRITEOP 0x01 351#define RL_MII_TURNAROUND 0x02 352 | 306 307#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 308#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 309 310#define RL_ETHER_ALIGN 2 311 312struct rl_chain_data { 313 u_int16_t cur_rx; --- 31 unchanged lines hidden (view full) --- 345/* 346 * MII constants 347 */ 348#define RL_MII_STARTDELIM 0x01 349#define RL_MII_READOP 0x02 350#define RL_MII_WRITEOP 0x01 351#define RL_MII_TURNAROUND 0x02 352 |
| 353#define RL_FLAG_FORCEDELAY 1 354#define RL_FLAG_SCHEDDELAY 2 355#define RL_FLAG_DELAYTIMEO 3 356 | |
| 357#define RL_8129 1 358#define RL_8139 2 359 360struct rl_softc { 361 struct arpcom arpcom; /* interface info */ | 353#define RL_8129 1 354#define RL_8139 2 355 356struct rl_softc { 357 struct arpcom arpcom; /* interface info */ |
| 362 struct ifmedia ifmedia; /* media info */ | |
| 363 bus_space_handle_t rl_bhandle; /* bus space handle */ 364 bus_space_tag_t rl_btag; /* bus space tag */ | 358 bus_space_handle_t rl_bhandle; /* bus space handle */ 359 bus_space_tag_t rl_btag; /* bus space tag */ |
| 365 struct rl_type *rl_pinfo; /* phy info */ | 360 struct resource *rl_res; 361 struct resource *rl_irq; 362 void *rl_intrhand; 363 device_t rl_miibus; |
| 366 u_int8_t rl_unit; /* interface number */ 367 u_int8_t rl_type; | 364 u_int8_t rl_unit; /* interface number */ 365 u_int8_t rl_type; |
| 368 u_int8_t rl_phy_addr; /* PHY address */ 369 u_int8_t rl_tx_pend; /* TX pending */ 370 u_int8_t rl_want_auto; 371 u_int8_t rl_autoneg; | |
| 372 u_int8_t rl_stats_no_timeout; 373 struct rl_chain_data rl_cdata; | 366 u_int8_t rl_stats_no_timeout; 367 struct rl_chain_data rl_cdata; |
| 368 struct callout_handle rl_stat_ch; |
|
| 374}; 375 376/* 377 * register space access macros 378 */ 379#define CSR_WRITE_4(sc, reg, val) \ 380 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 381#define CSR_WRITE_2(sc, reg, val) \ --- 49 unchanged lines hidden (view full) --- 431#define ADDTRON_VENDORID 0x4033 432 433/* 434 * Addtron device IDs. 435 */ 436#define ADDTRON_DEVICEID_8139 0x1360 437 438/* | 369}; 370 371/* 372 * register space access macros 373 */ 374#define CSR_WRITE_4(sc, reg, val) \ 375 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 376#define CSR_WRITE_2(sc, reg, val) \ --- 49 unchanged lines hidden (view full) --- 426#define ADDTRON_VENDORID 0x4033 427 428/* 429 * Addtron device IDs. 430 */ 431#define ADDTRON_DEVICEID_8139 0x1360 432 433/* |
| 439 * Texas Instruments PHY identifiers 440 */ 441#define TI_PHY_VENDORID 0x4000 442#define TI_PHY_10BT 0x501F 443#define TI_PHY_100VGPMI 0x502F 444 445/* 446 * These ID values are for the NS DP83840A 10/100 PHY 447 */ 448#define NS_PHY_VENDORID 0x2000 449#define NS_PHY_83840A 0x5C0F 450 451/* 452 * Level 1 10/100 PHY 453 */ 454#define LEVEL1_PHY_VENDORID 0x7810 455#define LEVEL1_PHY_LXT970 0x000F 456 457/* 458 * Intel 82555 10/100 PHY 459 */ 460#define INTEL_PHY_VENDORID 0x0A28 461#define INTEL_PHY_82555 0x015F 462 463/* 464 * SEEQ 80220 10/100 PHY 465 */ 466#define SEEQ_PHY_VENDORID 0x0016 467#define SEEQ_PHY_80220 0xF83F 468 469 470/* | |
| 471 * PCI low memory base and low I/O base register, and | 434 * PCI low memory base and low I/O base register, and |
| 472 * other PCI registers. Note: some are only available on 473 * the 3c905B, in particular those that related to power management. | 435 * other PCI registers. |
| 474 */ 475 476#define RL_PCI_VENDOR_ID 0x00 477#define RL_PCI_DEVICE_ID 0x02 478#define RL_PCI_COMMAND 0x04 479#define RL_PCI_STATUS 0x06 480#define RL_PCI_CLASSCODE 0x09 481#define RL_PCI_LATENCY_TIMER 0x0D --- 16 unchanged lines hidden (view full) --- 498#define RL_PSTATE_MASK 0x0003 499#define RL_PSTATE_D0 0x0000 500#define RL_PSTATE_D1 0x0002 501#define RL_PSTATE_D2 0x0002 502#define RL_PSTATE_D3 0x0003 503#define RL_PME_EN 0x0010 504#define RL_PME_STATUS 0x8000 505 | 436 */ 437 438#define RL_PCI_VENDOR_ID 0x00 439#define RL_PCI_DEVICE_ID 0x02 440#define RL_PCI_COMMAND 0x04 441#define RL_PCI_STATUS 0x06 442#define RL_PCI_CLASSCODE 0x09 443#define RL_PCI_LATENCY_TIMER 0x0D --- 16 unchanged lines hidden (view full) --- 460#define RL_PSTATE_MASK 0x0003 461#define RL_PSTATE_D0 0x0000 462#define RL_PSTATE_D1 0x0002 463#define RL_PSTATE_D2 0x0002 464#define RL_PSTATE_D3 0x0003 465#define RL_PME_EN 0x0010 466#define RL_PME_STATUS 0x8000 467 |
| 506#define PHY_UNKNOWN 6 507 508#define RL_PHYADDR_MIN 0x00 509#define RL_PHYADDR_MAX 0x1F 510 511#define PHY_BMCR 0x00 512#define PHY_BMSR 0x01 513#define PHY_VENID 0x02 514#define PHY_DEVID 0x03 515#define PHY_ANAR 0x04 516#define PHY_LPAR 0x05 517#define PHY_ANEXP 0x06 518 519#define PHY_ANAR_NEXTPAGE 0x8000 520#define PHY_ANAR_RSVD0 0x4000 521#define PHY_ANAR_TLRFLT 0x2000 522#define PHY_ANAR_RSVD1 0x1000 523#define PHY_ANAR_RSVD2 0x0800 524#define PHY_ANAR_RSVD3 0x0400 525#define PHY_ANAR_100BT4 0x0200 526#define PHY_ANAR_100BTXFULL 0x0100 527#define PHY_ANAR_100BTXHALF 0x0080 528#define PHY_ANAR_10BTFULL 0x0040 529#define PHY_ANAR_10BTHALF 0x0020 530#define PHY_ANAR_PROTO4 0x0010 531#define PHY_ANAR_PROTO3 0x0008 532#define PHY_ANAR_PROTO2 0x0004 533#define PHY_ANAR_PROTO1 0x0002 534#define PHY_ANAR_PROTO0 0x0001 535 536/* 537 * These are the register definitions for the PHY (physical layer 538 * interface chip). 539 */ 540/* 541 * PHY BMCR Basic Mode Control Register 542 */ 543#define PHY_BMCR_RESET 0x8000 544#define PHY_BMCR_LOOPBK 0x4000 545#define PHY_BMCR_SPEEDSEL 0x2000 546#define PHY_BMCR_AUTONEGENBL 0x1000 547#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 548#define PHY_BMCR_ISOLATE 0x0400 549#define PHY_BMCR_AUTONEGRSTR 0x0200 550#define PHY_BMCR_DUPLEX 0x0100 551#define PHY_BMCR_COLLTEST 0x0080 552#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 553#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 554#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 555#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 556#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 557#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 558#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 559/* 560 * RESET: 1 == software reset, 0 == normal operation 561 * Resets status and control registers to default values. 562 * Relatches all hardware config values. 563 * 564 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 565 * 566 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 567 * Link speed is selected byt his bit or if auto-negotiation if bit 568 * 12 (AUTONEGENBL) is set (in which case the value of this register 569 * is ignored). 570 * 571 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 572 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 573 * determine speed and mode. Should be cleared and then set if PHY configured 574 * for no autoneg on startup. 575 * 576 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 577 * 578 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 579 * 580 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 581 * 582 * COLLTEST: 1 == collision test enabled, 0 == normal operation 583 */ 584 585/* 586 * PHY, BMSR Basic Mode Status Register 587 */ 588#define PHY_BMSR_100BT4 0x8000 589#define PHY_BMSR_100BTXFULL 0x4000 590#define PHY_BMSR_100BTXHALF 0x2000 591#define PHY_BMSR_10BTFULL 0x1000 592#define PHY_BMSR_10BTHALF 0x0800 593#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 594#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 595#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 596#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 597#define PHY_BMSR_MFPRESUP 0x0040 598#define PHY_BMSR_AUTONEGCOMP 0x0020 599#define PHY_BMSR_REMFAULT 0x0010 600#define PHY_BMSR_CANAUTONEG 0x0008 601#define PHY_BMSR_LINKSTAT 0x0004 602#define PHY_BMSR_JABBER 0x0002 603#define PHY_BMSR_EXTENDED 0x0001 | |
| 604#ifdef __alpha__ 605#undef vtophys 606#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 607#endif | 468#ifdef __alpha__ 469#undef vtophys 470#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 471#endif |
| 608 | |