1/*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
| 1/*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
|
33 */
34
35/*
36 * RealTek 8129/8139 register offsets
37 */
38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40#define RL_IDR2 0x0002
41#define RL_IDR3 0x0003
42#define RL_IDR4 0x0004
43#define RL_IDR5 0x0005
44 /* 0006-0007 reserved */
45#define RL_MAR0 0x0008 /* Multicast hash table */
46#define RL_MAR1 0x0009
47#define RL_MAR2 0x000A
48#define RL_MAR3 0x000B
49#define RL_MAR4 0x000C
50#define RL_MAR5 0x000D
51#define RL_MAR6 0x000E
52#define RL_MAR7 0x000F
53
54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */
55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */
56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */
57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */
58
59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */
60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */
61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */
62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */
63
64#define RL_RXADDR 0x0030 /* RX ring start address */
65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */
66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */
67#define RL_COMMAND 0x0037 /* command register */
68#define RL_CURRXADDR 0x0038 /* current address of packet read */
69#define RL_CURRXBUF 0x003A /* current RX buffer address */
70#define RL_IMR 0x003C /* interrupt mask register */
71#define RL_ISR 0x003E /* interrupt status register */
72#define RL_TXCFG 0x0040 /* transmit config */
73#define RL_RXCFG 0x0044 /* receive config */
74#define RL_TIMERCNT 0x0048 /* timer count register */
75#define RL_MISSEDPKT 0x004C /* missed packet counter */
76#define RL_EECMD 0x0050 /* EEPROM command register */
77
78/* RTL8139/RTL8139C+ only */
79#define RL_8139_CFG0 0x0051 /* config register #0 */
80#define RL_8139_CFG1 0x0052 /* config register #1 */
81#define RL_8139_CFG3 0x0059 /* config register #3 */
82#define RL_8139_CFG4 0x005A /* config register #4 */
83#define RL_8139_CFG5 0x00D8 /* config register #5 */
84
85#define RL_CFG0 0x0051 /* config register #0 */
86#define RL_CFG1 0x0052 /* config register #1 */
87#define RL_CFG2 0x0053 /* config register #2 */
88#define RL_CFG3 0x0054 /* config register #3 */
89#define RL_CFG4 0x0055 /* config register #4 */
90#define RL_CFG5 0x0056 /* config register #5 */
91 /* 0057 reserved */
92#define RL_MEDIASTAT 0x0058 /* media status register (8139) */
93 /* 0059-005A reserved */
94#define RL_MII 0x005A /* 8129 chip only */
95#define RL_HALTCLK 0x005B
96#define RL_MULTIINTR 0x005C /* multiple interrupt */
97#define RL_PCIREV 0x005E /* PCI revision value */
98 /* 005F reserved */
99#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */
100
101/* Direct PHY access registers only available on 8139 */
102#define RL_BMCR 0x0062 /* PHY basic mode control */
103#define RL_BMSR 0x0064 /* PHY basic mode status */
104#define RL_ANAR 0x0066 /* PHY autoneg advert */
105#define RL_LPAR 0x0068 /* PHY link partner ability */
106#define RL_ANER 0x006A /* PHY autoneg expansion */
107
108#define RL_DISCCNT 0x006C /* disconnect counter */
109#define RL_FALSECAR 0x006E /* false carrier counter */
110#define RL_NWAYTST 0x0070 /* NWAY test register */
111#define RL_RX_ER 0x0072 /* RX_ER counter */
112#define RL_CSCFG 0x0074 /* CS configuration register */
113
114/*
115 * When operating in special C+ mode, some of the registers in an
116 * 8139C+ chip have different definitions. These are also used for
117 * the 8169 gigE chip.
118 */
119#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */
120#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */
121#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */
122#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */
123#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */
124#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */
125#define RL_CFG2 0x0053
126#define RL_TIMERINT 0x0054 /* interrupt on timer expire */
127#define RL_TXSTART 0x00D9 /* 8 bits */
128#define RL_CPLUS_CMD 0x00E0 /* 16 bits */
129#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */
130#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */
131#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */
132
133/*
134 * Registers specific to the 8169 gigE chip
135 */
136#define RL_GTXSTART 0x0038 /* 8 bits */
137#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */
138#define RL_PHYAR 0x0060
139#define RL_TBICSR 0x0064
140#define RL_TBI_ANAR 0x0068
141#define RL_TBI_LPAR 0x006A
142#define RL_GMEDIASTAT 0x006C /* 8 bits */
143#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */
144#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */
145#define RL_PMCH 0x006F /* 8 bits */
146#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
147#define RL_INTRMOD 0x00E2 /* 16 bits */
148#define RL_MISC 0x00F0
149
150/*
151 * TX config register bits
152 */
153#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
154#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
155#define RL_TXCFG_QUEUE_EMPTY 0x00000800 /* 8168E-VL or higher */
156#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
157#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
158#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */
159#define RL_TXCFG_IFG 0x03000000 /* interframe gap */
160#define RL_TXCFG_HWREV 0x7CC00000
161
162#define RL_LOOPTEST_OFF 0x00000000
163#define RL_LOOPTEST_ON 0x00020000
164#define RL_LOOPTEST_ON_CPLUS 0x00060000
165
166/* Known revision codes. */
167#define RL_HWREV_8169 0x00000000
168#define RL_HWREV_8169S 0x00800000
169#define RL_HWREV_8110S 0x04000000
170#define RL_HWREV_8169_8110SB 0x10000000
171#define RL_HWREV_8169_8110SC 0x18000000
172#define RL_HWREV_8401E 0x24000000
173#define RL_HWREV_8102EL 0x24800000
174#define RL_HWREV_8102EL_SPIN1 0x24C00000
175#define RL_HWREV_8168D 0x28000000
176#define RL_HWREV_8168DP 0x28800000
177#define RL_HWREV_8168E 0x2C000000
178#define RL_HWREV_8168E_VL 0x2C800000
179#define RL_HWREV_8168B_SPIN1 0x30000000
180#define RL_HWREV_8100E 0x30800000
181#define RL_HWREV_8101E 0x34000000
182#define RL_HWREV_8102E 0x34800000
183#define RL_HWREV_8103E 0x34C00000
184#define RL_HWREV_8168B_SPIN2 0x38000000
185#define RL_HWREV_8168B_SPIN3 0x38400000
186#define RL_HWREV_8168C 0x3C000000
187#define RL_HWREV_8168C_SPIN2 0x3C400000
188#define RL_HWREV_8168CP 0x3C800000
189#define RL_HWREV_8105E 0x40800000
190#define RL_HWREV_8105E_SPIN1 0x40C00000
191#define RL_HWREV_8402 0x44000000
192#define RL_HWREV_8106E 0x44800000
193#define RL_HWREV_8168F 0x48000000
194#define RL_HWREV_8411 0x48800000
195#define RL_HWREV_8168G 0x4C000000
196#define RL_HWREV_8168EP 0x50000000
197#define RL_HWREV_8168GU 0x50800000
198#define RL_HWREV_8411B 0x5C800000
199#define RL_HWREV_8139 0x60000000
200#define RL_HWREV_8139A 0x70000000
201#define RL_HWREV_8139AG 0x70800000
202#define RL_HWREV_8139B 0x78000000
203#define RL_HWREV_8130 0x7C000000
204#define RL_HWREV_8139C 0x74000000
205#define RL_HWREV_8139D 0x74400000
206#define RL_HWREV_8139CPLUS 0x74800000
207#define RL_HWREV_8101 0x74C00000
208#define RL_HWREV_8100 0x78800000
209#define RL_HWREV_8169_8110SBL 0x7CC00000
210#define RL_HWREV_8169_8110SCE 0x98000000
211
212#define RL_TXDMA_16BYTES 0x00000000
213#define RL_TXDMA_32BYTES 0x00000100
214#define RL_TXDMA_64BYTES 0x00000200
215#define RL_TXDMA_128BYTES 0x00000300
216#define RL_TXDMA_256BYTES 0x00000400
217#define RL_TXDMA_512BYTES 0x00000500
218#define RL_TXDMA_1024BYTES 0x00000600
219#define RL_TXDMA_2048BYTES 0x00000700
220
221/*
222 * Transmit descriptor status register bits.
223 */
224#define RL_TXSTAT_LENMASK 0x00001FFF
225#define RL_TXSTAT_OWN 0x00002000
226#define RL_TXSTAT_TX_UNDERRUN 0x00004000
227#define RL_TXSTAT_TX_OK 0x00008000
228#define RL_TXSTAT_EARLY_THRESH 0x003F0000
229#define RL_TXSTAT_COLLCNT 0x0F000000
230#define RL_TXSTAT_CARR_HBEAT 0x10000000
231#define RL_TXSTAT_OUTOFWIN 0x20000000
232#define RL_TXSTAT_TXABRT 0x40000000
233#define RL_TXSTAT_CARRLOSS 0x80000000
234
235/*
236 * Interrupt status register bits.
237 */
238#define RL_ISR_RX_OK 0x0001
239#define RL_ISR_RX_ERR 0x0002
240#define RL_ISR_TX_OK 0x0004
241#define RL_ISR_TX_ERR 0x0008
242#define RL_ISR_RX_OVERRUN 0x0010
243#define RL_ISR_PKT_UNDERRUN 0x0020
244#define RL_ISR_LINKCHG 0x0020 /* 8169 only */
245#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
246#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */
247#define RL_ISR_SWI 0x0100 /* C+ only */
248#define RL_ISR_CABLE_LEN_CHGD 0x2000
249#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
250#define RL_ISR_TIMEOUT_EXPIRED 0x4000
251#define RL_ISR_SYSTEM_ERR 0x8000
252
253#define RL_INTRS \
254 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
255 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
256 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
257
258#ifdef RE_TX_MODERATION
259#define RL_INTRS_CPLUS \
260 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
261 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
262 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
263#else
264#define RL_INTRS_CPLUS \
265 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \
266 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
267 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
268#endif
269
270/*
271 * Media status register. (8139 only)
272 */
273#define RL_MEDIASTAT_RXPAUSE 0x01
274#define RL_MEDIASTAT_TXPAUSE 0x02
275#define RL_MEDIASTAT_LINK 0x04
276#define RL_MEDIASTAT_SPEED10 0x08
277#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
278#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */
279
280/*
281 * Receive config register.
282 */
283#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */
284#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */
285#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */
286#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */
287#define RL_RXCFG_RX_RUNT 0x00000010
288#define RL_RXCFG_RX_ERRPKT 0x00000020
289#define RL_RXCFG_WRAP 0x00000080
290#define RL_RXCFG_EARLYOFFV2 0x00000800
291#define RL_RXCFG_MAXDMA 0x00000700
292#define RL_RXCFG_BUFSZ 0x00001800
293#define RL_RXCFG_EARLYOFF 0x00003800
294#define RL_RXCFG_FIFOTHRESH 0x0000E000
295#define RL_RXCFG_EARLYTHRESH 0x07000000
296
297#define RL_RXDMA_16BYTES 0x00000000
298#define RL_RXDMA_32BYTES 0x00000100
299#define RL_RXDMA_64BYTES 0x00000200
300#define RL_RXDMA_128BYTES 0x00000300
301#define RL_RXDMA_256BYTES 0x00000400
302#define RL_RXDMA_512BYTES 0x00000500
303#define RL_RXDMA_1024BYTES 0x00000600
304#define RL_RXDMA_UNLIMITED 0x00000700
305
306#define RL_RXBUF_8 0x00000000
307#define RL_RXBUF_16 0x00000800
308#define RL_RXBUF_32 0x00001000
309#define RL_RXBUF_64 0x00001800
310
311#define RL_RXFIFO_16BYTES 0x00000000
312#define RL_RXFIFO_32BYTES 0x00002000
313#define RL_RXFIFO_64BYTES 0x00004000
314#define RL_RXFIFO_128BYTES 0x00006000
315#define RL_RXFIFO_256BYTES 0x00008000
316#define RL_RXFIFO_512BYTES 0x0000A000
317#define RL_RXFIFO_1024BYTES 0x0000C000
318#define RL_RXFIFO_NOTHRESH 0x0000E000
319
320/*
321 * Bits in RX status header (included with RX'ed packet
322 * in ring buffer).
323 */
324#define RL_RXSTAT_RXOK 0x00000001
325#define RL_RXSTAT_ALIGNERR 0x00000002
326#define RL_RXSTAT_CRCERR 0x00000004
327#define RL_RXSTAT_GIANT 0x00000008
328#define RL_RXSTAT_RUNT 0x00000010
329#define RL_RXSTAT_BADSYM 0x00000020
330#define RL_RXSTAT_BROAD 0x00002000
331#define RL_RXSTAT_INDIV 0x00004000
332#define RL_RXSTAT_MULTI 0x00008000
333#define RL_RXSTAT_LENMASK 0xFFFF0000
334#define RL_RXSTAT_UNFINISHED 0x0000FFF0 /* DMA still in progress */
335
336/*
337 * Command register.
338 */
339#define RL_CMD_EMPTY_RXBUF 0x0001
340#define RL_CMD_TX_ENB 0x0004
341#define RL_CMD_RX_ENB 0x0008
342#define RL_CMD_RESET 0x0010
343#define RL_CMD_STOPREQ 0x0080
344
345/*
346 * Twister register values. These are completely undocumented and derived
347 * from public sources.
348 */
349#define RL_CSCFG_LINK_OK 0x0400
350#define RL_CSCFG_CHANGE 0x0800
351#define RL_CSCFG_STATUS 0xf000
352#define RL_CSCFG_ROW3 0x7000
353#define RL_CSCFG_ROW2 0x3000
354#define RL_CSCFG_ROW1 0x1000
355#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0
356#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0
357
358#define RL_NWAYTST_RESET 0
359#define RL_NWAYTST_CBL_TEST 0x20
360
361#define RL_PARA78 0x78
362#define RL_PARA78_DEF 0x78fa8388
363#define RL_PARA7C 0x7C
364#define RL_PARA7C_DEF 0xcb38de43
365#define RL_PARA7C_RETUNE 0xfb38de03
366
367/*
368 * EEPROM control register
369 */
370#define RL_EE_DATAOUT 0x01 /* Data out */
371#define RL_EE_DATAIN 0x02 /* Data in */
372#define RL_EE_CLK 0x04 /* clock */
373#define RL_EE_SEL 0x08 /* chip select */
374#define RL_EE_MODE (0x40|0x80)
375
376#define RL_EEMODE_OFF 0x00
377#define RL_EEMODE_AUTOLOAD 0x40
378#define RL_EEMODE_PROGRAM 0x80
379#define RL_EEMODE_WRITECFG (0x80|0x40)
380
381/* 9346 EEPROM commands */
382#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */
383#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */
384
385#define RL_9346_WRITE 0x5
386#define RL_9346_READ 0x6
387#define RL_9346_ERASE 0x7
388#define RL_9346_EWEN 0x4
389#define RL_9346_EWEN_ADDR 0x30
390#define RL_9456_EWDS 0x4
391#define RL_9346_EWDS_ADDR 0x00
392
393#define RL_EECMD_WRITE 0x140
394#define RL_EECMD_READ_6BIT 0x180
395#define RL_EECMD_READ_8BIT 0x600
396#define RL_EECMD_ERASE 0x1c0
397
398#define RL_EE_ID 0x00
399#define RL_EE_PCI_VID 0x01
400#define RL_EE_PCI_DID 0x02
401/* Location of station address inside EEPROM */
402#define RL_EE_EADDR 0x07
403
404/*
405 * MII register (8129 only)
406 */
407#define RL_MII_CLK 0x01
408#define RL_MII_DATAIN 0x02
409#define RL_MII_DATAOUT 0x04
410#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */
411
412/*
413 * Config 0 register
414 */
415#define RL_CFG0_ROM0 0x01
416#define RL_CFG0_ROM1 0x02
417#define RL_CFG0_ROM2 0x04
418#define RL_CFG0_PL0 0x08
419#define RL_CFG0_PL1 0x10
420#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */
421#define RL_CFG0_PCS 0x40
422#define RL_CFG0_SCR 0x80
423
424/*
425 * Config 1 register
426 */
427#define RL_CFG1_PWRDWN 0x01
428#define RL_CFG1_PME 0x01
429#define RL_CFG1_SLEEP 0x02
430#define RL_CFG1_VPDEN 0x02
431#define RL_CFG1_IOMAP 0x04
432#define RL_CFG1_MEMMAP 0x08
433#define RL_CFG1_RSVD 0x10
434#define RL_CFG1_LWACT 0x10
435#define RL_CFG1_DRVLOAD 0x20
436#define RL_CFG1_LED0 0x40
437#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
438#define RL_CFG1_LED1 0x80
439
440/*
441 * Config 2 register
442 */
443#define RL_CFG2_PCI33MHZ 0x00
444#define RL_CFG2_PCI66MHZ 0x01
445#define RL_CFG2_PCI64BIT 0x08
446#define RL_CFG2_AUXPWR 0x10
447#define RL_CFG2_MSI 0x20
448
449/*
450 * Config 3 register
451 */
452#define RL_CFG3_GRANTSEL 0x80
453#define RL_CFG3_WOL_MAGIC 0x20
454#define RL_CFG3_WOL_LINK 0x10
455#define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */
456#define RL_CFG3_FAST_B2B 0x01
457
458/*
459 * Config 4 register
460 */
461#define RL_CFG4_LWPTN 0x04
462#define RL_CFG4_LWPME 0x10
463#define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */
464
465/*
466 * Config 5 register
467 */
468#define RL_CFG5_WOL_BCAST 0x40
469#define RL_CFG5_WOL_MCAST 0x20
470#define RL_CFG5_WOL_UCAST 0x10
471#define RL_CFG5_WOL_LANWAKE 0x02
472#define RL_CFG5_PME_STS 0x01
473
474/*
475 * 8139C+ register definitions
476 */
477
478/* RL_DUMPSTATS_LO register */
479#define RL_DUMPSTATS_START 0x00000008
480
481/* Transmit start register */
482#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */
483#define RL_TXSTART_START 0x40 /* start normal queue transmit */
484#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
485
486/*
487 * Config 2 register, 8139C+/8169/8169S/8110S only
488 */
489#define RL_CFG2_BUSFREQ 0x07
490#define RL_CFG2_BUSWIDTH 0x08
491#define RL_CFG2_AUXPWRSTS 0x10
492
493#define RL_BUSFREQ_33MHZ 0x00
494#define RL_BUSFREQ_66MHZ 0x01
495
496#define RL_BUSWIDTH_32BITS 0x00
497#define RL_BUSWIDTH_64BITS 0x08
498
499/* C+ mode command register */
500#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
501#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
502#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
503#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
504#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
505#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
506#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */
507#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */
508#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */
509#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */
510#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */
511#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */
512#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */
513#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */
514#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */
515
516/* C+ early transmit threshold */
517#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
518
519/* Timer interrupt register */
520#define RL_TIMERINT_8169_VAL 0x00001FFF
521#define RL_TIMER_MIN 0
522#define RL_TIMER_MAX 65 /* 65.528us */
523#define RL_TIMER_DEFAULT RL_TIMER_MAX
524#define RL_TIMER_PCIE_CLK 125 /* 125MHZ */
525#define RL_USECS(x) ((x) * RL_TIMER_PCIE_CLK)
526
527/*
528 * Gigabit PHY access register (8169 only)
529 */
530#define RL_PHYAR_PHYDATA 0x0000FFFF
531#define RL_PHYAR_PHYREG 0x001F0000
532#define RL_PHYAR_BUSY 0x80000000
533
534/*
535 * Gigabit media status (8169 only)
536 */
537#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */
538#define RL_GMEDIASTAT_LINK 0x02 /* link up */
539#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */
540#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */
541#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */
542#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */
543#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */
544#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */
545
546/*
547 * The RealTek doesn't use a fragment-based descriptor mechanism.
548 * Instead, there are only four register sets, each or which represents
549 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
550 * packet buffer (32-bit aligned!) and we place the buffer addresses in
551 * the registers so the chip knows where they are.
552 *
553 * We can sort of kludge together the same kind of buffer management
554 * used in previous drivers, but we have to do buffer copies almost all
555 * the time, so it doesn't really buy us much.
556 *
557 * For reception, there's just one large buffer where the chip stores
558 * all received packets.
559 */
560#define RL_RX_BUF_SZ RL_RXBUF_64
561#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13))
562#define RL_TX_LIST_CNT 4
563#define RL_MIN_FRAMELEN 60
564#define RL_TX_8139_BUF_ALIGN 4
565#define RL_RX_8139_BUF_ALIGN 8
566#define RL_RX_8139_BUF_RESERVE sizeof(int64_t)
567#define RL_RX_8139_BUF_GUARD_SZ \
568 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE)
569#define RL_TXTHRESH(x) ((x) << 11)
570#define RL_TX_THRESH_INIT 96
571#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH
572#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED
573#define RL_TX_MAXDMA RL_TXDMA_2048BYTES
574
575#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
576#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA)
577
578#define RL_ETHER_ALIGN 2
579
580/*
581 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets.
582 */
583#define RL_IP4CSUMTX_MINLEN 28
584#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN)
585
586struct rl_chain_data {
587 uint16_t cur_rx;
588 uint8_t *rl_rx_buf;
589 uint8_t *rl_rx_buf_ptr;
590
591 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT];
592 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT];
593 bus_dma_tag_t rl_tx_tag;
594 bus_dma_tag_t rl_rx_tag;
595 bus_dmamap_t rl_rx_dmamap;
596 bus_addr_t rl_rx_buf_paddr;
597 uint8_t last_tx;
598 uint8_t cur_tx;
599};
600
601#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT)
602#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
603#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
604#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
605#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
606#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
607#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
608#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
609#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
610
611struct rl_type {
612 uint16_t rl_vid;
613 uint16_t rl_did;
614 int rl_basetype;
615 const char *rl_name;
616};
617
618struct rl_hwrev {
619 uint32_t rl_rev;
620 int rl_type;
621 const char *rl_desc;
622 int rl_max_mtu;
623};
624
625#define RL_8129 1
626#define RL_8139 2
627#define RL_8139CPLUS 3
628#define RL_8169 4
629
630#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \
631 (x)->rl_type == RL_8169)
632
633/*
634 * The 8139C+ and 8160 gigE chips support descriptor-based TX
635 * and RX. In fact, they even support TCP large send. Descriptors
636 * must be allocated in contiguous blocks that are aligned on a
637 * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
638 */
639
640/*
641 * RX/TX descriptor definition. When large send mode is enabled, the
642 * lower 11 bits of the TX rl_cmdstat word are used to hold the MSS, and
643 * the checksum offload bits are disabled. The structure layout is
644 * the same for RX and TX descriptors
645 */
646struct rl_desc {
647 uint32_t rl_cmdstat;
648 uint32_t rl_vlanctl;
649 uint32_t rl_bufaddr_lo;
650 uint32_t rl_bufaddr_hi;
651};
652
653#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF
654#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
655#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
656#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
657#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
658#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */
659#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */
660#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */
661#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
662#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
663#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */
664
665#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
666#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
667/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
668#define RL_TDESC_CMD_UDPCSUMV2 0x80000000
669#define RL_TDESC_CMD_TCPCSUMV2 0x40000000
670#define RL_TDESC_CMD_IPCSUMV2 0x20000000
671#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000
672#define RL_TDESC_CMD_MSSVALV2_SHIFT 18
673
674/*
675 * Error bits are valid only on the last descriptor of a frame
676 * (i.e. RL_TDESC_CMD_EOF == 1)
677 */
678#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
679#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
680#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
681#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */
682#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */
683#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */
684#define RL_TDESC_STAT_OWN 0x80000000
685
686/*
687 * RX descriptor cmd/vlan definitions
688 */
689#define RL_RDESC_CMD_EOR 0x40000000
690#define RL_RDESC_CMD_OWN 0x80000000
691#define RL_RDESC_CMD_BUFLEN 0x00001FFF
692
693#define RL_RDESC_STAT_OWN 0x80000000
694#define RL_RDESC_STAT_EOR 0x40000000
695#define RL_RDESC_STAT_SOF 0x20000000
696#define RL_RDESC_STAT_EOF 0x10000000
697#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */
698#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */
699#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */
700#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */
701#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */
702#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */
703#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */
704#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */
705#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */
706#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */
707#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */
708#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */
709#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */
710#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */
711#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */
712#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */
713#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */
714#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */
715#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \
716 RL_RDESC_STAT_CRCERR)
717
718#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available
719 (rl_vlandata valid)*/
720#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
721/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
722#define RL_RDESC_IPV6 0x80000000
723#define RL_RDESC_IPV4 0x40000000
724
725#define RL_PROTOID_NONIP 0x00000000
726#define RL_PROTOID_TCPIP 0x00010000
727#define RL_PROTOID_UDPIP 0x00020000
728#define RL_PROTOID_IP 0x00030000
729#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
730 RL_PROTOID_TCPIP)
731#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
732 RL_PROTOID_UDPIP)
733
734/*
735 * Statistics counter structure (8139C+ and 8169 only)
736 */
737struct rl_stats {
738 uint64_t rl_tx_pkts;
739 uint64_t rl_rx_pkts;
740 uint64_t rl_tx_errs;
741 uint32_t rl_rx_errs;
742 uint16_t rl_missed_pkts;
743 uint16_t rl_rx_framealign_errs;
744 uint32_t rl_tx_onecoll;
745 uint32_t rl_tx_multicolls;
746 uint64_t rl_rx_ucasts;
747 uint64_t rl_rx_bcasts;
748 uint32_t rl_rx_mcasts;
749 uint16_t rl_tx_aborts;
750 uint16_t rl_rx_underruns;
751};
752
753/*
754 * Rx/Tx descriptor parameters (8139C+ and 8169 only)
755 *
756 * 8139C+
757 * Number of descriptors supported : up to 64
758 * Descriptor alignment : 256 bytes
759 * Tx buffer : At least 4 bytes in length.
760 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
761 *
762 * 8169
763 * Number of descriptors supported : up to 1024
764 * Descriptor alignment : 256 bytes
765 * Tx buffer : At least 4 bytes in length.
766 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
767 */
768#ifndef __NO_STRICT_ALIGNMENT
769#define RE_FIXUP_RX 1
770#endif
771
772#define RL_8169_TX_DESC_CNT 256
773#define RL_8169_RX_DESC_CNT 256
774#define RL_8139_TX_DESC_CNT 64
775#define RL_8139_RX_DESC_CNT 64
776#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT
777#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT
778#define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT
779#define RL_NTXSEGS 35
780
781#define RL_RING_ALIGN 256
782#define RL_DUMP_ALIGN 64
783#define RL_IFQ_MAXLEN 512
784#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
785#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
786#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1))
787#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
788#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
789#define RL_PKTSZ(x) ((x)/* >> 3*/)
790#ifdef RE_FIXUP_RX
791#define RE_ETHER_ALIGN sizeof(uint64_t)
792#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN)
793#else
794#define RE_ETHER_ALIGN 0
795#define RE_RX_DESC_BUFLEN MCLBYTES
796#endif
797
798#define RL_MSI_MESSAGES 1
799
800#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
801#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32)
802
803/*
804 * The number of bits reserved for MSS in RealTek controllers is
805 * 11bits. This limits the maximum interface MTU size in TSO case
806 * as upper stack should not generate TCP segments with MSS greater
807 * than the limit.
808 */
809#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN)
810
811/* see comment in dev/re/if_re.c */
812#define RL_JUMBO_FRAMELEN 7440
813#define RL_JUMBO_MTU \
814 (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
815#define RL_JUMBO_MTU_6K \
816 ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
817#define RL_JUMBO_MTU_9K \
818 ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
819#define RL_MTU \
820 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
821
822struct rl_txdesc {
823 struct mbuf *tx_m;
824 bus_dmamap_t tx_dmamap;
825};
826
827struct rl_rxdesc {
828 struct mbuf *rx_m;
829 bus_dmamap_t rx_dmamap;
830 bus_size_t rx_size;
831};
832
833struct rl_list_data {
834 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT];
835 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT];
836 struct rl_rxdesc rl_jrx_desc[RL_RX_JUMBO_DESC_CNT];
837 int rl_tx_desc_cnt;
838 int rl_rx_desc_cnt;
839 int rl_tx_prodidx;
840 int rl_rx_prodidx;
841 int rl_tx_considx;
842 int rl_tx_free;
843 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */
844 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */
845 bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */
846 bus_dmamap_t rl_rx_sparemap;
847 bus_dmamap_t rl_jrx_sparemap;
848 bus_dma_tag_t rl_stag; /* stats mapping tag */
849 bus_dmamap_t rl_smap; /* stats map */
850 struct rl_stats *rl_stats;
851 bus_addr_t rl_stats_addr;
852 bus_dma_tag_t rl_rx_list_tag;
853 bus_dmamap_t rl_rx_list_map;
854 struct rl_desc *rl_rx_list;
855 bus_addr_t rl_rx_list_addr;
856 bus_dma_tag_t rl_tx_list_tag;
857 bus_dmamap_t rl_tx_list_map;
858 struct rl_desc *rl_tx_list;
859 bus_addr_t rl_tx_list_addr;
860};
861
862enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE };
863
864struct rl_softc {
865 struct ifnet *rl_ifp; /* interface info */
866 bus_space_handle_t rl_bhandle; /* bus space handle */
867 bus_space_tag_t rl_btag; /* bus space tag */
868 device_t rl_dev;
869 struct resource *rl_res;
870 int rl_res_id;
871 int rl_res_type;
872 struct resource *rl_res_pba;
873 struct resource *rl_irq[RL_MSI_MESSAGES];
874 void *rl_intrhand[RL_MSI_MESSAGES];
875 device_t rl_miibus;
876 bus_dma_tag_t rl_parent_tag;
877 uint8_t rl_type;
878 const struct rl_hwrev *rl_hwrev;
879 uint32_t rl_macrev;
880 int rl_eecmd_read;
881 int rl_eewidth;
882 int rl_expcap;
883 int rl_txthresh;
884 bus_size_t rl_cfg0;
885 bus_size_t rl_cfg1;
886 bus_size_t rl_cfg2;
887 bus_size_t rl_cfg3;
888 bus_size_t rl_cfg4;
889 bus_size_t rl_cfg5;
890 struct rl_chain_data rl_cdata;
891 struct rl_list_data rl_ldata;
892 struct callout rl_stat_callout;
893 int rl_watchdog_timer;
894 struct mtx rl_mtx;
895 struct mbuf *rl_head;
896 struct mbuf *rl_tail;
897 uint32_t rl_rxlenmask;
898 int rl_testmode;
899 int rl_if_flags;
900 int rl_twister_enable;
901 enum rl_twist rl_twister;
902 int rl_twist_row;
903 int rl_twist_col;
904 int suspended; /* 0 = normal 1 = suspended */
905#ifdef DEVICE_POLLING
906 int rxcycles;
907#endif
908
909 struct task rl_inttask;
910
911 int rl_txstart;
912 int rl_int_rx_act;
913 int rl_int_rx_mod;
914 uint32_t rl_flags;
915#define RL_FLAG_MSI 0x00000001
916#define RL_FLAG_AUTOPAD 0x00000002
917#define RL_FLAG_PHYWAKE_PM 0x00000004
918#define RL_FLAG_PHYWAKE 0x00000008
919#define RL_FLAG_JUMBOV2 0x00000010
920#define RL_FLAG_PAR 0x00000020
921#define RL_FLAG_DESCV2 0x00000040
922#define RL_FLAG_MACSTAT 0x00000080
923#define RL_FLAG_FASTETHER 0x00000100
924#define RL_FLAG_CMDSTOP 0x00000200
925#define RL_FLAG_MACRESET 0x00000400
926#define RL_FLAG_MSIX 0x00000800
927#define RL_FLAG_WOLRXENB 0x00001000
928#define RL_FLAG_MACSLEEP 0x00002000
929#define RL_FLAG_WAIT_TXPOLL 0x00004000
930#define RL_FLAG_CMDSTOP_WAIT_TXQ 0x00008000
931#define RL_FLAG_WOL_MANLINK 0x00010000
932#define RL_FLAG_EARLYOFF 0x00020000
933#define RL_FLAG_EARLYOFFV2 0x00040000
934#define RL_FLAG_RXDV_GATED 0x00080000
935#define RL_FLAG_PCIE 0x40000000
936#define RL_FLAG_LINK 0x80000000
937};
938
939#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx)
940#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx)
941#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
942
943/*
944 * register space access macros
945 */
946#define CSR_WRITE_STREAM_4(sc, reg, val) \
947 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
948#define CSR_WRITE_4(sc, reg, val) \
949 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
950#define CSR_WRITE_2(sc, reg, val) \
951 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
952#define CSR_WRITE_1(sc, reg, val) \
953 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
954
955#define CSR_READ_4(sc, reg) \
956 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
957#define CSR_READ_2(sc, reg) \
958 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
959#define CSR_READ_1(sc, reg) \
960 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
961
962#define CSR_BARRIER(sc, reg, length, flags) \
963 bus_space_barrier(sc->rl_btag, sc->rl_bhandle, reg, length, flags)
964
965#define CSR_SETBIT_1(sc, offset, val) \
966 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
967
968#define CSR_CLRBIT_1(sc, offset, val) \
969 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
970
971#define CSR_SETBIT_2(sc, offset, val) \
972 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
973
974#define CSR_CLRBIT_2(sc, offset, val) \
975 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
976
977#define CSR_SETBIT_4(sc, offset, val) \
978 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
979
980#define CSR_CLRBIT_4(sc, offset, val) \
981 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
982
983#define RL_TIMEOUT 1000
984#define RL_PHY_TIMEOUT 2000
985
986/*
987 * General constants that are fun to know.
988 *
989 * RealTek PCI vendor ID
990 */
991#define RT_VENDORID 0x10EC
992
993/*
994 * RealTek chip device IDs.
995 */
996#define RT_DEVICEID_8139D 0x8039
997#define RT_DEVICEID_8129 0x8129
998#define RT_DEVICEID_8101E 0x8136
999#define RT_DEVICEID_8138 0x8138
1000#define RT_DEVICEID_8139 0x8139
1001#define RT_DEVICEID_8169SC 0x8167
1002#define RT_DEVICEID_8168 0x8168
1003#define RT_DEVICEID_8169 0x8169
1004#define RT_DEVICEID_8100 0x8100
1005
1006#define RT_REVID_8139CPLUS 0x20
1007
1008/*
1009 * Accton PCI vendor ID
1010 */
1011#define ACCTON_VENDORID 0x1113
1012
1013/*
1014 * Accton MPX 5030/5038 device ID.
1015 */
1016#define ACCTON_DEVICEID_5030 0x1211
1017
1018/*
1019 * Nortel PCI vendor ID
1020 */
1021#define NORTEL_VENDORID 0x126C
1022
1023/*
1024 * Delta Electronics Vendor ID.
1025 */
1026#define DELTA_VENDORID 0x1500
1027
1028/*
1029 * Delta device IDs.
1030 */
1031#define DELTA_DEVICEID_8139 0x1360
1032
1033/*
1034 * Addtron vendor ID.
1035 */
1036#define ADDTRON_VENDORID 0x4033
1037
1038/*
1039 * Addtron device IDs.
1040 */
1041#define ADDTRON_DEVICEID_8139 0x1360
1042
1043/*
1044 * D-Link vendor ID.
1045 */
1046#define DLINK_VENDORID 0x1186
1047
1048/*
1049 * D-Link DFE-530TX+ device ID
1050 */
1051#define DLINK_DEVICEID_530TXPLUS 0x1300
1052
1053/*
1054 * D-Link DFE-520TX rev. C1 device ID
1055 */
1056#define DLINK_DEVICEID_520TX_REVC1 0x4200
1057
1058/*
1059 * D-Link DFE-5280T device ID
1060 */
1061#define DLINK_DEVICEID_528T 0x4300
1062#define DLINK_DEVICEID_530T_REVC 0x4302
1063
1064/*
1065 * D-Link DFE-690TXD device ID
1066 */
1067#define DLINK_DEVICEID_690TXD 0x1340
1068
1069/*
1070 * Corega K.K vendor ID
1071 */
1072#define COREGA_VENDORID 0x1259
1073
1074/*
1075 * Corega FEther CB-TXD device ID
1076 */
1077#define COREGA_DEVICEID_FETHERCBTXD 0xa117
1078
1079/*
1080 * Corega FEtherII CB-TXD device ID
1081 */
1082#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e
1083
1084/*
1085 * Corega CG-LAPCIGT device ID
1086 */
1087#define COREGA_DEVICEID_CGLAPCIGT 0xc107
1088
1089/*
1090 * Linksys vendor ID
1091 */
1092#define LINKSYS_VENDORID 0x1737
1093
1094/*
1095 * Linksys EG1032 device ID
1096 */
1097#define LINKSYS_DEVICEID_EG1032 0x1032
1098
1099/*
1100 * Linksys EG1032 rev 3 sub-device ID
1101 */
1102#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024
1103
1104/*
1105 * Peppercon vendor ID
1106 */
1107#define PEPPERCON_VENDORID 0x1743
1108
1109/*
1110 * Peppercon ROL-F device ID
1111 */
1112#define PEPPERCON_DEVICEID_ROLF 0x8139
1113
1114/*
1115 * Planex Communications, Inc. vendor ID
1116 */
1117#define PLANEX_VENDORID 0x14ea
1118
1119/*
1120 * Planex FNW-3603-TX device ID
1121 */
1122#define PLANEX_DEVICEID_FNW3603TX 0xab06
1123
1124/*
1125 * Planex FNW-3800-TX device ID
1126 */
1127#define PLANEX_DEVICEID_FNW3800TX 0xab07
1128
1129/*
1130 * LevelOne vendor ID
1131 */
1132#define LEVEL1_VENDORID 0x018A
1133
1134/*
1135 * LevelOne FPC-0106TX devide ID
1136 */
1137#define LEVEL1_DEVICEID_FPC0106TX 0x0106
1138
1139/*
1140 * Compaq vendor ID
1141 */
1142#define CP_VENDORID 0x021B
1143
1144/*
1145 * Edimax vendor ID
1146 */
1147#define EDIMAX_VENDORID 0x13D1
1148
1149/*
1150 * Edimax EP-4103DL cardbus device ID
1151 */
1152#define EDIMAX_DEVICEID_EP4103DL 0xAB06
1153
1154/* US Robotics vendor ID */
1155
1156#define USR_VENDORID 0x16EC
1157
1158/* US Robotics 997902 device ID */
1159
1160#define USR_DEVICEID_997902 0x0116
| 33 */
34
35/*
36 * RealTek 8129/8139 register offsets
37 */
38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40#define RL_IDR2 0x0002
41#define RL_IDR3 0x0003
42#define RL_IDR4 0x0004
43#define RL_IDR5 0x0005
44 /* 0006-0007 reserved */
45#define RL_MAR0 0x0008 /* Multicast hash table */
46#define RL_MAR1 0x0009
47#define RL_MAR2 0x000A
48#define RL_MAR3 0x000B
49#define RL_MAR4 0x000C
50#define RL_MAR5 0x000D
51#define RL_MAR6 0x000E
52#define RL_MAR7 0x000F
53
54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */
55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */
56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */
57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */
58
59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */
60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */
61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */
62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */
63
64#define RL_RXADDR 0x0030 /* RX ring start address */
65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */
66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */
67#define RL_COMMAND 0x0037 /* command register */
68#define RL_CURRXADDR 0x0038 /* current address of packet read */
69#define RL_CURRXBUF 0x003A /* current RX buffer address */
70#define RL_IMR 0x003C /* interrupt mask register */
71#define RL_ISR 0x003E /* interrupt status register */
72#define RL_TXCFG 0x0040 /* transmit config */
73#define RL_RXCFG 0x0044 /* receive config */
74#define RL_TIMERCNT 0x0048 /* timer count register */
75#define RL_MISSEDPKT 0x004C /* missed packet counter */
76#define RL_EECMD 0x0050 /* EEPROM command register */
77
78/* RTL8139/RTL8139C+ only */
79#define RL_8139_CFG0 0x0051 /* config register #0 */
80#define RL_8139_CFG1 0x0052 /* config register #1 */
81#define RL_8139_CFG3 0x0059 /* config register #3 */
82#define RL_8139_CFG4 0x005A /* config register #4 */
83#define RL_8139_CFG5 0x00D8 /* config register #5 */
84
85#define RL_CFG0 0x0051 /* config register #0 */
86#define RL_CFG1 0x0052 /* config register #1 */
87#define RL_CFG2 0x0053 /* config register #2 */
88#define RL_CFG3 0x0054 /* config register #3 */
89#define RL_CFG4 0x0055 /* config register #4 */
90#define RL_CFG5 0x0056 /* config register #5 */
91 /* 0057 reserved */
92#define RL_MEDIASTAT 0x0058 /* media status register (8139) */
93 /* 0059-005A reserved */
94#define RL_MII 0x005A /* 8129 chip only */
95#define RL_HALTCLK 0x005B
96#define RL_MULTIINTR 0x005C /* multiple interrupt */
97#define RL_PCIREV 0x005E /* PCI revision value */
98 /* 005F reserved */
99#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */
100
101/* Direct PHY access registers only available on 8139 */
102#define RL_BMCR 0x0062 /* PHY basic mode control */
103#define RL_BMSR 0x0064 /* PHY basic mode status */
104#define RL_ANAR 0x0066 /* PHY autoneg advert */
105#define RL_LPAR 0x0068 /* PHY link partner ability */
106#define RL_ANER 0x006A /* PHY autoneg expansion */
107
108#define RL_DISCCNT 0x006C /* disconnect counter */
109#define RL_FALSECAR 0x006E /* false carrier counter */
110#define RL_NWAYTST 0x0070 /* NWAY test register */
111#define RL_RX_ER 0x0072 /* RX_ER counter */
112#define RL_CSCFG 0x0074 /* CS configuration register */
113
114/*
115 * When operating in special C+ mode, some of the registers in an
116 * 8139C+ chip have different definitions. These are also used for
117 * the 8169 gigE chip.
118 */
119#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */
120#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */
121#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */
122#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */
123#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */
124#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */
125#define RL_CFG2 0x0053
126#define RL_TIMERINT 0x0054 /* interrupt on timer expire */
127#define RL_TXSTART 0x00D9 /* 8 bits */
128#define RL_CPLUS_CMD 0x00E0 /* 16 bits */
129#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */
130#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */
131#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */
132
133/*
134 * Registers specific to the 8169 gigE chip
135 */
136#define RL_GTXSTART 0x0038 /* 8 bits */
137#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */
138#define RL_PHYAR 0x0060
139#define RL_TBICSR 0x0064
140#define RL_TBI_ANAR 0x0068
141#define RL_TBI_LPAR 0x006A
142#define RL_GMEDIASTAT 0x006C /* 8 bits */
143#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */
144#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */
145#define RL_PMCH 0x006F /* 8 bits */
146#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
147#define RL_INTRMOD 0x00E2 /* 16 bits */
148#define RL_MISC 0x00F0
149
150/*
151 * TX config register bits
152 */
153#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
154#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
155#define RL_TXCFG_QUEUE_EMPTY 0x00000800 /* 8168E-VL or higher */
156#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
157#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
158#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */
159#define RL_TXCFG_IFG 0x03000000 /* interframe gap */
160#define RL_TXCFG_HWREV 0x7CC00000
161
162#define RL_LOOPTEST_OFF 0x00000000
163#define RL_LOOPTEST_ON 0x00020000
164#define RL_LOOPTEST_ON_CPLUS 0x00060000
165
166/* Known revision codes. */
167#define RL_HWREV_8169 0x00000000
168#define RL_HWREV_8169S 0x00800000
169#define RL_HWREV_8110S 0x04000000
170#define RL_HWREV_8169_8110SB 0x10000000
171#define RL_HWREV_8169_8110SC 0x18000000
172#define RL_HWREV_8401E 0x24000000
173#define RL_HWREV_8102EL 0x24800000
174#define RL_HWREV_8102EL_SPIN1 0x24C00000
175#define RL_HWREV_8168D 0x28000000
176#define RL_HWREV_8168DP 0x28800000
177#define RL_HWREV_8168E 0x2C000000
178#define RL_HWREV_8168E_VL 0x2C800000
179#define RL_HWREV_8168B_SPIN1 0x30000000
180#define RL_HWREV_8100E 0x30800000
181#define RL_HWREV_8101E 0x34000000
182#define RL_HWREV_8102E 0x34800000
183#define RL_HWREV_8103E 0x34C00000
184#define RL_HWREV_8168B_SPIN2 0x38000000
185#define RL_HWREV_8168B_SPIN3 0x38400000
186#define RL_HWREV_8168C 0x3C000000
187#define RL_HWREV_8168C_SPIN2 0x3C400000
188#define RL_HWREV_8168CP 0x3C800000
189#define RL_HWREV_8105E 0x40800000
190#define RL_HWREV_8105E_SPIN1 0x40C00000
191#define RL_HWREV_8402 0x44000000
192#define RL_HWREV_8106E 0x44800000
193#define RL_HWREV_8168F 0x48000000
194#define RL_HWREV_8411 0x48800000
195#define RL_HWREV_8168G 0x4C000000
196#define RL_HWREV_8168EP 0x50000000
197#define RL_HWREV_8168GU 0x50800000
198#define RL_HWREV_8411B 0x5C800000
199#define RL_HWREV_8139 0x60000000
200#define RL_HWREV_8139A 0x70000000
201#define RL_HWREV_8139AG 0x70800000
202#define RL_HWREV_8139B 0x78000000
203#define RL_HWREV_8130 0x7C000000
204#define RL_HWREV_8139C 0x74000000
205#define RL_HWREV_8139D 0x74400000
206#define RL_HWREV_8139CPLUS 0x74800000
207#define RL_HWREV_8101 0x74C00000
208#define RL_HWREV_8100 0x78800000
209#define RL_HWREV_8169_8110SBL 0x7CC00000
210#define RL_HWREV_8169_8110SCE 0x98000000
211
212#define RL_TXDMA_16BYTES 0x00000000
213#define RL_TXDMA_32BYTES 0x00000100
214#define RL_TXDMA_64BYTES 0x00000200
215#define RL_TXDMA_128BYTES 0x00000300
216#define RL_TXDMA_256BYTES 0x00000400
217#define RL_TXDMA_512BYTES 0x00000500
218#define RL_TXDMA_1024BYTES 0x00000600
219#define RL_TXDMA_2048BYTES 0x00000700
220
221/*
222 * Transmit descriptor status register bits.
223 */
224#define RL_TXSTAT_LENMASK 0x00001FFF
225#define RL_TXSTAT_OWN 0x00002000
226#define RL_TXSTAT_TX_UNDERRUN 0x00004000
227#define RL_TXSTAT_TX_OK 0x00008000
228#define RL_TXSTAT_EARLY_THRESH 0x003F0000
229#define RL_TXSTAT_COLLCNT 0x0F000000
230#define RL_TXSTAT_CARR_HBEAT 0x10000000
231#define RL_TXSTAT_OUTOFWIN 0x20000000
232#define RL_TXSTAT_TXABRT 0x40000000
233#define RL_TXSTAT_CARRLOSS 0x80000000
234
235/*
236 * Interrupt status register bits.
237 */
238#define RL_ISR_RX_OK 0x0001
239#define RL_ISR_RX_ERR 0x0002
240#define RL_ISR_TX_OK 0x0004
241#define RL_ISR_TX_ERR 0x0008
242#define RL_ISR_RX_OVERRUN 0x0010
243#define RL_ISR_PKT_UNDERRUN 0x0020
244#define RL_ISR_LINKCHG 0x0020 /* 8169 only */
245#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
246#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */
247#define RL_ISR_SWI 0x0100 /* C+ only */
248#define RL_ISR_CABLE_LEN_CHGD 0x2000
249#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
250#define RL_ISR_TIMEOUT_EXPIRED 0x4000
251#define RL_ISR_SYSTEM_ERR 0x8000
252
253#define RL_INTRS \
254 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
255 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
256 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
257
258#ifdef RE_TX_MODERATION
259#define RL_INTRS_CPLUS \
260 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
261 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
262 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
263#else
264#define RL_INTRS_CPLUS \
265 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \
266 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
267 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
268#endif
269
270/*
271 * Media status register. (8139 only)
272 */
273#define RL_MEDIASTAT_RXPAUSE 0x01
274#define RL_MEDIASTAT_TXPAUSE 0x02
275#define RL_MEDIASTAT_LINK 0x04
276#define RL_MEDIASTAT_SPEED10 0x08
277#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
278#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */
279
280/*
281 * Receive config register.
282 */
283#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */
284#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */
285#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */
286#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */
287#define RL_RXCFG_RX_RUNT 0x00000010
288#define RL_RXCFG_RX_ERRPKT 0x00000020
289#define RL_RXCFG_WRAP 0x00000080
290#define RL_RXCFG_EARLYOFFV2 0x00000800
291#define RL_RXCFG_MAXDMA 0x00000700
292#define RL_RXCFG_BUFSZ 0x00001800
293#define RL_RXCFG_EARLYOFF 0x00003800
294#define RL_RXCFG_FIFOTHRESH 0x0000E000
295#define RL_RXCFG_EARLYTHRESH 0x07000000
296
297#define RL_RXDMA_16BYTES 0x00000000
298#define RL_RXDMA_32BYTES 0x00000100
299#define RL_RXDMA_64BYTES 0x00000200
300#define RL_RXDMA_128BYTES 0x00000300
301#define RL_RXDMA_256BYTES 0x00000400
302#define RL_RXDMA_512BYTES 0x00000500
303#define RL_RXDMA_1024BYTES 0x00000600
304#define RL_RXDMA_UNLIMITED 0x00000700
305
306#define RL_RXBUF_8 0x00000000
307#define RL_RXBUF_16 0x00000800
308#define RL_RXBUF_32 0x00001000
309#define RL_RXBUF_64 0x00001800
310
311#define RL_RXFIFO_16BYTES 0x00000000
312#define RL_RXFIFO_32BYTES 0x00002000
313#define RL_RXFIFO_64BYTES 0x00004000
314#define RL_RXFIFO_128BYTES 0x00006000
315#define RL_RXFIFO_256BYTES 0x00008000
316#define RL_RXFIFO_512BYTES 0x0000A000
317#define RL_RXFIFO_1024BYTES 0x0000C000
318#define RL_RXFIFO_NOTHRESH 0x0000E000
319
320/*
321 * Bits in RX status header (included with RX'ed packet
322 * in ring buffer).
323 */
324#define RL_RXSTAT_RXOK 0x00000001
325#define RL_RXSTAT_ALIGNERR 0x00000002
326#define RL_RXSTAT_CRCERR 0x00000004
327#define RL_RXSTAT_GIANT 0x00000008
328#define RL_RXSTAT_RUNT 0x00000010
329#define RL_RXSTAT_BADSYM 0x00000020
330#define RL_RXSTAT_BROAD 0x00002000
331#define RL_RXSTAT_INDIV 0x00004000
332#define RL_RXSTAT_MULTI 0x00008000
333#define RL_RXSTAT_LENMASK 0xFFFF0000
334#define RL_RXSTAT_UNFINISHED 0x0000FFF0 /* DMA still in progress */
335
336/*
337 * Command register.
338 */
339#define RL_CMD_EMPTY_RXBUF 0x0001
340#define RL_CMD_TX_ENB 0x0004
341#define RL_CMD_RX_ENB 0x0008
342#define RL_CMD_RESET 0x0010
343#define RL_CMD_STOPREQ 0x0080
344
345/*
346 * Twister register values. These are completely undocumented and derived
347 * from public sources.
348 */
349#define RL_CSCFG_LINK_OK 0x0400
350#define RL_CSCFG_CHANGE 0x0800
351#define RL_CSCFG_STATUS 0xf000
352#define RL_CSCFG_ROW3 0x7000
353#define RL_CSCFG_ROW2 0x3000
354#define RL_CSCFG_ROW1 0x1000
355#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0
356#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0
357
358#define RL_NWAYTST_RESET 0
359#define RL_NWAYTST_CBL_TEST 0x20
360
361#define RL_PARA78 0x78
362#define RL_PARA78_DEF 0x78fa8388
363#define RL_PARA7C 0x7C
364#define RL_PARA7C_DEF 0xcb38de43
365#define RL_PARA7C_RETUNE 0xfb38de03
366
367/*
368 * EEPROM control register
369 */
370#define RL_EE_DATAOUT 0x01 /* Data out */
371#define RL_EE_DATAIN 0x02 /* Data in */
372#define RL_EE_CLK 0x04 /* clock */
373#define RL_EE_SEL 0x08 /* chip select */
374#define RL_EE_MODE (0x40|0x80)
375
376#define RL_EEMODE_OFF 0x00
377#define RL_EEMODE_AUTOLOAD 0x40
378#define RL_EEMODE_PROGRAM 0x80
379#define RL_EEMODE_WRITECFG (0x80|0x40)
380
381/* 9346 EEPROM commands */
382#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */
383#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */
384
385#define RL_9346_WRITE 0x5
386#define RL_9346_READ 0x6
387#define RL_9346_ERASE 0x7
388#define RL_9346_EWEN 0x4
389#define RL_9346_EWEN_ADDR 0x30
390#define RL_9456_EWDS 0x4
391#define RL_9346_EWDS_ADDR 0x00
392
393#define RL_EECMD_WRITE 0x140
394#define RL_EECMD_READ_6BIT 0x180
395#define RL_EECMD_READ_8BIT 0x600
396#define RL_EECMD_ERASE 0x1c0
397
398#define RL_EE_ID 0x00
399#define RL_EE_PCI_VID 0x01
400#define RL_EE_PCI_DID 0x02
401/* Location of station address inside EEPROM */
402#define RL_EE_EADDR 0x07
403
404/*
405 * MII register (8129 only)
406 */
407#define RL_MII_CLK 0x01
408#define RL_MII_DATAIN 0x02
409#define RL_MII_DATAOUT 0x04
410#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */
411
412/*
413 * Config 0 register
414 */
415#define RL_CFG0_ROM0 0x01
416#define RL_CFG0_ROM1 0x02
417#define RL_CFG0_ROM2 0x04
418#define RL_CFG0_PL0 0x08
419#define RL_CFG0_PL1 0x10
420#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */
421#define RL_CFG0_PCS 0x40
422#define RL_CFG0_SCR 0x80
423
424/*
425 * Config 1 register
426 */
427#define RL_CFG1_PWRDWN 0x01
428#define RL_CFG1_PME 0x01
429#define RL_CFG1_SLEEP 0x02
430#define RL_CFG1_VPDEN 0x02
431#define RL_CFG1_IOMAP 0x04
432#define RL_CFG1_MEMMAP 0x08
433#define RL_CFG1_RSVD 0x10
434#define RL_CFG1_LWACT 0x10
435#define RL_CFG1_DRVLOAD 0x20
436#define RL_CFG1_LED0 0x40
437#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
438#define RL_CFG1_LED1 0x80
439
440/*
441 * Config 2 register
442 */
443#define RL_CFG2_PCI33MHZ 0x00
444#define RL_CFG2_PCI66MHZ 0x01
445#define RL_CFG2_PCI64BIT 0x08
446#define RL_CFG2_AUXPWR 0x10
447#define RL_CFG2_MSI 0x20
448
449/*
450 * Config 3 register
451 */
452#define RL_CFG3_GRANTSEL 0x80
453#define RL_CFG3_WOL_MAGIC 0x20
454#define RL_CFG3_WOL_LINK 0x10
455#define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */
456#define RL_CFG3_FAST_B2B 0x01
457
458/*
459 * Config 4 register
460 */
461#define RL_CFG4_LWPTN 0x04
462#define RL_CFG4_LWPME 0x10
463#define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */
464
465/*
466 * Config 5 register
467 */
468#define RL_CFG5_WOL_BCAST 0x40
469#define RL_CFG5_WOL_MCAST 0x20
470#define RL_CFG5_WOL_UCAST 0x10
471#define RL_CFG5_WOL_LANWAKE 0x02
472#define RL_CFG5_PME_STS 0x01
473
474/*
475 * 8139C+ register definitions
476 */
477
478/* RL_DUMPSTATS_LO register */
479#define RL_DUMPSTATS_START 0x00000008
480
481/* Transmit start register */
482#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */
483#define RL_TXSTART_START 0x40 /* start normal queue transmit */
484#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
485
486/*
487 * Config 2 register, 8139C+/8169/8169S/8110S only
488 */
489#define RL_CFG2_BUSFREQ 0x07
490#define RL_CFG2_BUSWIDTH 0x08
491#define RL_CFG2_AUXPWRSTS 0x10
492
493#define RL_BUSFREQ_33MHZ 0x00
494#define RL_BUSFREQ_66MHZ 0x01
495
496#define RL_BUSWIDTH_32BITS 0x00
497#define RL_BUSWIDTH_64BITS 0x08
498
499/* C+ mode command register */
500#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
501#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
502#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
503#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
504#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
505#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
506#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */
507#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */
508#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */
509#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */
510#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */
511#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */
512#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */
513#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */
514#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */
515
516/* C+ early transmit threshold */
517#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
518
519/* Timer interrupt register */
520#define RL_TIMERINT_8169_VAL 0x00001FFF
521#define RL_TIMER_MIN 0
522#define RL_TIMER_MAX 65 /* 65.528us */
523#define RL_TIMER_DEFAULT RL_TIMER_MAX
524#define RL_TIMER_PCIE_CLK 125 /* 125MHZ */
525#define RL_USECS(x) ((x) * RL_TIMER_PCIE_CLK)
526
527/*
528 * Gigabit PHY access register (8169 only)
529 */
530#define RL_PHYAR_PHYDATA 0x0000FFFF
531#define RL_PHYAR_PHYREG 0x001F0000
532#define RL_PHYAR_BUSY 0x80000000
533
534/*
535 * Gigabit media status (8169 only)
536 */
537#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */
538#define RL_GMEDIASTAT_LINK 0x02 /* link up */
539#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */
540#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */
541#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */
542#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */
543#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */
544#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */
545
546/*
547 * The RealTek doesn't use a fragment-based descriptor mechanism.
548 * Instead, there are only four register sets, each or which represents
549 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
550 * packet buffer (32-bit aligned!) and we place the buffer addresses in
551 * the registers so the chip knows where they are.
552 *
553 * We can sort of kludge together the same kind of buffer management
554 * used in previous drivers, but we have to do buffer copies almost all
555 * the time, so it doesn't really buy us much.
556 *
557 * For reception, there's just one large buffer where the chip stores
558 * all received packets.
559 */
560#define RL_RX_BUF_SZ RL_RXBUF_64
561#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13))
562#define RL_TX_LIST_CNT 4
563#define RL_MIN_FRAMELEN 60
564#define RL_TX_8139_BUF_ALIGN 4
565#define RL_RX_8139_BUF_ALIGN 8
566#define RL_RX_8139_BUF_RESERVE sizeof(int64_t)
567#define RL_RX_8139_BUF_GUARD_SZ \
568 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE)
569#define RL_TXTHRESH(x) ((x) << 11)
570#define RL_TX_THRESH_INIT 96
571#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH
572#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED
573#define RL_TX_MAXDMA RL_TXDMA_2048BYTES
574
575#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
576#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA)
577
578#define RL_ETHER_ALIGN 2
579
580/*
581 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets.
582 */
583#define RL_IP4CSUMTX_MINLEN 28
584#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN)
585
586struct rl_chain_data {
587 uint16_t cur_rx;
588 uint8_t *rl_rx_buf;
589 uint8_t *rl_rx_buf_ptr;
590
591 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT];
592 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT];
593 bus_dma_tag_t rl_tx_tag;
594 bus_dma_tag_t rl_rx_tag;
595 bus_dmamap_t rl_rx_dmamap;
596 bus_addr_t rl_rx_buf_paddr;
597 uint8_t last_tx;
598 uint8_t cur_tx;
599};
600
601#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT)
602#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
603#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
604#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
605#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
606#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
607#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
608#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
609#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
610
611struct rl_type {
612 uint16_t rl_vid;
613 uint16_t rl_did;
614 int rl_basetype;
615 const char *rl_name;
616};
617
618struct rl_hwrev {
619 uint32_t rl_rev;
620 int rl_type;
621 const char *rl_desc;
622 int rl_max_mtu;
623};
624
625#define RL_8129 1
626#define RL_8139 2
627#define RL_8139CPLUS 3
628#define RL_8169 4
629
630#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \
631 (x)->rl_type == RL_8169)
632
633/*
634 * The 8139C+ and 8160 gigE chips support descriptor-based TX
635 * and RX. In fact, they even support TCP large send. Descriptors
636 * must be allocated in contiguous blocks that are aligned on a
637 * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
638 */
639
640/*
641 * RX/TX descriptor definition. When large send mode is enabled, the
642 * lower 11 bits of the TX rl_cmdstat word are used to hold the MSS, and
643 * the checksum offload bits are disabled. The structure layout is
644 * the same for RX and TX descriptors
645 */
646struct rl_desc {
647 uint32_t rl_cmdstat;
648 uint32_t rl_vlanctl;
649 uint32_t rl_bufaddr_lo;
650 uint32_t rl_bufaddr_hi;
651};
652
653#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF
654#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
655#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
656#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
657#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
658#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */
659#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */
660#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */
661#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
662#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
663#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */
664
665#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
666#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
667/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
668#define RL_TDESC_CMD_UDPCSUMV2 0x80000000
669#define RL_TDESC_CMD_TCPCSUMV2 0x40000000
670#define RL_TDESC_CMD_IPCSUMV2 0x20000000
671#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000
672#define RL_TDESC_CMD_MSSVALV2_SHIFT 18
673
674/*
675 * Error bits are valid only on the last descriptor of a frame
676 * (i.e. RL_TDESC_CMD_EOF == 1)
677 */
678#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
679#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
680#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
681#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */
682#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */
683#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */
684#define RL_TDESC_STAT_OWN 0x80000000
685
686/*
687 * RX descriptor cmd/vlan definitions
688 */
689#define RL_RDESC_CMD_EOR 0x40000000
690#define RL_RDESC_CMD_OWN 0x80000000
691#define RL_RDESC_CMD_BUFLEN 0x00001FFF
692
693#define RL_RDESC_STAT_OWN 0x80000000
694#define RL_RDESC_STAT_EOR 0x40000000
695#define RL_RDESC_STAT_SOF 0x20000000
696#define RL_RDESC_STAT_EOF 0x10000000
697#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */
698#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */
699#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */
700#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */
701#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */
702#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */
703#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */
704#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */
705#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */
706#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */
707#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */
708#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */
709#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */
710#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */
711#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */
712#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */
713#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */
714#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */
715#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \
716 RL_RDESC_STAT_CRCERR)
717
718#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available
719 (rl_vlandata valid)*/
720#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
721/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
722#define RL_RDESC_IPV6 0x80000000
723#define RL_RDESC_IPV4 0x40000000
724
725#define RL_PROTOID_NONIP 0x00000000
726#define RL_PROTOID_TCPIP 0x00010000
727#define RL_PROTOID_UDPIP 0x00020000
728#define RL_PROTOID_IP 0x00030000
729#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
730 RL_PROTOID_TCPIP)
731#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
732 RL_PROTOID_UDPIP)
733
734/*
735 * Statistics counter structure (8139C+ and 8169 only)
736 */
737struct rl_stats {
738 uint64_t rl_tx_pkts;
739 uint64_t rl_rx_pkts;
740 uint64_t rl_tx_errs;
741 uint32_t rl_rx_errs;
742 uint16_t rl_missed_pkts;
743 uint16_t rl_rx_framealign_errs;
744 uint32_t rl_tx_onecoll;
745 uint32_t rl_tx_multicolls;
746 uint64_t rl_rx_ucasts;
747 uint64_t rl_rx_bcasts;
748 uint32_t rl_rx_mcasts;
749 uint16_t rl_tx_aborts;
750 uint16_t rl_rx_underruns;
751};
752
753/*
754 * Rx/Tx descriptor parameters (8139C+ and 8169 only)
755 *
756 * 8139C+
757 * Number of descriptors supported : up to 64
758 * Descriptor alignment : 256 bytes
759 * Tx buffer : At least 4 bytes in length.
760 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
761 *
762 * 8169
763 * Number of descriptors supported : up to 1024
764 * Descriptor alignment : 256 bytes
765 * Tx buffer : At least 4 bytes in length.
766 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
767 */
768#ifndef __NO_STRICT_ALIGNMENT
769#define RE_FIXUP_RX 1
770#endif
771
772#define RL_8169_TX_DESC_CNT 256
773#define RL_8169_RX_DESC_CNT 256
774#define RL_8139_TX_DESC_CNT 64
775#define RL_8139_RX_DESC_CNT 64
776#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT
777#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT
778#define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT
779#define RL_NTXSEGS 35
780
781#define RL_RING_ALIGN 256
782#define RL_DUMP_ALIGN 64
783#define RL_IFQ_MAXLEN 512
784#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
785#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
786#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1))
787#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
788#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
789#define RL_PKTSZ(x) ((x)/* >> 3*/)
790#ifdef RE_FIXUP_RX
791#define RE_ETHER_ALIGN sizeof(uint64_t)
792#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN)
793#else
794#define RE_ETHER_ALIGN 0
795#define RE_RX_DESC_BUFLEN MCLBYTES
796#endif
797
798#define RL_MSI_MESSAGES 1
799
800#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
801#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32)
802
803/*
804 * The number of bits reserved for MSS in RealTek controllers is
805 * 11bits. This limits the maximum interface MTU size in TSO case
806 * as upper stack should not generate TCP segments with MSS greater
807 * than the limit.
808 */
809#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN)
810
811/* see comment in dev/re/if_re.c */
812#define RL_JUMBO_FRAMELEN 7440
813#define RL_JUMBO_MTU \
814 (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
815#define RL_JUMBO_MTU_6K \
816 ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
817#define RL_JUMBO_MTU_9K \
818 ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
819#define RL_MTU \
820 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
821
822struct rl_txdesc {
823 struct mbuf *tx_m;
824 bus_dmamap_t tx_dmamap;
825};
826
827struct rl_rxdesc {
828 struct mbuf *rx_m;
829 bus_dmamap_t rx_dmamap;
830 bus_size_t rx_size;
831};
832
833struct rl_list_data {
834 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT];
835 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT];
836 struct rl_rxdesc rl_jrx_desc[RL_RX_JUMBO_DESC_CNT];
837 int rl_tx_desc_cnt;
838 int rl_rx_desc_cnt;
839 int rl_tx_prodidx;
840 int rl_rx_prodidx;
841 int rl_tx_considx;
842 int rl_tx_free;
843 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */
844 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */
845 bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */
846 bus_dmamap_t rl_rx_sparemap;
847 bus_dmamap_t rl_jrx_sparemap;
848 bus_dma_tag_t rl_stag; /* stats mapping tag */
849 bus_dmamap_t rl_smap; /* stats map */
850 struct rl_stats *rl_stats;
851 bus_addr_t rl_stats_addr;
852 bus_dma_tag_t rl_rx_list_tag;
853 bus_dmamap_t rl_rx_list_map;
854 struct rl_desc *rl_rx_list;
855 bus_addr_t rl_rx_list_addr;
856 bus_dma_tag_t rl_tx_list_tag;
857 bus_dmamap_t rl_tx_list_map;
858 struct rl_desc *rl_tx_list;
859 bus_addr_t rl_tx_list_addr;
860};
861
862enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE };
863
864struct rl_softc {
865 struct ifnet *rl_ifp; /* interface info */
866 bus_space_handle_t rl_bhandle; /* bus space handle */
867 bus_space_tag_t rl_btag; /* bus space tag */
868 device_t rl_dev;
869 struct resource *rl_res;
870 int rl_res_id;
871 int rl_res_type;
872 struct resource *rl_res_pba;
873 struct resource *rl_irq[RL_MSI_MESSAGES];
874 void *rl_intrhand[RL_MSI_MESSAGES];
875 device_t rl_miibus;
876 bus_dma_tag_t rl_parent_tag;
877 uint8_t rl_type;
878 const struct rl_hwrev *rl_hwrev;
879 uint32_t rl_macrev;
880 int rl_eecmd_read;
881 int rl_eewidth;
882 int rl_expcap;
883 int rl_txthresh;
884 bus_size_t rl_cfg0;
885 bus_size_t rl_cfg1;
886 bus_size_t rl_cfg2;
887 bus_size_t rl_cfg3;
888 bus_size_t rl_cfg4;
889 bus_size_t rl_cfg5;
890 struct rl_chain_data rl_cdata;
891 struct rl_list_data rl_ldata;
892 struct callout rl_stat_callout;
893 int rl_watchdog_timer;
894 struct mtx rl_mtx;
895 struct mbuf *rl_head;
896 struct mbuf *rl_tail;
897 uint32_t rl_rxlenmask;
898 int rl_testmode;
899 int rl_if_flags;
900 int rl_twister_enable;
901 enum rl_twist rl_twister;
902 int rl_twist_row;
903 int rl_twist_col;
904 int suspended; /* 0 = normal 1 = suspended */
905#ifdef DEVICE_POLLING
906 int rxcycles;
907#endif
908
909 struct task rl_inttask;
910
911 int rl_txstart;
912 int rl_int_rx_act;
913 int rl_int_rx_mod;
914 uint32_t rl_flags;
915#define RL_FLAG_MSI 0x00000001
916#define RL_FLAG_AUTOPAD 0x00000002
917#define RL_FLAG_PHYWAKE_PM 0x00000004
918#define RL_FLAG_PHYWAKE 0x00000008
919#define RL_FLAG_JUMBOV2 0x00000010
920#define RL_FLAG_PAR 0x00000020
921#define RL_FLAG_DESCV2 0x00000040
922#define RL_FLAG_MACSTAT 0x00000080
923#define RL_FLAG_FASTETHER 0x00000100
924#define RL_FLAG_CMDSTOP 0x00000200
925#define RL_FLAG_MACRESET 0x00000400
926#define RL_FLAG_MSIX 0x00000800
927#define RL_FLAG_WOLRXENB 0x00001000
928#define RL_FLAG_MACSLEEP 0x00002000
929#define RL_FLAG_WAIT_TXPOLL 0x00004000
930#define RL_FLAG_CMDSTOP_WAIT_TXQ 0x00008000
931#define RL_FLAG_WOL_MANLINK 0x00010000
932#define RL_FLAG_EARLYOFF 0x00020000
933#define RL_FLAG_EARLYOFFV2 0x00040000
934#define RL_FLAG_RXDV_GATED 0x00080000
935#define RL_FLAG_PCIE 0x40000000
936#define RL_FLAG_LINK 0x80000000
937};
938
939#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx)
940#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx)
941#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
942
943/*
944 * register space access macros
945 */
946#define CSR_WRITE_STREAM_4(sc, reg, val) \
947 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
948#define CSR_WRITE_4(sc, reg, val) \
949 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
950#define CSR_WRITE_2(sc, reg, val) \
951 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
952#define CSR_WRITE_1(sc, reg, val) \
953 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
954
955#define CSR_READ_4(sc, reg) \
956 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
957#define CSR_READ_2(sc, reg) \
958 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
959#define CSR_READ_1(sc, reg) \
960 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
961
962#define CSR_BARRIER(sc, reg, length, flags) \
963 bus_space_barrier(sc->rl_btag, sc->rl_bhandle, reg, length, flags)
964
965#define CSR_SETBIT_1(sc, offset, val) \
966 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
967
968#define CSR_CLRBIT_1(sc, offset, val) \
969 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
970
971#define CSR_SETBIT_2(sc, offset, val) \
972 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
973
974#define CSR_CLRBIT_2(sc, offset, val) \
975 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
976
977#define CSR_SETBIT_4(sc, offset, val) \
978 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
979
980#define CSR_CLRBIT_4(sc, offset, val) \
981 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
982
983#define RL_TIMEOUT 1000
984#define RL_PHY_TIMEOUT 2000
985
986/*
987 * General constants that are fun to know.
988 *
989 * RealTek PCI vendor ID
990 */
991#define RT_VENDORID 0x10EC
992
993/*
994 * RealTek chip device IDs.
995 */
996#define RT_DEVICEID_8139D 0x8039
997#define RT_DEVICEID_8129 0x8129
998#define RT_DEVICEID_8101E 0x8136
999#define RT_DEVICEID_8138 0x8138
1000#define RT_DEVICEID_8139 0x8139
1001#define RT_DEVICEID_8169SC 0x8167
1002#define RT_DEVICEID_8168 0x8168
1003#define RT_DEVICEID_8169 0x8169
1004#define RT_DEVICEID_8100 0x8100
1005
1006#define RT_REVID_8139CPLUS 0x20
1007
1008/*
1009 * Accton PCI vendor ID
1010 */
1011#define ACCTON_VENDORID 0x1113
1012
1013/*
1014 * Accton MPX 5030/5038 device ID.
1015 */
1016#define ACCTON_DEVICEID_5030 0x1211
1017
1018/*
1019 * Nortel PCI vendor ID
1020 */
1021#define NORTEL_VENDORID 0x126C
1022
1023/*
1024 * Delta Electronics Vendor ID.
1025 */
1026#define DELTA_VENDORID 0x1500
1027
1028/*
1029 * Delta device IDs.
1030 */
1031#define DELTA_DEVICEID_8139 0x1360
1032
1033/*
1034 * Addtron vendor ID.
1035 */
1036#define ADDTRON_VENDORID 0x4033
1037
1038/*
1039 * Addtron device IDs.
1040 */
1041#define ADDTRON_DEVICEID_8139 0x1360
1042
1043/*
1044 * D-Link vendor ID.
1045 */
1046#define DLINK_VENDORID 0x1186
1047
1048/*
1049 * D-Link DFE-530TX+ device ID
1050 */
1051#define DLINK_DEVICEID_530TXPLUS 0x1300
1052
1053/*
1054 * D-Link DFE-520TX rev. C1 device ID
1055 */
1056#define DLINK_DEVICEID_520TX_REVC1 0x4200
1057
1058/*
1059 * D-Link DFE-5280T device ID
1060 */
1061#define DLINK_DEVICEID_528T 0x4300
1062#define DLINK_DEVICEID_530T_REVC 0x4302
1063
1064/*
1065 * D-Link DFE-690TXD device ID
1066 */
1067#define DLINK_DEVICEID_690TXD 0x1340
1068
1069/*
1070 * Corega K.K vendor ID
1071 */
1072#define COREGA_VENDORID 0x1259
1073
1074/*
1075 * Corega FEther CB-TXD device ID
1076 */
1077#define COREGA_DEVICEID_FETHERCBTXD 0xa117
1078
1079/*
1080 * Corega FEtherII CB-TXD device ID
1081 */
1082#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e
1083
1084/*
1085 * Corega CG-LAPCIGT device ID
1086 */
1087#define COREGA_DEVICEID_CGLAPCIGT 0xc107
1088
1089/*
1090 * Linksys vendor ID
1091 */
1092#define LINKSYS_VENDORID 0x1737
1093
1094/*
1095 * Linksys EG1032 device ID
1096 */
1097#define LINKSYS_DEVICEID_EG1032 0x1032
1098
1099/*
1100 * Linksys EG1032 rev 3 sub-device ID
1101 */
1102#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024
1103
1104/*
1105 * Peppercon vendor ID
1106 */
1107#define PEPPERCON_VENDORID 0x1743
1108
1109/*
1110 * Peppercon ROL-F device ID
1111 */
1112#define PEPPERCON_DEVICEID_ROLF 0x8139
1113
1114/*
1115 * Planex Communications, Inc. vendor ID
1116 */
1117#define PLANEX_VENDORID 0x14ea
1118
1119/*
1120 * Planex FNW-3603-TX device ID
1121 */
1122#define PLANEX_DEVICEID_FNW3603TX 0xab06
1123
1124/*
1125 * Planex FNW-3800-TX device ID
1126 */
1127#define PLANEX_DEVICEID_FNW3800TX 0xab07
1128
1129/*
1130 * LevelOne vendor ID
1131 */
1132#define LEVEL1_VENDORID 0x018A
1133
1134/*
1135 * LevelOne FPC-0106TX devide ID
1136 */
1137#define LEVEL1_DEVICEID_FPC0106TX 0x0106
1138
1139/*
1140 * Compaq vendor ID
1141 */
1142#define CP_VENDORID 0x021B
1143
1144/*
1145 * Edimax vendor ID
1146 */
1147#define EDIMAX_VENDORID 0x13D1
1148
1149/*
1150 * Edimax EP-4103DL cardbus device ID
1151 */
1152#define EDIMAX_DEVICEID_EP4103DL 0xAB06
1153
1154/* US Robotics vendor ID */
1155
1156#define USR_VENDORID 0x16EC
1157
1158/* US Robotics 997902 device ID */
1159
1160#define USR_DEVICEID_997902 0x0116
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