if_rl.c (50548) | if_rl.c (50703) |
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1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
32 * $FreeBSD: head/sys/pci/if_rl.c 50548 1999-08-29 09:03:58Z bde $ | 32 * $FreeBSD: head/sys/pci/if_rl.c 50703 1999-08-31 14:45:51Z wpaul $ |
33 */ 34 35/* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. --- 41 unchanged lines hidden (view full) --- 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include "bpf.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> | 33 */ 34 35/* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. --- 41 unchanged lines hidden (view full) --- 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include "bpf.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> |
90#include <sys/eventhandler.h> | |
91#include <sys/sockio.h> 92#include <sys/mbuf.h> 93#include <sys/malloc.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> --- 6 unchanged lines hidden (view full) --- 105#endif 106 107#include <vm/vm.h> /* for vtophys */ 108#include <vm/pmap.h> /* for vtophys */ 109#include <machine/clock.h> /* for DELAY */ 110#include <machine/bus_pio.h> 111#include <machine/bus_memio.h> 112#include <machine/bus.h> | 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> --- 6 unchanged lines hidden (view full) --- 104#endif 105 106#include <vm/vm.h> /* for vtophys */ 107#include <vm/pmap.h> /* for vtophys */ 108#include <machine/clock.h> /* for DELAY */ 109#include <machine/bus_pio.h> 110#include <machine/bus_memio.h> 111#include <machine/bus.h> |
112#include <machine/resource.h> 113#include <sys/bus.h> 114#include <sys/rman.h> |
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113 | 115 |
116#include <dev/mii/mii.h> 117#include <dev/mii/miivar.h> 118 |
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114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 | 119#include <pci/pcireg.h> 120#include <pci/pcivar.h> 121 |
122#include "miibus_if.h" 123 |
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117/* 118 * Default to using PIO access for this driver. On SMP systems, 119 * there appear to be problems with memory mapped mode: it looks like 120 * doing too many memory mapped access back to back in rapid succession 121 * can hang the bus. I'm inclined to blame this on crummy design/construction 122 * on the part of RealTek. Memory mapped mode does appear to work on 123 * uniprocessor systems though. 124 */ 125#define RL_USEIOSPACE 126 127#include <pci/if_rlreg.h> 128 129#ifndef lint 130static const char rcsid[] = | 124/* 125 * Default to using PIO access for this driver. On SMP systems, 126 * there appear to be problems with memory mapped mode: it looks like 127 * doing too many memory mapped access back to back in rapid succession 128 * can hang the bus. I'm inclined to blame this on crummy design/construction 129 * on the part of RealTek. Memory mapped mode does appear to work on 130 * uniprocessor systems though. 131 */ 132#define RL_USEIOSPACE 133 134#include <pci/if_rlreg.h> 135 136#ifndef lint 137static const char rcsid[] = |
131 "$FreeBSD: head/sys/pci/if_rl.c 50548 1999-08-29 09:03:58Z bde $"; | 138 "$FreeBSD: head/sys/pci/if_rl.c 50703 1999-08-31 14:45:51Z wpaul $"; |
132#endif 133 134/* 135 * Various supported device vendors/types and their names. 136 */ 137static struct rl_type rl_devs[] = { 138 { RT_VENDORID, RT_DEVICEID_8129, 139 "RealTek 8129 10/100BaseTX" }, 140 { RT_VENDORID, RT_DEVICEID_8139, 141 "RealTek 8139 10/100BaseTX" }, 142 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 143 "Accton MPX 5030/5038 10/100BaseTX" }, 144 { DELTA_VENDORID, DELTA_DEVICEID_8139, 145 "Delta Electronics 8139 10/100BaseTX" }, 146 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 147 "Addtron Technolgy 8139 10/100BaseTX" }, 148 { 0, 0, NULL } 149}; 150 | 139#endif 140 141/* 142 * Various supported device vendors/types and their names. 143 */ 144static struct rl_type rl_devs[] = { 145 { RT_VENDORID, RT_DEVICEID_8129, 146 "RealTek 8129 10/100BaseTX" }, 147 { RT_VENDORID, RT_DEVICEID_8139, 148 "RealTek 8139 10/100BaseTX" }, 149 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 150 "Accton MPX 5030/5038 10/100BaseTX" }, 151 { DELTA_VENDORID, DELTA_DEVICEID_8139, 152 "Delta Electronics 8139 10/100BaseTX" }, 153 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 154 "Addtron Technolgy 8139 10/100BaseTX" }, 155 { 0, 0, NULL } 156}; 157 |
151/* 152 * Various supported PHY vendors/types and their names. Note that 153 * this driver will work with pretty much any MII-compliant PHY, 154 * so failure to positively identify the chip is not a fatal error. 155 */ | 158static int rl_probe __P((device_t)); 159static int rl_attach __P((device_t)); 160static int rl_detach __P((device_t)); |
156 | 161 |
157static struct rl_type rl_phys[] = { 158 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" }, 159 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" }, 160 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"}, 161 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 162 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" }, 163 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" }, 164 { 0, 0, "<MII-compliant physical interface>" } 165}; 166 167static unsigned long rl_count = 0; 168static const char *rl_probe __P((pcici_t, pcidi_t)); 169static void rl_attach __P((pcici_t, int)); 170 | |
171static int rl_encap __P((struct rl_softc *, struct mbuf * )); 172 173static void rl_rxeof __P((struct rl_softc *)); 174static void rl_txeof __P((struct rl_softc *)); 175static void rl_intr __P((void *)); | 162static int rl_encap __P((struct rl_softc *, struct mbuf * )); 163 164static void rl_rxeof __P((struct rl_softc *)); 165static void rl_txeof __P((struct rl_softc *)); 166static void rl_intr __P((void *)); |
167static void rl_tick __P((void *)); |
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176static void rl_start __P((struct ifnet *)); 177static int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 178static void rl_init __P((void *)); 179static void rl_stop __P((struct rl_softc *)); 180static void rl_watchdog __P((struct ifnet *)); | 168static void rl_start __P((struct ifnet *)); 169static int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 170static void rl_init __P((void *)); 171static void rl_stop __P((struct rl_softc *)); 172static void rl_watchdog __P((struct ifnet *)); |
181static void rl_shutdown __P((void *, int)); | 173static void rl_shutdown __P((device_t)); |
182static int rl_ifmedia_upd __P((struct ifnet *)); 183static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 184 185static void rl_eeprom_putbyte __P((struct rl_softc *, int)); 186static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *)); 187static void rl_read_eeprom __P((struct rl_softc *, caddr_t, 188 int, int, int)); 189static void rl_mii_sync __P((struct rl_softc *)); 190static void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 191static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 192static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 193 | 174static int rl_ifmedia_upd __P((struct ifnet *)); 175static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 176 177static void rl_eeprom_putbyte __P((struct rl_softc *, int)); 178static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *)); 179static void rl_read_eeprom __P((struct rl_softc *, caddr_t, 180 int, int, int)); 181static void rl_mii_sync __P((struct rl_softc *)); 182static void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 183static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 184static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 185 |
194static u_int16_t rl_phy_readreg __P((struct rl_softc *, int)); 195static void rl_phy_writereg __P((struct rl_softc *, int, int)); | 186static int rl_miibus_readreg __P((device_t, int, int)); 187static int rl_miibus_writereg __P((device_t, int, int, int)); 188static void rl_miibus_statchg __P((device_t)); |
196 | 189 |
197static void rl_autoneg_xmit __P((struct rl_softc *)); 198static void rl_autoneg_mii __P((struct rl_softc *, int, int)); 199static void rl_setmode_mii __P((struct rl_softc *, int)); 200static void rl_getmode_mii __P((struct rl_softc *)); | |
201static u_int8_t rl_calchash __P((caddr_t)); 202static void rl_setmulti __P((struct rl_softc *)); 203static void rl_reset __P((struct rl_softc *)); 204static int rl_list_tx_init __P((struct rl_softc *)); 205 | 190static u_int8_t rl_calchash __P((caddr_t)); 191static void rl_setmulti __P((struct rl_softc *)); 192static void rl_reset __P((struct rl_softc *)); 193static int rl_list_tx_init __P((struct rl_softc *)); 194 |
195#ifdef RL_USEIOSPACE 196#define RL_RES SYS_RES_IOPORT 197#define RL_RID RL_PCI_LOIO 198#else 199#define RL_RES SYS_RES_MEMORY 200#define RL_RID RL_PCI_LOMEM 201#endif 202 203static device_method_t rl_methods[] = { 204 /* Device interface */ 205 DEVMETHOD(device_probe, rl_probe), 206 DEVMETHOD(device_attach, rl_attach), 207 DEVMETHOD(device_detach, rl_detach), 208 DEVMETHOD(device_shutdown, rl_shutdown), 209 210 /* bus interface */ 211 DEVMETHOD(bus_print_child, bus_generic_print_child), 212 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 213 214 /* MII interface */ 215 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 216 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 217 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 218 219 { 0, 0 } 220}; 221 222static driver_t rl_driver = { 223 "rl", 224 rl_methods, 225 sizeof(struct rl_softc) 226}; 227 228static devclass_t rl_devclass; 229 230DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0); 231DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 232 |
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206#define EE_SET(x) \ 207 CSR_WRITE_1(sc, RL_EECMD, \ 208 CSR_READ_1(sc, RL_EECMD) | x) 209 210#define EE_CLR(x) \ 211 CSR_WRITE_1(sc, RL_EECMD, \ 212 CSR_READ_1(sc, RL_EECMD) & ~x) 213 --- 290 unchanged lines hidden (view full) --- 504 */ 505 MII_CLR(RL_MII_DIR); 506 507 splx(s); 508 509 return(0); 510} 511 | 233#define EE_SET(x) \ 234 CSR_WRITE_1(sc, RL_EECMD, \ 235 CSR_READ_1(sc, RL_EECMD) | x) 236 237#define EE_CLR(x) \ 238 CSR_WRITE_1(sc, RL_EECMD, \ 239 CSR_READ_1(sc, RL_EECMD) & ~x) 240 --- 290 unchanged lines hidden (view full) --- 531 */ 532 MII_CLR(RL_MII_DIR); 533 534 splx(s); 535 536 return(0); 537} 538 |
512static u_int16_t rl_phy_readreg(sc, reg) 513 struct rl_softc *sc; 514 int reg; | 539static int rl_miibus_readreg(dev, phy, reg) 540 device_t dev; 541 int phy, reg; |
515{ | 542{ |
543 struct rl_softc *sc; |
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516 struct rl_mii_frame frame; 517 u_int16_t rval = 0; 518 u_int16_t rl8139_reg = 0; 519 | 544 struct rl_mii_frame frame; 545 u_int16_t rval = 0; 546 u_int16_t rl8139_reg = 0; 547 |
548 sc = device_get_softc(dev); 549 |
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520 if (sc->rl_type == RL_8139) { | 550 if (sc->rl_type == RL_8139) { |
551 /* Pretend the internal PHY is only at address 0 */ 552 if (phy) 553 return(0); |
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521 switch(reg) { | 554 switch(reg) { |
522 case PHY_BMCR: | 555 case MII_BMCR: |
523 rl8139_reg = RL_BMCR; 524 break; | 556 rl8139_reg = RL_BMCR; 557 break; |
525 case PHY_BMSR: | 558 case MII_BMSR: |
526 rl8139_reg = RL_BMSR; 527 break; | 559 rl8139_reg = RL_BMSR; 560 break; |
528 case PHY_ANAR: | 561 case MII_ANAR: |
529 rl8139_reg = RL_ANAR; 530 break; | 562 rl8139_reg = RL_ANAR; 563 break; |
531 case PHY_LPAR: | 564 case MII_ANER: 565 rl8139_reg = RL_ANER; 566 break; 567 case MII_ANLPAR: |
532 rl8139_reg = RL_LPAR; 533 break; | 568 rl8139_reg = RL_LPAR; 569 break; |
570 case MII_PHYIDR1: 571 case MII_PHYIDR2: 572 return(0); 573 break; |
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534 default: 535 printf("rl%d: bad phy register\n", sc->rl_unit); 536 return(0); 537 } 538 rval = CSR_READ_2(sc, rl8139_reg); 539 return(rval); 540 } 541 542 bzero((char *)&frame, sizeof(frame)); 543 | 574 default: 575 printf("rl%d: bad phy register\n", sc->rl_unit); 576 return(0); 577 } 578 rval = CSR_READ_2(sc, rl8139_reg); 579 return(rval); 580 } 581 582 bzero((char *)&frame, sizeof(frame)); 583 |
544 frame.mii_phyaddr = sc->rl_phy_addr; | 584 frame.mii_phyaddr = phy; |
545 frame.mii_regaddr = reg; 546 rl_mii_readreg(sc, &frame); 547 548 return(frame.mii_data); 549} 550 | 585 frame.mii_regaddr = reg; 586 rl_mii_readreg(sc, &frame); 587 588 return(frame.mii_data); 589} 590 |
551static void rl_phy_writereg(sc, reg, data) 552 struct rl_softc *sc; 553 int reg; 554 int data; | 591static int rl_miibus_writereg(dev, phy, reg, data) 592 device_t dev; 593 int phy, reg, data; |
555{ | 594{ |
595 struct rl_softc *sc; |
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556 struct rl_mii_frame frame; 557 u_int16_t rl8139_reg = 0; 558 | 596 struct rl_mii_frame frame; 597 u_int16_t rl8139_reg = 0; 598 |
599 sc = device_get_softc(dev); 600 |
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559 if (sc->rl_type == RL_8139) { | 601 if (sc->rl_type == RL_8139) { |
602 /* Pretend the internal PHY is only at address 0 */ 603 if (phy) 604 return(0); |
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560 switch(reg) { | 605 switch(reg) { |
561 case PHY_BMCR: | 606 case MII_BMCR: |
562 rl8139_reg = RL_BMCR; 563 break; | 607 rl8139_reg = RL_BMCR; 608 break; |
564 case PHY_BMSR: | 609 case MII_BMSR: |
565 rl8139_reg = RL_BMSR; 566 break; | 610 rl8139_reg = RL_BMSR; 611 break; |
567 case PHY_ANAR: | 612 case MII_ANAR: |
568 rl8139_reg = RL_ANAR; 569 break; | 613 rl8139_reg = RL_ANAR; 614 break; |
570 case PHY_LPAR: | 615 case MII_ANER: 616 rl8139_reg = RL_ANER; 617 break; 618 case MII_ANLPAR: |
571 rl8139_reg = RL_LPAR; 572 break; | 619 rl8139_reg = RL_LPAR; 620 break; |
621 case MII_PHYIDR1: 622 case MII_PHYIDR2: 623 return(0); 624 break; |
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573 default: 574 printf("rl%d: bad phy register\n", sc->rl_unit); | 625 default: 626 printf("rl%d: bad phy register\n", sc->rl_unit); |
575 return; | 627 return(0); |
576 } 577 CSR_WRITE_2(sc, rl8139_reg, data); | 628 } 629 CSR_WRITE_2(sc, rl8139_reg, data); |
578 return; | 630 return(0); |
579 } 580 581 bzero((char *)&frame, sizeof(frame)); 582 | 631 } 632 633 bzero((char *)&frame, sizeof(frame)); 634 |
583 frame.mii_phyaddr = sc->rl_phy_addr; | 635 frame.mii_phyaddr = phy; |
584 frame.mii_regaddr = reg; 585 frame.mii_data = data; 586 587 rl_mii_writereg(sc, &frame); 588 | 636 frame.mii_regaddr = reg; 637 frame.mii_data = data; 638 639 rl_mii_writereg(sc, &frame); 640 |
641 return(0); 642} 643 644static void rl_miibus_statchg(dev) 645 device_t dev; 646{ |
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589 return; 590} 591 592/* 593 * Calculate CRC of a multicast group address, return the upper 6 bits. 594 */ 595static u_int8_t rl_calchash(addr) 596 caddr_t addr; --- 69 unchanged lines hidden (view full) --- 666 667 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 668 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 669 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 670 671 return; 672} 673 | 647 return; 648} 649 650/* 651 * Calculate CRC of a multicast group address, return the upper 6 bits. 652 */ 653static u_int8_t rl_calchash(addr) 654 caddr_t addr; --- 69 unchanged lines hidden (view full) --- 724 725 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 726 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 727 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 728 729 return; 730} 731 |
674/* 675 * Initiate an autonegotiation session. 676 */ 677static void rl_autoneg_xmit(sc) 678 struct rl_softc *sc; 679{ 680 u_int16_t phy_sts; 681 682 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 683 DELAY(500); 684 while(rl_phy_readreg(sc, PHY_BMCR) 685 & PHY_BMCR_RESET); 686 687 phy_sts = rl_phy_readreg(sc, PHY_BMCR); 688 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 689 rl_phy_writereg(sc, PHY_BMCR, phy_sts); 690 691 return; 692} 693 694/* 695 * Invoke autonegotiation on a PHY. Also used with the 8139 internal 696 * transceiver. 697 */ 698static void rl_autoneg_mii(sc, flag, verbose) 699 struct rl_softc *sc; 700 int flag; 701 int verbose; 702{ 703 u_int16_t phy_sts = 0, media, advert, ability; 704 struct ifnet *ifp; 705 struct ifmedia *ifm; 706 707 ifm = &sc->ifmedia; 708 ifp = &sc->arpcom.ac_if; 709 710 /* 711 * The 100baseT4 PHY sometimes has the 'autoneg supported' 712 * bit cleared in the status register, but has the 'autoneg enabled' 713 * bit set in the control register. This is a contradiction, and 714 * I'm not sure how to handle it. If you want to force an attempt 715 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR 716 * and see what happens. 717 */ 718#ifndef FORCE_AUTONEG_TFOUR 719 /* 720 * First, see if autoneg is supported. If not, there's 721 * no point in continuing. 722 */ 723 phy_sts = rl_phy_readreg(sc, PHY_BMSR); 724 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 725 if (verbose) 726 printf("rl%d: autonegotiation not supported\n", 727 sc->rl_unit); 728 return; 729 } 730#endif 731 732 switch (flag) { 733 case RL_FLAG_FORCEDELAY: 734 /* 735 * XXX Never use this option anywhere but in the probe 736 * routine: making the kernel stop dead in its tracks 737 * for three whole seconds after we've gone multi-user 738 * is really bad manners. 739 */ 740 rl_autoneg_xmit(sc); 741 DELAY(5000000); 742 break; 743 case RL_FLAG_SCHEDDELAY: 744 /* 745 * Wait for the transmitter to go idle before starting 746 * an autoneg session, otherwise rl_start() may clobber 747 * our timeout, and we don't want to allow transmission 748 * during an autoneg session since that can screw it up. 749 */ 750 if (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx) { 751 sc->rl_want_auto = 1; 752 return; 753 } 754 rl_autoneg_xmit(sc); 755 ifp->if_timer = 5; 756 sc->rl_autoneg = 1; 757 sc->rl_want_auto = 0; 758 return; 759 break; 760 case RL_FLAG_DELAYTIMEO: 761 ifp->if_timer = 0; 762 sc->rl_autoneg = 0; 763 break; 764 default: 765 printf("rl%d: invalid autoneg flag: %d\n", sc->rl_unit, flag); 766 return; 767 } 768 769 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 770 if (verbose) 771 printf("rl%d: autoneg complete, ", sc->rl_unit); 772 phy_sts = rl_phy_readreg(sc, PHY_BMSR); 773 } else { 774 if (verbose) 775 printf("rl%d: autoneg not complete, ", sc->rl_unit); 776 } 777 778 media = rl_phy_readreg(sc, PHY_BMCR); 779 780 /* Link is good. Report modes and set duplex mode. */ 781 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 782 if (verbose) 783 printf("link status good "); 784 advert = rl_phy_readreg(sc, PHY_ANAR); 785 ability = rl_phy_readreg(sc, PHY_LPAR); 786 787 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 788 ifm->ifm_media = IFM_ETHER|IFM_100_T4; 789 media |= PHY_BMCR_SPEEDSEL; 790 media &= ~PHY_BMCR_DUPLEX; 791 printf("(100baseT4)\n"); 792 } else if (advert & PHY_ANAR_100BTXFULL && 793 ability & PHY_ANAR_100BTXFULL) { 794 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 795 media |= PHY_BMCR_SPEEDSEL; 796 media |= PHY_BMCR_DUPLEX; 797 printf("(full-duplex, 100Mbps)\n"); 798 } else if (advert & PHY_ANAR_100BTXHALF && 799 ability & PHY_ANAR_100BTXHALF) { 800 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 801 media |= PHY_BMCR_SPEEDSEL; 802 media &= ~PHY_BMCR_DUPLEX; 803 printf("(half-duplex, 100Mbps)\n"); 804 } else if (advert & PHY_ANAR_10BTFULL && 805 ability & PHY_ANAR_10BTFULL) { 806 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 807 media &= ~PHY_BMCR_SPEEDSEL; 808 media |= PHY_BMCR_DUPLEX; 809 printf("(full-duplex, 10Mbps)\n"); 810 } else { 811 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 812 media &= ~PHY_BMCR_SPEEDSEL; 813 media &= ~PHY_BMCR_DUPLEX; 814 printf("(half-duplex, 10Mbps)\n"); 815 } 816 817 /* Set ASIC's duplex mode to match the PHY. */ 818 rl_phy_writereg(sc, PHY_BMCR, media); 819 } else { 820 if (verbose) 821 printf("no carrier\n"); 822 } 823 824 rl_init(sc); 825 826 if (sc->rl_tx_pend) { 827 sc->rl_autoneg = 0; 828 sc->rl_tx_pend = 0; 829 rl_start(ifp); 830 } 831 832 return; 833} 834 835static void rl_getmode_mii(sc) 836 struct rl_softc *sc; 837{ 838 u_int16_t bmsr; 839 struct ifnet *ifp; 840 841 ifp = &sc->arpcom.ac_if; 842 843 bmsr = rl_phy_readreg(sc, PHY_BMSR); 844 if (bootverbose) 845 printf("rl%d: PHY status word: %x\n", sc->rl_unit, bmsr); 846 847 /* fallback */ 848 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 849 850 if (bmsr & PHY_BMSR_10BTHALF) { 851 if (bootverbose) 852 printf("rl%d: 10Mbps half-duplex mode supported\n", 853 sc->rl_unit); 854 ifmedia_add(&sc->ifmedia, 855 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 856 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 857 } 858 859 if (bmsr & PHY_BMSR_10BTFULL) { 860 if (bootverbose) 861 printf("rl%d: 10Mbps full-duplex mode supported\n", 862 sc->rl_unit); 863 ifmedia_add(&sc->ifmedia, 864 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 865 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 866 } 867 868 if (bmsr & PHY_BMSR_100BTXHALF) { 869 if (bootverbose) 870 printf("rl%d: 100Mbps half-duplex mode supported\n", 871 sc->rl_unit); 872 ifp->if_baudrate = 100000000; 873 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 874 ifmedia_add(&sc->ifmedia, 875 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 876 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 877 } 878 879 if (bmsr & PHY_BMSR_100BTXFULL) { 880 if (bootverbose) 881 printf("rl%d: 100Mbps full-duplex mode supported\n", 882 sc->rl_unit); 883 ifp->if_baudrate = 100000000; 884 ifmedia_add(&sc->ifmedia, 885 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 886 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 887 } 888 889 /* Some also support 100BaseT4. */ 890 if (bmsr & PHY_BMSR_100BT4) { 891 if (bootverbose) 892 printf("rl%d: 100baseT4 mode supported\n", sc->rl_unit); 893 ifp->if_baudrate = 100000000; 894 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); 895 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4; 896#ifdef FORCE_AUTONEG_TFOUR 897 if (bootverbose) 898 printf("rl%d: forcing on autoneg support for BT4\n", 899 sc->rl_unit); 900 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL): 901 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 902#endif 903 } 904 905 if (bmsr & PHY_BMSR_CANAUTONEG) { 906 if (bootverbose) 907 printf("rl%d: autoneg supported\n", sc->rl_unit); 908 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 909 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; 910 } 911 912 return; 913} 914 915/* 916 * Set speed and duplex mode. 917 */ 918static void rl_setmode_mii(sc, media) 919 struct rl_softc *sc; 920 int media; 921{ 922 u_int16_t bmcr; 923 924 printf("rl%d: selecting MII, ", sc->rl_unit); 925 926 bmcr = rl_phy_readreg(sc, PHY_BMCR); 927 928 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL| 929 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK); 930 931 if (IFM_SUBTYPE(media) == IFM_100_T4) { 932 printf("100Mbps/T4, half-duplex\n"); 933 bmcr |= PHY_BMCR_SPEEDSEL; 934 bmcr &= ~PHY_BMCR_DUPLEX; 935 } 936 937 if (IFM_SUBTYPE(media) == IFM_100_TX) { 938 printf("100Mbps, "); 939 bmcr |= PHY_BMCR_SPEEDSEL; 940 } 941 942 if (IFM_SUBTYPE(media) == IFM_10_T) { 943 printf("10Mbps, "); 944 bmcr &= ~PHY_BMCR_SPEEDSEL; 945 } 946 947 if ((media & IFM_GMASK) == IFM_FDX) { 948 printf("full duplex\n"); 949 bmcr |= PHY_BMCR_DUPLEX; 950 } else { 951 printf("half duplex\n"); 952 bmcr &= ~PHY_BMCR_DUPLEX; 953 } 954 955 rl_phy_writereg(sc, PHY_BMCR, bmcr); 956 957 return; 958} 959 | |
960static void rl_reset(sc) 961 struct rl_softc *sc; 962{ 963 register int i; 964 965 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 966 967 for (i = 0; i < RL_TIMEOUT; i++) { --- 6 unchanged lines hidden (view full) --- 974 975 return; 976} 977 978/* 979 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 980 * IDs against our list and return a device name if we find a match. 981 */ | 732static void rl_reset(sc) 733 struct rl_softc *sc; 734{ 735 register int i; 736 737 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 738 739 for (i = 0; i < RL_TIMEOUT; i++) { --- 6 unchanged lines hidden (view full) --- 746 747 return; 748} 749 750/* 751 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 752 * IDs against our list and return a device name if we find a match. 753 */ |
982static const char * 983rl_probe(config_id, device_id) 984 pcici_t config_id; 985 pcidi_t device_id; | 754static int rl_probe(dev) 755 device_t dev; |
986{ 987 struct rl_type *t; 988 989 t = rl_devs; 990 991 while(t->rl_name != NULL) { | 756{ 757 struct rl_type *t; 758 759 t = rl_devs; 760 761 while(t->rl_name != NULL) { |
992 if ((device_id & 0xFFFF) == t->rl_vid && 993 ((device_id >> 16) & 0xFFFF) == t->rl_did) { 994 return(t->rl_name); | 762 if ((pci_get_vendor(dev) == t->rl_vid) && 763 (pci_get_device(dev) == t->rl_did)) { 764 device_set_desc(dev, t->rl_name); 765 return(0); |
995 } 996 t++; 997 } 998 | 766 } 767 t++; 768 } 769 |
999 return(NULL); | 770 return(ENXIO); |
1000} 1001 1002/* 1003 * Attach the interface. Allocate softc structures, do ifmedia 1004 * setup and ethernet/BPF attach. 1005 */ | 771} 772 773/* 774 * Attach the interface. Allocate softc structures, do ifmedia 775 * setup and ethernet/BPF attach. 776 */ |
1006static void 1007rl_attach(config_id, unit) 1008 pcici_t config_id; 1009 int unit; | 777static int rl_attach(dev) 778 device_t dev; |
1010{ | 779{ |
1011 int s, i; 1012#ifndef RL_USEIOSPACE 1013 vm_offset_t pbase, vbase; 1014#endif | 780 int s; |
1015 u_char eaddr[ETHER_ADDR_LEN]; 1016 u_int32_t command; 1017 struct rl_softc *sc; 1018 struct ifnet *ifp; | 781 u_char eaddr[ETHER_ADDR_LEN]; 782 u_int32_t command; 783 struct rl_softc *sc; 784 struct ifnet *ifp; |
1019 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1020 struct rl_type *p; 1021 u_int16_t phy_vid, phy_did, phy_sts; | |
1022 u_int16_t rl_did = 0; | 785 u_int16_t rl_did = 0; |
786 int unit, error = 0, rid; |
|
1023 1024 s = splimp(); 1025 | 787 788 s = splimp(); 789 |
1026 sc = malloc(sizeof(struct rl_softc), M_DEVBUF, M_NOWAIT); 1027 if (sc == NULL) { 1028 printf("rl%d: no memory for softc struct!\n", unit); 1029 goto fail; 1030 } | 790 sc = device_get_softc(dev); 791 unit = device_get_unit(dev); |
1031 bzero(sc, sizeof(struct rl_softc)); 1032 1033 /* 1034 * Handle power management nonsense. 1035 */ 1036 | 792 bzero(sc, sizeof(struct rl_softc)); 793 794 /* 795 * Handle power management nonsense. 796 */ 797 |
1037 command = pci_conf_read(config_id, RL_PCI_CAPID) & 0x000000FF; | 798 command = pci_read_config(dev, RL_PCI_CAPID, 4) & 0x000000FF; |
1038 if (command == 0x01) { 1039 | 799 if (command == 0x01) { 800 |
1040 command = pci_conf_read(config_id, RL_PCI_PWRMGMTCTRL); | 801 command = pci_read_config(dev, RL_PCI_PWRMGMTCTRL, 4); |
1041 if (command & RL_PSTATE_MASK) { 1042 u_int32_t iobase, membase, irq; 1043 1044 /* Save important PCI config data. */ | 802 if (command & RL_PSTATE_MASK) { 803 u_int32_t iobase, membase, irq; 804 805 /* Save important PCI config data. */ |
1045 iobase = pci_conf_read(config_id, RL_PCI_LOIO); 1046 membase = pci_conf_read(config_id, RL_PCI_LOMEM); 1047 irq = pci_conf_read(config_id, RL_PCI_INTLINE); | 806 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 807 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 808 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); |
1048 1049 /* Reset the power state. */ 1050 printf("rl%d: chip is is in D%d power mode " 1051 "-- setting to D0\n", unit, command & RL_PSTATE_MASK); 1052 command &= 0xFFFFFFFC; | 809 810 /* Reset the power state. */ 811 printf("rl%d: chip is is in D%d power mode " 812 "-- setting to D0\n", unit, command & RL_PSTATE_MASK); 813 command &= 0xFFFFFFFC; |
1053 pci_conf_write(config_id, RL_PCI_PWRMGMTCTRL, command); | 814 pci_write_config(dev, RL_PCI_PWRMGMTCTRL, command, 4); |
1054 1055 /* Restore PCI config data. */ | 815 816 /* Restore PCI config data. */ |
1056 pci_conf_write(config_id, RL_PCI_LOIO, iobase); 1057 pci_conf_write(config_id, RL_PCI_LOMEM, membase); 1058 pci_conf_write(config_id, RL_PCI_INTLINE, irq); | 817 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 818 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 819 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); |
1059 } 1060 } 1061 1062 /* 1063 * Map control/status registers. 1064 */ | 820 } 821 } 822 823 /* 824 * Map control/status registers. 825 */ |
1065 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); | 826 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); |
1066 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); | 827 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); |
1067 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); 1068 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); | 828 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 829 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); |
1069 1070#ifdef RL_USEIOSPACE 1071 if (!(command & PCIM_CMD_PORTEN)) { 1072 printf("rl%d: failed to enable I/O ports!\n", unit); | 830 831#ifdef RL_USEIOSPACE 832 if (!(command & PCIM_CMD_PORTEN)) { 833 printf("rl%d: failed to enable I/O ports!\n", unit); |
1073 free(sc, M_DEVBUF); | 834 error = ENXIO; |
1074 goto fail; 1075 } | 835 goto fail; 836 } |
1076 1077 if (!pci_map_port(config_id, RL_PCI_LOIO, 1078 (pci_port_t *)&(sc->rl_bhandle))) { 1079 printf ("rl%d: couldn't map ports\n", unit); 1080 goto fail; 1081 } 1082#ifdef __i386__ 1083 sc->rl_btag = I386_BUS_SPACE_IO; 1084#endif 1085#ifdef __alpha__ 1086 sc->rl_btag = ALPHA_BUS_SPACE_IO; 1087#endif | |
1088#else 1089 if (!(command & PCIM_CMD_MEMEN)) { 1090 printf("rl%d: failed to enable memory mapping!\n", unit); | 837#else 838 if (!(command & PCIM_CMD_MEMEN)) { 839 printf("rl%d: failed to enable memory mapping!\n", unit); |
840 error = ENXIO; |
|
1091 goto fail; 1092 } | 841 goto fail; 842 } |
843#endif |
|
1093 | 844 |
1094 if (!pci_map_mem(config_id, RL_PCI_LOMEM, &vbase, &pbase)) { 1095 printf ("rl%d: couldn't map memory\n", unit); | 845 rid = RL_RID; 846 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 847 0, ~0, 1, RF_ACTIVE); 848 849 if (sc->rl_res == NULL) { 850 printf ("rl%d: couldn't map ports/memory\n", unit); 851 error = ENXIO; |
1096 goto fail; 1097 } | 852 goto fail; 853 } |
1098#ifdef __i386__ 1099 sc->rl_btag = I386_BUS_SPACE_MEM; 1100#endif 1101#ifdef __alpha__ 1102 sc->rl_btag = ALPHA_BUS_SPACE_MEM; 1103#endif 1104 sc->rl_bhandle = vbase; 1105#endif | |
1106 | 854 |
1107 /* Allocate interrupt */ 1108 if (!pci_map_int(config_id, rl_intr, sc, &net_imask)) { | 855 sc->rl_btag = rman_get_bustag(sc->rl_res); 856 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 857 858 rid = 0; 859 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 860 RF_SHAREABLE | RF_ACTIVE); 861 862 if (sc->rl_irq == NULL) { |
1109 printf("rl%d: couldn't map interrupt\n", unit); | 863 printf("rl%d: couldn't map interrupt\n", unit); |
864 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 865 error = ENXIO; |
|
1110 goto fail; 1111 } 1112 | 866 goto fail; 867 } 868 |
869 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 870 rl_intr, sc, &sc->rl_intrhand); 871 872 if (error) { 873 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 874 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 875 printf("rl%d: couldn't set up irq\n", unit); 876 goto fail; 877 } 878 879 callout_handle_init(&sc->rl_stat_ch); 880 |
|
1113 /* Reset the adapter. */ 1114 rl_reset(sc); 1115 1116 /* 1117 * Get station address from the EEPROM. 1118 */ 1119 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 1120 --- 13 unchanged lines hidden (view full) --- 1134 1135 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 1136 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139) 1137 sc->rl_type = RL_8139; 1138 else if (rl_did == RT_DEVICEID_8129) 1139 sc->rl_type = RL_8129; 1140 else { 1141 printf("rl%d: unknown device ID: %x\n", unit, rl_did); | 881 /* Reset the adapter. */ 882 rl_reset(sc); 883 884 /* 885 * Get station address from the EEPROM. 886 */ 887 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 888 --- 13 unchanged lines hidden (view full) --- 902 903 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 904 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139) 905 sc->rl_type = RL_8139; 906 else if (rl_did == RT_DEVICEID_8129) 907 sc->rl_type = RL_8129; 908 else { 909 printf("rl%d: unknown device ID: %x\n", unit, rl_did); |
1142 free(sc, M_DEVBUF); | 910 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 911 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 912 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 913 error = ENXIO; |
1143 goto fail; 1144 } 1145 1146 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 32, M_DEVBUF, | 914 goto fail; 915 } 916 917 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 32, M_DEVBUF, |
1147 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); | 918 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); |
1148 1149 if (sc->rl_cdata.rl_rx_buf == NULL) { | 919 920 if (sc->rl_cdata.rl_rx_buf == NULL) { |
1150 free(sc, M_DEVBUF); | |
1151 printf("rl%d: no memory for list buffers!\n", unit); | 921 printf("rl%d: no memory for list buffers!\n", unit); |
922 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 923 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 924 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 925 error = ENXIO; |
|
1152 goto fail; 1153 } 1154 1155 /* Leave a few bytes before the start of the RX ring buffer. */ 1156 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1157 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1158 | 926 goto fail; 927 } 928 929 /* Leave a few bytes before the start of the RX ring buffer. */ 930 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 931 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 932 |
933 /* Do MII setup */ 934 if (mii_phy_probe(dev, &sc->rl_miibus, 935 rl_ifmedia_upd, rl_ifmedia_sts)) { 936 printf("rl%d: MII without any phy!\n", sc->rl_unit); 937 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 938 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 939 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 940 free(sc->rl_cdata.rl_rx_buf, M_DEVBUF); 941 error = ENXIO; 942 goto fail; 943 } 944 |
|
1159 ifp = &sc->arpcom.ac_if; 1160 ifp->if_softc = sc; 1161 ifp->if_unit = unit; 1162 ifp->if_name = "rl"; 1163 ifp->if_mtu = ETHERMTU; 1164 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1165 ifp->if_ioctl = rl_ioctl; 1166 ifp->if_output = ether_output; 1167 ifp->if_start = rl_start; 1168 ifp->if_watchdog = rl_watchdog; 1169 ifp->if_init = rl_init; 1170 ifp->if_baudrate = 10000000; 1171 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1172 | 945 ifp = &sc->arpcom.ac_if; 946 ifp->if_softc = sc; 947 ifp->if_unit = unit; 948 ifp->if_name = "rl"; 949 ifp->if_mtu = ETHERMTU; 950 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 951 ifp->if_ioctl = rl_ioctl; 952 ifp->if_output = ether_output; 953 ifp->if_start = rl_start; 954 ifp->if_watchdog = rl_watchdog; 955 ifp->if_init = rl_init; 956 ifp->if_baudrate = 10000000; 957 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 958 |
1173 if (sc->rl_type == RL_8129) { 1174 if (bootverbose) 1175 printf("rl%d: probing for a PHY\n", sc->rl_unit); 1176 for (i = RL_PHYADDR_MIN; i < RL_PHYADDR_MAX + 1; i++) { 1177 if (bootverbose) 1178 printf("rl%d: checking address: %d\n", 1179 sc->rl_unit, i); 1180 sc->rl_phy_addr = i; 1181 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 1182 DELAY(500); 1183 while(rl_phy_readreg(sc, PHY_BMCR) 1184 & PHY_BMCR_RESET); 1185 if ((phy_sts = rl_phy_readreg(sc, PHY_BMSR))) 1186 break; 1187 } 1188 if (phy_sts) { 1189 phy_vid = rl_phy_readreg(sc, PHY_VENID); 1190 phy_did = rl_phy_readreg(sc, PHY_DEVID); 1191 if (bootverbose) 1192 printf("rl%d: found PHY at address %d, ", 1193 sc->rl_unit, sc->rl_phy_addr); 1194 if (bootverbose) 1195 printf("vendor id: %x device id: %x\n", 1196 phy_vid, phy_did); 1197 p = rl_phys; 1198 while(p->rl_vid) { 1199 if (phy_vid == p->rl_vid && 1200 (phy_did | 0x000F) == p->rl_did) { 1201 sc->rl_pinfo = p; 1202 break; 1203 } 1204 p++; 1205 } 1206 if (sc->rl_pinfo == NULL) 1207 sc->rl_pinfo = &rl_phys[PHY_UNKNOWN]; 1208 if (bootverbose) 1209 printf("rl%d: PHY type: %s\n", 1210 sc->rl_unit, sc->rl_pinfo->rl_name); 1211 } else { 1212 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1213 } 1214 } 1215 | |
1216 /* | 959 /* |
1217 * Do ifmedia setup. 1218 */ 1219 ifmedia_init(&sc->ifmedia, 0, rl_ifmedia_upd, rl_ifmedia_sts); 1220 1221 rl_getmode_mii(sc); 1222 1223 /* Choose a default media. */ 1224 media = IFM_ETHER|IFM_AUTO; 1225 ifmedia_set(&sc->ifmedia, media); 1226 1227 rl_autoneg_mii(sc, RL_FLAG_FORCEDELAY, 1); 1228 1229 /* | |
1230 * Call MI attach routines. 1231 */ 1232 if_attach(ifp); 1233 ether_ifattach(ifp); 1234 1235#if NBPF > 0 1236 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1237#endif | 960 * Call MI attach routines. 961 */ 962 if_attach(ifp); 963 ether_ifattach(ifp); 964 965#if NBPF > 0 966 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 967#endif |
1238 EVENTHANDLER_REGISTER(shutdown_post_sync, rl_shutdown, sc, 1239 SHUTDOWN_PRI_DEFAULT); | |
1240 1241fail: 1242 splx(s); | 968 969fail: 970 splx(s); |
1243 return; | 971 return(error); |
1244} 1245 | 972} 973 |
974static int rl_detach(dev) 975 device_t dev; 976{ 977 struct rl_softc *sc; 978 struct ifnet *ifp; 979 int s; 980 981 s = splimp(); 982 983 sc = device_get_softc(dev); 984 ifp = &sc->arpcom.ac_if; 985 986 if_detach(ifp); 987 rl_stop(sc); 988 989 bus_generic_detach(dev); 990 device_delete_child(dev, sc->rl_miibus); 991 992 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 993 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 994 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 995 996 free(sc->rl_cdata.rl_rx_buf, M_DEVBUF); 997 998 splx(s); 999 1000 return(0); 1001} 1002 |
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1246/* 1247 * Initialize the transmit descriptors. 1248 */ 1249static int rl_list_tx_init(sc) 1250 struct rl_softc *sc; 1251{ 1252 struct rl_chain_data *cd; 1253 int i; --- 76 unchanged lines hidden (view full) --- 1330 * datasheet makes absolutely no mention of this and 1331 * RealTek should be shot for this. 1332 */ 1333 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1334 break; 1335 1336 if (!(rxstat & RL_RXSTAT_RXOK)) { 1337 ifp->if_ierrors++; | 1003/* 1004 * Initialize the transmit descriptors. 1005 */ 1006static int rl_list_tx_init(sc) 1007 struct rl_softc *sc; 1008{ 1009 struct rl_chain_data *cd; 1010 int i; --- 76 unchanged lines hidden (view full) --- 1087 * datasheet makes absolutely no mention of this and 1088 * RealTek should be shot for this. 1089 */ 1090 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1091 break; 1092 1093 if (!(rxstat & RL_RXSTAT_RXOK)) { 1094 ifp->if_ierrors++; |
1338 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT| 1339 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR| 1340 RL_RXSTAT_ALIGNERR)) { 1341 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB); 1342 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB| 1343 RL_CMD_RX_ENB); 1344 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1345 CSR_WRITE_4(sc, RL_RXADDR, 1346 vtophys(sc->rl_cdata.rl_rx_buf)); 1347 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1348 cur_rx = 0; 1349 } 1350 break; | 1095 rl_init(sc); 1096 return; |
1351 } 1352 1353 /* No errors; receive the packet. */ 1354 total_len = rxstat >> 16; 1355 rx_bytes += total_len + 4; 1356 1357 /* 1358 * XXX The RealTek chip includes the CRC with every --- 121 unchanged lines hidden (view full) --- 1480 if ((txstat & RL_TXSTAT_TXABRT) || 1481 (txstat & RL_TXSTAT_OUTOFWIN)) 1482 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1483 } 1484 RL_INC(sc->rl_cdata.last_tx); 1485 ifp->if_flags &= ~IFF_OACTIVE; 1486 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1487 | 1097 } 1098 1099 /* No errors; receive the packet. */ 1100 total_len = rxstat >> 16; 1101 rx_bytes += total_len + 4; 1102 1103 /* 1104 * XXX The RealTek chip includes the CRC with every --- 121 unchanged lines hidden (view full) --- 1226 if ((txstat & RL_TXSTAT_TXABRT) || 1227 (txstat & RL_TXSTAT_OUTOFWIN)) 1228 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1229 } 1230 RL_INC(sc->rl_cdata.last_tx); 1231 ifp->if_flags &= ~IFF_OACTIVE; 1232 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1233 |
1488 if (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) { 1489 if (sc->rl_want_auto) 1490 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1); 1491 } | 1234 return; 1235} |
1492 | 1236 |
1237static void rl_tick(xsc) 1238 void *xsc; 1239{ 1240 struct rl_softc *sc; 1241 struct mii_data *mii; 1242 int s; 1243 1244 s = splimp(); 1245 1246 sc = xsc; 1247 mii = device_get_softc(sc->rl_miibus); 1248 1249 mii_tick(mii); 1250 1251 splx(s); 1252 1253 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1254 |
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1493 return; 1494} 1495 1496static void rl_intr(arg) 1497 void *arg; 1498{ 1499 struct rl_softc *sc; 1500 struct ifnet *ifp; --- 95 unchanged lines hidden (view full) --- 1596static void rl_start(ifp) 1597 struct ifnet *ifp; 1598{ 1599 struct rl_softc *sc; 1600 struct mbuf *m_head = NULL; 1601 1602 sc = ifp->if_softc; 1603 | 1255 return; 1256} 1257 1258static void rl_intr(arg) 1259 void *arg; 1260{ 1261 struct rl_softc *sc; 1262 struct ifnet *ifp; --- 95 unchanged lines hidden (view full) --- 1358static void rl_start(ifp) 1359 struct ifnet *ifp; 1360{ 1361 struct rl_softc *sc; 1362 struct mbuf *m_head = NULL; 1363 1364 sc = ifp->if_softc; 1365 |
1604 if (sc->rl_autoneg) { 1605 sc->rl_tx_pend = 1; 1606 return; 1607 } 1608 | |
1609 while(RL_CUR_TXMBUF(sc) == NULL) { 1610 IF_DEQUEUE(&ifp->if_snd, m_head); 1611 if (m_head == NULL) 1612 break; 1613 1614 rl_encap(sc, m_head); 1615 1616#if NBPF > 0 --- 31 unchanged lines hidden (view full) --- 1648 return; 1649} 1650 1651static void rl_init(xsc) 1652 void *xsc; 1653{ 1654 struct rl_softc *sc = xsc; 1655 struct ifnet *ifp = &sc->arpcom.ac_if; | 1366 while(RL_CUR_TXMBUF(sc) == NULL) { 1367 IF_DEQUEUE(&ifp->if_snd, m_head); 1368 if (m_head == NULL) 1369 break; 1370 1371 rl_encap(sc, m_head); 1372 1373#if NBPF > 0 --- 31 unchanged lines hidden (view full) --- 1405 return; 1406} 1407 1408static void rl_init(xsc) 1409 void *xsc; 1410{ 1411 struct rl_softc *sc = xsc; 1412 struct ifnet *ifp = &sc->arpcom.ac_if; |
1413 struct mii_data *mii; |
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1656 int s, i; 1657 u_int32_t rxcfg = 0; | 1414 int s, i; 1415 u_int32_t rxcfg = 0; |
1658 u_int16_t phy_bmcr = 0; | |
1659 | 1416 |
1660 if (sc->rl_autoneg) 1661 return; 1662 | |
1663 s = splimp(); 1664 | 1417 s = splimp(); 1418 |
1665 /* 1666 * XXX Hack for the 8139: the built-in autoneg logic's state 1667 * gets reset by rl_init() when we don't want it to. Try 1668 * to preserve it. (For 8129 cards with real external PHYs, 1669 * the BMCR register doesn't change, but this doesn't hurt.) 1670 */ 1671 if (sc->rl_type == RL_8139) 1672 phy_bmcr = rl_phy_readreg(sc, PHY_BMCR); | 1419 mii = device_get_softc(sc->rl_miibus); |
1673 1674 /* 1675 * Cancel pending I/O and free all RX/TX buffers. 1676 */ 1677 rl_stop(sc); 1678 1679 /* Init our MAC address */ 1680 for (i = 0; i < ETHER_ADDR_LEN; i++) { --- 52 unchanged lines hidden (view full) --- 1733 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1734 1735 /* Start RX/TX process. */ 1736 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1737 1738 /* Enable receiver and transmitter. */ 1739 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1740 | 1420 1421 /* 1422 * Cancel pending I/O and free all RX/TX buffers. 1423 */ 1424 rl_stop(sc); 1425 1426 /* Init our MAC address */ 1427 for (i = 0; i < ETHER_ADDR_LEN; i++) { --- 52 unchanged lines hidden (view full) --- 1480 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1481 1482 /* Start RX/TX process. */ 1483 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1484 1485 /* Enable receiver and transmitter. */ 1486 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1487 |
1741 /* Restore state of BMCR */ 1742 if (sc->rl_pinfo != NULL) 1743 rl_phy_writereg(sc, PHY_BMCR, phy_bmcr); | 1488 mii_mediachg(mii); |
1744 1745 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1746 1747 ifp->if_flags |= IFF_RUNNING; 1748 ifp->if_flags &= ~IFF_OACTIVE; 1749 1750 (void)splx(s); 1751 | 1489 1490 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1491 1492 ifp->if_flags |= IFF_RUNNING; 1493 ifp->if_flags &= ~IFF_OACTIVE; 1494 1495 (void)splx(s); 1496 |
1497 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1498 |
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1752 return; 1753} 1754 1755/* 1756 * Set media options. 1757 */ 1758static int rl_ifmedia_upd(ifp) 1759 struct ifnet *ifp; 1760{ 1761 struct rl_softc *sc; | 1499 return; 1500} 1501 1502/* 1503 * Set media options. 1504 */ 1505static int rl_ifmedia_upd(ifp) 1506 struct ifnet *ifp; 1507{ 1508 struct rl_softc *sc; |
1762 struct ifmedia *ifm; | 1509 struct mii_data *mii; |
1763 1764 sc = ifp->if_softc; | 1510 1511 sc = ifp->if_softc; |
1765 ifm = &sc->ifmedia; | 1512 mii = device_get_softc(sc->rl_miibus); 1513 mii_mediachg(mii); |
1766 | 1514 |
1767 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1768 return(EINVAL); 1769 1770 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1771 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1); 1772 else 1773 rl_setmode_mii(sc, ifm->ifm_media); 1774 | |
1775 return(0); 1776} 1777 1778/* 1779 * Report current media status. 1780 */ 1781static void rl_ifmedia_sts(ifp, ifmr) 1782 struct ifnet *ifp; 1783 struct ifmediareq *ifmr; 1784{ 1785 struct rl_softc *sc; | 1515 return(0); 1516} 1517 1518/* 1519 * Report current media status. 1520 */ 1521static void rl_ifmedia_sts(ifp, ifmr) 1522 struct ifnet *ifp; 1523 struct ifmediareq *ifmr; 1524{ 1525 struct rl_softc *sc; |
1786 u_int16_t advert = 0, ability = 0; | 1526 struct mii_data *mii; |
1787 1788 sc = ifp->if_softc; | 1527 1528 sc = ifp->if_softc; |
1529 mii = device_get_softc(sc->rl_miibus); |
|
1789 | 1530 |
1790 if (!(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1791 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1792 ifmr->ifm_active = IFM_ETHER|IFM_100_TX; 1793 else 1794 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 1795 1796 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1797 ifmr->ifm_active |= IFM_FDX; 1798 else 1799 ifmr->ifm_active |= IFM_HDX; 1800 return; 1801 } | 1531 mii_pollstat(mii); 1532 ifmr->ifm_active = mii->mii_media_active; 1533 ifmr->ifm_status = mii->mii_media_status; |
1802 | 1534 |
1803 ability = rl_phy_readreg(sc, PHY_LPAR); 1804 advert = rl_phy_readreg(sc, PHY_ANAR); 1805 if (advert & PHY_ANAR_100BT4 && 1806 ability & PHY_ANAR_100BT4) { 1807 ifmr->ifm_active = IFM_ETHER|IFM_100_T4; 1808 } else if (advert & PHY_ANAR_100BTXFULL && 1809 ability & PHY_ANAR_100BTXFULL) { 1810 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX; 1811 } else if (advert & PHY_ANAR_100BTXHALF && 1812 ability & PHY_ANAR_100BTXHALF) { 1813 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX; 1814 } else if (advert & PHY_ANAR_10BTFULL && 1815 ability & PHY_ANAR_10BTFULL) { 1816 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX; 1817 } else if (advert & PHY_ANAR_10BTHALF && 1818 ability & PHY_ANAR_10BTHALF) { 1819 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX; 1820 } 1821 | |
1822 return; 1823} 1824 1825static int rl_ioctl(ifp, command, data) 1826 struct ifnet *ifp; 1827 u_long command; 1828 caddr_t data; 1829{ 1830 struct rl_softc *sc = ifp->if_softc; 1831 struct ifreq *ifr = (struct ifreq *) data; | 1535 return; 1536} 1537 1538static int rl_ioctl(ifp, command, data) 1539 struct ifnet *ifp; 1540 u_long command; 1541 caddr_t data; 1542{ 1543 struct rl_softc *sc = ifp->if_softc; 1544 struct ifreq *ifr = (struct ifreq *) data; |
1545 struct mii_data *mii; |
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1832 int s, error = 0; 1833 1834 s = splimp(); 1835 1836 switch(command) { 1837 case SIOCSIFADDR: 1838 case SIOCGIFADDR: 1839 case SIOCSIFMTU: --- 10 unchanged lines hidden (view full) --- 1850 break; 1851 case SIOCADDMULTI: 1852 case SIOCDELMULTI: 1853 rl_setmulti(sc); 1854 error = 0; 1855 break; 1856 case SIOCGIFMEDIA: 1857 case SIOCSIFMEDIA: | 1546 int s, error = 0; 1547 1548 s = splimp(); 1549 1550 switch(command) { 1551 case SIOCSIFADDR: 1552 case SIOCGIFADDR: 1553 case SIOCSIFMTU: --- 10 unchanged lines hidden (view full) --- 1564 break; 1565 case SIOCADDMULTI: 1566 case SIOCDELMULTI: 1567 rl_setmulti(sc); 1568 error = 0; 1569 break; 1570 case SIOCGIFMEDIA: 1571 case SIOCSIFMEDIA: |
1858 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); | 1572 mii = device_get_softc(sc->rl_miibus); 1573 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); |
1859 break; 1860 default: 1861 error = EINVAL; 1862 break; 1863 } 1864 1865 (void)splx(s); 1866 1867 return(error); 1868} 1869 1870static void rl_watchdog(ifp) 1871 struct ifnet *ifp; 1872{ 1873 struct rl_softc *sc; 1874 1875 sc = ifp->if_softc; 1876 | 1574 break; 1575 default: 1576 error = EINVAL; 1577 break; 1578 } 1579 1580 (void)splx(s); 1581 1582 return(error); 1583} 1584 1585static void rl_watchdog(ifp) 1586 struct ifnet *ifp; 1587{ 1588 struct rl_softc *sc; 1589 1590 sc = ifp->if_softc; 1591 |
1877 if (sc->rl_autoneg) { 1878 rl_autoneg_mii(sc, RL_FLAG_DELAYTIMEO, 1); 1879 return; 1880 } 1881 | |
1882 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1883 ifp->if_oerrors++; | 1592 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1593 ifp->if_oerrors++; |
1884 if (!(rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1885 printf("rl%d: no carrier - transceiver cable problem?\n", 1886 sc->rl_unit); | 1594 |
1887 rl_txeof(sc); 1888 rl_rxeof(sc); 1889 rl_init(sc); 1890 1891 return; 1892} 1893 1894/* --- 4 unchanged lines hidden (view full) --- 1899 struct rl_softc *sc; 1900{ 1901 register int i; 1902 struct ifnet *ifp; 1903 1904 ifp = &sc->arpcom.ac_if; 1905 ifp->if_timer = 0; 1906 | 1595 rl_txeof(sc); 1596 rl_rxeof(sc); 1597 rl_init(sc); 1598 1599 return; 1600} 1601 1602/* --- 4 unchanged lines hidden (view full) --- 1607 struct rl_softc *sc; 1608{ 1609 register int i; 1610 struct ifnet *ifp; 1611 1612 ifp = &sc->arpcom.ac_if; 1613 ifp->if_timer = 0; 1614 |
1615 untimeout(rl_tick, sc, sc->rl_stat_ch); 1616 |
|
1907 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1908 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1909 1910 /* 1911 * Free the TX list buffers. 1912 */ 1913 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1914 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { --- 7 unchanged lines hidden (view full) --- 1922 1923 return; 1924} 1925 1926/* 1927 * Stop all chip I/O so that the kernel's probe routines don't 1928 * get confused by errant DMAs when rebooting. 1929 */ | 1617 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1618 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1619 1620 /* 1621 * Free the TX list buffers. 1622 */ 1623 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1624 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { --- 7 unchanged lines hidden (view full) --- 1632 1633 return; 1634} 1635 1636/* 1637 * Stop all chip I/O so that the kernel's probe routines don't 1638 * get confused by errant DMAs when rebooting. 1639 */ |
1930static void rl_shutdown(arg, howto) 1931 void *arg; 1932 int howto; | 1640static void rl_shutdown(dev) 1641 device_t dev; |
1933{ | 1642{ |
1934 struct rl_softc *sc = (struct rl_softc *)arg; | 1643 struct rl_softc *sc; |
1935 | 1644 |
1645 sc = device_get_softc(dev); 1646 |
|
1936 rl_stop(sc); 1937 1938 return; 1939} | 1647 rl_stop(sc); 1648 1649 return; 1650} |
1940 1941 1942static struct pci_device rl_device = { 1943 "rl", 1944 rl_probe, 1945 rl_attach, 1946 &rl_count, 1947 NULL 1948}; 1949COMPAT_PCI_DRIVER(rl, rl_device); | |