1/*
2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28/*
29 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
30 *
31 */
32
33#include "rc.h"
34#if NRC > 0
35
36/*#define RCDEBUG*/
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/ioctl.h>
41#include <sys/tty.h>
42#include <sys/proc.h>
43#include <sys/user.h>
44#include <sys/conf.h>
45#include <sys/dkstat.h>
46#include <sys/file.h>
47#include <sys/uio.h>
48#include <sys/kernel.h>
49#include <sys/syslog.h>
50#include <sys/devconf.h>
51
52#include <machine/clock.h>
53
54#include <i386/isa/isa.h>
55#include <i386/isa/isa_device.h>
56#include <i386/isa/sioreg.h>
57
58#include <i386/isa/ic/cd180.h>
59#include <i386/isa/rcreg.h>
60
61/* Prototypes */
62int rcprobe __P((struct isa_device *));
63int rcattach __P((struct isa_device *));
64
65int rcopen __P((dev_t, int, int, struct proc *));
66int rcclose __P((dev_t, int, int, struct proc *));
67int rcread __P((dev_t, struct uio *, int));
68int rcwrite __P((dev_t, struct uio *, int));
69void rcintr __P((int));
70void rcpoll __P((void));
71void rcstop __P((struct tty *, int));
72int rcioctl __P((dev_t, int, caddr_t, int, struct proc *));
73
74#define rcin(port) RC_IN (nec, port)
75#define rcout(port,v) RC_OUT (nec, port, v)
76
77#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
78#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
79
80#define RC_IBUFSIZE 256
81#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
82#define RC_OBUFSIZE 512
83#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4)
84#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
85#define LOTS_OF_EVENTS 64
86
87#define RC_FAKEID 0x10
88
89#define RC_PROBED 1
90#define RC_ATTACHED 2
91
92#define GET_UNIT(dev) (minor(dev) & 0x3F)
93#define CALLOUT(dev) (minor(dev) & 0x80)
94
95/* For isa routines */
96struct isa_driver rcdriver = {
97 rcprobe, rcattach, "rc"
98};
99
100/* Per-board structure */
101static struct rc_softc {
102 u_int rcb_probed; /* 1 - probed, 2 - attached */
103 u_int rcb_addr; /* Base I/O addr */
104 u_int rcb_unit; /* unit # */
105 u_char rcb_dtr; /* DTR status */
106 struct rc_chans *rcb_baserc; /* base rc ptr */
107} rc_softc[NRC];
108
109/* Per-channel structure */
110static struct rc_chans {
111 struct rc_softc *rc_rcb; /* back ptr */
112 u_short rc_flags; /* Misc. flags */
113 int rc_chan; /* Channel # */
114 u_char rc_ier; /* intr. enable reg */
115 u_char rc_msvr; /* modem sig. status */
116 u_char rc_cor2; /* options reg */
117 u_char rc_pendcmd; /* special cmd pending */
118 u_int rc_dtrwait; /* dtr timeout */
119 u_int rc_dcdwaits; /* how many waits DCD in open */
120 u_char rc_hotchar; /* end packed optimize */
121 struct tty *rc_tp; /* tty struct */
122 u_char *rc_iptr; /* Chars input buffer */
123 u_char *rc_hiwat; /* hi-water mark */
124 u_char *rc_bufend; /* end of buffer */
125 u_char *rc_optr; /* ptr in output buf */
126 u_char *rc_obufend; /* end of output buf */
127 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */
128 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */
129} rc_chans[NRC * CD180_NCHAN];
130
131static int rc_scheduled_event = 0;
132
133/* for pstat -t */
134struct tty rc_tty[NRC * CD180_NCHAN];
135int nrc_tty = NRC * CD180_NCHAN;
136
137/* Flags */
138#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */
139#define RC_ACTOUT 0x0002 /* Dial-out port active */
140#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */
141#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */
142#define RC_DORXFER 0x0010 /* RXFER event planned */
143#define RC_DOXXFER 0x0020 /* XXFER event planned */
144#define RC_MODCHG 0x0040 /* Modem status changed */
145#define RC_OSUSP 0x0080 /* Output suspended */
146#define RC_OSBUSY 0x0100 /* start() routine in progress */
147#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */
148#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */
149#define RC_SEND_RDY 0x0800 /* ready to send */
150
151static struct speedtab rc_speedtab[] = {
152 0, 0,
153 50, RC_BRD(50),
154 75, RC_BRD(75),
155 110, RC_BRD(110),
156 134, RC_BRD(134),
157 150, RC_BRD(150),
158 200, RC_BRD(200),
159 300, RC_BRD(300),
160 600, RC_BRD(600),
161 1200, RC_BRD(1200),
162 1800, RC_BRD(1800),
163 2400, RC_BRD(2400),
164 4800, RC_BRD(4800),
165 9600, RC_BRD(9600),
166 19200, RC_BRD(19200),
167 38400, RC_BRD(38400),
168 57600, RC_BRD(57600),
169 /* real max value is 76800 with 9.8304 MHz clock */
170 -1, -1
171};
172
173/* Table for translation of RCSR status bits to internal form */
174static int rc_rcsrt[16] = {
175 0, TTY_OE, TTY_FE,
176 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE,
177 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
178 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE,
179 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
180 TTY_BI|TTY_PE|TTY_FE|TTY_OE
181};
182
183/* Static prototypes */
184static void rc_hwreset __P((int, int, unsigned int));
185static int rc_test __P((int, int));
186static void rc_discard_output __P((struct rc_chans *));
187static void rc_hardclose __P((struct rc_chans *));
188static int rc_modctl __P((struct rc_chans *, int, int));
189static void rc_start __P((struct tty *));
190static int rc_param __P((struct tty *, struct termios *));
191static void rc_registerdev __P((struct isa_device *id));
192static void rc_reinit __P((struct rc_softc *));
193#ifdef RCDEBUG
194static void printrcflags();
195#endif
196static timeout_t rc_dtrwakeup;
197static timeout_t rc_wakeup;
198static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *));
199static void rc_wait0 __P((int nec, int unit, int chan, int line));
200
201/**********************************************/
202
203/* Quick device probing */
204int rcprobe(dvp)
205 struct isa_device *dvp;
206{
207 int irq = ffs(dvp->id_irq) - 1;
208 register int nec = dvp->id_iobase;
209
210 if (dvp->id_unit > NRC)
211 return 0;
212 if (!RC_VALIDADDR(nec)) {
213 printf("rc%d: illegal base address %x\n", nec);
214 return 0;
215 }
216 if (!RC_VALIDIRQ(irq)) {
217 printf("rc%d: illegal IRQ value %d\n", irq);
218 return 0;
219 }
220 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
221 rcout(CD180_PPRH, 0x11);
222 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
223 return 0;
224 /* Now, test the board more thoroughly, with diagnostic */
225 if (rc_test(nec, dvp->id_unit))
226 return 0;
227 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
228
229 return 0xF;
230}
231
232static struct kern_devconf kdc_rc[NRC] = { {
233 0, 0, 0, /* filled in by dev_attach */
234 "rc", 0, { MDDT_ISA, 0, "tty" },
235 isa_generic_externalize, 0, 0, ISA_EXTERNALLEN,
236 &kdc_isa0, /* parent */
237 0, /* parentdata */
238 DC_UNCONFIGURED, /* state */
239 "RISCom/8 multiport card",
240 DC_CLS_SERIAL /* class */
241} };
242
243static void
244rc_registerdev(id)
245 struct isa_device *id;
246{
247 int unit;
248
249 unit = id->id_unit;
250 if (unit != 0)
251 kdc_rc[unit] = kdc_rc[0];
252 kdc_rc[unit].kdc_unit = unit;
253 kdc_rc[unit].kdc_isa = id;
254 kdc_rc[unit].kdc_state = DC_UNKNOWN;
255 dev_attach(&kdc_rc[unit]);
256}
257
258int rcattach(dvp)
259 struct isa_device *dvp;
260{
261 register int i, chan, nec = dvp->id_iobase;
262 struct rc_softc *rcb = &rc_softc[dvp->id_unit];
263 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN];
264 static int rc_wakeup_started = 0;
265 struct tty *tp;
266
267 /* Thorooughly test the device */
268 if (rcb->rcb_probed != RC_PROBED)
269 return 0;
270 rcb->rcb_addr = nec;
271 rcb->rcb_dtr = 0;
272 rcb->rcb_baserc = rc;
273 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
274 printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit,
275 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
276
277 rc_registerdev(dvp);
278
279 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
280 rc->rc_rcb = rcb;
281 rc->rc_chan = chan;
282 rc->rc_iptr = rc->rc_ibuf;
283 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
284 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
285 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0;
286 rc->rc_cor2 = rc->rc_pendcmd = 0;
287 rc->rc_optr = rc->rc_obufend = rc->rc_obuf;
288 rc->rc_dtrwait = 3 * hz;
289 rc->rc_dcdwaits= 0;
290 rc->rc_hotchar = 0;
291 tp = rc->rc_tp = &rc_tty[chan];
292 ttychars(tp);
293 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
294 tp->t_cflag = TTYDEF_CFLAG;
295 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
296 }
297 rcb->rcb_probed = RC_ATTACHED;
298 if (!rc_wakeup_started) {
299 rc_wakeup((void *)NULL);
300 rc_wakeup_started = 0;
301 }
302 return 1;
303}
304
305/* RC interrupt handling */
306void rcintr(unit)
307 int unit;
308{
309 register struct rc_softc *rcb = &rc_softc[unit];
310 register struct rc_chans *rc;
311 register int nec, resid;
312 register u_char val, iack, bsr, ucnt, *optr;
313 int good_data, t_state;
314
315 if (rcb->rcb_probed != RC_ATTACHED) {
316 printf("rc%d: bogus interrupt\n", unit);
317 return;
318 }
319 nec = rcb->rcb_addr;
320
321 bsr = ~(rcin(RC_BSR));
322
323 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
324 printf("rc%d: extra interrupt\n", unit);
325 rcout(CD180_EOIR, 0);
326 return;
327 }
328
329 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
330#ifdef RCDEBUG_DETAILED
331 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
332 (bsr & RC_BSR_TOUT)?"TOUT ":"",
333 (bsr & RC_BSR_RXINT)?"RXINT ":"",
334 (bsr & RC_BSR_TXINT)?"TXINT ":"",
335 (bsr & RC_BSR_MOINT)?"MOINT":"");
336#endif
337 if (bsr & RC_BSR_TOUT) {
338 printf("rc%d: hardware failure, reset board\n", unit);
339 rcout(RC_CTOUT, 0);
340 rc_reinit(rcb);
341 return;
342 }
343 if (bsr & RC_BSR_RXINT) {
344 iack = rcin(RC_PILR_RX);
345 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
346 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
347 printf("rc%d: fake rxint: %02x\n", unit, iack);
348 goto more_intrs;
349 }
350 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
351 t_state = rc->rc_tp->t_state;
352 /* Do RTS flow control stuff */
353 if ( (rc->rc_flags & RC_RTSFLOW)
354 || !(t_state & TS_ISOPEN)
355 ) {
356 if ( ( !(t_state & TS_ISOPEN)
357 || (t_state & TS_TBLOCK)
358 )
359 && (rc->rc_msvr & MSVR_RTS)
360 )
361 rcout(CD180_MSVR,
362 rc->rc_msvr &= ~MSVR_RTS);
363 else if (!(rc->rc_msvr & MSVR_RTS))
364 rcout(CD180_MSVR,
365 rc->rc_msvr |= MSVR_RTS);
366 }
367 ucnt = rcin(CD180_RDCR) & 0xF;
368 resid = 0;
369
370 if (t_state & TS_ISOPEN) {
371 /* check for input buffer overflow */
372 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
373 resid = ucnt;
374 ucnt = rc->rc_bufend - rc->rc_iptr;
375 resid -= ucnt;
376 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
377 rc->rc_flags |= RC_WAS_BUFOVFL;
378 rc_scheduled_event++;
379 }
380 }
381 optr = rc->rc_iptr;
382 /* check foor good data */
383 if (good_data) {
384 while (ucnt-- > 0) {
385 val = rcin(CD180_RDR);
386 optr[0] = val;
387 optr[INPUT_FLAGS_SHIFT] = 0;
388 optr++;
389 rc_scheduled_event++;
390 if (val != 0 && val == rc->rc_hotchar)
391 setsofttty();
392 }
393 } else {
394 /* Store also status data */
395 while (ucnt-- > 0) {
396 iack = rcin(CD180_RCSR);
397 if (iack & RCSR_Timeout)
398 break;
399 if ( (iack & RCSR_OE)
400 && !(rc->rc_flags & RC_WAS_SILOVFL)) {
401 rc->rc_flags |= RC_WAS_SILOVFL;
402 rc_scheduled_event++;
403 }
404 val = rcin(CD180_RDR);
405 /*
406 Don't store PE if IGNPAR and BREAK if IGNBRK,
407 this hack allows "raw" tty optimization
408 works even if IGN* is set.
409 */
410 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
411 || (!(iack & (RCSR_PE|RCSR_FE))
412 || !(rc->rc_tp->t_iflag & IGNPAR))
413 && (!(iack & RCSR_Break)
414 || !(rc->rc_tp->t_iflag & IGNBRK))) {
415 if ( (iack & (RCSR_PE|RCSR_FE))
416 && (t_state & TS_CAN_BYPASS_L_RINT)
417 && ((iack & RCSR_FE)
418 || (iack & RCSR_PE)
419 && (rc->rc_tp->t_iflag & INPCK)))
420 val = 0;
421 else if (val != 0 && val == rc->rc_hotchar)
422 setsofttty();
423 optr[0] = val;
424 optr[INPUT_FLAGS_SHIFT] = iack;
425 optr++;
426 rc_scheduled_event++;
427 }
428 }
429 }
430 rc->rc_iptr = optr;
431 rc->rc_flags |= RC_DORXFER;
432 } else
433 resid = ucnt;
434 /* Clear FIFO if necessary */
435 while (resid-- > 0) {
436 if (!good_data)
437 iack = rcin(CD180_RCSR);
438 else
439 iack = 0;
440 if (iack & RCSR_Timeout)
441 break;
442 (void) rcin(CD180_RDR);
443 }
444 goto more_intrs;
445 }
446 if (bsr & RC_BSR_MOINT) {
447 iack = rcin(RC_PILR_MODEM);
448 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
449 printf("rc%d: fake moint: %02x\n", unit, iack);
450 goto more_intrs;
451 }
452 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
453 iack = rcin(CD180_MCR);
454 rc->rc_msvr = rcin(CD180_MSVR);
455 rcout(CD180_MCR, 0);
456#ifdef RCDEBUG
457 printrcflags(rc, "moint");
458#endif
459 if (rc->rc_flags & RC_CTSFLOW) {
460 if (rc->rc_msvr & MSVR_CTS)
461 rc->rc_flags |= RC_SEND_RDY;
462 else
463 rc->rc_flags &= ~RC_SEND_RDY;
464 } else
465 rc->rc_flags |= RC_SEND_RDY;
466 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
467 rc_scheduled_event += LOTS_OF_EVENTS;
468 rc->rc_flags |= RC_MODCHG;
469 setsofttty();
470 }
471 goto more_intrs;
472 }
473 if (bsr & RC_BSR_TXINT) {
474 iack = rcin(RC_PILR_TX);
475 if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
476 printf("rc%d: fake txint: %02x\n", unit, iack);
477 goto more_intrs;
478 }
479 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
480 if ( (rc->rc_flags & RC_OSUSP)
481 || !(rc->rc_flags & RC_SEND_RDY)
482 )
483 goto more_intrs;
484 /* Handle breaks and other stuff */
485 if (rc->rc_pendcmd) {
486 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
487 rcout(CD180_TDR, CD180_C_ESC);
488 rcout(CD180_TDR, rc->rc_pendcmd);
489 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
490 rc->rc_pendcmd = 0;
491 goto more_intrs;
492 }
493 optr = rc->rc_optr;
494 resid = rc->rc_obufend - optr;
495 if (resid > CD180_NFIFO)
496 resid = CD180_NFIFO;
497 while (resid-- > 0)
498 rcout(CD180_TDR, *optr++);
499 rc->rc_optr = optr;
500
501 /* output completed? */
502 if (optr >= rc->rc_obufend) {
503 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
504#ifdef RCDEBUG
505 printf("rc%d/%d: output completed\n", unit, rc->rc_chan);
506#endif
507 if (!(rc->rc_flags & RC_DOXXFER)) {
508 rc_scheduled_event += LOTS_OF_EVENTS;
509 rc->rc_flags |= RC_DOXXFER;
510 setsofttty();
511 }
512 }
513 }
514 more_intrs:
515 rcout(CD180_EOIR, 0); /* end of interrupt */
516 rcout(RC_CTOUT, 0);
517 bsr = ~(rcin(RC_BSR));
518 }
519}
520
521/* Feed characters to output buffer */
522static void rc_start(tp)
523register struct tty *tp;
524{
525 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
526 register int nec = rc->rc_rcb->rcb_addr, s;
527
528 if (rc->rc_flags & RC_OSBUSY)
529 return;
530 s = spltty();
531 rc->rc_flags |= RC_OSBUSY;
532 disable_intr();
533 if (tp->t_state & TS_TTSTOP)
534 rc->rc_flags |= RC_OSUSP;
535 else
536 rc->rc_flags &= ~RC_OSUSP;
537 /* Do RTS flow control stuff */
538 if ( (rc->rc_flags & RC_RTSFLOW)
539 && (tp->t_state & TS_TBLOCK)
540 && (rc->rc_msvr & MSVR_RTS)
541 ) {
542 rcout(CD180_CAR, rc->rc_chan);
543 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
544 } else if (!(rc->rc_msvr & MSVR_RTS)) {
545 rcout(CD180_CAR, rc->rc_chan);
546 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
547 }
548 enable_intr();
549 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
550 goto out;
551#ifdef RCDEBUG
552 printrcflags(rc, "rcstart");
553#endif
| 1/*
2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28/*
29 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
30 *
31 */
32
33#include "rc.h"
34#if NRC > 0
35
36/*#define RCDEBUG*/
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/ioctl.h>
41#include <sys/tty.h>
42#include <sys/proc.h>
43#include <sys/user.h>
44#include <sys/conf.h>
45#include <sys/dkstat.h>
46#include <sys/file.h>
47#include <sys/uio.h>
48#include <sys/kernel.h>
49#include <sys/syslog.h>
50#include <sys/devconf.h>
51
52#include <machine/clock.h>
53
54#include <i386/isa/isa.h>
55#include <i386/isa/isa_device.h>
56#include <i386/isa/sioreg.h>
57
58#include <i386/isa/ic/cd180.h>
59#include <i386/isa/rcreg.h>
60
61/* Prototypes */
62int rcprobe __P((struct isa_device *));
63int rcattach __P((struct isa_device *));
64
65int rcopen __P((dev_t, int, int, struct proc *));
66int rcclose __P((dev_t, int, int, struct proc *));
67int rcread __P((dev_t, struct uio *, int));
68int rcwrite __P((dev_t, struct uio *, int));
69void rcintr __P((int));
70void rcpoll __P((void));
71void rcstop __P((struct tty *, int));
72int rcioctl __P((dev_t, int, caddr_t, int, struct proc *));
73
74#define rcin(port) RC_IN (nec, port)
75#define rcout(port,v) RC_OUT (nec, port, v)
76
77#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
78#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
79
80#define RC_IBUFSIZE 256
81#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
82#define RC_OBUFSIZE 512
83#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4)
84#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
85#define LOTS_OF_EVENTS 64
86
87#define RC_FAKEID 0x10
88
89#define RC_PROBED 1
90#define RC_ATTACHED 2
91
92#define GET_UNIT(dev) (minor(dev) & 0x3F)
93#define CALLOUT(dev) (minor(dev) & 0x80)
94
95/* For isa routines */
96struct isa_driver rcdriver = {
97 rcprobe, rcattach, "rc"
98};
99
100/* Per-board structure */
101static struct rc_softc {
102 u_int rcb_probed; /* 1 - probed, 2 - attached */
103 u_int rcb_addr; /* Base I/O addr */
104 u_int rcb_unit; /* unit # */
105 u_char rcb_dtr; /* DTR status */
106 struct rc_chans *rcb_baserc; /* base rc ptr */
107} rc_softc[NRC];
108
109/* Per-channel structure */
110static struct rc_chans {
111 struct rc_softc *rc_rcb; /* back ptr */
112 u_short rc_flags; /* Misc. flags */
113 int rc_chan; /* Channel # */
114 u_char rc_ier; /* intr. enable reg */
115 u_char rc_msvr; /* modem sig. status */
116 u_char rc_cor2; /* options reg */
117 u_char rc_pendcmd; /* special cmd pending */
118 u_int rc_dtrwait; /* dtr timeout */
119 u_int rc_dcdwaits; /* how many waits DCD in open */
120 u_char rc_hotchar; /* end packed optimize */
121 struct tty *rc_tp; /* tty struct */
122 u_char *rc_iptr; /* Chars input buffer */
123 u_char *rc_hiwat; /* hi-water mark */
124 u_char *rc_bufend; /* end of buffer */
125 u_char *rc_optr; /* ptr in output buf */
126 u_char *rc_obufend; /* end of output buf */
127 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */
128 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */
129} rc_chans[NRC * CD180_NCHAN];
130
131static int rc_scheduled_event = 0;
132
133/* for pstat -t */
134struct tty rc_tty[NRC * CD180_NCHAN];
135int nrc_tty = NRC * CD180_NCHAN;
136
137/* Flags */
138#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */
139#define RC_ACTOUT 0x0002 /* Dial-out port active */
140#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */
141#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */
142#define RC_DORXFER 0x0010 /* RXFER event planned */
143#define RC_DOXXFER 0x0020 /* XXFER event planned */
144#define RC_MODCHG 0x0040 /* Modem status changed */
145#define RC_OSUSP 0x0080 /* Output suspended */
146#define RC_OSBUSY 0x0100 /* start() routine in progress */
147#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */
148#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */
149#define RC_SEND_RDY 0x0800 /* ready to send */
150
151static struct speedtab rc_speedtab[] = {
152 0, 0,
153 50, RC_BRD(50),
154 75, RC_BRD(75),
155 110, RC_BRD(110),
156 134, RC_BRD(134),
157 150, RC_BRD(150),
158 200, RC_BRD(200),
159 300, RC_BRD(300),
160 600, RC_BRD(600),
161 1200, RC_BRD(1200),
162 1800, RC_BRD(1800),
163 2400, RC_BRD(2400),
164 4800, RC_BRD(4800),
165 9600, RC_BRD(9600),
166 19200, RC_BRD(19200),
167 38400, RC_BRD(38400),
168 57600, RC_BRD(57600),
169 /* real max value is 76800 with 9.8304 MHz clock */
170 -1, -1
171};
172
173/* Table for translation of RCSR status bits to internal form */
174static int rc_rcsrt[16] = {
175 0, TTY_OE, TTY_FE,
176 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE,
177 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
178 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE,
179 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
180 TTY_BI|TTY_PE|TTY_FE|TTY_OE
181};
182
183/* Static prototypes */
184static void rc_hwreset __P((int, int, unsigned int));
185static int rc_test __P((int, int));
186static void rc_discard_output __P((struct rc_chans *));
187static void rc_hardclose __P((struct rc_chans *));
188static int rc_modctl __P((struct rc_chans *, int, int));
189static void rc_start __P((struct tty *));
190static int rc_param __P((struct tty *, struct termios *));
191static void rc_registerdev __P((struct isa_device *id));
192static void rc_reinit __P((struct rc_softc *));
193#ifdef RCDEBUG
194static void printrcflags();
195#endif
196static timeout_t rc_dtrwakeup;
197static timeout_t rc_wakeup;
198static void disc_optim __P((struct tty *tp, struct termios *t, struct rc_chans *));
199static void rc_wait0 __P((int nec, int unit, int chan, int line));
200
201/**********************************************/
202
203/* Quick device probing */
204int rcprobe(dvp)
205 struct isa_device *dvp;
206{
207 int irq = ffs(dvp->id_irq) - 1;
208 register int nec = dvp->id_iobase;
209
210 if (dvp->id_unit > NRC)
211 return 0;
212 if (!RC_VALIDADDR(nec)) {
213 printf("rc%d: illegal base address %x\n", nec);
214 return 0;
215 }
216 if (!RC_VALIDIRQ(irq)) {
217 printf("rc%d: illegal IRQ value %d\n", irq);
218 return 0;
219 }
220 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
221 rcout(CD180_PPRH, 0x11);
222 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
223 return 0;
224 /* Now, test the board more thoroughly, with diagnostic */
225 if (rc_test(nec, dvp->id_unit))
226 return 0;
227 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
228
229 return 0xF;
230}
231
232static struct kern_devconf kdc_rc[NRC] = { {
233 0, 0, 0, /* filled in by dev_attach */
234 "rc", 0, { MDDT_ISA, 0, "tty" },
235 isa_generic_externalize, 0, 0, ISA_EXTERNALLEN,
236 &kdc_isa0, /* parent */
237 0, /* parentdata */
238 DC_UNCONFIGURED, /* state */
239 "RISCom/8 multiport card",
240 DC_CLS_SERIAL /* class */
241} };
242
243static void
244rc_registerdev(id)
245 struct isa_device *id;
246{
247 int unit;
248
249 unit = id->id_unit;
250 if (unit != 0)
251 kdc_rc[unit] = kdc_rc[0];
252 kdc_rc[unit].kdc_unit = unit;
253 kdc_rc[unit].kdc_isa = id;
254 kdc_rc[unit].kdc_state = DC_UNKNOWN;
255 dev_attach(&kdc_rc[unit]);
256}
257
258int rcattach(dvp)
259 struct isa_device *dvp;
260{
261 register int i, chan, nec = dvp->id_iobase;
262 struct rc_softc *rcb = &rc_softc[dvp->id_unit];
263 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN];
264 static int rc_wakeup_started = 0;
265 struct tty *tp;
266
267 /* Thorooughly test the device */
268 if (rcb->rcb_probed != RC_PROBED)
269 return 0;
270 rcb->rcb_addr = nec;
271 rcb->rcb_dtr = 0;
272 rcb->rcb_baserc = rc;
273 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
274 printf("rc%d: %d chans, firmware rev. %c\n", dvp->id_unit,
275 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
276
277 rc_registerdev(dvp);
278
279 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
280 rc->rc_rcb = rcb;
281 rc->rc_chan = chan;
282 rc->rc_iptr = rc->rc_ibuf;
283 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
284 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
285 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0;
286 rc->rc_cor2 = rc->rc_pendcmd = 0;
287 rc->rc_optr = rc->rc_obufend = rc->rc_obuf;
288 rc->rc_dtrwait = 3 * hz;
289 rc->rc_dcdwaits= 0;
290 rc->rc_hotchar = 0;
291 tp = rc->rc_tp = &rc_tty[chan];
292 ttychars(tp);
293 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
294 tp->t_cflag = TTYDEF_CFLAG;
295 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
296 }
297 rcb->rcb_probed = RC_ATTACHED;
298 if (!rc_wakeup_started) {
299 rc_wakeup((void *)NULL);
300 rc_wakeup_started = 0;
301 }
302 return 1;
303}
304
305/* RC interrupt handling */
306void rcintr(unit)
307 int unit;
308{
309 register struct rc_softc *rcb = &rc_softc[unit];
310 register struct rc_chans *rc;
311 register int nec, resid;
312 register u_char val, iack, bsr, ucnt, *optr;
313 int good_data, t_state;
314
315 if (rcb->rcb_probed != RC_ATTACHED) {
316 printf("rc%d: bogus interrupt\n", unit);
317 return;
318 }
319 nec = rcb->rcb_addr;
320
321 bsr = ~(rcin(RC_BSR));
322
323 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
324 printf("rc%d: extra interrupt\n", unit);
325 rcout(CD180_EOIR, 0);
326 return;
327 }
328
329 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
330#ifdef RCDEBUG_DETAILED
331 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
332 (bsr & RC_BSR_TOUT)?"TOUT ":"",
333 (bsr & RC_BSR_RXINT)?"RXINT ":"",
334 (bsr & RC_BSR_TXINT)?"TXINT ":"",
335 (bsr & RC_BSR_MOINT)?"MOINT":"");
336#endif
337 if (bsr & RC_BSR_TOUT) {
338 printf("rc%d: hardware failure, reset board\n", unit);
339 rcout(RC_CTOUT, 0);
340 rc_reinit(rcb);
341 return;
342 }
343 if (bsr & RC_BSR_RXINT) {
344 iack = rcin(RC_PILR_RX);
345 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
346 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
347 printf("rc%d: fake rxint: %02x\n", unit, iack);
348 goto more_intrs;
349 }
350 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
351 t_state = rc->rc_tp->t_state;
352 /* Do RTS flow control stuff */
353 if ( (rc->rc_flags & RC_RTSFLOW)
354 || !(t_state & TS_ISOPEN)
355 ) {
356 if ( ( !(t_state & TS_ISOPEN)
357 || (t_state & TS_TBLOCK)
358 )
359 && (rc->rc_msvr & MSVR_RTS)
360 )
361 rcout(CD180_MSVR,
362 rc->rc_msvr &= ~MSVR_RTS);
363 else if (!(rc->rc_msvr & MSVR_RTS))
364 rcout(CD180_MSVR,
365 rc->rc_msvr |= MSVR_RTS);
366 }
367 ucnt = rcin(CD180_RDCR) & 0xF;
368 resid = 0;
369
370 if (t_state & TS_ISOPEN) {
371 /* check for input buffer overflow */
372 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
373 resid = ucnt;
374 ucnt = rc->rc_bufend - rc->rc_iptr;
375 resid -= ucnt;
376 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
377 rc->rc_flags |= RC_WAS_BUFOVFL;
378 rc_scheduled_event++;
379 }
380 }
381 optr = rc->rc_iptr;
382 /* check foor good data */
383 if (good_data) {
384 while (ucnt-- > 0) {
385 val = rcin(CD180_RDR);
386 optr[0] = val;
387 optr[INPUT_FLAGS_SHIFT] = 0;
388 optr++;
389 rc_scheduled_event++;
390 if (val != 0 && val == rc->rc_hotchar)
391 setsofttty();
392 }
393 } else {
394 /* Store also status data */
395 while (ucnt-- > 0) {
396 iack = rcin(CD180_RCSR);
397 if (iack & RCSR_Timeout)
398 break;
399 if ( (iack & RCSR_OE)
400 && !(rc->rc_flags & RC_WAS_SILOVFL)) {
401 rc->rc_flags |= RC_WAS_SILOVFL;
402 rc_scheduled_event++;
403 }
404 val = rcin(CD180_RDR);
405 /*
406 Don't store PE if IGNPAR and BREAK if IGNBRK,
407 this hack allows "raw" tty optimization
408 works even if IGN* is set.
409 */
410 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
411 || (!(iack & (RCSR_PE|RCSR_FE))
412 || !(rc->rc_tp->t_iflag & IGNPAR))
413 && (!(iack & RCSR_Break)
414 || !(rc->rc_tp->t_iflag & IGNBRK))) {
415 if ( (iack & (RCSR_PE|RCSR_FE))
416 && (t_state & TS_CAN_BYPASS_L_RINT)
417 && ((iack & RCSR_FE)
418 || (iack & RCSR_PE)
419 && (rc->rc_tp->t_iflag & INPCK)))
420 val = 0;
421 else if (val != 0 && val == rc->rc_hotchar)
422 setsofttty();
423 optr[0] = val;
424 optr[INPUT_FLAGS_SHIFT] = iack;
425 optr++;
426 rc_scheduled_event++;
427 }
428 }
429 }
430 rc->rc_iptr = optr;
431 rc->rc_flags |= RC_DORXFER;
432 } else
433 resid = ucnt;
434 /* Clear FIFO if necessary */
435 while (resid-- > 0) {
436 if (!good_data)
437 iack = rcin(CD180_RCSR);
438 else
439 iack = 0;
440 if (iack & RCSR_Timeout)
441 break;
442 (void) rcin(CD180_RDR);
443 }
444 goto more_intrs;
445 }
446 if (bsr & RC_BSR_MOINT) {
447 iack = rcin(RC_PILR_MODEM);
448 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
449 printf("rc%d: fake moint: %02x\n", unit, iack);
450 goto more_intrs;
451 }
452 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
453 iack = rcin(CD180_MCR);
454 rc->rc_msvr = rcin(CD180_MSVR);
455 rcout(CD180_MCR, 0);
456#ifdef RCDEBUG
457 printrcflags(rc, "moint");
458#endif
459 if (rc->rc_flags & RC_CTSFLOW) {
460 if (rc->rc_msvr & MSVR_CTS)
461 rc->rc_flags |= RC_SEND_RDY;
462 else
463 rc->rc_flags &= ~RC_SEND_RDY;
464 } else
465 rc->rc_flags |= RC_SEND_RDY;
466 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
467 rc_scheduled_event += LOTS_OF_EVENTS;
468 rc->rc_flags |= RC_MODCHG;
469 setsofttty();
470 }
471 goto more_intrs;
472 }
473 if (bsr & RC_BSR_TXINT) {
474 iack = rcin(RC_PILR_TX);
475 if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
476 printf("rc%d: fake txint: %02x\n", unit, iack);
477 goto more_intrs;
478 }
479 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
480 if ( (rc->rc_flags & RC_OSUSP)
481 || !(rc->rc_flags & RC_SEND_RDY)
482 )
483 goto more_intrs;
484 /* Handle breaks and other stuff */
485 if (rc->rc_pendcmd) {
486 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
487 rcout(CD180_TDR, CD180_C_ESC);
488 rcout(CD180_TDR, rc->rc_pendcmd);
489 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
490 rc->rc_pendcmd = 0;
491 goto more_intrs;
492 }
493 optr = rc->rc_optr;
494 resid = rc->rc_obufend - optr;
495 if (resid > CD180_NFIFO)
496 resid = CD180_NFIFO;
497 while (resid-- > 0)
498 rcout(CD180_TDR, *optr++);
499 rc->rc_optr = optr;
500
501 /* output completed? */
502 if (optr >= rc->rc_obufend) {
503 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
504#ifdef RCDEBUG
505 printf("rc%d/%d: output completed\n", unit, rc->rc_chan);
506#endif
507 if (!(rc->rc_flags & RC_DOXXFER)) {
508 rc_scheduled_event += LOTS_OF_EVENTS;
509 rc->rc_flags |= RC_DOXXFER;
510 setsofttty();
511 }
512 }
513 }
514 more_intrs:
515 rcout(CD180_EOIR, 0); /* end of interrupt */
516 rcout(RC_CTOUT, 0);
517 bsr = ~(rcin(RC_BSR));
518 }
519}
520
521/* Feed characters to output buffer */
522static void rc_start(tp)
523register struct tty *tp;
524{
525 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
526 register int nec = rc->rc_rcb->rcb_addr, s;
527
528 if (rc->rc_flags & RC_OSBUSY)
529 return;
530 s = spltty();
531 rc->rc_flags |= RC_OSBUSY;
532 disable_intr();
533 if (tp->t_state & TS_TTSTOP)
534 rc->rc_flags |= RC_OSUSP;
535 else
536 rc->rc_flags &= ~RC_OSUSP;
537 /* Do RTS flow control stuff */
538 if ( (rc->rc_flags & RC_RTSFLOW)
539 && (tp->t_state & TS_TBLOCK)
540 && (rc->rc_msvr & MSVR_RTS)
541 ) {
542 rcout(CD180_CAR, rc->rc_chan);
543 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
544 } else if (!(rc->rc_msvr & MSVR_RTS)) {
545 rcout(CD180_CAR, rc->rc_chan);
546 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
547 }
548 enable_intr();
549 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
550 goto out;
551#ifdef RCDEBUG
552 printrcflags(rc, "rcstart");
553#endif
|
561#ifdef RCDEBUG
562 printf("rcstart: outq = %d obuf = %d\n",
563 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
564#endif
565 if (tp->t_state & TS_BUSY)
566 goto out; /* output still in progress ... */
567
568 if (tp->t_outq.c_cc > 0) {
569 u_int ocnt;
570
571 tp->t_state |= TS_BUSY;
572 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
573 disable_intr();
574 rc->rc_optr = rc->rc_obuf;
575 rc->rc_obufend = rc->rc_optr + ocnt;
576 enable_intr();
577 if (!(rc->rc_ier & IER_TxRdy)) {
578#ifdef RCDEBUG
579 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
580#endif
581 rcout(CD180_CAR, rc->rc_chan);
582 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
583 }
584 }
585out:
586 rc->rc_flags &= ~RC_OSBUSY;
587 (void) splx(s);
588}
589
590/* Handle delayed events. */
591void rcpoll()
592{
593 register struct rc_chans *rc;
594 register struct rc_softc *rcb;
595 register u_char *tptr, *eptr;
596 register int s;
597 register struct tty *tp;
598 register int chan, icnt, c, nec, unit;
599
600 if (rc_scheduled_event == 0)
601 return;
602repeat:
603 for (unit = 0; unit < NRC; unit++) {
604 rcb = &rc_softc[unit];
605 rc = rcb->rcb_baserc;
606 nec = rc->rc_rcb->rcb_addr;
607 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
608 tp = rc->rc_tp;
609#ifdef RCDEBUG
610 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
611 RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
612 printrcflags(rc, "rcevent");
613#endif
614 if (rc->rc_flags & RC_WAS_BUFOVFL) {
615 disable_intr();
616 rc->rc_flags &= ~RC_WAS_BUFOVFL;
617 rc_scheduled_event--;
618 enable_intr();
619 printf("rc%d/%d: interrupt-level buffer overflow\n",
620 unit, chan);
621 }
622 if (rc->rc_flags & RC_WAS_SILOVFL) {
623 disable_intr();
624 rc->rc_flags &= ~RC_WAS_SILOVFL;
625 rc_scheduled_event--;
626 enable_intr();
627 printf("rc%d/%d: silo overflow\n",
628 unit, chan);
629 }
630 if (rc->rc_flags & RC_MODCHG) {
631 disable_intr();
632 rc->rc_flags &= ~RC_MODCHG;
633 rc_scheduled_event -= LOTS_OF_EVENTS;
634 enable_intr();
635 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
636 }
637 if (rc->rc_flags & RC_DORXFER) {
638 disable_intr();
639 rc->rc_flags &= ~RC_DORXFER;
640 eptr = rc->rc_iptr;
641 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
642 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
643 else
644 tptr = rc->rc_ibuf;
645 icnt = eptr - tptr;
646 if (icnt > 0) {
647 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
648 rc->rc_iptr = rc->rc_ibuf;
649 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
650 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
651 } else {
652 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
653 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
654 rc->rc_hiwat =
655 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
656 }
657 if ( (rc->rc_flags & RC_RTSFLOW)
658 && (tp->t_state & TS_ISOPEN)
659 && !(tp->t_state & TS_TBLOCK)
660 && !(rc->rc_msvr & MSVR_RTS)
661 ) {
662 rcout(CD180_CAR, chan);
663 rcout(CD180_MSVR,
664 rc->rc_msvr |= MSVR_RTS);
665 }
666 rc_scheduled_event -= icnt;
667 }
668 enable_intr();
669
670 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
671 goto done1;
672
673 if ( linesw[tp->t_line].l_rint == ttyinput
674 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
675 && !(tp->t_state & TS_TBLOCK)
676 && (tp->t_rawq.c_cc + icnt) > RB_I_HIGH_WATER) {
677 int queue_full = 0;
678
679 if ((tp->t_iflag & IXOFF) &&
680 tp->t_cc[VSTOP] != _POSIX_VDISABLE &&
681 (queue_full = putc(tp->t_cc[VSTOP], &tp->t_outq)) == 0 ||
682 (rc->rc_flags & RC_RTSFLOW)) {
683 tp->t_state |= TS_TBLOCK;
684 ttstart(tp);
685 if (queue_full) /* try again */
686 tp->t_state &= ~TS_TBLOCK;
687 }
688 }
689 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT)
690 && !(tp->t_state & TS_LOCAL)) {
691 tk_nin += icnt;
692 tk_rawcc += icnt;
693 tp->t_rawcc += icnt;
694 if (b_to_q(tptr, icnt, &tp->t_rawq))
695 printf("rc%d/%d: tty-level buffer overflow\n",
696 unit, chan);
697 ttwakeup(tp);
698 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
699 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
700 tp->t_state &= ~TS_TTSTOP;
701 tp->t_lflag &= ~FLUSHO;
702 ttstart(tp);
703 }
704 } else {
705 for (; tptr < eptr; tptr++)
706 (*linesw[tp->t_line].l_rint)
707 (tptr[0] |
708 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
709 }
710done1:
711 }
712 if (rc->rc_flags & RC_DOXXFER) {
713 disable_intr();
714 rc_scheduled_event -= LOTS_OF_EVENTS;
715 rc->rc_flags &= ~RC_DOXXFER;
716 rc->rc_tp->t_state &= ~TS_BUSY;
717 enable_intr();
718 (*linesw[tp->t_line].l_start)(tp);
719 }
720 }
721 if (rc_scheduled_event == 0)
722 break;
723 }
724 if (rc_scheduled_event >= LOTS_OF_EVENTS)
725 goto repeat;
726}
727
728void rcstop(tp, rw)
729 register struct tty *tp;
730 int rw;
731{
732 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
733 u_char *tptr, *eptr;
734
735#ifdef RCDEBUG
736 printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
737 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
738#endif
739 if (rw & FWRITE)
740 rc_discard_output(rc);
741 disable_intr();
742 if (rw & FREAD) {
743 rc->rc_flags &= ~RC_DORXFER;
744 eptr = rc->rc_iptr;
745 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
746 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
747 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
748 } else {
749 tptr = rc->rc_ibuf;
750 rc->rc_iptr = rc->rc_ibuf;
751 }
752 rc_scheduled_event -= eptr - tptr;
753 }
754 if (tp->t_state & TS_TTSTOP)
755 rc->rc_flags |= RC_OSUSP;
756 else
757 rc->rc_flags &= ~RC_OSUSP;
758 enable_intr();
759}
760
761int rcopen(dev, flag, mode, p)
762 dev_t dev;
763 int flag, mode;
764 struct proc *p;
765{
766 register struct rc_chans *rc;
767 register struct tty *tp;
768 int unit, nec, s, error = 0;
769
770 unit = GET_UNIT(dev);
771 if (unit >= NRC * CD180_NCHAN)
772 return ENXIO;
773 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
774 return ENXIO;
775 rc = &rc_chans[unit];
776 tp = rc->rc_tp;
777 nec = rc->rc_rcb->rcb_addr;
778#ifdef RCDEBUG
779 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
780#endif
781 s = spltty();
782
783again:
784 while (rc->rc_flags & RC_DTR_OFF) {
785 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0);
786 if (error != 0)
787 goto out;
788 }
789 if (tp->t_state & TS_ISOPEN) {
790 if (CALLOUT(dev)) {
791 if (!(rc->rc_flags & RC_ACTOUT)) {
792 error = EBUSY;
793 goto out;
794 }
795 } else {
796 if (rc->rc_flags & RC_ACTOUT) {
797 if (flag & O_NONBLOCK) {
798 error = EBUSY;
799 goto out;
800 }
801 if (error = tsleep(&rc->rc_rcb,
802 TTIPRI|PCATCH, "rcbi", 0))
803 goto out;
804 goto again;
805 }
806 }
807 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) {
808 error = EBUSY;
809 goto out;
810 }
811 } else {
812 tp->t_oproc = rc_start;
813 tp->t_param = rc_param;
814 tp->t_dev = dev;
815
816 if (CALLOUT(dev))
817 tp->t_cflag |= CLOCAL;
818 else
819 tp->t_cflag &= ~CLOCAL;
820
821 error = rc_param(tp, &tp->t_termios);
822 if (error)
823 goto out;
824 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
825
826 ttsetwater(tp);
827
828 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
829 (*linesw[tp->t_line].l_modem)(tp, 1);
830 }
831 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
832 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
833 rc->rc_dcdwaits++;
834 error = tsleep(&tp->t_rawq, TTIPRI | PCATCH, "rcdcd", 0);
835 rc->rc_dcdwaits--;
836 if (error != 0)
837 goto out;
838 goto again;
839 }
840 error = (*linesw[tp->t_line].l_open)(dev, tp);
841 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
842 rc->rc_flags |= RC_ACTOUT;
843out:
844 (void) splx(s);
845
846 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
847 rc_hardclose(rc);
848
849 return error;
850}
851
852int rcclose(dev, flag, mode, p)
853 dev_t dev;
854 int flag, mode;
855 struct proc *p;
856{
857 register struct rc_chans *rc;
858 register struct tty *tp;
859 int s, unit = GET_UNIT(dev);
860
861 if (unit >= NRC * CD180_NCHAN)
862 return ENXIO;
863 rc = &rc_chans[unit];
864 tp = rc->rc_tp;
865#ifdef RCDEBUG
866 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
867#endif
868 s = spltty();
869 (*linesw[tp->t_line].l_close)(tp, flag);
870 rcstop(tp, FREAD | FWRITE);
871 rc_hardclose(rc);
872 ttyclose(tp);
873 splx(s);
874 return 0;
875}
876
877static void rc_hardclose(rc)
878register struct rc_chans *rc;
879{
880 register int s, nec = rc->rc_rcb->rcb_addr;
881 register struct tty *tp = rc->rc_tp;
882
883 s = spltty();
884 rcout(CD180_CAR, rc->rc_chan);
885
886 /* Disable rx/tx intrs */
887 rcout(CD180_IER, rc->rc_ier = 0);
888 if ( (tp->t_cflag & HUPCL)
889 || !(rc->rc_flags & RC_ACTOUT)
890 && !(rc->rc_msvr & MSVR_CD)
891 && !(tp->t_cflag & CLOCAL)
892 || !(tp->t_state & TS_ISOPEN)
893 ) {
894 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
895 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
896 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
897 if (rc->rc_dtrwait) {
898 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait);
899 rc->rc_flags |= RC_DTR_OFF;
900 }
901 }
902 rc->rc_flags &= ~RC_ACTOUT;
903 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */
904 wakeup((caddr_t) &tp->t_rawq); /* wake dcd */
905 (void) splx(s);
906}
907
908/* Read from line */
909int rcread(dev, uio, flag)
910 dev_t dev;
911 struct uio *uio;
912 int flag;
913{
914 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp;
915
916 return ((*linesw[tp->t_line].l_read)(tp, uio, flag));
917}
918
919/* Write to line */
920int rcwrite(dev, uio, flag)
921 dev_t dev;
922 struct uio *uio;
923 int flag;
924{
925 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp;
926
927 return ((*linesw[tp->t_line].l_write)(tp, uio, flag));
928}
929
930/* Reset the bastard */
931static void rc_hwreset(unit, nec, chipid)
932 register int unit, nec;
933 unsigned int chipid;
934{
935 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */
936 DELAY(20000);
937 WAITFORCCR(unit, -1);
938
939 rcout(RC_CTOUT, 0); /* Clear timeout */
940 rcout(CD180_GIVR, chipid);
941 rcout(CD180_GICR, 0);
942
943 /* Set Prescaler Registers (1 msec) */
944 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
945 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
946
947 /* Initialize Priority Interrupt Level Registers */
948 rcout(CD180_PILR1, RC_PILR_MODEM);
949 rcout(CD180_PILR2, RC_PILR_TX);
950 rcout(CD180_PILR3, RC_PILR_RX);
951
952 /* Reset DTR */
953 rcout(RC_DTREG, ~0);
954}
955
956/* Set channel parameters */
957static int rc_param(tp, ts)
958 register struct tty *tp;
959 struct termios *ts;
960{
961 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
962 register int nec = rc->rc_rcb->rcb_addr;
963 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow;
964
965 odivs = ttspeedtab(ts->c_ospeed, rc_speedtab);
966 if (ts->c_ispeed == 0)
967 ts->c_ispeed = ts->c_ospeed;
968 idivs = ttspeedtab(ts->c_ispeed, rc_speedtab);
969 if (idivs < 0 || odivs < 0)
970 return (EINVAL);
971
972 s = spltty();
973
974 /* Select channel */
975 rcout(CD180_CAR, rc->rc_chan);
976
977 /* If speed == 0, hangup line */
978 if (ts->c_ospeed == 0) {
979 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
980 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
981 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
982 }
983
984 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
985 cflag = ts->c_cflag;
986 iflag = ts->c_iflag;
987 lflag = ts->c_lflag;
988
989 if (idivs > 0) {
990 rcout(CD180_RBPRL, idivs & 0xFF);
991 rcout(CD180_RBPRH, idivs >> 8);
992 }
993 if (odivs > 0) {
994 rcout(CD180_TBPRL, odivs & 0xFF);
995 rcout(CD180_TBPRH, odivs >> 8);
996 }
997
998 /* set timeout value */
999 if (ts->c_ispeed > 0) {
1000 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
1001
1002 if ( !(lflag & ICANON)
1003 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
1004 && ts->c_cc[VTIME] * 10 > itm)
1005 itm = ts->c_cc[VTIME] * 10;
1006
1007 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
1008 }
1009
1010 switch (cflag & CSIZE) {
1011 case CS5: val = COR1_5BITS; break;
1012 case CS6: val = COR1_6BITS; break;
1013 case CS7: val = COR1_7BITS; break;
1014 default:
1015 case CS8: val = COR1_8BITS; break;
1016 }
1017 if (cflag & PARENB) {
1018 val |= COR1_NORMPAR;
1019 if (cflag & PARODD)
1020 val |= COR1_ODDP;
1021 if (!(cflag & INPCK))
1022 val |= COR1_Ignore;
1023 } else
1024 val |= COR1_Ignore;
1025 if (cflag & CSTOPB)
1026 val |= COR1_2SB;
1027 rcout(CD180_COR1, val);
1028
1029 /* Set FIFO threshold */
1030 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
1031 inpflow = 0;
1032 if ( (iflag & IXOFF)
1033 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE
1034 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE
1035 || (iflag & IXANY)
1036 )
1037 )
1038 ) {
1039 inpflow = 1;
1040 val |= COR3_SCDE|COR3_FCT;
1041 }
1042 rcout(CD180_COR3, val);
1043
1044 /* Initialize on-chip automatic flow control */
1045 val = 0;
1046 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
1047 if (cflag & CCTS_OFLOW) {
1048 rc->rc_flags |= RC_CTSFLOW;
1049 val |= COR2_CtsAE;
1050 } else
1051 rc->rc_flags |= RC_SEND_RDY;
1052 if (tp->t_state & TS_TTSTOP)
1053 rc->rc_flags |= RC_OSUSP;
1054 else
1055 rc->rc_flags &= ~RC_OSUSP;
1056 if (cflag & CRTS_IFLOW)
1057 rc->rc_flags |= RC_RTSFLOW;
1058 else
1059 rc->rc_flags &= ~RC_RTSFLOW;
1060
1061 if (inpflow) {
1062 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
1063 rcout(CD180_SCHR1, ts->c_cc[VSTART]);
1064 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
1065 val |= COR2_TxIBE;
1066 if (iflag & IXANY)
1067 val |= COR2_IXM;
1068 }
1069
1070 rcout(CD180_COR2, rc->rc_cor2 = val);
1071
1072 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1073 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1074
1075 disc_optim(tp, ts, rc);
1076
1077 /* modem ctl */
1078 val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1079 if (cflag & CCTS_OFLOW)
1080 val |= MCOR1_CTSzd;
1081 rcout(CD180_MCOR1, val);
1082
1083 val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1084 if (cflag & CCTS_OFLOW)
1085 val |= MCOR2_CTSod;
1086 rcout(CD180_MCOR2, val);
1087
1088 /* enable i/o and interrupts */
1089 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1090 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1091 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1092
1093 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1094 if (cflag & CCTS_OFLOW)
1095 rc->rc_ier |= IER_CTS;
1096 if (cflag & CREAD)
1097 rc->rc_ier |= IER_RxData;
1098 if (tp->t_state & TS_BUSY)
1099 rc->rc_ier |= IER_TxRdy;
1100 if (ts->c_ospeed != 0)
1101 rc_modctl(rc, TIOCM_DTR, DMBIS);
1102 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1103 rc->rc_flags |= RC_SEND_RDY;
1104 rcout(CD180_IER, rc->rc_ier);
1105 (void) splx(s);
1106 return 0;
1107}
1108
1109/* Re-initialize board after bogus interrupts */
1110static void rc_reinit(rcb)
1111struct rc_softc *rcb;
1112{
1113 register struct rc_chans *rc, *rce;
1114 register int i, nec;
1115
1116 nec = rcb->rcb_addr;
1117 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1118 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1119 rce = rc + CD180_NCHAN;
1120 for (; rc < rce; rc++)
1121 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1122}
1123
1124int rcioctl(dev, cmd, data, flag, p)
1125dev_t dev;
1126int cmd, flag;
1127caddr_t data;
1128struct proc *p;
1129{
1130 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)];
1131 register int s, error;
1132 struct tty *tp = rc->rc_tp;
1133
1134 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
1135 if (error >= 0)
1136 return (error);
1137 error = ttioctl(tp, cmd, data, flag);
1138 if (error >= 0)
1139 return (error);
1140 s = spltty();
1141
1142 switch (cmd) {
1143 case TIOCSBRK:
1144 rc->rc_pendcmd = CD180_C_SBRK;
1145 break;
1146
1147 case TIOCCBRK:
1148 rc->rc_pendcmd = CD180_C_EBRK;
1149 break;
1150
1151 case TIOCSDTR:
1152 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1153 break;
1154
1155 case TIOCCDTR:
1156 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1157 break;
1158
1159 case TIOCMGET:
1160 *(int *) data = rc_modctl(rc, 0, DMGET);
1161 break;
1162
1163 case TIOCMSET:
1164 (void) rc_modctl(rc, *(int *) data, DMSET);
1165 break;
1166
1167 case TIOCMBIC:
1168 (void) rc_modctl(rc, *(int *) data, DMBIC);
1169 break;
1170
1171 case TIOCMBIS:
1172 (void) rc_modctl(rc, *(int *) data, DMBIS);
1173 break;
1174
1175 case TIOCMSDTRWAIT:
1176 error = suser(p->p_ucred, &p->p_acflag);
1177 if (error != 0) {
1178 splx(s);
1179 return (error);
1180 }
1181 rc->rc_dtrwait = *(int *)data * hz / 100;
1182 break;
1183
1184 case TIOCMGDTRWAIT:
1185 *(int *)data = rc->rc_dtrwait * 100 / hz;
1186 break;
1187
1188 default:
1189 (void) splx(s);
1190 return ENOTTY;
1191 }
1192 (void) splx(s);
1193 return 0;
1194}
1195
1196
1197/* Modem control routines */
1198
1199static int rc_modctl(rc, bits, cmd)
1200register struct rc_chans *rc;
1201int bits, cmd;
1202{
1203 register int nec = rc->rc_rcb->rcb_addr;
1204 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1205
1206 rcout(CD180_CAR, rc->rc_chan);
1207
1208 switch (cmd) {
1209 case DMSET:
1210 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1211 ~(*dtr |= 1 << rc->rc_chan) :
1212 ~(*dtr &= ~(1 << rc->rc_chan)));
1213 msvr = rcin(CD180_MSVR);
1214 if (bits & TIOCM_RTS)
1215 msvr |= MSVR_RTS;
1216 else
1217 msvr &= ~MSVR_RTS;
1218 if (bits & TIOCM_DTR)
1219 msvr |= MSVR_DTR;
1220 else
1221 msvr &= ~MSVR_DTR;
1222 rcout(CD180_MSVR, msvr);
1223 break;
1224
1225 case DMBIS:
1226 if (bits & TIOCM_DTR)
1227 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1228 msvr = rcin(CD180_MSVR);
1229 if (bits & TIOCM_RTS)
1230 msvr |= MSVR_RTS;
1231 if (bits & TIOCM_DTR)
1232 msvr |= MSVR_DTR;
1233 rcout(CD180_MSVR, msvr);
1234 break;
1235
1236 case DMGET:
1237 bits = TIOCM_LE;
1238 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1239
1240 if (msvr & MSVR_RTS)
1241 bits |= TIOCM_RTS;
1242 if (msvr & MSVR_CTS)
1243 bits |= TIOCM_CTS;
1244 if (msvr & MSVR_DSR)
1245 bits |= TIOCM_DSR;
1246 if (msvr & MSVR_DTR)
1247 bits |= TIOCM_DTR;
1248 if (msvr & MSVR_CD)
1249 bits |= TIOCM_CD;
1250 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1251 bits |= TIOCM_RI;
1252 return bits;
1253
1254 case DMBIC:
1255 if (bits & TIOCM_DTR)
1256 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1257 msvr = rcin(CD180_MSVR);
1258 if (bits & TIOCM_RTS)
1259 msvr &= ~MSVR_RTS;
1260 if (bits & TIOCM_DTR)
1261 msvr &= ~MSVR_DTR;
1262 rcout(CD180_MSVR, msvr);
1263 break;
1264 }
1265 rc->rc_msvr = rcin(CD180_MSVR);
1266 return 0;
1267}
1268
1269/* Test the board. */
1270int rc_test(nec, unit)
1271 register int nec;
1272 int unit;
1273{
1274 int chan = 0, nopt = 0;
1275 int i = 0, rcnt, old_level;
1276 unsigned int iack, chipid;
1277 unsigned short divs;
1278 static u_char ctest[] = "\377\125\252\045\244\0\377";
1279#define CTLEN 8
1280#define ERR(s) { \
1281 printf("rc%d: ", unit); printf s ; printf("\n"); \
1282 (void) splx(old_level); return 1; }
1283
1284 struct rtest {
1285 u_char txbuf[CD180_NFIFO]; /* TX buffer */
1286 u_char rxbuf[CD180_NFIFO]; /* RX buffer */
1287 int rxptr; /* RX pointer */
1288 int txptr; /* TX pointer */
1289 } tchans[CD180_NCHAN];
1290
1291 old_level = spltty();
1292
1293 chipid = RC_FAKEID;
1294
1295 /* First, reset board to inital state */
1296 rc_hwreset(unit, nec, chipid);
1297
1298 divs = RC_BRD(19200);
1299
1300 /* Initialize channels */
1301 for (chan = 0; chan < CD180_NCHAN; chan++) {
1302
1303 /* Select and reset channel */
1304 rcout(CD180_CAR, chan);
1305 CCRCMD(unit, chan, CCR_ResetChan);
1306 WAITFORCCR(unit, chan);
1307
1308 /* Set speed */
1309 rcout(CD180_RBPRL, divs & 0xFF);
1310 rcout(CD180_RBPRH, divs >> 8);
1311 rcout(CD180_TBPRL, divs & 0xFF);
1312 rcout(CD180_TBPRH, divs >> 8);
1313
1314 /* set timeout value */
1315 rcout(CD180_RTPR, 0);
1316
1317 /* Establish local loopback */
1318 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1319 rcout(CD180_COR2, COR2_LLM);
1320 rcout(CD180_COR3, CD180_NFIFO);
1321 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1322 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1323 WAITFORCCR(unit, chan);
1324 rcout(CD180_MSVR, MSVR_RTS);
1325
1326 /* Fill TXBUF with test data */
1327 for (i = 0; i < CD180_NFIFO; i++) {
1328 tchans[chan].txbuf[i] = ctest[i];
1329 tchans[chan].rxbuf[i] = 0;
1330 }
1331 tchans[chan].txptr = tchans[chan].rxptr = 0;
1332
1333 /* Now, start transmit */
1334 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1335 }
1336 /* Pseudo-interrupt poll stuff */
1337 for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1338 i = ~(rcin(RC_BSR));
1339 if (i & RC_BSR_TOUT)
1340 ERR(("BSR timeout bit set\n"))
1341 else if (i & RC_BSR_TXINT) {
1342 iack = rcin(RC_PILR_TX);
1343 if (iack != (GIVR_IT_TDI | chipid))
1344 ERR(("Bad TX intr ack (%02x != %02x)\n",
1345 iack, GIVR_IT_TDI | chipid));
1346 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1347 /* If no more data to transmit, disable TX intr */
1348 if (tchans[chan].txptr >= CD180_NFIFO) {
1349 iack = rcin(CD180_IER);
1350 rcout(CD180_IER, iack & ~IER_TxMpty);
1351 } else {
1352 for (iack = tchans[chan].txptr;
1353 iack < CD180_NFIFO; iack++)
1354 rcout(CD180_TDR,
1355 tchans[chan].txbuf[iack]);
1356 tchans[chan].txptr = iack;
1357 }
1358 rcout(CD180_EOIR, 0);
1359 } else if (i & RC_BSR_RXINT) {
1360 u_char ucnt;
1361
1362 iack = rcin(RC_PILR_RX);
1363 if (iack != (GIVR_IT_RGDI | chipid) &&
1364 iack != (GIVR_IT_REI | chipid))
1365 ERR(("Bad RX intr ack (%02x != %02x)\n",
1366 iack, GIVR_IT_RGDI | chipid))
1367 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1368 ucnt = rcin(CD180_RDCR) & 0xF;
1369 while (ucnt-- > 0) {
1370 iack = rcin(CD180_RCSR);
1371 if (iack & RCSR_Timeout)
1372 break;
1373 if (iack & 0xF)
1374 ERR(("Bad char chan %d (RCSR = %02X)\n",
1375 chan, iack))
1376 if (tchans[chan].rxptr > CD180_NFIFO)
1377 ERR(("Got extra chars chan %d\n",
1378 chan))
1379 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1380 rcin(CD180_RDR);
1381 }
1382 rcout(CD180_EOIR, 0);
1383 }
1384 rcout(RC_CTOUT, 0);
1385 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1386 if (tchans[chan].rxptr >= CD180_NFIFO)
1387 iack++;
1388 if (iack == CD180_NCHAN)
1389 break;
1390 }
1391 for (chan = 0; chan < CD180_NCHAN; chan++) {
1392 /* Select and reset channel */
1393 rcout(CD180_CAR, chan);
1394 CCRCMD(unit, chan, CCR_ResetChan);
1395 }
1396
1397 if (!rcnt)
1398 ERR(("looses characters during local loopback\n"))
1399 /* Now, check data */
1400 for (chan = 0; chan < CD180_NCHAN; chan++)
1401 for (i = 0; i < CD180_NFIFO; i++)
1402 if (ctest[i] != tchans[chan].rxbuf[i])
1403 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1404 chan, i, ctest[i], tchans[chan].rxbuf[i]))
1405 (void) splx(old_level);
1406 return 0;
1407}
1408
1409#ifdef RCDEBUG
1410static void printrcflags(rc, comment)
1411struct rc_chans *rc;
1412char *comment;
1413{
1414 u_short f = rc->rc_flags;
1415 register int nec = rc->rc_rcb->rcb_addr;
1416
1417 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1418 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1419 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1420 (f & RC_ACTOUT) ?"ACTOUT " :"",
1421 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1422 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1423 (f & RC_DORXFER)?"DORXFER " :"",
1424 (f & RC_DOXXFER)?"DOXXFER " :"",
1425 (f & RC_MODCHG) ?"MODCHG " :"",
1426 (f & RC_OSUSP) ?"OSUSP " :"",
1427 (f & RC_OSBUSY) ?"OSBUSY " :"",
1428 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1429 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1430 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1431
1432 rcout(CD180_CAR, rc->rc_chan);
1433
1434 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1435 rc->rc_rcb->rcb_unit, rc->rc_chan,
1436 rcin(CD180_MSVR),
1437 rcin(CD180_IER),
1438 rcin(CD180_CCSR));
1439}
1440#endif /* RCDEBUG */
1441
1442struct tty *
1443rcdevtotty(dev)
1444 dev_t dev;
1445{
1446 int unit;
1447
1448 unit = GET_UNIT(dev);
1449 if (unit >= NRC * CD180_NCHAN)
1450 return NULL;
1451 return (&rc_tty[unit]);
1452}
1453
1454static void
1455rc_dtrwakeup(chan)
1456 void *chan;
1457{
1458 struct rc_chans *rc;
1459
1460 rc = (struct rc_chans *)chan;
1461 rc->rc_flags &= ~RC_DTR_OFF;
1462 wakeup(&rc->rc_dtrwait);
1463}
1464
1465static void
1466rc_discard_output(rc)
1467 struct rc_chans *rc;
1468{
1469 disable_intr();
1470 if (rc->rc_flags & RC_DOXXFER) {
1471 rc_scheduled_event -= LOTS_OF_EVENTS;
1472 rc->rc_flags &= ~RC_DOXXFER;
1473 }
1474 rc->rc_optr = rc->rc_obufend;
1475 rc->rc_tp->t_state &= ~TS_BUSY;
1476 enable_intr();
1477}
1478
1479static void
1480rc_wakeup(chan)
1481 void *chan;
1482{
1483 int unit;
1484
1485 timeout(rc_wakeup, (caddr_t)NULL, 1);
1486
1487 if (rc_scheduled_event != 0) {
1488 int s;
1489
1490 s = splsofttty();
1491 rcpoll();
1492 splx(s);
1493 }
1494}
1495
1496static void
1497disc_optim(tp, t, rc)
1498 struct tty *tp;
1499 struct termios *t;
1500 struct rc_chans *rc;
1501{
1502
1503 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP
1504 | IXOFF | IXON))
1505 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1506 && (!(t->c_iflag & PARMRK) ||
1507 (t->c_iflag & (IGNPAR|IGNBRK)) == (IGNPAR|IGNBRK))
1508 && !(t->c_lflag & (ECHO | ECHONL | ICANON | IEXTEN | ISIG
1509 | PENDIN))
1510 && linesw[tp->t_line].l_rint == ttyinput)
1511 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1512 else
1513 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1514 if (tp->t_line == SLIPDISC)
1515 rc->rc_hotchar = 0xc0;
1516 else if (tp->t_line == PPPDISC)
1517 rc->rc_hotchar = 0x7e;
1518 else
1519 rc->rc_hotchar = 0;
1520}
1521
1522static void
1523rc_wait0(nec, unit, chan, line)
1524 int nec, unit, chan, line;
1525{
1526 int rcnt;
1527
1528 for (rcnt = 100; rcnt && rcin(CD180_CCR); rcnt--)
1529 DELAY(15);
1530 if (rcnt == 0)
1531 printf("rc%d/%d: channel command timeout, rc.c line: %d\n",
1532 unit, chan, line);
1533}
1534#endif /* NRC */
| 555#ifdef RCDEBUG
556 printf("rcstart: outq = %d obuf = %d\n",
557 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
558#endif
559 if (tp->t_state & TS_BUSY)
560 goto out; /* output still in progress ... */
561
562 if (tp->t_outq.c_cc > 0) {
563 u_int ocnt;
564
565 tp->t_state |= TS_BUSY;
566 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
567 disable_intr();
568 rc->rc_optr = rc->rc_obuf;
569 rc->rc_obufend = rc->rc_optr + ocnt;
570 enable_intr();
571 if (!(rc->rc_ier & IER_TxRdy)) {
572#ifdef RCDEBUG
573 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
574#endif
575 rcout(CD180_CAR, rc->rc_chan);
576 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
577 }
578 }
579out:
580 rc->rc_flags &= ~RC_OSBUSY;
581 (void) splx(s);
582}
583
584/* Handle delayed events. */
585void rcpoll()
586{
587 register struct rc_chans *rc;
588 register struct rc_softc *rcb;
589 register u_char *tptr, *eptr;
590 register int s;
591 register struct tty *tp;
592 register int chan, icnt, c, nec, unit;
593
594 if (rc_scheduled_event == 0)
595 return;
596repeat:
597 for (unit = 0; unit < NRC; unit++) {
598 rcb = &rc_softc[unit];
599 rc = rcb->rcb_baserc;
600 nec = rc->rc_rcb->rcb_addr;
601 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
602 tp = rc->rc_tp;
603#ifdef RCDEBUG
604 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
605 RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
606 printrcflags(rc, "rcevent");
607#endif
608 if (rc->rc_flags & RC_WAS_BUFOVFL) {
609 disable_intr();
610 rc->rc_flags &= ~RC_WAS_BUFOVFL;
611 rc_scheduled_event--;
612 enable_intr();
613 printf("rc%d/%d: interrupt-level buffer overflow\n",
614 unit, chan);
615 }
616 if (rc->rc_flags & RC_WAS_SILOVFL) {
617 disable_intr();
618 rc->rc_flags &= ~RC_WAS_SILOVFL;
619 rc_scheduled_event--;
620 enable_intr();
621 printf("rc%d/%d: silo overflow\n",
622 unit, chan);
623 }
624 if (rc->rc_flags & RC_MODCHG) {
625 disable_intr();
626 rc->rc_flags &= ~RC_MODCHG;
627 rc_scheduled_event -= LOTS_OF_EVENTS;
628 enable_intr();
629 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
630 }
631 if (rc->rc_flags & RC_DORXFER) {
632 disable_intr();
633 rc->rc_flags &= ~RC_DORXFER;
634 eptr = rc->rc_iptr;
635 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
636 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
637 else
638 tptr = rc->rc_ibuf;
639 icnt = eptr - tptr;
640 if (icnt > 0) {
641 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
642 rc->rc_iptr = rc->rc_ibuf;
643 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
644 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
645 } else {
646 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
647 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
648 rc->rc_hiwat =
649 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
650 }
651 if ( (rc->rc_flags & RC_RTSFLOW)
652 && (tp->t_state & TS_ISOPEN)
653 && !(tp->t_state & TS_TBLOCK)
654 && !(rc->rc_msvr & MSVR_RTS)
655 ) {
656 rcout(CD180_CAR, chan);
657 rcout(CD180_MSVR,
658 rc->rc_msvr |= MSVR_RTS);
659 }
660 rc_scheduled_event -= icnt;
661 }
662 enable_intr();
663
664 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
665 goto done1;
666
667 if ( linesw[tp->t_line].l_rint == ttyinput
668 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
669 && !(tp->t_state & TS_TBLOCK)
670 && (tp->t_rawq.c_cc + icnt) > RB_I_HIGH_WATER) {
671 int queue_full = 0;
672
673 if ((tp->t_iflag & IXOFF) &&
674 tp->t_cc[VSTOP] != _POSIX_VDISABLE &&
675 (queue_full = putc(tp->t_cc[VSTOP], &tp->t_outq)) == 0 ||
676 (rc->rc_flags & RC_RTSFLOW)) {
677 tp->t_state |= TS_TBLOCK;
678 ttstart(tp);
679 if (queue_full) /* try again */
680 tp->t_state &= ~TS_TBLOCK;
681 }
682 }
683 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT)
684 && !(tp->t_state & TS_LOCAL)) {
685 tk_nin += icnt;
686 tk_rawcc += icnt;
687 tp->t_rawcc += icnt;
688 if (b_to_q(tptr, icnt, &tp->t_rawq))
689 printf("rc%d/%d: tty-level buffer overflow\n",
690 unit, chan);
691 ttwakeup(tp);
692 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
693 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
694 tp->t_state &= ~TS_TTSTOP;
695 tp->t_lflag &= ~FLUSHO;
696 ttstart(tp);
697 }
698 } else {
699 for (; tptr < eptr; tptr++)
700 (*linesw[tp->t_line].l_rint)
701 (tptr[0] |
702 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
703 }
704done1:
705 }
706 if (rc->rc_flags & RC_DOXXFER) {
707 disable_intr();
708 rc_scheduled_event -= LOTS_OF_EVENTS;
709 rc->rc_flags &= ~RC_DOXXFER;
710 rc->rc_tp->t_state &= ~TS_BUSY;
711 enable_intr();
712 (*linesw[tp->t_line].l_start)(tp);
713 }
714 }
715 if (rc_scheduled_event == 0)
716 break;
717 }
718 if (rc_scheduled_event >= LOTS_OF_EVENTS)
719 goto repeat;
720}
721
722void rcstop(tp, rw)
723 register struct tty *tp;
724 int rw;
725{
726 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
727 u_char *tptr, *eptr;
728
729#ifdef RCDEBUG
730 printf("rc%d/%d: rcstop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
731 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
732#endif
733 if (rw & FWRITE)
734 rc_discard_output(rc);
735 disable_intr();
736 if (rw & FREAD) {
737 rc->rc_flags &= ~RC_DORXFER;
738 eptr = rc->rc_iptr;
739 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
740 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
741 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
742 } else {
743 tptr = rc->rc_ibuf;
744 rc->rc_iptr = rc->rc_ibuf;
745 }
746 rc_scheduled_event -= eptr - tptr;
747 }
748 if (tp->t_state & TS_TTSTOP)
749 rc->rc_flags |= RC_OSUSP;
750 else
751 rc->rc_flags &= ~RC_OSUSP;
752 enable_intr();
753}
754
755int rcopen(dev, flag, mode, p)
756 dev_t dev;
757 int flag, mode;
758 struct proc *p;
759{
760 register struct rc_chans *rc;
761 register struct tty *tp;
762 int unit, nec, s, error = 0;
763
764 unit = GET_UNIT(dev);
765 if (unit >= NRC * CD180_NCHAN)
766 return ENXIO;
767 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
768 return ENXIO;
769 rc = &rc_chans[unit];
770 tp = rc->rc_tp;
771 nec = rc->rc_rcb->rcb_addr;
772#ifdef RCDEBUG
773 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
774#endif
775 s = spltty();
776
777again:
778 while (rc->rc_flags & RC_DTR_OFF) {
779 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0);
780 if (error != 0)
781 goto out;
782 }
783 if (tp->t_state & TS_ISOPEN) {
784 if (CALLOUT(dev)) {
785 if (!(rc->rc_flags & RC_ACTOUT)) {
786 error = EBUSY;
787 goto out;
788 }
789 } else {
790 if (rc->rc_flags & RC_ACTOUT) {
791 if (flag & O_NONBLOCK) {
792 error = EBUSY;
793 goto out;
794 }
795 if (error = tsleep(&rc->rc_rcb,
796 TTIPRI|PCATCH, "rcbi", 0))
797 goto out;
798 goto again;
799 }
800 }
801 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) {
802 error = EBUSY;
803 goto out;
804 }
805 } else {
806 tp->t_oproc = rc_start;
807 tp->t_param = rc_param;
808 tp->t_dev = dev;
809
810 if (CALLOUT(dev))
811 tp->t_cflag |= CLOCAL;
812 else
813 tp->t_cflag &= ~CLOCAL;
814
815 error = rc_param(tp, &tp->t_termios);
816 if (error)
817 goto out;
818 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
819
820 ttsetwater(tp);
821
822 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
823 (*linesw[tp->t_line].l_modem)(tp, 1);
824 }
825 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
826 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
827 rc->rc_dcdwaits++;
828 error = tsleep(&tp->t_rawq, TTIPRI | PCATCH, "rcdcd", 0);
829 rc->rc_dcdwaits--;
830 if (error != 0)
831 goto out;
832 goto again;
833 }
834 error = (*linesw[tp->t_line].l_open)(dev, tp);
835 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
836 rc->rc_flags |= RC_ACTOUT;
837out:
838 (void) splx(s);
839
840 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
841 rc_hardclose(rc);
842
843 return error;
844}
845
846int rcclose(dev, flag, mode, p)
847 dev_t dev;
848 int flag, mode;
849 struct proc *p;
850{
851 register struct rc_chans *rc;
852 register struct tty *tp;
853 int s, unit = GET_UNIT(dev);
854
855 if (unit >= NRC * CD180_NCHAN)
856 return ENXIO;
857 rc = &rc_chans[unit];
858 tp = rc->rc_tp;
859#ifdef RCDEBUG
860 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
861#endif
862 s = spltty();
863 (*linesw[tp->t_line].l_close)(tp, flag);
864 rcstop(tp, FREAD | FWRITE);
865 rc_hardclose(rc);
866 ttyclose(tp);
867 splx(s);
868 return 0;
869}
870
871static void rc_hardclose(rc)
872register struct rc_chans *rc;
873{
874 register int s, nec = rc->rc_rcb->rcb_addr;
875 register struct tty *tp = rc->rc_tp;
876
877 s = spltty();
878 rcout(CD180_CAR, rc->rc_chan);
879
880 /* Disable rx/tx intrs */
881 rcout(CD180_IER, rc->rc_ier = 0);
882 if ( (tp->t_cflag & HUPCL)
883 || !(rc->rc_flags & RC_ACTOUT)
884 && !(rc->rc_msvr & MSVR_CD)
885 && !(tp->t_cflag & CLOCAL)
886 || !(tp->t_state & TS_ISOPEN)
887 ) {
888 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
889 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
890 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
891 if (rc->rc_dtrwait) {
892 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait);
893 rc->rc_flags |= RC_DTR_OFF;
894 }
895 }
896 rc->rc_flags &= ~RC_ACTOUT;
897 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */
898 wakeup((caddr_t) &tp->t_rawq); /* wake dcd */
899 (void) splx(s);
900}
901
902/* Read from line */
903int rcread(dev, uio, flag)
904 dev_t dev;
905 struct uio *uio;
906 int flag;
907{
908 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp;
909
910 return ((*linesw[tp->t_line].l_read)(tp, uio, flag));
911}
912
913/* Write to line */
914int rcwrite(dev, uio, flag)
915 dev_t dev;
916 struct uio *uio;
917 int flag;
918{
919 struct tty *tp = rc_chans[GET_UNIT(dev)].rc_tp;
920
921 return ((*linesw[tp->t_line].l_write)(tp, uio, flag));
922}
923
924/* Reset the bastard */
925static void rc_hwreset(unit, nec, chipid)
926 register int unit, nec;
927 unsigned int chipid;
928{
929 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */
930 DELAY(20000);
931 WAITFORCCR(unit, -1);
932
933 rcout(RC_CTOUT, 0); /* Clear timeout */
934 rcout(CD180_GIVR, chipid);
935 rcout(CD180_GICR, 0);
936
937 /* Set Prescaler Registers (1 msec) */
938 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
939 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
940
941 /* Initialize Priority Interrupt Level Registers */
942 rcout(CD180_PILR1, RC_PILR_MODEM);
943 rcout(CD180_PILR2, RC_PILR_TX);
944 rcout(CD180_PILR3, RC_PILR_RX);
945
946 /* Reset DTR */
947 rcout(RC_DTREG, ~0);
948}
949
950/* Set channel parameters */
951static int rc_param(tp, ts)
952 register struct tty *tp;
953 struct termios *ts;
954{
955 register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
956 register int nec = rc->rc_rcb->rcb_addr;
957 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow;
958
959 odivs = ttspeedtab(ts->c_ospeed, rc_speedtab);
960 if (ts->c_ispeed == 0)
961 ts->c_ispeed = ts->c_ospeed;
962 idivs = ttspeedtab(ts->c_ispeed, rc_speedtab);
963 if (idivs < 0 || odivs < 0)
964 return (EINVAL);
965
966 s = spltty();
967
968 /* Select channel */
969 rcout(CD180_CAR, rc->rc_chan);
970
971 /* If speed == 0, hangup line */
972 if (ts->c_ospeed == 0) {
973 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
974 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
975 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
976 }
977
978 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
979 cflag = ts->c_cflag;
980 iflag = ts->c_iflag;
981 lflag = ts->c_lflag;
982
983 if (idivs > 0) {
984 rcout(CD180_RBPRL, idivs & 0xFF);
985 rcout(CD180_RBPRH, idivs >> 8);
986 }
987 if (odivs > 0) {
988 rcout(CD180_TBPRL, odivs & 0xFF);
989 rcout(CD180_TBPRH, odivs >> 8);
990 }
991
992 /* set timeout value */
993 if (ts->c_ispeed > 0) {
994 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
995
996 if ( !(lflag & ICANON)
997 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
998 && ts->c_cc[VTIME] * 10 > itm)
999 itm = ts->c_cc[VTIME] * 10;
1000
1001 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
1002 }
1003
1004 switch (cflag & CSIZE) {
1005 case CS5: val = COR1_5BITS; break;
1006 case CS6: val = COR1_6BITS; break;
1007 case CS7: val = COR1_7BITS; break;
1008 default:
1009 case CS8: val = COR1_8BITS; break;
1010 }
1011 if (cflag & PARENB) {
1012 val |= COR1_NORMPAR;
1013 if (cflag & PARODD)
1014 val |= COR1_ODDP;
1015 if (!(cflag & INPCK))
1016 val |= COR1_Ignore;
1017 } else
1018 val |= COR1_Ignore;
1019 if (cflag & CSTOPB)
1020 val |= COR1_2SB;
1021 rcout(CD180_COR1, val);
1022
1023 /* Set FIFO threshold */
1024 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
1025 inpflow = 0;
1026 if ( (iflag & IXOFF)
1027 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE
1028 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE
1029 || (iflag & IXANY)
1030 )
1031 )
1032 ) {
1033 inpflow = 1;
1034 val |= COR3_SCDE|COR3_FCT;
1035 }
1036 rcout(CD180_COR3, val);
1037
1038 /* Initialize on-chip automatic flow control */
1039 val = 0;
1040 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
1041 if (cflag & CCTS_OFLOW) {
1042 rc->rc_flags |= RC_CTSFLOW;
1043 val |= COR2_CtsAE;
1044 } else
1045 rc->rc_flags |= RC_SEND_RDY;
1046 if (tp->t_state & TS_TTSTOP)
1047 rc->rc_flags |= RC_OSUSP;
1048 else
1049 rc->rc_flags &= ~RC_OSUSP;
1050 if (cflag & CRTS_IFLOW)
1051 rc->rc_flags |= RC_RTSFLOW;
1052 else
1053 rc->rc_flags &= ~RC_RTSFLOW;
1054
1055 if (inpflow) {
1056 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
1057 rcout(CD180_SCHR1, ts->c_cc[VSTART]);
1058 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
1059 val |= COR2_TxIBE;
1060 if (iflag & IXANY)
1061 val |= COR2_IXM;
1062 }
1063
1064 rcout(CD180_COR2, rc->rc_cor2 = val);
1065
1066 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1067 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1068
1069 disc_optim(tp, ts, rc);
1070
1071 /* modem ctl */
1072 val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1073 if (cflag & CCTS_OFLOW)
1074 val |= MCOR1_CTSzd;
1075 rcout(CD180_MCOR1, val);
1076
1077 val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1078 if (cflag & CCTS_OFLOW)
1079 val |= MCOR2_CTSod;
1080 rcout(CD180_MCOR2, val);
1081
1082 /* enable i/o and interrupts */
1083 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1084 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1085 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1086
1087 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1088 if (cflag & CCTS_OFLOW)
1089 rc->rc_ier |= IER_CTS;
1090 if (cflag & CREAD)
1091 rc->rc_ier |= IER_RxData;
1092 if (tp->t_state & TS_BUSY)
1093 rc->rc_ier |= IER_TxRdy;
1094 if (ts->c_ospeed != 0)
1095 rc_modctl(rc, TIOCM_DTR, DMBIS);
1096 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1097 rc->rc_flags |= RC_SEND_RDY;
1098 rcout(CD180_IER, rc->rc_ier);
1099 (void) splx(s);
1100 return 0;
1101}
1102
1103/* Re-initialize board after bogus interrupts */
1104static void rc_reinit(rcb)
1105struct rc_softc *rcb;
1106{
1107 register struct rc_chans *rc, *rce;
1108 register int i, nec;
1109
1110 nec = rcb->rcb_addr;
1111 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1112 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1113 rce = rc + CD180_NCHAN;
1114 for (; rc < rce; rc++)
1115 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1116}
1117
1118int rcioctl(dev, cmd, data, flag, p)
1119dev_t dev;
1120int cmd, flag;
1121caddr_t data;
1122struct proc *p;
1123{
1124 register struct rc_chans *rc = &rc_chans[GET_UNIT(dev)];
1125 register int s, error;
1126 struct tty *tp = rc->rc_tp;
1127
1128 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
1129 if (error >= 0)
1130 return (error);
1131 error = ttioctl(tp, cmd, data, flag);
1132 if (error >= 0)
1133 return (error);
1134 s = spltty();
1135
1136 switch (cmd) {
1137 case TIOCSBRK:
1138 rc->rc_pendcmd = CD180_C_SBRK;
1139 break;
1140
1141 case TIOCCBRK:
1142 rc->rc_pendcmd = CD180_C_EBRK;
1143 break;
1144
1145 case TIOCSDTR:
1146 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1147 break;
1148
1149 case TIOCCDTR:
1150 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1151 break;
1152
1153 case TIOCMGET:
1154 *(int *) data = rc_modctl(rc, 0, DMGET);
1155 break;
1156
1157 case TIOCMSET:
1158 (void) rc_modctl(rc, *(int *) data, DMSET);
1159 break;
1160
1161 case TIOCMBIC:
1162 (void) rc_modctl(rc, *(int *) data, DMBIC);
1163 break;
1164
1165 case TIOCMBIS:
1166 (void) rc_modctl(rc, *(int *) data, DMBIS);
1167 break;
1168
1169 case TIOCMSDTRWAIT:
1170 error = suser(p->p_ucred, &p->p_acflag);
1171 if (error != 0) {
1172 splx(s);
1173 return (error);
1174 }
1175 rc->rc_dtrwait = *(int *)data * hz / 100;
1176 break;
1177
1178 case TIOCMGDTRWAIT:
1179 *(int *)data = rc->rc_dtrwait * 100 / hz;
1180 break;
1181
1182 default:
1183 (void) splx(s);
1184 return ENOTTY;
1185 }
1186 (void) splx(s);
1187 return 0;
1188}
1189
1190
1191/* Modem control routines */
1192
1193static int rc_modctl(rc, bits, cmd)
1194register struct rc_chans *rc;
1195int bits, cmd;
1196{
1197 register int nec = rc->rc_rcb->rcb_addr;
1198 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1199
1200 rcout(CD180_CAR, rc->rc_chan);
1201
1202 switch (cmd) {
1203 case DMSET:
1204 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1205 ~(*dtr |= 1 << rc->rc_chan) :
1206 ~(*dtr &= ~(1 << rc->rc_chan)));
1207 msvr = rcin(CD180_MSVR);
1208 if (bits & TIOCM_RTS)
1209 msvr |= MSVR_RTS;
1210 else
1211 msvr &= ~MSVR_RTS;
1212 if (bits & TIOCM_DTR)
1213 msvr |= MSVR_DTR;
1214 else
1215 msvr &= ~MSVR_DTR;
1216 rcout(CD180_MSVR, msvr);
1217 break;
1218
1219 case DMBIS:
1220 if (bits & TIOCM_DTR)
1221 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1222 msvr = rcin(CD180_MSVR);
1223 if (bits & TIOCM_RTS)
1224 msvr |= MSVR_RTS;
1225 if (bits & TIOCM_DTR)
1226 msvr |= MSVR_DTR;
1227 rcout(CD180_MSVR, msvr);
1228 break;
1229
1230 case DMGET:
1231 bits = TIOCM_LE;
1232 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1233
1234 if (msvr & MSVR_RTS)
1235 bits |= TIOCM_RTS;
1236 if (msvr & MSVR_CTS)
1237 bits |= TIOCM_CTS;
1238 if (msvr & MSVR_DSR)
1239 bits |= TIOCM_DSR;
1240 if (msvr & MSVR_DTR)
1241 bits |= TIOCM_DTR;
1242 if (msvr & MSVR_CD)
1243 bits |= TIOCM_CD;
1244 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1245 bits |= TIOCM_RI;
1246 return bits;
1247
1248 case DMBIC:
1249 if (bits & TIOCM_DTR)
1250 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1251 msvr = rcin(CD180_MSVR);
1252 if (bits & TIOCM_RTS)
1253 msvr &= ~MSVR_RTS;
1254 if (bits & TIOCM_DTR)
1255 msvr &= ~MSVR_DTR;
1256 rcout(CD180_MSVR, msvr);
1257 break;
1258 }
1259 rc->rc_msvr = rcin(CD180_MSVR);
1260 return 0;
1261}
1262
1263/* Test the board. */
1264int rc_test(nec, unit)
1265 register int nec;
1266 int unit;
1267{
1268 int chan = 0, nopt = 0;
1269 int i = 0, rcnt, old_level;
1270 unsigned int iack, chipid;
1271 unsigned short divs;
1272 static u_char ctest[] = "\377\125\252\045\244\0\377";
1273#define CTLEN 8
1274#define ERR(s) { \
1275 printf("rc%d: ", unit); printf s ; printf("\n"); \
1276 (void) splx(old_level); return 1; }
1277
1278 struct rtest {
1279 u_char txbuf[CD180_NFIFO]; /* TX buffer */
1280 u_char rxbuf[CD180_NFIFO]; /* RX buffer */
1281 int rxptr; /* RX pointer */
1282 int txptr; /* TX pointer */
1283 } tchans[CD180_NCHAN];
1284
1285 old_level = spltty();
1286
1287 chipid = RC_FAKEID;
1288
1289 /* First, reset board to inital state */
1290 rc_hwreset(unit, nec, chipid);
1291
1292 divs = RC_BRD(19200);
1293
1294 /* Initialize channels */
1295 for (chan = 0; chan < CD180_NCHAN; chan++) {
1296
1297 /* Select and reset channel */
1298 rcout(CD180_CAR, chan);
1299 CCRCMD(unit, chan, CCR_ResetChan);
1300 WAITFORCCR(unit, chan);
1301
1302 /* Set speed */
1303 rcout(CD180_RBPRL, divs & 0xFF);
1304 rcout(CD180_RBPRH, divs >> 8);
1305 rcout(CD180_TBPRL, divs & 0xFF);
1306 rcout(CD180_TBPRH, divs >> 8);
1307
1308 /* set timeout value */
1309 rcout(CD180_RTPR, 0);
1310
1311 /* Establish local loopback */
1312 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1313 rcout(CD180_COR2, COR2_LLM);
1314 rcout(CD180_COR3, CD180_NFIFO);
1315 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1316 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1317 WAITFORCCR(unit, chan);
1318 rcout(CD180_MSVR, MSVR_RTS);
1319
1320 /* Fill TXBUF with test data */
1321 for (i = 0; i < CD180_NFIFO; i++) {
1322 tchans[chan].txbuf[i] = ctest[i];
1323 tchans[chan].rxbuf[i] = 0;
1324 }
1325 tchans[chan].txptr = tchans[chan].rxptr = 0;
1326
1327 /* Now, start transmit */
1328 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1329 }
1330 /* Pseudo-interrupt poll stuff */
1331 for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1332 i = ~(rcin(RC_BSR));
1333 if (i & RC_BSR_TOUT)
1334 ERR(("BSR timeout bit set\n"))
1335 else if (i & RC_BSR_TXINT) {
1336 iack = rcin(RC_PILR_TX);
1337 if (iack != (GIVR_IT_TDI | chipid))
1338 ERR(("Bad TX intr ack (%02x != %02x)\n",
1339 iack, GIVR_IT_TDI | chipid));
1340 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1341 /* If no more data to transmit, disable TX intr */
1342 if (tchans[chan].txptr >= CD180_NFIFO) {
1343 iack = rcin(CD180_IER);
1344 rcout(CD180_IER, iack & ~IER_TxMpty);
1345 } else {
1346 for (iack = tchans[chan].txptr;
1347 iack < CD180_NFIFO; iack++)
1348 rcout(CD180_TDR,
1349 tchans[chan].txbuf[iack]);
1350 tchans[chan].txptr = iack;
1351 }
1352 rcout(CD180_EOIR, 0);
1353 } else if (i & RC_BSR_RXINT) {
1354 u_char ucnt;
1355
1356 iack = rcin(RC_PILR_RX);
1357 if (iack != (GIVR_IT_RGDI | chipid) &&
1358 iack != (GIVR_IT_REI | chipid))
1359 ERR(("Bad RX intr ack (%02x != %02x)\n",
1360 iack, GIVR_IT_RGDI | chipid))
1361 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1362 ucnt = rcin(CD180_RDCR) & 0xF;
1363 while (ucnt-- > 0) {
1364 iack = rcin(CD180_RCSR);
1365 if (iack & RCSR_Timeout)
1366 break;
1367 if (iack & 0xF)
1368 ERR(("Bad char chan %d (RCSR = %02X)\n",
1369 chan, iack))
1370 if (tchans[chan].rxptr > CD180_NFIFO)
1371 ERR(("Got extra chars chan %d\n",
1372 chan))
1373 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1374 rcin(CD180_RDR);
1375 }
1376 rcout(CD180_EOIR, 0);
1377 }
1378 rcout(RC_CTOUT, 0);
1379 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1380 if (tchans[chan].rxptr >= CD180_NFIFO)
1381 iack++;
1382 if (iack == CD180_NCHAN)
1383 break;
1384 }
1385 for (chan = 0; chan < CD180_NCHAN; chan++) {
1386 /* Select and reset channel */
1387 rcout(CD180_CAR, chan);
1388 CCRCMD(unit, chan, CCR_ResetChan);
1389 }
1390
1391 if (!rcnt)
1392 ERR(("looses characters during local loopback\n"))
1393 /* Now, check data */
1394 for (chan = 0; chan < CD180_NCHAN; chan++)
1395 for (i = 0; i < CD180_NFIFO; i++)
1396 if (ctest[i] != tchans[chan].rxbuf[i])
1397 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1398 chan, i, ctest[i], tchans[chan].rxbuf[i]))
1399 (void) splx(old_level);
1400 return 0;
1401}
1402
1403#ifdef RCDEBUG
1404static void printrcflags(rc, comment)
1405struct rc_chans *rc;
1406char *comment;
1407{
1408 u_short f = rc->rc_flags;
1409 register int nec = rc->rc_rcb->rcb_addr;
1410
1411 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1412 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1413 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1414 (f & RC_ACTOUT) ?"ACTOUT " :"",
1415 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1416 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1417 (f & RC_DORXFER)?"DORXFER " :"",
1418 (f & RC_DOXXFER)?"DOXXFER " :"",
1419 (f & RC_MODCHG) ?"MODCHG " :"",
1420 (f & RC_OSUSP) ?"OSUSP " :"",
1421 (f & RC_OSBUSY) ?"OSBUSY " :"",
1422 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1423 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1424 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1425
1426 rcout(CD180_CAR, rc->rc_chan);
1427
1428 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1429 rc->rc_rcb->rcb_unit, rc->rc_chan,
1430 rcin(CD180_MSVR),
1431 rcin(CD180_IER),
1432 rcin(CD180_CCSR));
1433}
1434#endif /* RCDEBUG */
1435
1436struct tty *
1437rcdevtotty(dev)
1438 dev_t dev;
1439{
1440 int unit;
1441
1442 unit = GET_UNIT(dev);
1443 if (unit >= NRC * CD180_NCHAN)
1444 return NULL;
1445 return (&rc_tty[unit]);
1446}
1447
1448static void
1449rc_dtrwakeup(chan)
1450 void *chan;
1451{
1452 struct rc_chans *rc;
1453
1454 rc = (struct rc_chans *)chan;
1455 rc->rc_flags &= ~RC_DTR_OFF;
1456 wakeup(&rc->rc_dtrwait);
1457}
1458
1459static void
1460rc_discard_output(rc)
1461 struct rc_chans *rc;
1462{
1463 disable_intr();
1464 if (rc->rc_flags & RC_DOXXFER) {
1465 rc_scheduled_event -= LOTS_OF_EVENTS;
1466 rc->rc_flags &= ~RC_DOXXFER;
1467 }
1468 rc->rc_optr = rc->rc_obufend;
1469 rc->rc_tp->t_state &= ~TS_BUSY;
1470 enable_intr();
1471}
1472
1473static void
1474rc_wakeup(chan)
1475 void *chan;
1476{
1477 int unit;
1478
1479 timeout(rc_wakeup, (caddr_t)NULL, 1);
1480
1481 if (rc_scheduled_event != 0) {
1482 int s;
1483
1484 s = splsofttty();
1485 rcpoll();
1486 splx(s);
1487 }
1488}
1489
1490static void
1491disc_optim(tp, t, rc)
1492 struct tty *tp;
1493 struct termios *t;
1494 struct rc_chans *rc;
1495{
1496
1497 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP
1498 | IXOFF | IXON))
1499 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1500 && (!(t->c_iflag & PARMRK) ||
1501 (t->c_iflag & (IGNPAR|IGNBRK)) == (IGNPAR|IGNBRK))
1502 && !(t->c_lflag & (ECHO | ECHONL | ICANON | IEXTEN | ISIG
1503 | PENDIN))
1504 && linesw[tp->t_line].l_rint == ttyinput)
1505 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1506 else
1507 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1508 if (tp->t_line == SLIPDISC)
1509 rc->rc_hotchar = 0xc0;
1510 else if (tp->t_line == PPPDISC)
1511 rc->rc_hotchar = 0x7e;
1512 else
1513 rc->rc_hotchar = 0;
1514}
1515
1516static void
1517rc_wait0(nec, unit, chan, line)
1518 int nec, unit, chan, line;
1519{
1520 int rcnt;
1521
1522 for (rcnt = 100; rcnt && rcin(CD180_CCR); rcnt--)
1523 DELAY(15);
1524 if (rcnt == 0)
1525 printf("rc%d/%d: channel command timeout, rc.c line: %d\n",
1526 unit, chan, line);
1527}
1528#endif /* NRC */
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