Deleted Added
sdiff udiff text old ( 251715 ) new ( 263109 )
full compact
1/*-
2 * Copyright (c) 2006 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/puc/pucdata.c 251715 2013-06-13 22:13:41Z marius $");
28__FBSDID("$FreeBSD: head/sys/dev/puc/pucdata.c 263109 2014-03-13 15:57:25Z rstone $");
29
30/*
31 * PCI "universal" communications card driver configuration data (used to
32 * match/attach the cards).
33 */
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/bus.h>
39#include <sys/sysctl.h>
40
41#include <machine/resource.h>
42#include <machine/bus.h>
43#include <sys/rman.h>
44
45#include <dev/pci/pcivar.h>
46
47#include <dev/puc/puc_bus.h>
48#include <dev/puc/puc_cfg.h>
49#include <dev/puc/puc_bfe.h>
50
51static puc_config_f puc_config_amc;
52static puc_config_f puc_config_diva;
53static puc_config_f puc_config_exar;
54static puc_config_f puc_config_exar_pcie;
55static puc_config_f puc_config_icbook;
56static puc_config_f puc_config_moxa;
57static puc_config_f puc_config_oxford_pci954;
58static puc_config_f puc_config_oxford_pcie;
59static puc_config_f puc_config_quatech;
60static puc_config_f puc_config_syba;
61static puc_config_f puc_config_siig;
62static puc_config_f puc_config_timedia;
63static puc_config_f puc_config_titan;
64
65const struct puc_cfg puc_pci_devices[] = {
66
67 { 0x0009, 0x7168, 0xffff, 0,
68 "Sunix SUN1889",
69 DEFAULT_RCLK * 8,
70 PUC_PORT_2S, 0x10, 0, 8,
71 },
72
73 { 0x103c, 0x1048, 0x103c, 0x1049,
74 "HP Diva Serial [GSP] Multiport UART - Tosca Console",
75 DEFAULT_RCLK,
76 PUC_PORT_3S, 0x10, 0, -1,
77 .config_function = puc_config_diva
78 },
79
80 { 0x103c, 0x1048, 0x103c, 0x104a,
81 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
82 DEFAULT_RCLK,
83 PUC_PORT_2S, 0x10, 0, -1,
84 .config_function = puc_config_diva
85 },
86
87 { 0x103c, 0x1048, 0x103c, 0x104b,
88 "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
89 DEFAULT_RCLK,
90 PUC_PORT_4S, 0x10, 0, -1,
91 .config_function = puc_config_diva
92 },
93
94 { 0x103c, 0x1048, 0x103c, 0x1223,
95 "HP Diva Serial [GSP] Multiport UART - Superdome Console",
96 DEFAULT_RCLK,
97 PUC_PORT_3S, 0x10, 0, -1,
98 .config_function = puc_config_diva
99 },
100
101 { 0x103c, 0x1048, 0x103c, 0x1226,
102 "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
103 DEFAULT_RCLK,
104 PUC_PORT_3S, 0x10, 0, -1,
105 .config_function = puc_config_diva
106 },
107
108 { 0x103c, 0x1048, 0x103c, 0x1282,
109 "HP Diva Serial [GSP] Multiport UART - Everest SP2",
110 DEFAULT_RCLK,
111 PUC_PORT_3S, 0x10, 0, -1,
112 .config_function = puc_config_diva
113 },
114
115 { 0x10b5, 0x1076, 0x10b5, 0x1076,
116 "VScom PCI-800",
117 DEFAULT_RCLK * 8,
118 PUC_PORT_8S, 0x18, 0, 8,
119 },
120
121 { 0x10b5, 0x1077, 0x10b5, 0x1077,
122 "VScom PCI-400",
123 DEFAULT_RCLK * 8,
124 PUC_PORT_4S, 0x18, 0, 8,
125 },
126
127 { 0x10b5, 0x1103, 0x10b5, 0x1103,
128 "VScom PCI-200",
129 DEFAULT_RCLK * 8,
130 PUC_PORT_2S, 0x18, 4, 0,
131 },
132
133 /*
134 * Boca Research Turbo Serial 658 (8 serial port) card.
135 * Appears to be the same as Chase Research PLC PCI-FAST8
136 * and Perle PCI-FAST8 Multi-Port serial cards.
137 */
138 { 0x10b5, 0x9050, 0x12e0, 0x0021,
139 "Boca Research Turbo Serial 658",
140 DEFAULT_RCLK * 4,
141 PUC_PORT_8S, 0x18, 0, 8,
142 },
143
144 { 0x10b5, 0x9050, 0x12e0, 0x0031,
145 "Boca Research Turbo Serial 654",
146 DEFAULT_RCLK * 4,
147 PUC_PORT_4S, 0x18, 0, 8,
148 },
149
150 /*
151 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with
152 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
153 * into the subsystem fields, and claims that it's a
154 * network/misc (0x02/0x80) device.
155 */
156 { 0x10b5, 0x9050, 0xd84d, 0x6808,
157 "Dolphin Peripherals 4035",
158 DEFAULT_RCLK,
159 PUC_PORT_2S, 0x18, 4, 0,
160 },
161
162 /*
163 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with
164 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
165 * into the subsystem fields, and claims that it's a
166 * network/misc (0x02/0x80) device.
167 */
168 { 0x10b5, 0x9050, 0xd84d, 0x6810,
169 "Dolphin Peripherals 4014",
170 0,
171 PUC_PORT_2P, 0x20, 4, 0,
172 },
173
174 { 0x10e8, 0x818e, 0xffff, 0,
175 "Applied Micro Circuits 8 Port UART",
176 DEFAULT_RCLK,
177 PUC_PORT_8S, 0x14, -1, -1,
178 .config_function = puc_config_amc
179 },
180
181 { 0x11fe, 0x8010, 0xffff, 0,
182 "Comtrol RocketPort 550/8 RJ11 part A",
183 DEFAULT_RCLK * 4,
184 PUC_PORT_4S, 0x10, 0, 8,
185 },
186
187 { 0x11fe, 0x8011, 0xffff, 0,
188 "Comtrol RocketPort 550/8 RJ11 part B",
189 DEFAULT_RCLK * 4,
190 PUC_PORT_4S, 0x10, 0, 8,
191 },
192
193 { 0x11fe, 0x8012, 0xffff, 0,
194 "Comtrol RocketPort 550/8 Octa part A",
195 DEFAULT_RCLK * 4,
196 PUC_PORT_4S, 0x10, 0, 8,
197 },
198
199 { 0x11fe, 0x8013, 0xffff, 0,
200 "Comtrol RocketPort 550/8 Octa part B",
201 DEFAULT_RCLK * 4,
202 PUC_PORT_4S, 0x10, 0, 8,
203 },
204
205 { 0x11fe, 0x8014, 0xffff, 0,
206 "Comtrol RocketPort 550/4 RJ45",
207 DEFAULT_RCLK * 4,
208 PUC_PORT_4S, 0x10, 0, 8,
209 },
210
211 { 0x11fe, 0x8015, 0xffff, 0,
212 "Comtrol RocketPort 550/Quad",
213 DEFAULT_RCLK * 4,
214 PUC_PORT_4S, 0x10, 0, 8,
215 },
216
217 { 0x11fe, 0x8016, 0xffff, 0,
218 "Comtrol RocketPort 550/16 part A",
219 DEFAULT_RCLK * 4,
220 PUC_PORT_4S, 0x10, 0, 8,
221 },
222
223 { 0x11fe, 0x8017, 0xffff, 0,
224 "Comtrol RocketPort 550/16 part B",
225 DEFAULT_RCLK * 4,
226 PUC_PORT_12S, 0x10, 0, 8,
227 },
228
229 { 0x11fe, 0x8018, 0xffff, 0,
230 "Comtrol RocketPort 550/8 part A",
231 DEFAULT_RCLK * 4,
232 PUC_PORT_4S, 0x10, 0, 8,
233 },
234
235 { 0x11fe, 0x8019, 0xffff, 0,
236 "Comtrol RocketPort 550/8 part B",
237 DEFAULT_RCLK * 4,
238 PUC_PORT_4S, 0x10, 0, 8,
239 },
240
241 /*
242 * IBM SurePOS 300 Series (481033H) serial ports
243 * Details can be found on the IBM RSS websites
244 */
245
246 { 0x1014, 0x0297, 0xffff, 0,
247 "IBM SurePOS 300 Series (481033H) serial ports",
248 DEFAULT_RCLK,
249 PUC_PORT_4S, 0x10, 4, 0
250 },
251
252 /*
253 * SIIG Boards.
254 *
255 * SIIG provides documentation for their boards at:
256 * <URL:http://www.siig.com/downloads.asp>
257 */
258
259 { 0x131f, 0x1010, 0xffff, 0,
260 "SIIG Cyber I/O PCI 16C550 (10x family)",
261 DEFAULT_RCLK,
262 PUC_PORT_1S1P, 0x18, 4, 0,
263 },
264
265 { 0x131f, 0x1011, 0xffff, 0,
266 "SIIG Cyber I/O PCI 16C650 (10x family)",
267 DEFAULT_RCLK,
268 PUC_PORT_1S1P, 0x18, 4, 0,
269 },
270
271 { 0x131f, 0x1012, 0xffff, 0,
272 "SIIG Cyber I/O PCI 16C850 (10x family)",
273 DEFAULT_RCLK,
274 PUC_PORT_1S1P, 0x18, 4, 0,
275 },
276
277 { 0x131f, 0x1021, 0xffff, 0,
278 "SIIG Cyber Parallel Dual PCI (10x family)",
279 0,
280 PUC_PORT_2P, 0x18, 8, 0,
281 },
282
283 { 0x131f, 0x1030, 0xffff, 0,
284 "SIIG Cyber Serial Dual PCI 16C550 (10x family)",
285 DEFAULT_RCLK,
286 PUC_PORT_2S, 0x18, 4, 0,
287 },
288
289 { 0x131f, 0x1031, 0xffff, 0,
290 "SIIG Cyber Serial Dual PCI 16C650 (10x family)",
291 DEFAULT_RCLK,
292 PUC_PORT_2S, 0x18, 4, 0,
293 },
294
295 { 0x131f, 0x1032, 0xffff, 0,
296 "SIIG Cyber Serial Dual PCI 16C850 (10x family)",
297 DEFAULT_RCLK,
298 PUC_PORT_2S, 0x18, 4, 0,
299 },
300
301 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */
302 "SIIG Cyber 2S1P PCI 16C550 (10x family)",
303 DEFAULT_RCLK,
304 PUC_PORT_2S1P, 0x18, 4, 0,
305 },
306
307 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */
308 "SIIG Cyber 2S1P PCI 16C650 (10x family)",
309 DEFAULT_RCLK,
310 PUC_PORT_2S1P, 0x18, 4, 0,
311 },
312
313 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */
314 "SIIG Cyber 2S1P PCI 16C850 (10x family)",
315 DEFAULT_RCLK,
316 PUC_PORT_2S1P, 0x18, 4, 0,
317 },
318
319 { 0x131f, 0x1050, 0xffff, 0,
320 "SIIG Cyber 4S PCI 16C550 (10x family)",
321 DEFAULT_RCLK,
322 PUC_PORT_4S, 0x18, 4, 0,
323 },
324
325 { 0x131f, 0x1051, 0xffff, 0,
326 "SIIG Cyber 4S PCI 16C650 (10x family)",
327 DEFAULT_RCLK,
328 PUC_PORT_4S, 0x18, 4, 0,
329 },
330
331 { 0x131f, 0x1052, 0xffff, 0,
332 "SIIG Cyber 4S PCI 16C850 (10x family)",
333 DEFAULT_RCLK,
334 PUC_PORT_4S, 0x18, 4, 0,
335 },
336
337 { 0x131f, 0x2010, 0xffff, 0,
338 "SIIG Cyber I/O PCI 16C550 (20x family)",
339 DEFAULT_RCLK,
340 PUC_PORT_1S1P, 0x10, 4, 0,
341 },
342
343 { 0x131f, 0x2011, 0xffff, 0,
344 "SIIG Cyber I/O PCI 16C650 (20x family)",
345 DEFAULT_RCLK,
346 PUC_PORT_1S1P, 0x10, 4, 0,
347 },
348
349 { 0x131f, 0x2012, 0xffff, 0,
350 "SIIG Cyber I/O PCI 16C850 (20x family)",
351 DEFAULT_RCLK,
352 PUC_PORT_1S1P, 0x10, 4, 0,
353 },
354
355 { 0x131f, 0x2021, 0xffff, 0,
356 "SIIG Cyber Parallel Dual PCI (20x family)",
357 0,
358 PUC_PORT_2P, 0x10, 8, 0,
359 },
360
361 { 0x131f, 0x2030, 0xffff, 0,
362 "SIIG Cyber Serial Dual PCI 16C550 (20x family)",
363 DEFAULT_RCLK,
364 PUC_PORT_2S, 0x10, 4, 0,
365 },
366
367 { 0x131f, 0x2031, 0xffff, 0,
368 "SIIG Cyber Serial Dual PCI 16C650 (20x family)",
369 DEFAULT_RCLK,
370 PUC_PORT_2S, 0x10, 4, 0,
371 },
372
373 { 0x131f, 0x2032, 0xffff, 0,
374 "SIIG Cyber Serial Dual PCI 16C850 (20x family)",
375 DEFAULT_RCLK,
376 PUC_PORT_2S, 0x10, 4, 0,
377 },
378
379 { 0x131f, 0x2040, 0xffff, 0,
380 "SIIG Cyber 2P1S PCI 16C550 (20x family)",
381 DEFAULT_RCLK,
382 PUC_PORT_1S2P, 0x10, -1, 0,
383 .config_function = puc_config_siig
384 },
385
386 { 0x131f, 0x2041, 0xffff, 0,
387 "SIIG Cyber 2P1S PCI 16C650 (20x family)",
388 DEFAULT_RCLK,
389 PUC_PORT_1S2P, 0x10, -1, 0,
390 .config_function = puc_config_siig
391 },
392
393 { 0x131f, 0x2042, 0xffff, 0,
394 "SIIG Cyber 2P1S PCI 16C850 (20x family)",
395 DEFAULT_RCLK,
396 PUC_PORT_1S2P, 0x10, -1, 0,
397 .config_function = puc_config_siig
398 },
399
400 { 0x131f, 0x2050, 0xffff, 0,
401 "SIIG Cyber 4S PCI 16C550 (20x family)",
402 DEFAULT_RCLK,
403 PUC_PORT_4S, 0x10, 4, 0,
404 },
405
406 { 0x131f, 0x2051, 0xffff, 0,
407 "SIIG Cyber 4S PCI 16C650 (20x family)",
408 DEFAULT_RCLK,
409 PUC_PORT_4S, 0x10, 4, 0,
410 },
411
412 { 0x131f, 0x2052, 0xffff, 0,
413 "SIIG Cyber 4S PCI 16C850 (20x family)",
414 DEFAULT_RCLK,
415 PUC_PORT_4S, 0x10, 4, 0,
416 },
417
418 { 0x131f, 0x2060, 0xffff, 0,
419 "SIIG Cyber 2S1P PCI 16C550 (20x family)",
420 DEFAULT_RCLK,
421 PUC_PORT_2S1P, 0x10, 4, 0,
422 },
423
424 { 0x131f, 0x2061, 0xffff, 0,
425 "SIIG Cyber 2S1P PCI 16C650 (20x family)",
426 DEFAULT_RCLK,
427 PUC_PORT_2S1P, 0x10, 4, 0,
428 },
429
430 { 0x131f, 0x2062, 0xffff, 0,
431 "SIIG Cyber 2S1P PCI 16C850 (20x family)",
432 DEFAULT_RCLK,
433 PUC_PORT_2S1P, 0x10, 4, 0,
434 },
435
436 { 0x131f, 0x2081, 0xffff, 0,
437 "SIIG PS8000 8S PCI 16C650 (20x family)",
438 DEFAULT_RCLK,
439 PUC_PORT_8S, 0x10, -1, -1,
440 .config_function = puc_config_siig
441 },
442
443 { 0x135c, 0x0010, 0xffff, 0,
444 "Quatech QSC-100",
445 -3, /* max 8x clock rate */
446 PUC_PORT_4S, 0x14, 0, 8,
447 .config_function = puc_config_quatech
448 },
449
450 { 0x135c, 0x0020, 0xffff, 0,
451 "Quatech DSC-100",
452 -1, /* max 2x clock rate */
453 PUC_PORT_2S, 0x14, 0, 8,
454 .config_function = puc_config_quatech
455 },
456
457 { 0x135c, 0x0030, 0xffff, 0,
458 "Quatech DSC-200/300",
459 -1, /* max 2x clock rate */
460 PUC_PORT_2S, 0x14, 0, 8,
461 .config_function = puc_config_quatech
462 },
463
464 { 0x135c, 0x0040, 0xffff, 0,
465 "Quatech QSC-200/300",
466 -3, /* max 8x clock rate */
467 PUC_PORT_4S, 0x14, 0, 8,
468 .config_function = puc_config_quatech
469 },
470
471 { 0x135c, 0x0050, 0xffff, 0,
472 "Quatech ESC-100D",
473 -3, /* max 8x clock rate */
474 PUC_PORT_8S, 0x14, 0, 8,
475 .config_function = puc_config_quatech
476 },
477
478 { 0x135c, 0x0060, 0xffff, 0,
479 "Quatech ESC-100M",
480 -3, /* max 8x clock rate */
481 PUC_PORT_8S, 0x14, 0, 8,
482 .config_function = puc_config_quatech
483 },
484
485 { 0x135c, 0x0170, 0xffff, 0,
486 "Quatech QSCLP-100",
487 -1, /* max 2x clock rate */
488 PUC_PORT_4S, 0x18, 0, 8,
489 .config_function = puc_config_quatech
490 },
491
492 { 0x135c, 0x0180, 0xffff, 0,
493 "Quatech DSCLP-100",
494 -1, /* max 3x clock rate */
495 PUC_PORT_2S, 0x18, 0, 8,
496 .config_function = puc_config_quatech
497 },
498
499 { 0x135c, 0x01b0, 0xffff, 0,
500 "Quatech DSCLP-200/300",
501 -1, /* max 2x clock rate */
502 PUC_PORT_2S, 0x18, 0, 8,
503 .config_function = puc_config_quatech
504 },
505
506 { 0x135c, 0x01e0, 0xffff, 0,
507 "Quatech ESCLP-100",
508 -3, /* max 8x clock rate */
509 PUC_PORT_8S, 0x10, 0, 8,
510 .config_function = puc_config_quatech
511 },
512
513 { 0x1393, 0x1024, 0xffff, 0,
514 "Moxa Technologies, Smartio CP-102E/PCIe",
515 DEFAULT_RCLK * 8,
516 PUC_PORT_2S, 0x14, 0, -1,
517 .config_function = puc_config_moxa
518 },
519
520 { 0x1393, 0x1025, 0xffff, 0,
521 "Moxa Technologies, Smartio CP-102EL/PCIe",
522 DEFAULT_RCLK * 8,
523 PUC_PORT_2S, 0x14, 0, -1,
524 .config_function = puc_config_moxa
525 },
526
527 { 0x1393, 0x1040, 0xffff, 0,
528 "Moxa Technologies, Smartio C104H/PCI",
529 DEFAULT_RCLK * 8,
530 PUC_PORT_4S, 0x18, 0, 8,
531 },
532
533 { 0x1393, 0x1041, 0xffff, 0,
534 "Moxa Technologies, Smartio CP-104UL/PCI",
535 DEFAULT_RCLK * 8,
536 PUC_PORT_4S, 0x18, 0, 8,
537 },
538
539 { 0x1393, 0x1042, 0xffff, 0,
540 "Moxa Technologies, Smartio CP-104JU/PCI",
541 DEFAULT_RCLK * 8,
542 PUC_PORT_4S, 0x18, 0, 8,
543 },
544
545 { 0x1393, 0x1043, 0xffff, 0,
546 "Moxa Technologies, Smartio CP-104EL/PCIe",
547 DEFAULT_RCLK * 8,
548 PUC_PORT_4S, 0x18, 0, 8,
549 },
550
551 { 0x1393, 0x1045, 0xffff, 0,
552 "Moxa Technologies, Smartio CP-104EL-A/PCIe",
553 DEFAULT_RCLK * 8,
554 PUC_PORT_4S, 0x14, 0, -1,
555 .config_function = puc_config_moxa
556 },
557
558 { 0x1393, 0x1120, 0xffff, 0,
559 "Moxa Technologies, CP-112UL",
560 DEFAULT_RCLK * 8,
561 PUC_PORT_2S, 0x18, 0, 8,
562 },
563
564 { 0x1393, 0x1141, 0xffff, 0,
565 "Moxa Technologies, Industio CP-114",
566 DEFAULT_RCLK * 8,
567 PUC_PORT_4S, 0x18, 0, 8,
568 },
569
570 { 0x1393, 0x1144, 0xffff, 0,
571 "Moxa Technologies, Smartio CP-114EL/PCIe",
572 DEFAULT_RCLK * 8,
573 PUC_PORT_4S, 0x14, 0, -1,
574 .config_function = puc_config_moxa
575 },
576
577 { 0x1393, 0x1182, 0xffff, 0,
578 "Moxa Technologies, Smartio CP-118EL-A/PCIe",
579 DEFAULT_RCLK * 8,
580 PUC_PORT_8S, 0x14, 0, -1,
581 .config_function = puc_config_moxa
582 },
583
584 { 0x1393, 0x1680, 0xffff, 0,
585 "Moxa Technologies, C168H/PCI",
586 DEFAULT_RCLK * 8,
587 PUC_PORT_8S, 0x18, 0, 8,
588 },
589
590 { 0x1393, 0x1681, 0xffff, 0,
591 "Moxa Technologies, C168U/PCI",
592 DEFAULT_RCLK * 8,
593 PUC_PORT_8S, 0x18, 0, 8,
594 },
595
596 { 0x1393, 0x1682, 0xffff, 0,
597 "Moxa Technologies, CP-168EL/PCIe",
598 DEFAULT_RCLK * 8,
599 PUC_PORT_8S, 0x18, 0, 8,
600 },
601
602 { 0x1393, 0x1683, 0xffff, 0,
603 "Moxa Technologies, Smartio CP-168EL-A/PCIe",
604 DEFAULT_RCLK * 8,
605 PUC_PORT_8S, 0x14, 0, -1,
606 .config_function = puc_config_moxa
607 },
608
609 { 0x13a8, 0x0152, 0xffff, 0,
610 "Exar XR17C/D152",
611 DEFAULT_RCLK * 8,
612 PUC_PORT_2S, 0x10, 0, -1,
613 .config_function = puc_config_exar
614 },
615
616 { 0x13a8, 0x0154, 0xffff, 0,
617 "Exar XR17C154",
618 DEFAULT_RCLK * 8,
619 PUC_PORT_4S, 0x10, 0, -1,
620 .config_function = puc_config_exar
621 },
622
623 { 0x13a8, 0x0158, 0xffff, 0,
624 "Exar XR17C158",
625 DEFAULT_RCLK * 8,
626 PUC_PORT_8S, 0x10, 0, -1,
627 .config_function = puc_config_exar
628 },
629
630 { 0x13a8, 0x0258, 0xffff, 0,
631 "Exar XR17V258IV",
632 DEFAULT_RCLK * 8,
633 PUC_PORT_8S, 0x10, 0, -1,
634 .config_function = puc_config_exar
635 },
636
637 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */
638 { 0x13a8, 0x0358, 0xffff, 0,
639 "Exar XR17V358",
640 125000000,
641 PUC_PORT_8S, 0x10, 0, -1,
642 .config_function = puc_config_exar_pcie
643 },
644
645 { 0x13fe, 0x1600, 0x1602, 0x0002,
646 "Advantech PCI-1602",
647 DEFAULT_RCLK * 8,
648 PUC_PORT_2S, 0x10, 0, 8,
649 },
650
651 { 0x1407, 0x0100, 0xffff, 0,
652 "Lava Computers Dual Serial",
653 DEFAULT_RCLK,
654 PUC_PORT_2S, 0x10, 4, 0,
655 },
656
657 { 0x1407, 0x0101, 0xffff, 0,
658 "Lava Computers Quatro A",
659 DEFAULT_RCLK,
660 PUC_PORT_2S, 0x10, 4, 0,
661 },
662
663 { 0x1407, 0x0102, 0xffff, 0,
664 "Lava Computers Quatro B",
665 DEFAULT_RCLK,
666 PUC_PORT_2S, 0x10, 4, 0,
667 },
668
669 { 0x1407, 0x0120, 0xffff, 0,
670 "Lava Computers Quattro-PCI A",
671 DEFAULT_RCLK,
672 PUC_PORT_2S, 0x10, 4, 0,
673 },
674
675 { 0x1407, 0x0121, 0xffff, 0,
676 "Lava Computers Quattro-PCI B",
677 DEFAULT_RCLK,
678 PUC_PORT_2S, 0x10, 4, 0,
679 },
680
681 { 0x1407, 0x0180, 0xffff, 0,
682 "Lava Computers Octo A",
683 DEFAULT_RCLK,
684 PUC_PORT_4S, 0x10, 4, 0,
685 },
686
687 { 0x1407, 0x0181, 0xffff, 0,
688 "Lava Computers Octo B",
689 DEFAULT_RCLK,
690 PUC_PORT_4S, 0x10, 4, 0,
691 },
692
693 { 0x1409, 0x7268, 0xffff, 0,
694 "Sunix SUN1888",
695 0,
696 PUC_PORT_2P, 0x10, 0, 8,
697 },
698
699 { 0x1409, 0x7168, 0xffff, 0,
700 NULL,
701 DEFAULT_RCLK * 8,
702 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
703 .config_function = puc_config_timedia
704 },
705
706 /*
707 * Boards with an Oxford Semiconductor chip.
708 *
709 * Oxford Semiconductor provides documentation for their chip at:
710 * <URL:http://www.plxtech.com/products/uart/>
711 *
712 * As sold by Kouwell <URL:http://www.kouwell.com/>.
713 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
714 */
715 {
716 0x1415, 0x9501, 0x10fc, 0xc070,
717 "I-O DATA RSA-PCI2/R",
718 DEFAULT_RCLK * 8,
719 PUC_PORT_2S, 0x10, 0, 8,
720 },
721
722 { 0x1415, 0x9501, 0x131f, 0x2050,
723 "SIIG Cyber 4 PCI 16550",
724 DEFAULT_RCLK * 10,
725 PUC_PORT_4S, 0x10, 0, 8,
726 },
727
728 { 0x1415, 0x9501, 0x131f, 0x2051,
729 "SIIG Cyber 4S PCI 16C650 (20x family)",
730 DEFAULT_RCLK * 10,
731 PUC_PORT_4S, 0x10, 0, 8,
732 },
733
734 { 0x1415, 0x9501, 0x131f, 0x2052,
735 "SIIG Quartet Serial 850",
736 DEFAULT_RCLK * 10,
737 PUC_PORT_4S, 0x10, 0, 8,
738 },
739
740 { 0x1415, 0x9501, 0x14db, 0x2150,
741 "Kuroutoshikou SERIAL4P-LPPCI2",
742 DEFAULT_RCLK * 10,
743 PUC_PORT_4S, 0x10, 0, 8,
744 },
745
746 { 0x1415, 0x9501, 0xffff, 0,
747 "Oxford Semiconductor OX16PCI954 UARTs",
748 0,
749 PUC_PORT_4S, 0x10, 0, 8,
750 .config_function = puc_config_oxford_pci954
751 },
752
753 { 0x1415, 0x950a, 0x131f, 0x2030,
754 "SIIG Cyber 2S PCIe",
755 DEFAULT_RCLK * 10,
756 PUC_PORT_2S, 0x10, 0, 8,
757 },
758
759 { 0x1415, 0x950a, 0x131f, 0x2032,
760 "SIIG Cyber Serial Dual PCI 16C850",
761 DEFAULT_RCLK * 10,
762 PUC_PORT_4S, 0x10, 0, 8,
763 },
764
765 { 0x1415, 0x950a, 0xffff, 0,
766 "Oxford Semiconductor OX16PCI954 UARTs",
767 DEFAULT_RCLK,
768 PUC_PORT_4S, 0x10, 0, 8,
769 },
770
771 { 0x1415, 0x9511, 0xffff, 0,
772 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)",
773 DEFAULT_RCLK,
774 PUC_PORT_4S, 0x10, 0, 8,
775 },
776
777 { 0x1415, 0x9521, 0xffff, 0,
778 "Oxford Semiconductor OX16PCI952 UARTs",
779 DEFAULT_RCLK,
780 PUC_PORT_2S, 0x10, 4, 0,
781 },
782
783 { 0x1415, 0x9538, 0xffff, 0,
784 "Oxford Semiconductor OX16PCI958 UARTs",
785 DEFAULT_RCLK,
786 PUC_PORT_8S, 0x18, 0, 8,
787 },
788
789 /*
790 * Perle boards use Oxford Semiconductor chips, but they store the
791 * Oxford Semiconductor device ID as a subvendor device ID and use
792 * their own device IDs.
793 */
794
795 { 0x155f, 0x0331, 0xffff, 0,
796 "Perle Ultraport4 Express",
797 DEFAULT_RCLK * 8,
798 PUC_PORT_4S, 0x10, 0, 8,
799 },
800
801 { 0x155f, 0xB012, 0xffff, 0,
802 "Perle Speed2 LE",
803 DEFAULT_RCLK * 8,
804 PUC_PORT_2S, 0x10, 0, 8,
805 },
806
807 { 0x155f, 0xB022, 0xffff, 0,
808 "Perle Speed2 LE",
809 DEFAULT_RCLK * 8,
810 PUC_PORT_2S, 0x10, 0, 8,
811 },
812
813 { 0x155f, 0xB004, 0xffff, 0,
814 "Perle Speed4 LE",
815 DEFAULT_RCLK * 8,
816 PUC_PORT_4S, 0x10, 0, 8,
817 },
818
819 { 0x155f, 0xB008, 0xffff, 0,
820 "Perle Speed8 LE",
821 DEFAULT_RCLK * 8,
822 PUC_PORT_8S, 0x10, 0, 8,
823 },
824
825
826 /*
827 * Oxford Semiconductor PCI Express Expresso family
828 *
829 * Found in many 'native' PCI Express serial boards such as:
830 *
831 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port)
832 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html>
833 *
834 * Lindy 51189 (4 port)
835 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189>
836 *
837 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port)
838 * <URL:http://www.startech.com>
839 */
840
841 { 0x1415, 0xc138, 0xffff, 0,
842 "Oxford Semiconductor OXPCIe952 UARTs",
843 DEFAULT_RCLK * 0x22,
844 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
845 .config_function = puc_config_oxford_pcie
846 },
847
848 { 0x1415, 0xc158, 0xffff, 0,
849 "Oxford Semiconductor OXPCIe952 UARTs",
850 DEFAULT_RCLK * 0x22,
851 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
852 .config_function = puc_config_oxford_pcie
853 },
854
855 { 0x1415, 0xc15d, 0xffff, 0,
856 "Oxford Semiconductor OXPCIe952 UARTs (function 1)",
857 DEFAULT_RCLK * 0x22,
858 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
859 .config_function = puc_config_oxford_pcie
860 },
861
862 { 0x1415, 0xc208, 0xffff, 0,
863 "Oxford Semiconductor OXPCIe954 UARTs",
864 DEFAULT_RCLK * 0x22,
865 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
866 .config_function = puc_config_oxford_pcie
867 },
868
869 { 0x1415, 0xc20d, 0xffff, 0,
870 "Oxford Semiconductor OXPCIe954 UARTs (function 1)",
871 DEFAULT_RCLK * 0x22,
872 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
873 .config_function = puc_config_oxford_pcie
874 },
875
876 { 0x1415, 0xc308, 0xffff, 0,
877 "Oxford Semiconductor OXPCIe958 UARTs",
878 DEFAULT_RCLK * 0x22,
879 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
880 .config_function = puc_config_oxford_pcie
881 },
882
883 { 0x1415, 0xc30d, 0xffff, 0,
884 "Oxford Semiconductor OXPCIe958 UARTs (function 1)",
885 DEFAULT_RCLK * 0x22,
886 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
887 .config_function = puc_config_oxford_pcie
888 },
889
890 { 0x14d2, 0x8010, 0xffff, 0,
891 "VScom PCI-100L",
892 DEFAULT_RCLK * 8,
893 PUC_PORT_1S, 0x14, 0, 0,
894 },
895
896 { 0x14d2, 0x8020, 0xffff, 0,
897 "VScom PCI-200L",
898 DEFAULT_RCLK * 8,
899 PUC_PORT_2S, 0x14, 4, 0,
900 },
901
902 { 0x14d2, 0x8028, 0xffff, 0,
903 "VScom 200Li",
904 DEFAULT_RCLK,
905 PUC_PORT_2S, 0x20, 0, 8,
906 },
907
908 /*
909 * VScom (Titan?) PCI-800L. More modern variant of the
910 * PCI-800. Uses 6 discrete 16550 UARTs, plus another
911 * two of them obviously implemented as macro cells in
912 * the ASIC. This causes the weird port access pattern
913 * below, where two of the IO port ranges each access
914 * one of the ASIC UARTs, and a block of IO addresses
915 * access the external UARTs.
916 */
917 { 0x14d2, 0x8080, 0xffff, 0,
918 "Titan VScom PCI-800L",
919 DEFAULT_RCLK * 8,
920 PUC_PORT_8S, 0x14, -1, -1,
921 .config_function = puc_config_titan
922 },
923
924 /*
925 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
926 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
927 * device ID 3 and PCI device 1 device ID 4.
928 */
929 { 0x14d2, 0xa003, 0xffff, 0,
930 "Titan PCI-800H",
931 DEFAULT_RCLK * 8,
932 PUC_PORT_4S, 0x10, 0, 8,
933 },
934
935 { 0x14d2, 0xa004, 0xffff, 0,
936 "Titan PCI-800H",
937 DEFAULT_RCLK * 8,
938 PUC_PORT_4S, 0x10, 0, 8,
939 },
940
941 { 0x14d2, 0xa005, 0xffff, 0,
942 "Titan PCI-200H",
943 DEFAULT_RCLK * 8,
944 PUC_PORT_2S, 0x10, 0, 8,
945 },
946
947 { 0x14d2, 0xe020, 0xffff, 0,
948 "Titan VScom PCI-200HV2",
949 DEFAULT_RCLK * 8,
950 PUC_PORT_2S, 0x10, 4, 0,
951 },
952
953 { 0x14d2, 0xa007, 0xffff, 0,
954 "Titan VScom PCIex-800H",
955 DEFAULT_RCLK * 8,
956 PUC_PORT_4S, 0x10, 0, 8,
957 },
958
959 { 0x14d2, 0xa008, 0xffff, 0,
960 "Titan VScom PCIex-800H",
961 DEFAULT_RCLK * 8,
962 PUC_PORT_4S, 0x10, 0, 8,
963 },
964
965 { 0x14db, 0x2130, 0xffff, 0,
966 "Avlab Technology, PCI IO 2S",
967 DEFAULT_RCLK,
968 PUC_PORT_2S, 0x10, 4, 0,
969 },
970
971 { 0x14db, 0x2150, 0xffff, 0,
972 "Avlab Low Profile PCI 4 Serial",
973 DEFAULT_RCLK,
974 PUC_PORT_4S, 0x10, 4, 0,
975 },
976
977 { 0x14db, 0x2152, 0xffff, 0,
978 "Avlab Low Profile PCI 4 Serial",
979 DEFAULT_RCLK,
980 PUC_PORT_4S, 0x10, 4, 0,
981 },
982
983 { 0x1592, 0x0781, 0xffff, 0,
984 "Syba Tech Ltd. PCI-4S2P-550-ECP",
985 DEFAULT_RCLK,
986 PUC_PORT_4S1P, 0x10, 0, -1,
987 .config_function = puc_config_syba
988 },
989
990 { 0x1fd4, 0x1999, 0xffff, 0,
991 "Sunix SER5437A",
992 DEFAULT_RCLK * 8,
993 PUC_PORT_2S, 0x10, 0, 8,
994 },
995
996 { 0x5372, 0x6873, 0xffff, 0,
997 "Sun 1040 PCI Quad Serial",
998 DEFAULT_RCLK,
999 PUC_PORT_4S, 0x10, 4, 0,
1000 },
1001
1002 { 0x6666, 0x0001, 0xffff, 0,
1003 "Decision Computer Inc, PCCOM 4-port serial",
1004 DEFAULT_RCLK,
1005 PUC_PORT_4S, 0x1c, 0, 8,
1006 },
1007
1008 { 0x6666, 0x0002, 0xffff, 0,
1009 "Decision Computer Inc, PCCOM 8-port serial",
1010 DEFAULT_RCLK,
1011 PUC_PORT_8S, 0x1c, 0, 8,
1012 },
1013
1014 { 0x6666, 0x0004, 0xffff, 0,
1015 "PCCOM dual port RS232/422/485",
1016 DEFAULT_RCLK,
1017 PUC_PORT_2S, 0x1c, 0, 8,
1018 },
1019
1020 { 0x9710, 0x9815, 0xffff, 0,
1021 "NetMos NM9815 Dual 1284 Printer port",
1022 0,
1023 PUC_PORT_2P, 0x10, 8, 0,
1024 },
1025
1026 /*
1027 * This is more specific than the generic NM9835 entry that follows, and
1028 * is placed here to _prevent_ puc from claiming this single port card.
1029 *
1030 * uart(4) will claim this device.
1031 */
1032 { 0x9710, 0x9835, 0x1000, 1,
1033 "NetMos NM9835 based 1-port serial",
1034 DEFAULT_RCLK,
1035 PUC_PORT_1S, 0x10, 4, 0,
1036 },
1037
1038 { 0x9710, 0x9835, 0x1000, 2,
1039 "NetMos NM9835 based 2-port serial",
1040 DEFAULT_RCLK,
1041 PUC_PORT_2S, 0x10, 4, 0,
1042 },
1043
1044 { 0x9710, 0x9835, 0xffff, 0,
1045 "NetMos NM9835 Dual UART and 1284 Printer port",
1046 DEFAULT_RCLK,
1047 PUC_PORT_2S1P, 0x10, 4, 0,
1048 },
1049
1050 { 0x9710, 0x9845, 0x1000, 0x0006,
1051 "NetMos NM9845 6 Port UART",
1052 DEFAULT_RCLK,
1053 PUC_PORT_6S, 0x10, 4, 0,
1054 },
1055
1056 { 0x9710, 0x9845, 0xffff, 0,
1057 "NetMos NM9845 Quad UART and 1284 Printer port",
1058 DEFAULT_RCLK,
1059 PUC_PORT_4S1P, 0x10, 4, 0,
1060 },
1061
1062 { 0x9710, 0x9865, 0xa000, 0x3002,
1063 "NetMos NM9865 Dual UART",
1064 DEFAULT_RCLK,
1065 PUC_PORT_2S, 0x10, 4, 0,
1066 },
1067
1068 { 0x9710, 0x9865, 0xa000, 0x3003,
1069 "NetMos NM9865 Triple UART",
1070 DEFAULT_RCLK,
1071 PUC_PORT_3S, 0x10, 4, 0,
1072 },
1073
1074 { 0x9710, 0x9865, 0xa000, 0x3004,
1075 "NetMos NM9865 Quad UART",
1076 DEFAULT_RCLK,
1077 PUC_PORT_4S, 0x10, 4, 0,
1078 },
1079
1080 { 0x9710, 0x9865, 0xa000, 0x3011,
1081 "NetMos NM9865 Single UART and 1284 Printer port",
1082 DEFAULT_RCLK,
1083 PUC_PORT_1S1P, 0x10, 4, 0,
1084 },
1085
1086 { 0x9710, 0x9865, 0xa000, 0x3012,
1087 "NetMos NM9865 Dual UART and 1284 Printer port",
1088 DEFAULT_RCLK,
1089 PUC_PORT_2S1P, 0x10, 4, 0,
1090 },
1091
1092 { 0x9710, 0x9865, 0xa000, 0x3020,
1093 "NetMos NM9865 Dual 1284 Printer port",
1094 DEFAULT_RCLK,
1095 PUC_PORT_2P, 0x10, 4, 0,
1096 },
1097
1098 { 0xb00c, 0x021c, 0xffff, 0,
1099 "IC Book Labs Gunboat x4 Lite",
1100 DEFAULT_RCLK,
1101 PUC_PORT_4S, 0x10, 0, 8,
1102 .config_function = puc_config_icbook
1103 },
1104
1105 { 0xb00c, 0x031c, 0xffff, 0,
1106 "IC Book Labs Gunboat x4 Pro",
1107 DEFAULT_RCLK,
1108 PUC_PORT_4S, 0x10, 0, 8,
1109 .config_function = puc_config_icbook
1110 },
1111
1112 { 0xb00c, 0x041c, 0xffff, 0,
1113 "IC Book Labs Ironclad x8 Lite",
1114 DEFAULT_RCLK,
1115 PUC_PORT_8S, 0x10, 0, 8,
1116 .config_function = puc_config_icbook
1117 },
1118
1119 { 0xb00c, 0x051c, 0xffff, 0,
1120 "IC Book Labs Ironclad x8 Pro",
1121 DEFAULT_RCLK,
1122 PUC_PORT_8S, 0x10, 0, 8,
1123 .config_function = puc_config_icbook
1124 },
1125
1126 { 0xb00c, 0x081c, 0xffff, 0,
1127 "IC Book Labs Dreadnought x16 Pro",
1128 DEFAULT_RCLK * 8,
1129 PUC_PORT_16S, 0x10, 0, 8,
1130 .config_function = puc_config_icbook
1131 },
1132
1133 { 0xb00c, 0x091c, 0xffff, 0,
1134 "IC Book Labs Dreadnought x16 Lite",
1135 DEFAULT_RCLK,
1136 PUC_PORT_16S, 0x10, 0, 8,
1137 .config_function = puc_config_icbook
1138 },
1139
1140 { 0xb00c, 0x0a1c, 0xffff, 0,
1141 "IC Book Labs Gunboat x2 Low Profile",
1142 DEFAULT_RCLK,
1143 PUC_PORT_2S, 0x10, 0, 8,
1144 },
1145
1146 { 0xb00c, 0x0b1c, 0xffff, 0,
1147 "IC Book Labs Gunboat x4 Low Profile",
1148 DEFAULT_RCLK,
1149 PUC_PORT_4S, 0x10, 0, 8,
1150 .config_function = puc_config_icbook
1151 },
1152
1153 { 0xffff, 0, 0xffff, 0, NULL, 0 }
1154};
1155
1156static int
1157puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1158 intptr_t *res)
1159{
1160 switch (cmd) {
1161 case PUC_CFG_GET_OFS:
1162 *res = 8 * (port & 1);
1163 return (0);
1164 case PUC_CFG_GET_RID:
1165 *res = 0x14 + (port >> 1) * 4;
1166 return (0);
1167 default:
1168 break;
1169 }
1170 return (ENXIO);
1171}
1172
1173static int
1174puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1175 intptr_t *res)
1176{
1177 const struct puc_cfg *cfg = sc->sc_cfg;
1178
1179 if (cmd == PUC_CFG_GET_OFS) {
1180 if (cfg->subdevice == 0x1282) /* Everest SP */
1181 port <<= 1;
1182 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */
1183 port = (port == 3) ? 4 : port;
1184 *res = port * 8 + ((port > 2) ? 0x18 : 0);
1185 return (0);
1186 }
1187 return (ENXIO);
1188}
1189
1190static int
1191puc_config_exar(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1192 intptr_t *res)
1193{
1194 if (cmd == PUC_CFG_GET_OFS) {
1195 *res = port * 0x200;
1196 return (0);
1197 }
1198 return (ENXIO);
1199}
1200
1201static int
1202puc_config_exar_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1203 intptr_t *res)
1204{
1205 if (cmd == PUC_CFG_GET_OFS) {
1206 *res = port * 0x400;
1207 return (0);
1208 }
1209 return (ENXIO);
1210}
1211
1212static int
1213puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1214 intptr_t *res)
1215{
1216 if (cmd == PUC_CFG_GET_ILR) {
1217 *res = PUC_ILR_DIGI;
1218 return (0);
1219 }
1220 return (ENXIO);
1221}
1222
1223static int
1224puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1225 intptr_t *res)
1226{
1227 if (cmd == PUC_CFG_GET_OFS) {
1228 const struct puc_cfg *cfg = sc->sc_cfg;
1229
1230 if (port == 3 && (cfg->device == 0x1045 || cfg->device == 0x1144))
1231 port = 7;
1232 *res = port * 0x200;
1233
1234 return 0;
1235 }
1236 return (ENXIO);
1237}
1238
1239static int
1240puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1241 intptr_t *res)
1242{
1243 const struct puc_cfg *cfg = sc->sc_cfg;
1244 struct puc_bar *bar;
1245 uint8_t v0, v1;
1246
1247 switch (cmd) {
1248 case PUC_CFG_SETUP:
1249 /*
1250 * Check if the scratchpad register is enabled or if the
1251 * interrupt status and options registers are active.
1252 */
1253 bar = puc_get_bar(sc, cfg->rid);
1254 if (bar == NULL)
1255 return (ENXIO);
1256 /* Set DLAB in the LCR register of UART 0. */
1257 bus_write_1(bar->b_res, 3, 0x80);
1258 /* Write 0 to the SPR register of UART 0. */
1259 bus_write_1(bar->b_res, 7, 0);
1260 /* Read back the contents of the SPR register of UART 0. */
1261 v0 = bus_read_1(bar->b_res, 7);
1262 /* Write a specific value to the SPR register of UART 0. */
1263 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock);
1264 /* Read back the contents of the SPR register of UART 0. */
1265 v1 = bus_read_1(bar->b_res, 7);
1266 /* Clear DLAB in the LCR register of UART 0. */
1267 bus_write_1(bar->b_res, 3, 0);
1268 /* Save the two values read-back from the SPR register. */
1269 sc->sc_cfg_data = (v0 << 8) | v1;
1270 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1271 /*
1272 * The SPR register echoed the two values written
1273 * by us. This means that the SPAD jumper is set.
1274 */
1275 device_printf(sc->sc_dev, "warning: extra features "
1276 "not usable -- SPAD compatibility enabled\n");
1277 return (0);
1278 }
1279 if (v0 != 0) {
1280 /*
1281 * The first value doesn't match. This can only mean
1282 * that the SPAD jumper is not set and that a non-
1283 * standard fixed clock multiplier jumper is set.
1284 */
1285 if (bootverbose)
1286 device_printf(sc->sc_dev, "fixed clock rate "
1287 "multiplier of %d\n", 1 << v0);
1288 if (v0 < -cfg->clock)
1289 device_printf(sc->sc_dev, "warning: "
1290 "suboptimal fixed clock rate multiplier "
1291 "setting\n");
1292 return (0);
1293 }
1294 /*
1295 * The first value matched, but the second didn't. We know
1296 * that the SPAD jumper is not set. We also know that the
1297 * clock rate multiplier is software controlled *and* that
1298 * we just programmed it to the maximum allowed.
1299 */
1300 if (bootverbose)
1301 device_printf(sc->sc_dev, "clock rate multiplier of "
1302 "%d selected\n", 1 << -cfg->clock);
1303 return (0);
1304 case PUC_CFG_GET_CLOCK:
1305 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1306 v1 = sc->sc_cfg_data & 0xff;
1307 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1308 /*
1309 * XXX With the SPAD jumper applied, there's no
1310 * easy way of knowing if there's also a clock
1311 * rate multiplier jumper installed. Let's hope
1312 * not...
1313 */
1314 *res = DEFAULT_RCLK;
1315 } else if (v0 == 0) {
1316 /*
1317 * No clock rate multiplier jumper installed,
1318 * so we programmed the board with the maximum
1319 * multiplier allowed as given to us in the
1320 * clock field of the config record (negated).
1321 */
1322 *res = DEFAULT_RCLK << -cfg->clock;
1323 } else
1324 *res = DEFAULT_RCLK << v0;
1325 return (0);
1326 case PUC_CFG_GET_ILR:
1327 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1328 v1 = sc->sc_cfg_data & 0xff;
1329 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock)
1330 ? PUC_ILR_NONE : PUC_ILR_QUATECH;
1331 return (0);
1332 default:
1333 break;
1334 }
1335 return (ENXIO);
1336}
1337
1338static int
1339puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1340 intptr_t *res)
1341{
1342 static int base[] = { 0x251, 0x3f0, 0 };
1343 const struct puc_cfg *cfg = sc->sc_cfg;
1344 struct puc_bar *bar;
1345 int efir, idx, ofs;
1346 uint8_t v;
1347
1348 switch (cmd) {
1349 case PUC_CFG_SETUP:
1350 bar = puc_get_bar(sc, cfg->rid);
1351 if (bar == NULL)
1352 return (ENXIO);
1353
1354 /* configure both W83877TFs */
1355 bus_write_1(bar->b_res, 0x250, 0x89);
1356 bus_write_1(bar->b_res, 0x3f0, 0x87);
1357 bus_write_1(bar->b_res, 0x3f0, 0x87);
1358 idx = 0;
1359 while (base[idx] != 0) {
1360 efir = base[idx];
1361 bus_write_1(bar->b_res, efir, 0x09);
1362 v = bus_read_1(bar->b_res, efir + 1);
1363 if ((v & 0x0f) != 0x0c)
1364 return (ENXIO);
1365 bus_write_1(bar->b_res, efir, 0x16);
1366 v = bus_read_1(bar->b_res, efir + 1);
1367 bus_write_1(bar->b_res, efir, 0x16);
1368 bus_write_1(bar->b_res, efir + 1, v | 0x04);
1369 bus_write_1(bar->b_res, efir, 0x16);
1370 bus_write_1(bar->b_res, efir + 1, v & ~0x04);
1371 ofs = base[idx] & 0x300;
1372 bus_write_1(bar->b_res, efir, 0x23);
1373 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);
1374 bus_write_1(bar->b_res, efir, 0x24);
1375 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);
1376 bus_write_1(bar->b_res, efir, 0x25);
1377 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);
1378 bus_write_1(bar->b_res, efir, 0x17);
1379 bus_write_1(bar->b_res, efir + 1, 0x03);
1380 bus_write_1(bar->b_res, efir, 0x28);
1381 bus_write_1(bar->b_res, efir + 1, 0x43);
1382 idx++;
1383 }
1384 bus_write_1(bar->b_res, 0x250, 0xaa);
1385 bus_write_1(bar->b_res, 0x3f0, 0xaa);
1386 return (0);
1387 case PUC_CFG_GET_OFS:
1388 switch (port) {
1389 case 0:
1390 *res = 0x2f8;
1391 return (0);
1392 case 1:
1393 *res = 0x2e8;
1394 return (0);
1395 case 2:
1396 *res = 0x3f8;
1397 return (0);
1398 case 3:
1399 *res = 0x3e8;
1400 return (0);
1401 case 4:
1402 *res = 0x278;
1403 return (0);
1404 }
1405 break;
1406 default:
1407 break;
1408 }
1409 return (ENXIO);
1410}
1411
1412static int
1413puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1414 intptr_t *res)
1415{
1416 const struct puc_cfg *cfg = sc->sc_cfg;
1417
1418 switch (cmd) {
1419 case PUC_CFG_GET_OFS:
1420 if (cfg->ports == PUC_PORT_8S) {
1421 *res = (port > 4) ? 8 * (port - 4) : 0;
1422 return (0);
1423 }
1424 break;
1425 case PUC_CFG_GET_RID:
1426 if (cfg->ports == PUC_PORT_8S) {
1427 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port);
1428 return (0);
1429 }
1430 if (cfg->ports == PUC_PORT_2S1P) {
1431 switch (port) {
1432 case 0: *res = 0x10; return (0);
1433 case 1: *res = 0x14; return (0);
1434 case 2: *res = 0x1c; return (0);
1435 }
1436 }
1437 break;
1438 default:
1439 break;
1440 }
1441 return (ENXIO);
1442}
1443
1444static int
1445puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1446 intptr_t *res)
1447{
1448 static const uint16_t dual[] = {
1449 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
1450 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
1451 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1452 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
1453 0xD079, 0
1454 };
1455 static const uint16_t quad[] = {
1456 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
1457 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1458 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
1459 0xB157, 0
1460 };
1461 static const uint16_t octa[] = {
1462 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1463 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
1464 };
1465 static const struct {
1466 int ports;
1467 const uint16_t *ids;
1468 } subdevs[] = {
1469 { 2, dual },
1470 { 4, quad },
1471 { 8, octa },
1472 { 0, NULL }
1473 };
1474 static char desc[64];
1475 int dev, id;
1476 uint16_t subdev;
1477
1478 switch (cmd) {
1479 case PUC_CFG_GET_CLOCK:
1480 if (port < 2)
1481 *res = DEFAULT_RCLK * 8;
1482 else
1483 *res = DEFAULT_RCLK;
1484 return (0);
1485 case PUC_CFG_GET_DESC:
1486 snprintf(desc, sizeof(desc),
1487 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data);
1488 *res = (intptr_t)desc;
1489 return (0);
1490 case PUC_CFG_GET_NPORTS:
1491 subdev = pci_get_subdevice(sc->sc_dev);
1492 dev = 0;
1493 while (subdevs[dev].ports != 0) {
1494 id = 0;
1495 while (subdevs[dev].ids[id] != 0) {
1496 if (subdev == subdevs[dev].ids[id]) {
1497 sc->sc_cfg_data = subdevs[dev].ports;
1498 *res = sc->sc_cfg_data;
1499 return (0);
1500 }
1501 id++;
1502 }
1503 dev++;
1504 }
1505 return (ENXIO);
1506 case PUC_CFG_GET_OFS:
1507 *res = (port == 1 || port == 3) ? 8 : 0;
1508 return (0);
1509 case PUC_CFG_GET_RID:
1510 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4;
1511 return (0);
1512 case PUC_CFG_GET_TYPE:
1513 *res = PUC_TYPE_SERIAL;
1514 return (0);
1515 default:
1516 break;
1517 }
1518 return (ENXIO);
1519}
1520
1521static int
1522puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd,
1523 int port __unused, intptr_t *res)
1524{
1525
1526 switch (cmd) {
1527 case PUC_CFG_GET_CLOCK:
1528 /*
1529 * OXu16PCI954 use a 14.7456 MHz clock by default while
1530 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one.
1531 */
1532 if (pci_get_revid(sc->sc_dev) == 1)
1533 *res = DEFAULT_RCLK * 8;
1534 else
1535 *res = DEFAULT_RCLK;
1536 return (0);
1537 default:
1538 break;
1539 }
1540 return (ENXIO);
1541}
1542
1543static int
1544puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1545 intptr_t *res)
1546{
1547 const struct puc_cfg *cfg = sc->sc_cfg;
1548 int idx;
1549 struct puc_bar *bar;
1550 uint8_t value;
1551
1552 switch (cmd) {
1553 case PUC_CFG_SETUP:
1554 device_printf(sc->sc_dev, "%d UARTs detected\n",
1555 sc->sc_nports);
1556
1557 /* Set UARTs to enhanced mode */
1558 bar = puc_get_bar(sc, cfg->rid);
1559 if (bar == NULL)
1560 return (ENXIO);
1561 for (idx = 0; idx < sc->sc_nports; idx++) {
1562 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) +
1563 0x92);
1564 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92,
1565 value | 0x10);
1566 }
1567 return (0);
1568 case PUC_CFG_GET_LEN:
1569 *res = 0x200;
1570 return (0);
1571 case PUC_CFG_GET_NPORTS:
1572 /*
1573 * Check if we are being called from puc_bfe_attach()
1574 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot
1575 * puc_get_bar(), so we return a value of 16. This has cosmetic
1576 * side-effects at worst; in PUC_CFG_GET_DESC,
1577 * (int)sc->sc_cfg_data will not contain the true number of
1578 * ports in PUC_CFG_GET_DESC, but we are not implementing that
1579 * call for this device family anyway.
1580 *
1581 * The check is for initialisation of sc->sc_bar[idx], which is
1582 * only done in puc_bfe_attach().
1583 */
1584 idx = 0;
1585 do {
1586 if (sc->sc_bar[idx++].b_rid != -1) {
1587 sc->sc_cfg_data = 16;
1588 *res = sc->sc_cfg_data;
1589 return (0);
1590 }
1591 } while (idx < PUC_PCI_BARS);
1592
1593 bar = puc_get_bar(sc, cfg->rid);
1594 if (bar == NULL)
1595 return (ENXIO);
1596
1597 value = bus_read_1(bar->b_res, 0x04);
1598 if (value == 0)
1599 return (ENXIO);
1600
1601 sc->sc_cfg_data = value;
1602 *res = sc->sc_cfg_data;
1603 return (0);
1604 case PUC_CFG_GET_OFS:
1605 *res = 0x1000 + (port << 9);
1606 return (0);
1607 case PUC_CFG_GET_TYPE:
1608 *res = PUC_TYPE_SERIAL;
1609 return (0);
1610 default:
1611 break;
1612 }
1613 return (ENXIO);
1614}
1615
1616static int
1617puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1618 intptr_t *res)
1619{
1620 switch (cmd) {
1621 case PUC_CFG_GET_OFS:
1622 *res = (port < 3) ? 0 : (port - 2) << 3;
1623 return (0);
1624 case PUC_CFG_GET_RID:
1625 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2);
1626 return (0);
1627 default:
1628 break;
1629 }
1630 return (ENXIO);
1631}