| ppcreg.h (40784) | ppcreg.h (42475) |
|---|---|
| 1/*- 2 * Copyright (c) 1997 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 1997 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $Id: ppcreg.h,v 1.4 1998/09/13 18:26:44 nsouch Exp $ | 26 * $Id: ppcreg.h,v 1.5 1998/10/31 11:37:09 nsouch Exp $ |
| 27 * 28 */ 29#ifndef __PPCREG_H 30#define __PPCREG_H 31 32/* 33 * Parallel Port Chipset type. 34 */ --- 15 unchanged lines hidden (view full) --- 50struct ppc_data { 51 52 int ppc_unit; 53 int ppc_type; 54 55 int ppc_mode; /* chipset current mode */ 56 int ppc_avm; /* chipset available modes */ 57 | 27 * 28 */ 29#ifndef __PPCREG_H 30#define __PPCREG_H 31 32/* 33 * Parallel Port Chipset type. 34 */ --- 15 unchanged lines hidden (view full) --- 50struct ppc_data { 51 52 int ppc_unit; 53 int ppc_type; 54 55 int ppc_mode; /* chipset current mode */ 56 int ppc_avm; /* chipset available modes */ 57 |
| 58#define PPC_IRQ_NONE 0x0 59#define PPC_IRQ_nACK 0x1 60#define PPC_IRQ_DMA 0x2 61#define PPC_IRQ_FIFO 0x4 62#define PPC_IRQ_nFAULT 0x8 63 int ppc_irqstat; /* remind irq settings */ 64 65#define PPC_DMA_INIT 0x01 66#define PPC_DMA_STARTED 0x02 67#define PPC_DMA_COMPLETE 0x03 68#define PPC_DMA_INTERRUPTED 0x04 69#define PPC_DMA_ERROR 0x05 70 int ppc_dmastat; /* dma state */ 71 int ppc_dmachan; /* dma channel */ 72 int ppc_dmaflags; /* dma transfer flags */ 73 caddr_t ppc_dmaddr; /* buffer address */ 74 u_int ppc_dmacnt; /* count of bytes sent with dma */ 75 76#define PPC_PWORD_MASK 0x30 77#define PPC_PWORD_16 0x00 78#define PPC_PWORD_8 0x10 79#define PPC_PWORD_32 0x20 80 char ppc_pword; /* PWord size */ 81 short ppc_fifo; /* FIFO threshold */ 82 83 short ppc_wthr; /* writeIntrThresold */ 84 short ppc_rthr; /* readIntrThresold */ 85 |
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| 58#define ppc_base ppc_link.base 59#define ppc_epp ppc_link.epp_protocol 60#define ppc_irq ppc_link.id_irq 61#define ppc_subm ppc_link.submicroseq 62#define ppc_ptr ppc_link.ptr 63#define ppc_accum ppc_link.accum 64 65 unsigned char ppc_flags; 66 67 struct ppb_link ppc_link; 68}; 69 70/* 71 * Parallel Port Chipset registers. 72 */ 73#define PPC_SPP_DTR 0 /* SPP data register */ | 86#define ppc_base ppc_link.base 87#define ppc_epp ppc_link.epp_protocol 88#define ppc_irq ppc_link.id_irq 89#define ppc_subm ppc_link.submicroseq 90#define ppc_ptr ppc_link.ptr 91#define ppc_accum ppc_link.accum 92 93 unsigned char ppc_flags; 94 95 struct ppb_link ppc_link; 96}; 97 98/* 99 * Parallel Port Chipset registers. 100 */ 101#define PPC_SPP_DTR 0 /* SPP data register */ |
| 102#define PPC_ECP_A_FIFO 0 /* ECP Address fifo register */ |
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| 74#define PPC_SPP_STR 1 /* SPP status register */ 75#define PPC_SPP_CTR 2 /* SPP control register */ 76#define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */ | 103#define PPC_SPP_STR 1 /* SPP status register */ 104#define PPC_SPP_CTR 2 /* SPP control register */ 105#define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */ |
| 77#define PPC_ECP_FIFO 0x400 /* ECP fifo register */ | 106#define PPC_ECP_D_FIFO 0x400 /* ECP Data fifo register */ 107#define PPC_ECP_CNFGA 0x400 /* Configuration register A */ 108#define PPC_ECP_CNFGB 0x401 /* Configuration register B */ |
| 78#define PPC_ECP_ECR 0x402 /* ECP extended control register */ 79 | 109#define PPC_ECP_ECR 0x402 /* ECP extended control register */ 110 |
| 111#define PPC_FIFO_EMPTY 0x1 /* ecr register - bit 0 */ 112#define PPC_FIFO_FULL 0x2 /* ecr register - bit 1 */ 113#define PPC_SERVICE_INTR 0x4 /* ecr register - bit 2 */ 114#define PPC_ENABLE_DMA 0x8 /* ecr register - bit 3 */ 115#define PPC_nFAULT_INTR 0x10 /* ecr register - bit 4 */ 116#define PPC_ECR_STD 0x0 117#define PPC_ECR_PS2 0x20 118#define PPC_ECR_FIFO 0x40 119#define PPC_ECR_ECP 0x60 120#define PPC_ECR_EPP 0x80 121 122#define PPC_DISABLE_INTR (PPC_SERVICE_INTR | PPC_nFAULT_INTR) 123#define PPC_ECR_RESET (PPC_ECR_PS2 | PPC_DISABLE_INTR) 124 |
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| 80#define r_dtr(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_DTR)) 81#define r_str(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_STR)) 82#define r_ctr(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_CTR)) 83#define r_epp(ppc) ((char)inb((ppc)->ppc_base + PPC_EPP_DATA)) | 125#define r_dtr(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_DTR)) 126#define r_str(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_STR)) 127#define r_ctr(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_CTR)) 128#define r_epp(ppc) ((char)inb((ppc)->ppc_base + PPC_EPP_DATA)) |
| 129#define r_cnfgA(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_CNFGA)) 130#define r_cnfgB(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_CNFGB)) |
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| 84#define r_ecr(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_ECR)) | 131#define r_ecr(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_ECR)) |
| 85#define r_fifo(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_FIFO)) | 132#define r_fifo(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_D_FIFO)) |
| 86 87#define w_dtr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_DTR, byte) 88#define w_str(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_STR, byte) 89#define w_ctr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_CTR, byte) 90#define w_epp(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_DATA, byte) 91#define w_ecr(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_ECR, byte) | 133 134#define w_dtr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_DTR, byte) 135#define w_str(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_STR, byte) 136#define w_ctr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_CTR, byte) 137#define w_epp(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_DATA, byte) 138#define w_ecr(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_ECR, byte) |
| 92#define w_fifo(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_FIFO, byte) | 139#define w_fifo(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_D_FIFO, byte) |
| 93 94/* 95 * Register defines for the PC873xx parts 96 */ 97 98#define PC873_FER 0x00 99#define PC873_PPENABLE (1<<0) 100#define PC873_FAR 0x01 --- 75 unchanged lines hidden --- | 140 141/* 142 * Register defines for the PC873xx parts 143 */ 144 145#define PC873_FER 0x00 146#define PC873_PPENABLE (1<<0) 147#define PC873_FAR 0x01 --- 75 unchanged lines hidden --- |