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1/*******************************************************************************
2*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
3*
4*Redistribution and use in source and binary forms, with or without modification, are permitted provided
5*that the following conditions are met:
6*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
7*following disclaimer.
8*2. Redistributions in binary form must reproduce the above copyright notice,
9*this list of conditions and the following disclaimer in the documentation and/or other materials provided
10*with the distribution.
11*
12*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
13*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
14*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
15*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
17*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
19*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
20*
1/*******************************************************************************
2*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
3*
4*Redistribution and use in source and binary forms, with or without modification, are permitted provided
5*that the following conditions are met:
6*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
7*following disclaimer.
8*2. Redistributions in binary form must reproduce the above copyright notice,
9*this list of conditions and the following disclaimer in the documentation and/or other materials provided
10*with the distribution.
11*
12*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
13*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
14*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
15*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
17*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
19*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
20*
21* $FreeBSD: head/sys/dev/pms/freebsd/driver/common/lxcommon.h 285242 2015-07-07 13:17:02Z achim $
21* $FreeBSD: head/sys/dev/pms/freebsd/driver/common/lxcommon.h 299081 2016-05-04 17:52:53Z pfg $
22*
23*******************************************************************************/
24/******************************************************************************
25
26Module Name:
27 lxcommon.h
28Abstract:
29 TISA Initiator/target driver module constant define header file
30Environment:
31 Kernel or loadable module
32
33******************************************************************************/
34
35
36#include <dev/pms/RefTisa/tisa/api/titypes.h>
37
38
39#define LINUX_DMA_MEM_MAX 0x1ffe0 /* 128k - 32, real 128k - 24 */
40#define DEK_MAX_TABLE_ITEMS DEK_MAX_TABLE_ENTRIES // from tisa/api/titypes.h
41
42/*
43** IP address length based on character.
44*/
45#ifdef AGTIAPI_IP6_SUPPORT
46# define IP_ADDR_CHAR_LEN 64
47#else
48# define IP_ADDR_CHAR_LEN 16
49#endif
50
51#define MSEC_PER_TICK (1000/hz) /* milisecond per tick */
52#define USEC_PER_TICK (1000000/hz) /* microsecond per tick */
53#define AGTIAPI_64BIT_ALIGN 8 /* 64 bit environment alignment */
54
55/*
56** Max device supported
57*/
58#define AGTIAPI_MAX_CARDS 4 /* card supported up to system limit */
59#define AGTIAPI_TOO_MANY_CARDS -1 /* beyond defined max support */
60#define AGTIAPI_MAX_PORTALS 16 /* max portal per card */
61/* max device per portal */
62
63/*
64** Adjustable Parameter Options
65*/
66#define AGTIAPI_OPTION_ON 1 /* adjustable parameter available */
67#define AGTIAPI_KEY_MAX 64 /* max number of keys */
68#define AGTIAPI_STRING_MAX 512 /* max length for string */
69#define AGTIAPI_PARAM_MAX 256 /* max number of parameters */
70#ifdef TARGET_DRIVER
71#define AGTIAPI_DMA_MEM_LIST_MAX 4096 /* max number of DMA memory list */
72#define AGTIAPI_CACHE_MEM_LIST_MAX 24 /* max number of CACHE memory list */
73#else /* INITIATOR_DRIVER */
74#define AGTIAPI_DMA_MEM_LIST_MAX 1024 /* max number of DMA memory list */
75#define AGTIAPI_CACHE_MEM_LIST_MAX 1024 /* max number of CACHE memory list */
76#endif
77#ifndef AGTIAPI_DYNAMIC_MAX
78#define AGTIAPI_DYNAMIC_MAX 4096 /* max unreleased dynamic memory */
79#endif
80#define AGTIAPI_LOOP_MAX 4 /* max loop for init process */
81
82#define AGTIAPI_MAX_NAME 70 // Max string name length
83#define AGTIAPI_MIN_NAME 10 // minimum space for SAS name string
84#define AGTIAPI_MAX_ID 8 // Max string id length
85
86/*
87** Card-port status definitions
88*/
89#define AGTIAPI_INIT_TIME 0x00000001
90#define AGTIAPI_SOFT_RESET 0x00000002
91#define AGTIAPI_HAD_RESET 0x00000004 // ###
92#define AGTIAPI_DISC_DONE 0x00000008
93#define AGTIAPI_INSTALLED 0x00000010
94#define AGTIAPI_RESET 0x00000020
95#define AGTIAPI_FLAG_UP 0x00000040
96#define AGTIAPI_CB_DONE 0x00000080
97#define AGTIAPI_DISC_COMPLETE 0x00000100
98#define AGTIAPI_IOREGION_REQUESTED 0x00000200
99#define AGTIAPI_IRQ_REQUESTED 0x00000400
100#define AGTIAPI_SCSI_REGISTERED 0x00000800
101#define AGTIAPI_NAME_SERVER_UP 0x00001000
102#define AGTIAPI_PORT_INITIALIZED 0x00002000
103#define AGTIAPI_PORT_LINK_UP 0x00004000
104#define AGTIAPI_LGN_LINK_UP 0x00008000
105#define AGTIAPI_PORT_PANIC 0x00010000
106#define AGTIAPI_RESET_SUCCESS 0x00020000
107#define AGTIAPI_PORT_START 0x00040000
108#define AGTIAPI_PORT_STOPPED 0x00080000
109#define AGTIAPI_PORT_SHUTDOWN 0x00100000
110#define AGTIAPI_IN_USE 0x00200000
111#define AGTIAPI_SYS_INTR_ON 0x00400000
112#define AGTIAPI_PORT_DISC_READY 0x00800000
113#define AGTIAPI_SIG_DOWN 0x01000000
114#define AGTIAPI_SIG_UP 0x02000000
115#define AGTIAPI_TASK 0x04000000
116#define AGTIAPI_INITIATOR 0x08000000
117#define AGTIAPI_TARGET 0x10000000
118#define AGTIAPI_TIMER_ON 0x20000000
119#define AGTIAPI_SHUT_DOWN 0x40000000
120/* reserved for ccb flag TASK_MANAGEMENT
121#define AGTIAPI_RESERVED 0x80000000
122*/
123#define AGTIAPI_RESET_ALL 0xFFFFFFFF
124
125/*
126** PCI defines
127*/
128#ifndef PCI_VENDOR_ID_HP
129#define PCI_VENDOR_ID_HP 0x103c
130#endif
131
132#ifndef PCI_VENDOR_ID_PMC_SIERRA
133#define PCI_VENDOR_ID_PMC_SIERRA 0x11F8
134#endif
135
136#ifndef PCI_VENDOR_ID_AGILENT
137#define PCI_VENDOR_ID_AGILENT 0x15bc
138#endif
139
140#ifndef PCI_VENDOR_ID_CYCLONE
141#define PCI_VENDOR_ID_CYCLONE 0x113C
142#endif
143
144#ifndef PCI_VENDOR_ID_SPCV_FPGA
145#define PCI_VENDOR_ID_SPCV_FPGA 0x1855
146#endif
147
148#ifndef PCI_VENDOR_ID_HIALEAH
149#define PCI_VENDOR_ID_HIALEAH 0x9005
150#endif
151
152#define PCI_DEVICE_ID_HP_TS 0x102a
153#define PCI_DEVICE_ID_HP_TL 0x1028
154#define PCI_DEVICE_ID_HP_XL2 0x1029
155#define PCI_DEVICE_ID_AG_DX2 0x0100
156#define PCI_DEVICE_ID_AG_DX2PLUS 0x0101
157#define PCI_DEVICE_ID_AG_QX2 0x0102
158#define PCI_DEVICE_ID_AG_QX4 0x0103
159#define PCI_DEVICE_ID_AG_QE4 0x1200
160#define PCI_DEVICE_ID_AG_DE4 0x1203
161#define PCI_DEVICE_ID_AG_XL10 0x0104
162#define PCI_DEVICE_ID_AG_DX4PLUS 0x0105
163#define PCI_DEVICE_ID_AG_DIXL 0x0110
164#define PCI_DEVICE_ID_AG_IDX1 0x050A
165#define PCI_DEVICE_ID_PMC_SIERRA_SPC 0x8001
166#define PCI_DEVICE_ID_PMC_SIERRA_SPCV 0x8008
167#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE 0x8009
168#define PCI_DEVICE_ID_PMC_SIERRA_SPCVPLUS 0x8018
169#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE_16 0x8019
170#define PCI_DEVICE_ID_SPCV_FPGA 0xabcd
171#define PCI_DEVICE_ID_PMC_SIERRA_SPCV12G 0x8070
172#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G 0x8071
173#define PCI_DEVICE_ID_PMC_SIERRA_SPCV12G_16 0x8072
174#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G_16 0x8073
175#define PCI_DEVICE_ID_HIALEAH_HBA_SPC 0x8081
176#define PCI_DEVICE_ID_HIALEAH_RAID_SPC 0x8091
177#define PCI_DEVICE_ID_HIALEAH_HBA_SPCV 0x8088
178#define PCI_DEVICE_ID_HIALEAH_RAID_SPCV 0x8098
179#define PCI_DEVICE_ID_HIALEAH_HBA_SPCVE 0x8089
180#define PCI_DEVICE_ID_HIALEAH_RAID_SPCVE 0x8099
181#define PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCV 0x8074
182#define PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCVE 0x8075
183#define PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV 0x8076
184#define PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCVE 0x8077
185#define PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV_SATA 0x8006
186
187
188#define PCI_SUB_VENDOR_ID_HP PCI_VENDOR_ID_HP
189#define PCI_SUB_VENDOR_ID_AG PCI_VENDOR_ID_AGILENT
190#define PCI_SUB_VENDOR_ID_MASK 0xFFFF
191#define PCI_SUB_SYSTEM_ID_AG 0x0001
192#define PCI_BASE_MEM_MASK (~0x0F)
193
194#define PCI_DEVICE_ID_CYCLONE 0xB555
195#define PCI_ENABLE_VALUE 0x0157
196#ifdef PMC_SPC
197#define PCI_NUMBER_BARS 6
198#endif
199#define IOCTL_MN_GET_CARD_INFO 0x11
200/*
201** Constant defines
202*/
203#define _08B 8
204#define _16B 16
205#define _24B 24
206#define _32B 32
207#define _64B 64
208#define _128B 128
209#define _256B 256
210#define _512B 512
211
212#define _1K 1024
213#define _2K 2048
214#define _4K 4096
215#define _128K (128*(_1K))
216
217// Card property related info.
218typedef struct _ag_card_id {
219 U16 vendorId; /* pci vendor id */
220 U16 deviceId; /* pci device id */
221 S32 cardNameIndex; /* structure index */
222 U16 membar; /* pci memory bar offset */
223 U16 iobar1; /* pci io bar 1 offset */
224 U16 iobar2; /* pci io bar 2 offest */
225 U16 reg; /* pci memory bar number */
226} ag_card_id_t;
227
228
229#define PCI_BASE_ADDRESS_0 PCIR_BAR(0)
230#define PCI_BASE_ADDRESS_1 PCIR_BAR(1)
231#define PCI_BASE_ADDRESS_2 PCIR_BAR(2)
232#define PCI_BASE_ADDRESS_3 PCIR_BAR(3)
233#define PCI_BASE_ADDRESS_4 PCIR_BAR(4)
234
235
236ag_card_id_t ag_card_type[] = {
237#ifdef AGTIAPI_ISCSI
238 {PCI_VENDOR_ID_AGILENTj, PCI_DEVICE_ID_AG_DIXL, 1,
239 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_0, 0},
240 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_IDX1, 2,
241 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_0, 0},
242#endif
243#ifdef AGTIAPI_FC
244 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_TS, 3,
245 PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, 3},
246 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_TL, 4,
247 PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, 3},
248 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_XL2, 5,
249 PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, 3},
250 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DX2, 6,
251 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
252 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DX2PLUS, 7,
253 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
254 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DX4PLUS, 8,
255 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
256 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_QX2, 9,
257 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
258 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_QX4, 10,
259 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
260 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DE4, 11,
261 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
262 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_QE4, 12,
263 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
264 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_XL10, 13,
265 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
266#endif
267#ifdef AGTIAPI_SA
268#ifdef PMC_SPC
269 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPC, 14,
270 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
271 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCV, 15,
272 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
273 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE, 16,
274 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
275 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVPLUS, 17,
276 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
277 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE_16, 18,
278 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
279 {PCI_VENDOR_ID_SPCV_FPGA, PCI_DEVICE_ID_SPCV_FPGA, 19,
280 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
281 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCV12G, 20,
282 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
283 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G, 21,
284 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
285 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCV12G_16, 22,
286 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
287 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G_16, 23,
288 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
289 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_HBA_SPC, 24,
290 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
291 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_RAID_SPC, 25,
292 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
293 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_HBA_SPCV, 26,
294 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
295 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_RAID_SPCV, 27,
296 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
297 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_HBA_SPCVE, 28,
298 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
299 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_RAID_SPCVE, 29,
300 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
301 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCV, 30,
302 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
303 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCVE, 31,
304 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
305 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV, 32,
306 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
307 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCVE, 33,
308 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
309 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV_SATA, 34,
310 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
311
312#endif
313#endif //AGTIAPI_SA
314};
315
316static const char *ag_card_names[] = {
317 "Unknown",
318 "iSCSI DiXL Card",
319 "iSCSI iDX1 Card",
320 "Tachyon TS Fibre Channel Card",
321 "Tachyon TL Fibre Channel Card",
322 "Tachyon XL2 Fibre Channel Card",
323 "Tachyon DX2 Fibre Channel Card",
324 "Tachyon DX2+ Fibre Channel Card",
325 "Tachyon DX4+ Fibre Channel Card",
326 "Tachyon QX2 Fibre Channel Card",
327 "Tachyon QX4 Fibre Channel Card",
328 "Tachyon DE4 Fibre Channel Card",
329 "Tachyon QE4 Fibre Channel Card",
330 "Tachyon XL10 Fibre Channel Card",
331#ifdef AGTIAPI_SA
332#ifdef PMC_SPC
333 "PMC Sierra SPC SAS-SATA Card",
334 "PMC Sierra SPC-V SAS-SATA Card",
335 "PMC Sierra SPC-VE SAS-SATA Card",
336 "PMC Sierra SPC-V 16 Port SAS-SATA Card",
337 "PMC Sierra SPC-VE 16 Port SAS-SATA Card",
338 "PMC Sierra FPGA",
339 "PMC Sierra SPC-V SAS-SATA Card 12Gig",
340 "PMC Sierra SPC-VE SAS-SATA Card 12Gig",
341 "PMC Sierra SPC-V 16 Port SAS-SATA Card 12Gig",
342 "PMC Sierra SPC-VE 16 Port SAS-SATA Card 12Gig",
343 "Adaptec Hialeah 4/8 Port SAS-SATA HBA Card 6Gig",
344 "Adaptec Hialeah 4/8 Port SAS-SATA RAID Card 6Gig",
345 "Adaptec Hialeah 8/16 Port SAS-SATA HBA Card 6Gig",
346 "Adaptec Hialeah 8/16 Port SAS-SATA RAID Card 6Gig",
347 "Adaptec Hialeah 8/16 Port SAS-SATA HBA Encryption Card 6Gig",
348 "Adaptec Hialeah 8/16 Port SAS-SATA RAID Encryption Card 6Gig",
349 "Adaptec Delray 8 Port SAS-SATA HBA Card 12Gig",
350 "Adaptec Delray 8 Port SAS-SATA HBA Encryption Card 12Gig",
351 "Adaptec Delray 16 Port SAS-SATA HBA Card 12Gig",
352 "Adaptec Delray 16 Port SAS-SATA HBA Encryption Card 12Gig",
353 "Adaptec SATA Adapter",
354
355#endif
356#endif
357};
358
359
360
361/*
362** Resource Info Structure
363*/
364typedef struct _ag_resource_info {
365 tiLoLevelResource_t tiLoLevelResource; // Low level resource required
366 tiInitiatorResource_t tiInitiatorResource; // Initiator resource required
367 tiTargetResource_t tiTargetResource; // Target resource required
368 tiTdSharedMem_t tiSharedMem; // Shared memory by ti and td
369} ag_resource_info_t;
370
371
372// DMA memory address pair
373typedef struct _ag_dma_addr {
374 void *dmaVirtAddr;
375 vm_paddr_t dmaPhysAddr;
376 U32 memSize;
377 bit32 type;
378 bus_addr_t nocache_busaddr;
379 void *nocache_mem;
380} ag_dma_addr_t;
381
382
383typedef struct _CardInfo
384{
385 U32 pciIOAddrLow; /* PCI IOBASE lower */
386 U32 pciIOAddrUp; /* PCI IOBASE Upper */
387 U32_64 pciMemBase; /* PCI MEMBASE, physical */
388 U32_64 pciMemBaseSpc[PCI_NUMBER_BARS]; // PCI MEMBASE, physical
389 U16 deviceId; // PCI device id
390 U16 vendorId; // PCI Vendor id
391 U32 busNum;
392 U32 deviceNum;
393}CardInfo_t;
394
395// Card info. for all cards and drivers
396typedef struct _ag_card_info {
397 struct mtx pmIOLock;
398 device_t pPCIDev; // PCI device pointer
399 void *pCard; // pointer to per card data structure
400 S32 cardNameIndex;
401 U32 cardID; // card system ID
402 U32 cardIdIndex;
403 U32 pciIOAddrLow; // PCI IOBASE lower
404 U32 pciIOAddrUp; // PCI IOBASE Upper
405 U32_64 pciMemBase; // PCI MEMBASE, physical
406 caddr_t pciMemVirtAddr; // PCI MEMBASE, virtual ptr
407 U32 pciMemSize; // PCI MEMBASE memory size
408#ifdef AGTIAPI_SA
409#ifdef FPGA_CARD
410 U32_64 pciMemBase0; // PCI MEMBASE, physical
411 caddr_t pciMemVirtAddr0; // PCI MEMBASE, virtual ptr
412 U32 pciMemSize0; // PCI MEMBASE memory size
413#endif
414#ifdef PMC_SPC
415 struct resource *pciMemBaseRscSpc[PCI_NUMBER_BARS];
416 int pciMemBaseRIDSpc[PCI_NUMBER_BARS];
417 U32_64 pciMemBaseSpc[PCI_NUMBER_BARS]; // PCI MEMBASE, physical
418 caddr_t pciMemVirtAddrSpc[PCI_NUMBER_BARS];//PCI MEMBASE, virt ptr
419 U32 pciMemSizeSpc[PCI_NUMBER_BARS]; // PCI MEMBASE memory size
420#endif
421#endif
422 U16 memBar;
423 U16 memReg;
424 U32 cacheIndex;
425 U32 dmaIndex;
426 ag_dma_addr_t tiDmaMem[AGTIAPI_DMA_MEM_LIST_MAX]; // dma addr list
427
428 // all (free and allocated) mem slots
429 ag_dma_addr_t dynamicMem[AGTIAPI_DYNAMIC_MAX];
430
431 // ptr to free mem slots
432 ag_dma_addr_t *freeDynamicMem[AGTIAPI_DYNAMIC_MAX];
433
434 U16 topOfFreeDynamicMem; // idx to the first free slot ptr
435
436 void *tiCachedMem[AGTIAPI_CACHE_MEM_LIST_MAX];// cached mem list
437 ag_resource_info_t tiRscInfo; /* low level resource requirement */
438 U08 WWN[AGTIAPI_MAX_NAME]; /* WWN for this card */
439 U08 WWNLen;
440
441// #define MAX_MSIX_NUM_VECTOR 64 ##
442#define MAX_MSIX_NUM_VECTOR 16 // 1 then 16 just for testing;
443#define MAX_MSIX_NUM_DPC 64 // 16
444#define MAX_MSIX_NUM_ISR 64 // 16
445#ifdef SPC_MSIX_INTR
446
447 // ## use as a map instead of presirq
448 struct resource *msix_entries[MAX_MSIX_NUM_VECTOR];
449#endif
450 U32 maxInterruptVectors;
451} ag_card_info_t;
452
453/*
454** Optional Adjustable Parameters Structures.
22*
23*******************************************************************************/
24/******************************************************************************
25
26Module Name:
27 lxcommon.h
28Abstract:
29 TISA Initiator/target driver module constant define header file
30Environment:
31 Kernel or loadable module
32
33******************************************************************************/
34
35
36#include <dev/pms/RefTisa/tisa/api/titypes.h>
37
38
39#define LINUX_DMA_MEM_MAX 0x1ffe0 /* 128k - 32, real 128k - 24 */
40#define DEK_MAX_TABLE_ITEMS DEK_MAX_TABLE_ENTRIES // from tisa/api/titypes.h
41
42/*
43** IP address length based on character.
44*/
45#ifdef AGTIAPI_IP6_SUPPORT
46# define IP_ADDR_CHAR_LEN 64
47#else
48# define IP_ADDR_CHAR_LEN 16
49#endif
50
51#define MSEC_PER_TICK (1000/hz) /* milisecond per tick */
52#define USEC_PER_TICK (1000000/hz) /* microsecond per tick */
53#define AGTIAPI_64BIT_ALIGN 8 /* 64 bit environment alignment */
54
55/*
56** Max device supported
57*/
58#define AGTIAPI_MAX_CARDS 4 /* card supported up to system limit */
59#define AGTIAPI_TOO_MANY_CARDS -1 /* beyond defined max support */
60#define AGTIAPI_MAX_PORTALS 16 /* max portal per card */
61/* max device per portal */
62
63/*
64** Adjustable Parameter Options
65*/
66#define AGTIAPI_OPTION_ON 1 /* adjustable parameter available */
67#define AGTIAPI_KEY_MAX 64 /* max number of keys */
68#define AGTIAPI_STRING_MAX 512 /* max length for string */
69#define AGTIAPI_PARAM_MAX 256 /* max number of parameters */
70#ifdef TARGET_DRIVER
71#define AGTIAPI_DMA_MEM_LIST_MAX 4096 /* max number of DMA memory list */
72#define AGTIAPI_CACHE_MEM_LIST_MAX 24 /* max number of CACHE memory list */
73#else /* INITIATOR_DRIVER */
74#define AGTIAPI_DMA_MEM_LIST_MAX 1024 /* max number of DMA memory list */
75#define AGTIAPI_CACHE_MEM_LIST_MAX 1024 /* max number of CACHE memory list */
76#endif
77#ifndef AGTIAPI_DYNAMIC_MAX
78#define AGTIAPI_DYNAMIC_MAX 4096 /* max unreleased dynamic memory */
79#endif
80#define AGTIAPI_LOOP_MAX 4 /* max loop for init process */
81
82#define AGTIAPI_MAX_NAME 70 // Max string name length
83#define AGTIAPI_MIN_NAME 10 // minimum space for SAS name string
84#define AGTIAPI_MAX_ID 8 // Max string id length
85
86/*
87** Card-port status definitions
88*/
89#define AGTIAPI_INIT_TIME 0x00000001
90#define AGTIAPI_SOFT_RESET 0x00000002
91#define AGTIAPI_HAD_RESET 0x00000004 // ###
92#define AGTIAPI_DISC_DONE 0x00000008
93#define AGTIAPI_INSTALLED 0x00000010
94#define AGTIAPI_RESET 0x00000020
95#define AGTIAPI_FLAG_UP 0x00000040
96#define AGTIAPI_CB_DONE 0x00000080
97#define AGTIAPI_DISC_COMPLETE 0x00000100
98#define AGTIAPI_IOREGION_REQUESTED 0x00000200
99#define AGTIAPI_IRQ_REQUESTED 0x00000400
100#define AGTIAPI_SCSI_REGISTERED 0x00000800
101#define AGTIAPI_NAME_SERVER_UP 0x00001000
102#define AGTIAPI_PORT_INITIALIZED 0x00002000
103#define AGTIAPI_PORT_LINK_UP 0x00004000
104#define AGTIAPI_LGN_LINK_UP 0x00008000
105#define AGTIAPI_PORT_PANIC 0x00010000
106#define AGTIAPI_RESET_SUCCESS 0x00020000
107#define AGTIAPI_PORT_START 0x00040000
108#define AGTIAPI_PORT_STOPPED 0x00080000
109#define AGTIAPI_PORT_SHUTDOWN 0x00100000
110#define AGTIAPI_IN_USE 0x00200000
111#define AGTIAPI_SYS_INTR_ON 0x00400000
112#define AGTIAPI_PORT_DISC_READY 0x00800000
113#define AGTIAPI_SIG_DOWN 0x01000000
114#define AGTIAPI_SIG_UP 0x02000000
115#define AGTIAPI_TASK 0x04000000
116#define AGTIAPI_INITIATOR 0x08000000
117#define AGTIAPI_TARGET 0x10000000
118#define AGTIAPI_TIMER_ON 0x20000000
119#define AGTIAPI_SHUT_DOWN 0x40000000
120/* reserved for ccb flag TASK_MANAGEMENT
121#define AGTIAPI_RESERVED 0x80000000
122*/
123#define AGTIAPI_RESET_ALL 0xFFFFFFFF
124
125/*
126** PCI defines
127*/
128#ifndef PCI_VENDOR_ID_HP
129#define PCI_VENDOR_ID_HP 0x103c
130#endif
131
132#ifndef PCI_VENDOR_ID_PMC_SIERRA
133#define PCI_VENDOR_ID_PMC_SIERRA 0x11F8
134#endif
135
136#ifndef PCI_VENDOR_ID_AGILENT
137#define PCI_VENDOR_ID_AGILENT 0x15bc
138#endif
139
140#ifndef PCI_VENDOR_ID_CYCLONE
141#define PCI_VENDOR_ID_CYCLONE 0x113C
142#endif
143
144#ifndef PCI_VENDOR_ID_SPCV_FPGA
145#define PCI_VENDOR_ID_SPCV_FPGA 0x1855
146#endif
147
148#ifndef PCI_VENDOR_ID_HIALEAH
149#define PCI_VENDOR_ID_HIALEAH 0x9005
150#endif
151
152#define PCI_DEVICE_ID_HP_TS 0x102a
153#define PCI_DEVICE_ID_HP_TL 0x1028
154#define PCI_DEVICE_ID_HP_XL2 0x1029
155#define PCI_DEVICE_ID_AG_DX2 0x0100
156#define PCI_DEVICE_ID_AG_DX2PLUS 0x0101
157#define PCI_DEVICE_ID_AG_QX2 0x0102
158#define PCI_DEVICE_ID_AG_QX4 0x0103
159#define PCI_DEVICE_ID_AG_QE4 0x1200
160#define PCI_DEVICE_ID_AG_DE4 0x1203
161#define PCI_DEVICE_ID_AG_XL10 0x0104
162#define PCI_DEVICE_ID_AG_DX4PLUS 0x0105
163#define PCI_DEVICE_ID_AG_DIXL 0x0110
164#define PCI_DEVICE_ID_AG_IDX1 0x050A
165#define PCI_DEVICE_ID_PMC_SIERRA_SPC 0x8001
166#define PCI_DEVICE_ID_PMC_SIERRA_SPCV 0x8008
167#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE 0x8009
168#define PCI_DEVICE_ID_PMC_SIERRA_SPCVPLUS 0x8018
169#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE_16 0x8019
170#define PCI_DEVICE_ID_SPCV_FPGA 0xabcd
171#define PCI_DEVICE_ID_PMC_SIERRA_SPCV12G 0x8070
172#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G 0x8071
173#define PCI_DEVICE_ID_PMC_SIERRA_SPCV12G_16 0x8072
174#define PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G_16 0x8073
175#define PCI_DEVICE_ID_HIALEAH_HBA_SPC 0x8081
176#define PCI_DEVICE_ID_HIALEAH_RAID_SPC 0x8091
177#define PCI_DEVICE_ID_HIALEAH_HBA_SPCV 0x8088
178#define PCI_DEVICE_ID_HIALEAH_RAID_SPCV 0x8098
179#define PCI_DEVICE_ID_HIALEAH_HBA_SPCVE 0x8089
180#define PCI_DEVICE_ID_HIALEAH_RAID_SPCVE 0x8099
181#define PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCV 0x8074
182#define PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCVE 0x8075
183#define PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV 0x8076
184#define PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCVE 0x8077
185#define PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV_SATA 0x8006
186
187
188#define PCI_SUB_VENDOR_ID_HP PCI_VENDOR_ID_HP
189#define PCI_SUB_VENDOR_ID_AG PCI_VENDOR_ID_AGILENT
190#define PCI_SUB_VENDOR_ID_MASK 0xFFFF
191#define PCI_SUB_SYSTEM_ID_AG 0x0001
192#define PCI_BASE_MEM_MASK (~0x0F)
193
194#define PCI_DEVICE_ID_CYCLONE 0xB555
195#define PCI_ENABLE_VALUE 0x0157
196#ifdef PMC_SPC
197#define PCI_NUMBER_BARS 6
198#endif
199#define IOCTL_MN_GET_CARD_INFO 0x11
200/*
201** Constant defines
202*/
203#define _08B 8
204#define _16B 16
205#define _24B 24
206#define _32B 32
207#define _64B 64
208#define _128B 128
209#define _256B 256
210#define _512B 512
211
212#define _1K 1024
213#define _2K 2048
214#define _4K 4096
215#define _128K (128*(_1K))
216
217// Card property related info.
218typedef struct _ag_card_id {
219 U16 vendorId; /* pci vendor id */
220 U16 deviceId; /* pci device id */
221 S32 cardNameIndex; /* structure index */
222 U16 membar; /* pci memory bar offset */
223 U16 iobar1; /* pci io bar 1 offset */
224 U16 iobar2; /* pci io bar 2 offest */
225 U16 reg; /* pci memory bar number */
226} ag_card_id_t;
227
228
229#define PCI_BASE_ADDRESS_0 PCIR_BAR(0)
230#define PCI_BASE_ADDRESS_1 PCIR_BAR(1)
231#define PCI_BASE_ADDRESS_2 PCIR_BAR(2)
232#define PCI_BASE_ADDRESS_3 PCIR_BAR(3)
233#define PCI_BASE_ADDRESS_4 PCIR_BAR(4)
234
235
236ag_card_id_t ag_card_type[] = {
237#ifdef AGTIAPI_ISCSI
238 {PCI_VENDOR_ID_AGILENTj, PCI_DEVICE_ID_AG_DIXL, 1,
239 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_0, 0},
240 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_IDX1, 2,
241 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_0, 0},
242#endif
243#ifdef AGTIAPI_FC
244 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_TS, 3,
245 PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, 3},
246 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_TL, 4,
247 PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, 3},
248 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_XL2, 5,
249 PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2, 3},
250 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DX2, 6,
251 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
252 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DX2PLUS, 7,
253 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
254 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DX4PLUS, 8,
255 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
256 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_QX2, 9,
257 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
258 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_QX4, 10,
259 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
260 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_DE4, 11,
261 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
262 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_QE4, 12,
263 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
264 {PCI_VENDOR_ID_AGILENT, PCI_DEVICE_ID_AG_XL10, 13,
265 PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 4},
266#endif
267#ifdef AGTIAPI_SA
268#ifdef PMC_SPC
269 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPC, 14,
270 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
271 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCV, 15,
272 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
273 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE, 16,
274 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
275 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVPLUS, 17,
276 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
277 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE_16, 18,
278 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
279 {PCI_VENDOR_ID_SPCV_FPGA, PCI_DEVICE_ID_SPCV_FPGA, 19,
280 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
281 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCV12G, 20,
282 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
283 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G, 21,
284 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
285 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCV12G_16, 22,
286 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
287 {PCI_VENDOR_ID_PMC_SIERRA, PCI_DEVICE_ID_PMC_SIERRA_SPCVE12G_16, 23,
288 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
289 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_HBA_SPC, 24,
290 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
291 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_RAID_SPC, 25,
292 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
293 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_HBA_SPCV, 26,
294 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
295 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_RAID_SPCV, 27,
296 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
297 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_HBA_SPCVE, 28,
298 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
299 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_HIALEAH_RAID_SPCVE, 29,
300 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
301 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCV, 30,
302 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
303 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_8PORTS_SPCVE, 31,
304 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
305 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV, 32,
306 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
307 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCVE, 33,
308 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
309 {PCI_VENDOR_ID_HIALEAH, PCI_DEVICE_ID_DELRAY_HBA_16PORTS_SPCV_SATA, 34,
310 PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3, 0},
311
312#endif
313#endif //AGTIAPI_SA
314};
315
316static const char *ag_card_names[] = {
317 "Unknown",
318 "iSCSI DiXL Card",
319 "iSCSI iDX1 Card",
320 "Tachyon TS Fibre Channel Card",
321 "Tachyon TL Fibre Channel Card",
322 "Tachyon XL2 Fibre Channel Card",
323 "Tachyon DX2 Fibre Channel Card",
324 "Tachyon DX2+ Fibre Channel Card",
325 "Tachyon DX4+ Fibre Channel Card",
326 "Tachyon QX2 Fibre Channel Card",
327 "Tachyon QX4 Fibre Channel Card",
328 "Tachyon DE4 Fibre Channel Card",
329 "Tachyon QE4 Fibre Channel Card",
330 "Tachyon XL10 Fibre Channel Card",
331#ifdef AGTIAPI_SA
332#ifdef PMC_SPC
333 "PMC Sierra SPC SAS-SATA Card",
334 "PMC Sierra SPC-V SAS-SATA Card",
335 "PMC Sierra SPC-VE SAS-SATA Card",
336 "PMC Sierra SPC-V 16 Port SAS-SATA Card",
337 "PMC Sierra SPC-VE 16 Port SAS-SATA Card",
338 "PMC Sierra FPGA",
339 "PMC Sierra SPC-V SAS-SATA Card 12Gig",
340 "PMC Sierra SPC-VE SAS-SATA Card 12Gig",
341 "PMC Sierra SPC-V 16 Port SAS-SATA Card 12Gig",
342 "PMC Sierra SPC-VE 16 Port SAS-SATA Card 12Gig",
343 "Adaptec Hialeah 4/8 Port SAS-SATA HBA Card 6Gig",
344 "Adaptec Hialeah 4/8 Port SAS-SATA RAID Card 6Gig",
345 "Adaptec Hialeah 8/16 Port SAS-SATA HBA Card 6Gig",
346 "Adaptec Hialeah 8/16 Port SAS-SATA RAID Card 6Gig",
347 "Adaptec Hialeah 8/16 Port SAS-SATA HBA Encryption Card 6Gig",
348 "Adaptec Hialeah 8/16 Port SAS-SATA RAID Encryption Card 6Gig",
349 "Adaptec Delray 8 Port SAS-SATA HBA Card 12Gig",
350 "Adaptec Delray 8 Port SAS-SATA HBA Encryption Card 12Gig",
351 "Adaptec Delray 16 Port SAS-SATA HBA Card 12Gig",
352 "Adaptec Delray 16 Port SAS-SATA HBA Encryption Card 12Gig",
353 "Adaptec SATA Adapter",
354
355#endif
356#endif
357};
358
359
360
361/*
362** Resource Info Structure
363*/
364typedef struct _ag_resource_info {
365 tiLoLevelResource_t tiLoLevelResource; // Low level resource required
366 tiInitiatorResource_t tiInitiatorResource; // Initiator resource required
367 tiTargetResource_t tiTargetResource; // Target resource required
368 tiTdSharedMem_t tiSharedMem; // Shared memory by ti and td
369} ag_resource_info_t;
370
371
372// DMA memory address pair
373typedef struct _ag_dma_addr {
374 void *dmaVirtAddr;
375 vm_paddr_t dmaPhysAddr;
376 U32 memSize;
377 bit32 type;
378 bus_addr_t nocache_busaddr;
379 void *nocache_mem;
380} ag_dma_addr_t;
381
382
383typedef struct _CardInfo
384{
385 U32 pciIOAddrLow; /* PCI IOBASE lower */
386 U32 pciIOAddrUp; /* PCI IOBASE Upper */
387 U32_64 pciMemBase; /* PCI MEMBASE, physical */
388 U32_64 pciMemBaseSpc[PCI_NUMBER_BARS]; // PCI MEMBASE, physical
389 U16 deviceId; // PCI device id
390 U16 vendorId; // PCI Vendor id
391 U32 busNum;
392 U32 deviceNum;
393}CardInfo_t;
394
395// Card info. for all cards and drivers
396typedef struct _ag_card_info {
397 struct mtx pmIOLock;
398 device_t pPCIDev; // PCI device pointer
399 void *pCard; // pointer to per card data structure
400 S32 cardNameIndex;
401 U32 cardID; // card system ID
402 U32 cardIdIndex;
403 U32 pciIOAddrLow; // PCI IOBASE lower
404 U32 pciIOAddrUp; // PCI IOBASE Upper
405 U32_64 pciMemBase; // PCI MEMBASE, physical
406 caddr_t pciMemVirtAddr; // PCI MEMBASE, virtual ptr
407 U32 pciMemSize; // PCI MEMBASE memory size
408#ifdef AGTIAPI_SA
409#ifdef FPGA_CARD
410 U32_64 pciMemBase0; // PCI MEMBASE, physical
411 caddr_t pciMemVirtAddr0; // PCI MEMBASE, virtual ptr
412 U32 pciMemSize0; // PCI MEMBASE memory size
413#endif
414#ifdef PMC_SPC
415 struct resource *pciMemBaseRscSpc[PCI_NUMBER_BARS];
416 int pciMemBaseRIDSpc[PCI_NUMBER_BARS];
417 U32_64 pciMemBaseSpc[PCI_NUMBER_BARS]; // PCI MEMBASE, physical
418 caddr_t pciMemVirtAddrSpc[PCI_NUMBER_BARS];//PCI MEMBASE, virt ptr
419 U32 pciMemSizeSpc[PCI_NUMBER_BARS]; // PCI MEMBASE memory size
420#endif
421#endif
422 U16 memBar;
423 U16 memReg;
424 U32 cacheIndex;
425 U32 dmaIndex;
426 ag_dma_addr_t tiDmaMem[AGTIAPI_DMA_MEM_LIST_MAX]; // dma addr list
427
428 // all (free and allocated) mem slots
429 ag_dma_addr_t dynamicMem[AGTIAPI_DYNAMIC_MAX];
430
431 // ptr to free mem slots
432 ag_dma_addr_t *freeDynamicMem[AGTIAPI_DYNAMIC_MAX];
433
434 U16 topOfFreeDynamicMem; // idx to the first free slot ptr
435
436 void *tiCachedMem[AGTIAPI_CACHE_MEM_LIST_MAX];// cached mem list
437 ag_resource_info_t tiRscInfo; /* low level resource requirement */
438 U08 WWN[AGTIAPI_MAX_NAME]; /* WWN for this card */
439 U08 WWNLen;
440
441// #define MAX_MSIX_NUM_VECTOR 64 ##
442#define MAX_MSIX_NUM_VECTOR 16 // 1 then 16 just for testing;
443#define MAX_MSIX_NUM_DPC 64 // 16
444#define MAX_MSIX_NUM_ISR 64 // 16
445#ifdef SPC_MSIX_INTR
446
447 // ## use as a map instead of presirq
448 struct resource *msix_entries[MAX_MSIX_NUM_VECTOR];
449#endif
450 U32 maxInterruptVectors;
451} ag_card_info_t;
452
453/*
454** Optional Adjustable Parameters Structures.
455** Not using pointer stucture for easy read and access tree structure.
455** Not using pointer structure for easy read and access tree structure.
456** In the future if more layer of key tree involved, it might be a good
457** idea to change the structure and program.
458*/
459typedef struct _ag_param_value{
460 char valueName[AGTIAPI_MAX_NAME];
461 char valueString[AGTIAPI_STRING_MAX];
462 struct _ag_param_value *next;
463} ag_value_t;
464
465typedef struct _ag_param_key{
466 char keyName[AGTIAPI_MAX_NAME];
467 ag_value_t *pValueHead;
468 ag_value_t *pValueTail;
469 struct _ag_param_key *pSubkeyHead;
470 struct _ag_param_key *pSubkeyTail;
471 struct _ag_param_key *next;
472} ag_key_t;
473
474/*
475** Portal info data structure
476*/
477typedef struct _ag_portal_info {
478 U32 portID;
479 U32 portStatus;
480 U32 devTotal;
481 U32 devPrev;
482 tiPortInfo_t tiPortInfo;
483 tiPortalContext_t tiPortalContext;
484#ifdef INITIATOR_DRIVER
485 void *pDevList[AGTIAPI_HW_LIMIT_DEVICE];
486#endif
487} ag_portal_info_t;
488
489#define MAP_TABLE_ENTRY(pC, c, d, l) (pC->encrypt_map + \
490 (c * pC->devDiscover * AGTIAPI_MAX_LUN) + \
491 (d * AGTIAPI_MAX_LUN) + \
492 (l))
493
494#ifdef CHAR_DEVICE
495/*************************************************************************
496Purpose: Payload Wraper for ioctl commands
497***********************************************************************/
498typedef struct datatosendt{
499bit32 datasize; //buffer size
500bit8 *data; //buffer
501}datatosend;
502/***********************************************************************/
503#define AGTIAPI_IOCTL_BASE 'x'
504#define AGTIAPI_IOCTL _IOWR(AGTIAPI_IOCTL_BASE, 0,datatosend ) //receiving payload here//
505#define AGTIAPI_IOCTL_MAX 1
506#endif
507
508#ifdef AGTIAPI_FLOW_DEBUG
509#define AGTIAPI_FLOW(format, a...) printf(format, ## a)
510#else
511#define AGTIAPI_FLOW(format, a...)
512#endif
513
514#ifdef AGTIAPI_DEBUG
515#define AGTIAPI_PRINTK(format, a...) printf(format, ## a)
516#else
517#define AGTIAPI_PRINTK(format, a...)
518#endif
519
520#ifdef AGTIAPI_INIT_DEBUG
521#define AGTIAPI_INIT(format, a...) printf(format, ## a)
522/* to avoid losing the logs */
523#define AGTIAPI_INIT_MDELAY(dly) mdelay(dly)
524#else
525#define AGTIAPI_INIT(format, a...)
526#define AGTIAPI_INIT_MDELAY(dly)
527#endif
528
529#ifdef AGTIAPI_INIT2_DEBUG
530#define AGTIAPI_INIT2(format, a...) printf(format, ## a)
531#else
532#define AGTIAPI_INIT2(format, a...)
533#endif
534
535#ifdef AGTIAPI_INIT_MEM_DEBUG
536#define AGTIAPI_INITMEM(format, a...) printf(format, ## a)
537#else
538#define AGTIAPI_INITMEM(format, a...)
539#endif
540
541#ifdef AGTIAPI_IO_DEBUG
542#define AGTIAPI_IO(format, a...) printf(format, ## a)
543#else
544#define AGTIAPI_IO(format, a...)
545#endif
546
547#ifdef AGTIAPI_LOAD_DELAY
548#define AGTIAPI_INIT_DELAY(delay_time) \
549 { \
550 agtiapi_DelayMSec(delay_time); \
551 }
552#else
553#define AGTIAPI_INIT_DELAY(delay_time)
554#endif
555
556/*
557 * AGTIAPI_KDB() will be used to drop into kernel debugger
558 * from driver code if kdb is involved.
559 */
560#ifdef AGTIAPI_KDB_ENABLE
561#define AGTIAPI_KDB() KDB_ENTER()
562#else
563#define AGTIAPI_KDB()
564#endif
565
566#if (BITS_PER_LONG == 64)
567//#if 1
568#define LOW_32_BITS(addr) (U32)(addr & 0xffffffff)
569#define HIGH_32_BITS(addr) (U32)((addr >> 32) & 0xffffffff)
570#else
571#define LOW_32_BITS(addr) (U32)addr
572#define HIGH_32_BITS(addr) 0
573#endif
574
575#define AG_SWAP16(data) (((data<<8) & 0xFF00) | (data>>8))
576#define AG_SWAP24(data) (((data<<16) & 0xFF0000) | \
577 ((data>>16) & 0xFF) | (data & 0xFF00))
578#define AG_SWAP32(data) ((data<<24) | ((data<<8) & 0xFF0000) | \
579 ((data>>8) & 0xFF00) | (data>>24))
580
581#define AG_PCI_DEV_INFO(pdev) ( \
582 AGTIAPI_PRINTK("vendor id 0x%x device id 0x%x, slot %d, function %d\n", \
583 pdev->vendor, pdev->device, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)) \
584 )
585
586#define COUNT(arr) (sizeof(arr) / sizeof(arr[0]))
587
588#define PORTAL_CONTEXT_TO_PORTALDATA(pPortalContext) \
589 ((ag_portal_data_t *)(((tiPortalContext_t *)pPortalContext)->osData))
590#define PORTAL_STATUS(pPortalData) (pPortalData->portalInfo.portStatus)
591
592#if (defined(DEFINE_OSTI_PORT_EVENT_IN_IBE)) || \
593 (defined(DEFINE_OSTI_PORT_EVENT_IN_TFE))
594#define TIROOT_TO_CARD(ptiRoot) \
595 ((ag_card_t *)(((appRoot_t *)(ptiRoot->osData))->oscData))
596#define TIROOT_TO_CARDINFO(ptiRoot) (TIROOT_TO_CARD(ptiRoot)->pCardInfo)
597#define TIROOT_TO_PCIDEV(ptiRoot) (TIROOT_TO_CARDINFO(ptiRoot)->pPCIDev)
598#else
599
600#define TIROOT_TO_CARD(ptiRoot) ((struct agtiapi_softc *)(ptiRoot->osData))
601#define TIROOT_TO_CARDINFO(ptiRoot) (TIROOT_TO_CARD(ptiRoot)->pCardInfo)
602#define TIROOT_TO_PCIDEV(ptiRoot) (TIROOT_TO_CARD(ptiRoot)->my_dev)
603
604#endif
605
606
607#define Is_ADP7H(pmsc) ((0x90058088 == (pmsc->VidDid))?1:\
608 (0x90058089 == (pmsc->VidDid))?1:0)
609#define Is_ADP8H(pmsc) ((0x90058074 == (pmsc->VidDid))?1:\
610 (0x90058076 == (pmsc->VidDid))?1:0)
611
612
613#define __cacheline_aligned __attribute__((__aligned__(CACHE_LINE_SIZE)))
614
615/*
616** link data, need to be included at the start (offset 0)
617** of any strutures that are to be stored in the link list
618*/
619typedef struct _LINK_NODE
620{
621 struct _LINK_NODE *pNext;
622 struct _LINK_NODE *pPrev;
623
624 /*
625 ** for assertion purpose only
626 */
627 struct _LINK_NODE * pHead; // track the link list the link is a member of
628 void * pad;
629
630} LINK_NODE, * PLINK_NODE __cacheline_aligned;
631
632
633/*
634** link list basic pointers
635*/
636typedef struct _LINK_LIST
637{
638 PLINK_NODE pHead;
639 bit32 Count;
456** In the future if more layer of key tree involved, it might be a good
457** idea to change the structure and program.
458*/
459typedef struct _ag_param_value{
460 char valueName[AGTIAPI_MAX_NAME];
461 char valueString[AGTIAPI_STRING_MAX];
462 struct _ag_param_value *next;
463} ag_value_t;
464
465typedef struct _ag_param_key{
466 char keyName[AGTIAPI_MAX_NAME];
467 ag_value_t *pValueHead;
468 ag_value_t *pValueTail;
469 struct _ag_param_key *pSubkeyHead;
470 struct _ag_param_key *pSubkeyTail;
471 struct _ag_param_key *next;
472} ag_key_t;
473
474/*
475** Portal info data structure
476*/
477typedef struct _ag_portal_info {
478 U32 portID;
479 U32 portStatus;
480 U32 devTotal;
481 U32 devPrev;
482 tiPortInfo_t tiPortInfo;
483 tiPortalContext_t tiPortalContext;
484#ifdef INITIATOR_DRIVER
485 void *pDevList[AGTIAPI_HW_LIMIT_DEVICE];
486#endif
487} ag_portal_info_t;
488
489#define MAP_TABLE_ENTRY(pC, c, d, l) (pC->encrypt_map + \
490 (c * pC->devDiscover * AGTIAPI_MAX_LUN) + \
491 (d * AGTIAPI_MAX_LUN) + \
492 (l))
493
494#ifdef CHAR_DEVICE
495/*************************************************************************
496Purpose: Payload Wraper for ioctl commands
497***********************************************************************/
498typedef struct datatosendt{
499bit32 datasize; //buffer size
500bit8 *data; //buffer
501}datatosend;
502/***********************************************************************/
503#define AGTIAPI_IOCTL_BASE 'x'
504#define AGTIAPI_IOCTL _IOWR(AGTIAPI_IOCTL_BASE, 0,datatosend ) //receiving payload here//
505#define AGTIAPI_IOCTL_MAX 1
506#endif
507
508#ifdef AGTIAPI_FLOW_DEBUG
509#define AGTIAPI_FLOW(format, a...) printf(format, ## a)
510#else
511#define AGTIAPI_FLOW(format, a...)
512#endif
513
514#ifdef AGTIAPI_DEBUG
515#define AGTIAPI_PRINTK(format, a...) printf(format, ## a)
516#else
517#define AGTIAPI_PRINTK(format, a...)
518#endif
519
520#ifdef AGTIAPI_INIT_DEBUG
521#define AGTIAPI_INIT(format, a...) printf(format, ## a)
522/* to avoid losing the logs */
523#define AGTIAPI_INIT_MDELAY(dly) mdelay(dly)
524#else
525#define AGTIAPI_INIT(format, a...)
526#define AGTIAPI_INIT_MDELAY(dly)
527#endif
528
529#ifdef AGTIAPI_INIT2_DEBUG
530#define AGTIAPI_INIT2(format, a...) printf(format, ## a)
531#else
532#define AGTIAPI_INIT2(format, a...)
533#endif
534
535#ifdef AGTIAPI_INIT_MEM_DEBUG
536#define AGTIAPI_INITMEM(format, a...) printf(format, ## a)
537#else
538#define AGTIAPI_INITMEM(format, a...)
539#endif
540
541#ifdef AGTIAPI_IO_DEBUG
542#define AGTIAPI_IO(format, a...) printf(format, ## a)
543#else
544#define AGTIAPI_IO(format, a...)
545#endif
546
547#ifdef AGTIAPI_LOAD_DELAY
548#define AGTIAPI_INIT_DELAY(delay_time) \
549 { \
550 agtiapi_DelayMSec(delay_time); \
551 }
552#else
553#define AGTIAPI_INIT_DELAY(delay_time)
554#endif
555
556/*
557 * AGTIAPI_KDB() will be used to drop into kernel debugger
558 * from driver code if kdb is involved.
559 */
560#ifdef AGTIAPI_KDB_ENABLE
561#define AGTIAPI_KDB() KDB_ENTER()
562#else
563#define AGTIAPI_KDB()
564#endif
565
566#if (BITS_PER_LONG == 64)
567//#if 1
568#define LOW_32_BITS(addr) (U32)(addr & 0xffffffff)
569#define HIGH_32_BITS(addr) (U32)((addr >> 32) & 0xffffffff)
570#else
571#define LOW_32_BITS(addr) (U32)addr
572#define HIGH_32_BITS(addr) 0
573#endif
574
575#define AG_SWAP16(data) (((data<<8) & 0xFF00) | (data>>8))
576#define AG_SWAP24(data) (((data<<16) & 0xFF0000) | \
577 ((data>>16) & 0xFF) | (data & 0xFF00))
578#define AG_SWAP32(data) ((data<<24) | ((data<<8) & 0xFF0000) | \
579 ((data>>8) & 0xFF00) | (data>>24))
580
581#define AG_PCI_DEV_INFO(pdev) ( \
582 AGTIAPI_PRINTK("vendor id 0x%x device id 0x%x, slot %d, function %d\n", \
583 pdev->vendor, pdev->device, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)) \
584 )
585
586#define COUNT(arr) (sizeof(arr) / sizeof(arr[0]))
587
588#define PORTAL_CONTEXT_TO_PORTALDATA(pPortalContext) \
589 ((ag_portal_data_t *)(((tiPortalContext_t *)pPortalContext)->osData))
590#define PORTAL_STATUS(pPortalData) (pPortalData->portalInfo.portStatus)
591
592#if (defined(DEFINE_OSTI_PORT_EVENT_IN_IBE)) || \
593 (defined(DEFINE_OSTI_PORT_EVENT_IN_TFE))
594#define TIROOT_TO_CARD(ptiRoot) \
595 ((ag_card_t *)(((appRoot_t *)(ptiRoot->osData))->oscData))
596#define TIROOT_TO_CARDINFO(ptiRoot) (TIROOT_TO_CARD(ptiRoot)->pCardInfo)
597#define TIROOT_TO_PCIDEV(ptiRoot) (TIROOT_TO_CARDINFO(ptiRoot)->pPCIDev)
598#else
599
600#define TIROOT_TO_CARD(ptiRoot) ((struct agtiapi_softc *)(ptiRoot->osData))
601#define TIROOT_TO_CARDINFO(ptiRoot) (TIROOT_TO_CARD(ptiRoot)->pCardInfo)
602#define TIROOT_TO_PCIDEV(ptiRoot) (TIROOT_TO_CARD(ptiRoot)->my_dev)
603
604#endif
605
606
607#define Is_ADP7H(pmsc) ((0x90058088 == (pmsc->VidDid))?1:\
608 (0x90058089 == (pmsc->VidDid))?1:0)
609#define Is_ADP8H(pmsc) ((0x90058074 == (pmsc->VidDid))?1:\
610 (0x90058076 == (pmsc->VidDid))?1:0)
611
612
613#define __cacheline_aligned __attribute__((__aligned__(CACHE_LINE_SIZE)))
614
615/*
616** link data, need to be included at the start (offset 0)
617** of any strutures that are to be stored in the link list
618*/
619typedef struct _LINK_NODE
620{
621 struct _LINK_NODE *pNext;
622 struct _LINK_NODE *pPrev;
623
624 /*
625 ** for assertion purpose only
626 */
627 struct _LINK_NODE * pHead; // track the link list the link is a member of
628 void * pad;
629
630} LINK_NODE, * PLINK_NODE __cacheline_aligned;
631
632
633/*
634** link list basic pointers
635*/
636typedef struct _LINK_LIST
637{
638 PLINK_NODE pHead;
639 bit32 Count;
640 LINK_NODE Head __cacheline_aligned; // allways one link to speed up insert&rm
640 LINK_NODE Head __cacheline_aligned; // always one link to speed up insert&rm
641} LINK_LIST, * PLINK_LIST __cacheline_aligned;
642
643
644/********************************************************************
645** MACROS
646********************************************************************/
647/*******************************************************************************
648**
649** MODULE NAME: comListInitialize
650**
651** PURPOSE: Initialize a link list.
652**
653** PARAMETERS: PLINK_LIST OUT - Link list definition.
654**
655** SIDE EFFECTS & CAVEATS:
656**
657** ALGORITHM:
658**
659*******************************************************************************/
660#define comListInitialize(pList) {(pList)->pHead = &((pList)->Head); \
661 (pList)->pHead->pNext = (pList)->pHead; \
662 (pList)->pHead->pPrev = (pList)->pHead; \
663 (pList)->Count = 0; \
664 }
665
666/*******************************************************************************
667**
668** MODULE NAME: comLinkInitialize
669**
670** PURPOSE: Initialize a link.
671** This function should be used to initialize a new link before it
672** is used in the linked list. This will initialize the link so
673** the assertion will work
674**
675** PARAMETERS: PLINK_NODE IN - Link to be initialized.
676**
677** SIDE EFFECTS & CAVEATS:
678**
679** ALGORITHM:
680**
681*******************************************************************************/
682
683#define comLinkInitialize(pLink) { (pLink)->pHead = NULL; \
684 (pLink)->pNext = NULL; \
685 (pLink)->pPrev = NULL; \
686 }
687
688/*******************************************************************************
689**
690** MODULE NAME: comListAdd
691**
692** PURPOSE: add a link at the tail of the list
693**
694** PARAMETERS: PLINK_LIST OUT - Link list definition.
695** PLINK_NODE IN - Link to be inserted.
696**
697** SIDE EFFECTS & CAVEATS:
698** !!! assumes that fcllistInitialize has been called on the linklist
699** !!! if not, this function behavior is un-predictable
700**
701** ALGORITHM:
702**
703*******************************************************************************/
704#define comListAdd(pList, pLink) { \
705 (pLink)->pNext = (pList)->pHead; \
706 (pLink)->pPrev = (pList)->pHead->pPrev; \
707 (pLink)->pPrev->pNext = (pLink); \
708 (pList)->pHead->pPrev = (pLink); \
709 (pList)->Count ++; \
710 (pLink)->pHead = (pList)->pHead; \
711 }
712
713/*******************************************************************************
714**
715** MODULE NAME: comListInsert
716**
717** PURPOSE: insert a link preceding the given one
718**
719** PARAMETERS: PLINK_LIST OUT - Link list definition.
720** PLINK_NODE IN - Link to be inserted after.
721** PLINK_NODE IN - Link to be inserted.
722**
723** SIDE EFFECTS & CAVEATS:
724** !!! assumes that fcllistInitialize has been called on the linklist
725** !!! if not, this function behavior is un-predictable
726**
727** ALGORITHM:
728**
729*******************************************************************************/
730
731#define comListInsert(pList, pLink, pNew) { \
732 (pNew)->pNext = (pLink); \
733 (pNew)->pPrev = (pLink)->pPrev; \
734 (pNew)->pPrev->pNext = (pNew); \
735 (pLink)->pPrev = (pNew); \
736 (pList)->Count ++; \
737 (pNew)->pHead = (pList)->pHead; \
738 }
739
740/*******************************************************************************
741**
742** MODULE NAME: comListRemove
743**
744** PURPOSE: remove the link from the list.
745**
746** PARAMETERS: PLINK_LIST OUT - Link list definition.
747** PLINK_NODE IN - Link to delet from list
748**
749** SIDE EFFECTS & CAVEATS:
750** !!! assumes that fcllistInitialize has been called on the linklist
751** !!! if not, this function behavior is un-predictable
752**
753** !!! No validation is made on the list or the validity of the link
754** !!! the caller must make sure that the link is in the list
755**
756**
757** ALGORITHM:
758**
759*******************************************************************************/
760#define comListRemove(pList, pLink) { \
761 (pLink)->pPrev->pNext = (pLink)->pNext; \
762 (pLink)->pNext->pPrev = (pLink)->pPrev; \
763 (pLink)->pHead = NULL; \
764 (pList)->Count --; \
765 }
766
767/*******************************************************************************
768**
769** MODULE NAME: comListGetHead
770**
771** PURPOSE: get the link following the head link.
772**
773** PARAMETERS: PLINK_LIST OUT - Link list definition.
774** RETURNS - PLINK_NODE the link following the head
775** NULL if the following link is the head
776**
777** SIDE EFFECTS & CAVEATS:
778** !!! assumes that fcllistInitialize has been called on the linklist
779** !!! if not, this function behavior is un-predictable
780**
781** ALGORITHM:
782**
783*******************************************************************************/
784#define comListGetHead(pList) comListGetNext(pList,(pList)->pHead)
785
786/*******************************************************************************
787**
788** MODULE NAME: comListGetTail
789**
790** PURPOSE: get the link preceding the tail link.
791**
792** PARAMETERS: PLINK_LIST OUT - Link list definition.
793** RETURNS - PLINK_NODE the link preceding the head
794** NULL if the preceding link is the head
795**
796** SIDE EFFECTS & CAVEATS:
797**
798** ALGORITHM:
799**
800*******************************************************************************/
801#define comListGetTail(pList) comListGetPrev((pList), (pList)->pHead)
802
803/*******************************************************************************
804**
805** MODULE NAME: comListGetCount
806**
807** PURPOSE: get the number of links in the list excluding head and tail.
808**
809** PARAMETERS: LINK_LIST OUT - Link list definition.
810**
811** SIDE EFFECTS & CAVEATS:
812** !!! assumes that fcllistInitialize has been called on the linklist
813** !!! if not, this function behavior is un-predictable
814**
815** ALGORITHM:
816**
817*******************************************************************************/
818
819#define comListGetCount(pList) ((pList)->Count)
820
821
822
823/*******************************************************************************
824**
825** MODULE NAME: comListGetNext
826**
827** PURPOSE: get the next link in the list. (one toward tail)
828**
829** PARAMETERS: PLINK_LIST OUT - Link list definition.
830** PLINK_NODE IN - Link to get next to
831**
832** return PLINK - points to next link
833** NULL if next link is head
834**
835** SIDE EFFECTS & CAVEATS:
836** !!! assumes that fcllistInitialize has been called on the linklist
837** !!! if not, this function behavior is un-predictable
838**
839** !!! No validation is made on the list or the validity of the link
840** !!! the caller must make sure that the link is in the list
841**
842** ALGORITHM:
843**
844*******************************************************************************/
845
846#define comListGetNext(pList, pLink) (((pLink)->pNext == (pList)->pHead) ? \
847 NULL : (pLink)->pNext)
848
849
850/*******************************************************************************
851**
852** MODULE NAME: comListGetPrev
853**
854** PURPOSE: get the previous link in the list. (one toward head)
855**
856** PARAMETERS: PLINK_LIST OUT - Link list definition.
857** PLINK_NODE IN - Link to get prev to
858**
859** return PLINK - points to previous link
860** NULL if previous link is head
861**
862** SIDE EFFECTS & CAVEATS:
863** !!! assumes that fcllistInitialize has been called on the linklist
864** !!! if not, this function behavior is un-predictable
865**
866** !!! No validation is made on the list or the validity of the link
867** !!! the caller must make sure that the link is in the list
868**
869** ALGORITHM:
870**
871*******************************************************************************/
872
873/*lint -emacro(613,fiLlistGetPrev) */
874
875#define comListGetPrev(pList, pLink) (((pLink)->pPrev == (pList)->pHead) ? \
876 NULL : (pLink)->pPrev)
877
878#define AGT_INTERRUPT IRQF_DISABLED
879#define AGT_SAMPLE_RANDOM IRQF_SAMPLE_RANDOM
880#define AGT_SHIRQ IRQF_SHARED
881#define AGT_PROBEIRQ IRQF_PROBE_SHARED
882#define AGT_PERCPU IRQF_PERCPU
883
884
885#include "lxproto.h"
886
641} LINK_LIST, * PLINK_LIST __cacheline_aligned;
642
643
644/********************************************************************
645** MACROS
646********************************************************************/
647/*******************************************************************************
648**
649** MODULE NAME: comListInitialize
650**
651** PURPOSE: Initialize a link list.
652**
653** PARAMETERS: PLINK_LIST OUT - Link list definition.
654**
655** SIDE EFFECTS & CAVEATS:
656**
657** ALGORITHM:
658**
659*******************************************************************************/
660#define comListInitialize(pList) {(pList)->pHead = &((pList)->Head); \
661 (pList)->pHead->pNext = (pList)->pHead; \
662 (pList)->pHead->pPrev = (pList)->pHead; \
663 (pList)->Count = 0; \
664 }
665
666/*******************************************************************************
667**
668** MODULE NAME: comLinkInitialize
669**
670** PURPOSE: Initialize a link.
671** This function should be used to initialize a new link before it
672** is used in the linked list. This will initialize the link so
673** the assertion will work
674**
675** PARAMETERS: PLINK_NODE IN - Link to be initialized.
676**
677** SIDE EFFECTS & CAVEATS:
678**
679** ALGORITHM:
680**
681*******************************************************************************/
682
683#define comLinkInitialize(pLink) { (pLink)->pHead = NULL; \
684 (pLink)->pNext = NULL; \
685 (pLink)->pPrev = NULL; \
686 }
687
688/*******************************************************************************
689**
690** MODULE NAME: comListAdd
691**
692** PURPOSE: add a link at the tail of the list
693**
694** PARAMETERS: PLINK_LIST OUT - Link list definition.
695** PLINK_NODE IN - Link to be inserted.
696**
697** SIDE EFFECTS & CAVEATS:
698** !!! assumes that fcllistInitialize has been called on the linklist
699** !!! if not, this function behavior is un-predictable
700**
701** ALGORITHM:
702**
703*******************************************************************************/
704#define comListAdd(pList, pLink) { \
705 (pLink)->pNext = (pList)->pHead; \
706 (pLink)->pPrev = (pList)->pHead->pPrev; \
707 (pLink)->pPrev->pNext = (pLink); \
708 (pList)->pHead->pPrev = (pLink); \
709 (pList)->Count ++; \
710 (pLink)->pHead = (pList)->pHead; \
711 }
712
713/*******************************************************************************
714**
715** MODULE NAME: comListInsert
716**
717** PURPOSE: insert a link preceding the given one
718**
719** PARAMETERS: PLINK_LIST OUT - Link list definition.
720** PLINK_NODE IN - Link to be inserted after.
721** PLINK_NODE IN - Link to be inserted.
722**
723** SIDE EFFECTS & CAVEATS:
724** !!! assumes that fcllistInitialize has been called on the linklist
725** !!! if not, this function behavior is un-predictable
726**
727** ALGORITHM:
728**
729*******************************************************************************/
730
731#define comListInsert(pList, pLink, pNew) { \
732 (pNew)->pNext = (pLink); \
733 (pNew)->pPrev = (pLink)->pPrev; \
734 (pNew)->pPrev->pNext = (pNew); \
735 (pLink)->pPrev = (pNew); \
736 (pList)->Count ++; \
737 (pNew)->pHead = (pList)->pHead; \
738 }
739
740/*******************************************************************************
741**
742** MODULE NAME: comListRemove
743**
744** PURPOSE: remove the link from the list.
745**
746** PARAMETERS: PLINK_LIST OUT - Link list definition.
747** PLINK_NODE IN - Link to delet from list
748**
749** SIDE EFFECTS & CAVEATS:
750** !!! assumes that fcllistInitialize has been called on the linklist
751** !!! if not, this function behavior is un-predictable
752**
753** !!! No validation is made on the list or the validity of the link
754** !!! the caller must make sure that the link is in the list
755**
756**
757** ALGORITHM:
758**
759*******************************************************************************/
760#define comListRemove(pList, pLink) { \
761 (pLink)->pPrev->pNext = (pLink)->pNext; \
762 (pLink)->pNext->pPrev = (pLink)->pPrev; \
763 (pLink)->pHead = NULL; \
764 (pList)->Count --; \
765 }
766
767/*******************************************************************************
768**
769** MODULE NAME: comListGetHead
770**
771** PURPOSE: get the link following the head link.
772**
773** PARAMETERS: PLINK_LIST OUT - Link list definition.
774** RETURNS - PLINK_NODE the link following the head
775** NULL if the following link is the head
776**
777** SIDE EFFECTS & CAVEATS:
778** !!! assumes that fcllistInitialize has been called on the linklist
779** !!! if not, this function behavior is un-predictable
780**
781** ALGORITHM:
782**
783*******************************************************************************/
784#define comListGetHead(pList) comListGetNext(pList,(pList)->pHead)
785
786/*******************************************************************************
787**
788** MODULE NAME: comListGetTail
789**
790** PURPOSE: get the link preceding the tail link.
791**
792** PARAMETERS: PLINK_LIST OUT - Link list definition.
793** RETURNS - PLINK_NODE the link preceding the head
794** NULL if the preceding link is the head
795**
796** SIDE EFFECTS & CAVEATS:
797**
798** ALGORITHM:
799**
800*******************************************************************************/
801#define comListGetTail(pList) comListGetPrev((pList), (pList)->pHead)
802
803/*******************************************************************************
804**
805** MODULE NAME: comListGetCount
806**
807** PURPOSE: get the number of links in the list excluding head and tail.
808**
809** PARAMETERS: LINK_LIST OUT - Link list definition.
810**
811** SIDE EFFECTS & CAVEATS:
812** !!! assumes that fcllistInitialize has been called on the linklist
813** !!! if not, this function behavior is un-predictable
814**
815** ALGORITHM:
816**
817*******************************************************************************/
818
819#define comListGetCount(pList) ((pList)->Count)
820
821
822
823/*******************************************************************************
824**
825** MODULE NAME: comListGetNext
826**
827** PURPOSE: get the next link in the list. (one toward tail)
828**
829** PARAMETERS: PLINK_LIST OUT - Link list definition.
830** PLINK_NODE IN - Link to get next to
831**
832** return PLINK - points to next link
833** NULL if next link is head
834**
835** SIDE EFFECTS & CAVEATS:
836** !!! assumes that fcllistInitialize has been called on the linklist
837** !!! if not, this function behavior is un-predictable
838**
839** !!! No validation is made on the list or the validity of the link
840** !!! the caller must make sure that the link is in the list
841**
842** ALGORITHM:
843**
844*******************************************************************************/
845
846#define comListGetNext(pList, pLink) (((pLink)->pNext == (pList)->pHead) ? \
847 NULL : (pLink)->pNext)
848
849
850/*******************************************************************************
851**
852** MODULE NAME: comListGetPrev
853**
854** PURPOSE: get the previous link in the list. (one toward head)
855**
856** PARAMETERS: PLINK_LIST OUT - Link list definition.
857** PLINK_NODE IN - Link to get prev to
858**
859** return PLINK - points to previous link
860** NULL if previous link is head
861**
862** SIDE EFFECTS & CAVEATS:
863** !!! assumes that fcllistInitialize has been called on the linklist
864** !!! if not, this function behavior is un-predictable
865**
866** !!! No validation is made on the list or the validity of the link
867** !!! the caller must make sure that the link is in the list
868**
869** ALGORITHM:
870**
871*******************************************************************************/
872
873/*lint -emacro(613,fiLlistGetPrev) */
874
875#define comListGetPrev(pList, pLink) (((pLink)->pPrev == (pList)->pHead) ? \
876 NULL : (pLink)->pPrev)
877
878#define AGT_INTERRUPT IRQF_DISABLED
879#define AGT_SAMPLE_RANDOM IRQF_SAMPLE_RANDOM
880#define AGT_SHIRQ IRQF_SHARED
881#define AGT_PROBEIRQ IRQF_PROBE_SHARED
882#define AGT_PERCPU IRQF_PERCPU
883
884
885#include "lxproto.h"
886