1/*-
2 * Copyright (c) 2000 Berkeley Software Design, Inc.
3 * Copyright (c) 1997, 1998, 1999, 2000
4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/pcn/if_pcn.c 221407 2011-05-03 19:51:29Z marius $");
36
37/*
38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available
39 * from http://www.amd.com.
40 *
41 * The AMD PCnet/PCI controllers are more advanced and functional
42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
43 * backwards compatibility with the LANCE and thus can be made
44 * to work with older LANCE drivers. This is in fact how the
45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble
46 * is that the PCnet/PCI devices offer several performance enhancements
47 * which can't be exploited in LANCE compatibility mode. Chief among
48 * these enhancements is the ability to perform PCI DMA operations
49 * using 32-bit addressing (which eliminates the need for ISA
50 * bounce-buffering), and special receive buffer alignment (which
51 * allows the receive handler to pass packets to the upper protocol
52 * layers without copying on both the x86 and alpha platforms).
53 */
54
55#include <sys/param.h>
56#include <sys/systm.h>
57#include <sys/sockio.h>
58#include <sys/mbuf.h>
59#include <sys/malloc.h>
60#include <sys/kernel.h>
61#include <sys/module.h>
62#include <sys/socket.h>
63
64#include <net/if.h>
65#include <net/if_arp.h>
66#include <net/ethernet.h>
67#include <net/if_dl.h>
68#include <net/if_media.h>
69#include <net/if_types.h>
70
71#include <net/bpf.h>
72
73#include <vm/vm.h> /* for vtophys */
74#include <vm/pmap.h> /* for vtophys */
75#include <machine/bus.h>
76#include <machine/resource.h>
77#include <sys/bus.h>
78#include <sys/rman.h>
79
80#include <dev/mii/mii.h>
81#include <dev/mii/miivar.h>
82
83#include <dev/pci/pcireg.h>
84#include <dev/pci/pcivar.h>
85
86#define PCN_USEIOSPACE
87
88#include <dev/pcn/if_pcnreg.h>
89
90MODULE_DEPEND(pcn, pci, 1, 1, 1);
91MODULE_DEPEND(pcn, ether, 1, 1, 1);
92MODULE_DEPEND(pcn, miibus, 1, 1, 1);
93
94/* "device miibus" required. See GENERIC if you get errors here. */
95#include "miibus_if.h"
96
97/*
98 * Various supported device vendors/types and their names.
99 */
100static const struct pcn_type pcn_devs[] = {
101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
103 { 0, 0, NULL }
104};
105
106static const struct pcn_chipid {
107 u_int32_t id;
108 const char *name;
109} pcn_chipid[] = {
110 { Am79C971, "Am79C971" },
111 { Am79C972, "Am79C972" },
112 { Am79C973, "Am79C973" },
113 { Am79C978, "Am79C978" },
114 { Am79C975, "Am79C975" },
115 { Am79C976, "Am79C976" },
116 { 0, NULL },
117};
118
119static const char *pcn_chipid_name(u_int32_t);
120static u_int32_t pcn_chip_id(device_t);
121static const struct pcn_type *pcn_match(u_int16_t, u_int16_t);
122
123static u_int32_t pcn_csr_read(struct pcn_softc *, int);
124static u_int16_t pcn_csr_read16(struct pcn_softc *, int);
125static u_int16_t pcn_bcr_read16(struct pcn_softc *, int);
126static void pcn_csr_write(struct pcn_softc *, int, int);
127static u_int32_t pcn_bcr_read(struct pcn_softc *, int);
128static void pcn_bcr_write(struct pcn_softc *, int, int);
129
130static int pcn_probe(device_t);
131static int pcn_attach(device_t);
132static int pcn_detach(device_t);
133
134static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *);
135static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *);
136static void pcn_rxeof(struct pcn_softc *);
137static void pcn_txeof(struct pcn_softc *);
138static void pcn_intr(void *);
139static void pcn_tick(void *);
140static void pcn_start(struct ifnet *);
141static void pcn_start_locked(struct ifnet *);
142static int pcn_ioctl(struct ifnet *, u_long, caddr_t);
143static void pcn_init(void *);
144static void pcn_init_locked(struct pcn_softc *);
145static void pcn_stop(struct pcn_softc *);
146static void pcn_watchdog(struct pcn_softc *);
147static int pcn_shutdown(device_t);
148static int pcn_ifmedia_upd(struct ifnet *);
149static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *);
150
151static int pcn_miibus_readreg(device_t, int, int);
152static int pcn_miibus_writereg(device_t, int, int, int);
153static void pcn_miibus_statchg(device_t);
154
155static void pcn_setfilt(struct ifnet *);
156static void pcn_setmulti(struct pcn_softc *);
157static void pcn_reset(struct pcn_softc *);
158static int pcn_list_rx_init(struct pcn_softc *);
159static int pcn_list_tx_init(struct pcn_softc *);
160
161#ifdef PCN_USEIOSPACE
162#define PCN_RES SYS_RES_IOPORT
163#define PCN_RID PCN_PCI_LOIO
164#else
165#define PCN_RES SYS_RES_MEMORY
166#define PCN_RID PCN_PCI_LOMEM
167#endif
168
169static device_method_t pcn_methods[] = {
170 /* Device interface */
171 DEVMETHOD(device_probe, pcn_probe),
172 DEVMETHOD(device_attach, pcn_attach),
173 DEVMETHOD(device_detach, pcn_detach),
174 DEVMETHOD(device_shutdown, pcn_shutdown),
175
176 /* bus interface */
177 DEVMETHOD(bus_print_child, bus_generic_print_child),
178 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
179
180 /* MII interface */
181 DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
182 DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
183 DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
184
185 { 0, 0 }
186};
187
188static driver_t pcn_driver = {
189 "pcn",
190 pcn_methods,
191 sizeof(struct pcn_softc)
192};
193
194static devclass_t pcn_devclass;
195
196DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0);
197DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
198
199#define PCN_CSR_SETBIT(sc, reg, x) \
200 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
201
202#define PCN_CSR_CLRBIT(sc, reg, x) \
203 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
204
205#define PCN_BCR_SETBIT(sc, reg, x) \
206 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
207
208#define PCN_BCR_CLRBIT(sc, reg, x) \
209 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
210
211static u_int32_t
212pcn_csr_read(sc, reg)
213 struct pcn_softc *sc;
214 int reg;
215{
216 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
217 return(CSR_READ_4(sc, PCN_IO32_RDP));
218}
219
220static u_int16_t
221pcn_csr_read16(sc, reg)
222 struct pcn_softc *sc;
223 int reg;
224{
225 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
226 return(CSR_READ_2(sc, PCN_IO16_RDP));
227}
228
229static void
230pcn_csr_write(sc, reg, val)
231 struct pcn_softc *sc;
232 int reg;
233 int val;
234{
235 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
236 CSR_WRITE_4(sc, PCN_IO32_RDP, val);
237 return;
238}
239
240static u_int32_t
241pcn_bcr_read(sc, reg)
242 struct pcn_softc *sc;
243 int reg;
244{
245 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
246 return(CSR_READ_4(sc, PCN_IO32_BDP));
247}
248
249static u_int16_t
250pcn_bcr_read16(sc, reg)
251 struct pcn_softc *sc;
252 int reg;
253{
254 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
255 return(CSR_READ_2(sc, PCN_IO16_BDP));
256}
257
258static void
259pcn_bcr_write(sc, reg, val)
260 struct pcn_softc *sc;
261 int reg;
262 int val;
263{
264 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
265 CSR_WRITE_4(sc, PCN_IO32_BDP, val);
266 return;
267}
268
269static int
270pcn_miibus_readreg(dev, phy, reg)
271 device_t dev;
272 int phy, reg;
273{
274 struct pcn_softc *sc;
275 int val;
276
277 sc = device_get_softc(dev);
278
279 /*
280 * At least Am79C971 with DP83840A wedge when isolating the
281 * external PHY so we can't allow multiple external PHYs.
282 * There are cards that use Am79C971 with both the internal
283 * and an external PHY though.
284 * For internal PHYs it doesn't really matter whether we can
285 * isolate the remaining internal and the external ones in
286 * the PHY drivers as the internal PHYs have to be enabled
287 * individually in PCN_BCR_PHYSEL, PCN_CSR_MODE, etc.
288 * With Am79C97{3,5,8} we don't support switching beetween
289 * the internal and external PHYs, yet, so we can't allow
290 * multiple PHYs with these either.
291 * Am79C97{2,6} actually only support external PHYs (not
292 * connectable internal ones respond at the usual addresses,
293 * which don't hurt if we let them show up on the bus) and
294 * isolating them works.
295 */
296 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) ||
297 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 ||
298 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr != -1 &&
299 phy != sc->pcn_extphyaddr)
300 return(0);
301
302 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
303 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
304 if (val == 0xFFFF)
305 return(0);
306
307 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) ||
308 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 ||
309 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr == -1)
310 sc->pcn_extphyaddr = phy;
311
312 return(val);
313}
314
315static int
316pcn_miibus_writereg(dev, phy, reg, data)
317 device_t dev;
318 int phy, reg, data;
319{
320 struct pcn_softc *sc;
321
322 sc = device_get_softc(dev);
323
324 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
325 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
326
327 return(0);
328}
329
330static void
331pcn_miibus_statchg(dev)
332 device_t dev;
333{
334 struct pcn_softc *sc;
335 struct mii_data *mii;
336
337 sc = device_get_softc(dev);
338 mii = device_get_softc(sc->pcn_miibus);
339
340 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
341 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
342 } else {
343 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
344 }
345
346 return;
347}
348
349static void
350pcn_setmulti(sc)
351 struct pcn_softc *sc;
352{
353 struct ifnet *ifp;
354 struct ifmultiaddr *ifma;
355 u_int32_t h, i;
356 u_int16_t hashes[4] = { 0, 0, 0, 0 };
357
358 ifp = sc->pcn_ifp;
359
360 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
361
362 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
363 for (i = 0; i < 4; i++)
364 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
365 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
366 return;
367 }
368
369 /* first, zot all the existing hash bits */
370 for (i = 0; i < 4; i++)
371 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
372
373 /* now program new ones */
374 if_maddr_rlock(ifp);
375 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
376 if (ifma->ifma_addr->sa_family != AF_LINK)
377 continue;
378 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
379 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
380 hashes[h >> 4] |= 1 << (h & 0xF);
381 }
382 if_maddr_runlock(ifp);
383
384 for (i = 0; i < 4; i++)
385 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
386
387 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
388
389 return;
390}
391
392static void
393pcn_reset(sc)
394 struct pcn_softc *sc;
395{
396 /*
397 * Issue a reset by reading from the RESET register.
398 * Note that we don't know if the chip is operating in
399 * 16-bit or 32-bit mode at this point, so we attempt
400 * to reset the chip both ways. If one fails, the other
401 * will succeed.
402 */
403 CSR_READ_2(sc, PCN_IO16_RESET);
404 CSR_READ_4(sc, PCN_IO32_RESET);
405
406 /* Wait a little while for the chip to get its brains in order. */
407 DELAY(1000);
408
409 /* Select 32-bit (DWIO) mode */
410 CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
411
412 /* Select software style 3. */
413 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
414
415 return;
416}
417
418static const char *
419pcn_chipid_name(u_int32_t id)
420{
421 const struct pcn_chipid *p;
422
423 p = pcn_chipid;
424 while (p->name) {
425 if (id == p->id)
426 return (p->name);
427 p++;
428 }
429 return ("Unknown");
430}
431
432static u_int32_t
433pcn_chip_id(device_t dev)
434{
435 struct pcn_softc *sc;
436 u_int32_t chip_id;
437
438 sc = device_get_softc(dev);
439 /*
440 * Note: we can *NOT* put the chip into
441 * 32-bit mode yet. The le(4) driver will only
442 * work in 16-bit mode, and once the chip
443 * goes into 32-bit mode, the only way to
444 * get it out again is with a hardware reset.
445 * So if pcn_probe() is called before the
446 * le(4) driver's probe routine, the chip will
447 * be locked into 32-bit operation and the
448 * le(4) driver will be unable to attach to it.
449 * Note II: if the chip happens to already
450 * be in 32-bit mode, we still need to check
451 * the chip ID, but first we have to detect
452 * 32-bit mode using only 16-bit operations.
453 * The safest way to do this is to read the
454 * PCI subsystem ID from BCR23/24 and compare
455 * that with the value read from PCI config
456 * space.
457 */
458 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
459 chip_id <<= 16;
460 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
461 /*
462 * Note III: the test for 0x10001000 is a hack to
463 * pacify VMware, who's pseudo-PCnet interface is
464 * broken. Reading the subsystem register from PCI
465 * config space yields 0x00000000 while reading the
466 * same value from I/O space yields 0x10001000. It's
467 * not supposed to be that way.
468 */
469 if (chip_id == pci_read_config(dev,
470 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
471 /* We're in 16-bit mode. */
472 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
473 chip_id <<= 16;
474 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
475 } else {
476 /* We're in 32-bit mode. */
477 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
478 chip_id <<= 16;
479 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
480 }
481
482 return (chip_id);
483}
484
485static const struct pcn_type *
486pcn_match(u_int16_t vid, u_int16_t did)
487{
488 const struct pcn_type *t;
489
490 t = pcn_devs;
491 while (t->pcn_name != NULL) {
492 if ((vid == t->pcn_vid) && (did == t->pcn_did))
493 return (t);
494 t++;
495 }
496 return (NULL);
497}
498
499/*
500 * Probe for an AMD chip. Check the PCI vendor and device
501 * IDs against our list and return a device name if we find a match.
502 */
503static int
504pcn_probe(dev)
505 device_t dev;
506{
507 const struct pcn_type *t;
508 struct pcn_softc *sc;
509 int rid;
510 u_int32_t chip_id;
511
512 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev));
513 if (t == NULL)
514 return (ENXIO);
515 sc = device_get_softc(dev);
516
517 /*
518 * Temporarily map the I/O space so we can read the chip ID register.
519 */
520 rid = PCN_RID;
521 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
522 if (sc->pcn_res == NULL) {
523 device_printf(dev, "couldn't map ports/memory\n");
524 return(ENXIO);
525 }
526 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
527 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
528
529 chip_id = pcn_chip_id(dev);
530
531 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
532
533 switch((chip_id >> 12) & PART_MASK) {
534 case Am79C971:
535 case Am79C972:
536 case Am79C973:
537 case Am79C975:
538 case Am79C976:
539 case Am79C978:
540 break;
541 default:
542 return(ENXIO);
543 }
544 device_set_desc(dev, t->pcn_name);
545 return(BUS_PROBE_DEFAULT);
546}
547
548/*
549 * Attach the interface. Allocate softc structures, do ifmedia
550 * setup and ethernet/BPF attach.
551 */
552static int
553pcn_attach(dev)
554 device_t dev;
555{
556 u_int32_t eaddr[2];
557 struct pcn_softc *sc;
558 struct mii_data *mii;
559 struct mii_softc *miisc;
560 struct ifnet *ifp;
561 int error = 0, rid;
562
563 sc = device_get_softc(dev);
564
565 /* Initialize our mutex. */
566 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
567 MTX_DEF);
568 /*
569 * Map control/status registers.
570 */
571 pci_enable_busmaster(dev);
572
573 /* Retrieve the chip ID */
574 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK;
575 device_printf(dev, "Chip ID %04x (%s)\n",
576 sc->pcn_type, pcn_chipid_name(sc->pcn_type));
577
578 rid = PCN_RID;
579 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
580
581 if (sc->pcn_res == NULL) {
582 device_printf(dev, "couldn't map ports/memory\n");
583 error = ENXIO;
584 goto fail;
585 }
586
587 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
588 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
589
590 /* Allocate interrupt */
591 rid = 0;
592 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
593 RF_SHAREABLE | RF_ACTIVE);
594
595 if (sc->pcn_irq == NULL) {
596 device_printf(dev, "couldn't map interrupt\n");
597 error = ENXIO;
598 goto fail;
599 }
600
601 /* Reset the adapter. */
602 pcn_reset(sc);
603
604 /*
605 * Get station address from the EEPROM.
606 */
607 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00);
608 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01);
609
610 callout_init_mtx(&sc->pcn_stat_callout, &sc->pcn_mtx, 0);
611
612 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
613 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
614
615 if (sc->pcn_ldata == NULL) {
616 device_printf(dev, "no memory for list buffers!\n");
617 error = ENXIO;
618 goto fail;
619 }
620 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
621
622 ifp = sc->pcn_ifp = if_alloc(IFT_ETHER);
623 if (ifp == NULL) {
624 device_printf(dev, "can not if_alloc()\n");
625 error = ENOSPC;
626 goto fail;
627 }
628 ifp->if_softc = sc;
629 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
630 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
631 ifp->if_ioctl = pcn_ioctl;
632 ifp->if_start = pcn_start;
633 ifp->if_init = pcn_init;
634 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1;
635
636 /*
637 * Do MII setup.
638 * See the comment in pcn_miibus_readreg() for why we can't
639 * universally pass MIIF_NOISOLATE here.
640 */
641 sc->pcn_extphyaddr = -1;
642 error = mii_attach(dev, &sc->pcn_miibus, ifp, pcn_ifmedia_upd,
643 pcn_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
644 if (error != 0) {
645 device_printf(dev, "attaching PHYs failed\n");
646 goto fail;
647 }
648 /*
649 * Record the media instances of internal PHYs, which map the
650 * built-in interfaces to the MII, so we can set the active
651 * PHY/port based on the currently selected media.
652 */
653 sc->pcn_inst_10bt = -1;
654 mii = device_get_softc(sc->pcn_miibus);
655 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
656 switch (miisc->mii_phy) {
657 case PCN_PHYAD_10BT:
658 sc->pcn_inst_10bt = miisc->mii_inst;
659 break;
660 /*
661 * XXX deal with the Am79C97{3,5} internal 100baseT
662 * and the Am79C978 internal HomePNA PHYs.
663 */
664 }
665 }
666
667 /*
668 * Call MI attach routine.
669 */
670 ether_ifattach(ifp, (u_int8_t *) eaddr);
671
672 /* Hook interrupt last to avoid having to lock softc */
673 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET | INTR_MPSAFE,
674 NULL, pcn_intr, sc, &sc->pcn_intrhand);
675
676 if (error) {
677 device_printf(dev, "couldn't set up irq\n");
678 ether_ifdetach(ifp);
679 goto fail;
680 }
681
682fail:
683 if (error)
684 pcn_detach(dev);
685
686 return(error);
687}
688
689/*
690 * Shutdown hardware and free up resources. This can be called any
691 * time after the mutex has been initialized. It is called in both
692 * the error case in attach and the normal detach case so it needs
693 * to be careful about only freeing resources that have actually been
694 * allocated.
695 */
696static int
697pcn_detach(dev)
698 device_t dev;
699{
700 struct pcn_softc *sc;
701 struct ifnet *ifp;
702
703 sc = device_get_softc(dev);
704 ifp = sc->pcn_ifp;
705
706 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized"));
707
708 /* These should only be active if attach succeeded */
709 if (device_is_attached(dev)) {
710 PCN_LOCK(sc);
711 pcn_reset(sc);
712 pcn_stop(sc);
713 PCN_UNLOCK(sc);
714 callout_drain(&sc->pcn_stat_callout);
715 ether_ifdetach(ifp);
716 }
717 if (sc->pcn_miibus)
718 device_delete_child(dev, sc->pcn_miibus);
719 bus_generic_detach(dev);
720
721 if (sc->pcn_intrhand)
722 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
723 if (sc->pcn_irq)
724 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
725 if (sc->pcn_res)
726 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
727
728 if (ifp)
729 if_free(ifp);
730
731 if (sc->pcn_ldata) {
732 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
733 M_DEVBUF);
734 }
735
736 mtx_destroy(&sc->pcn_mtx);
737
738 return(0);
739}
740
741/*
742 * Initialize the transmit descriptors.
743 */
744static int
745pcn_list_tx_init(sc)
746 struct pcn_softc *sc;
747{
748 struct pcn_list_data *ld;
749 struct pcn_ring_data *cd;
750 int i;
751
752 cd = &sc->pcn_cdata;
753 ld = sc->pcn_ldata;
754
755 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
756 cd->pcn_tx_chain[i] = NULL;
757 ld->pcn_tx_list[i].pcn_tbaddr = 0;
758 ld->pcn_tx_list[i].pcn_txctl = 0;
759 ld->pcn_tx_list[i].pcn_txstat = 0;
760 }
761
762 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
763
764 return(0);
765}
766
767
768/*
769 * Initialize the RX descriptors and allocate mbufs for them.
770 */
771static int
772pcn_list_rx_init(sc)
773 struct pcn_softc *sc;
774{
775 struct pcn_ring_data *cd;
776 int i;
777
778 cd = &sc->pcn_cdata;
779
780 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
781 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
782 return(ENOBUFS);
783 }
784
785 cd->pcn_rx_prod = 0;
786
787 return(0);
788}
789
790/*
791 * Initialize an RX descriptor and attach an MBUF cluster.
792 */
793static int
794pcn_newbuf(sc, idx, m)
795 struct pcn_softc *sc;
796 int idx;
797 struct mbuf *m;
798{
799 struct mbuf *m_new = NULL;
800 struct pcn_rx_desc *c;
801
802 c = &sc->pcn_ldata->pcn_rx_list[idx];
803
804 if (m == NULL) {
805 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
806 if (m_new == NULL)
807 return(ENOBUFS);
808
809 MCLGET(m_new, M_DONTWAIT);
810 if (!(m_new->m_flags & M_EXT)) {
811 m_freem(m_new);
812 return(ENOBUFS);
813 }
814 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
815 } else {
816 m_new = m;
817 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
818 m_new->m_data = m_new->m_ext.ext_buf;
819 }
820
821 m_adj(m_new, ETHER_ALIGN);
822
823 sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
824 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
825 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
826 c->pcn_bufsz |= PCN_RXLEN_MBO;
827 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
828
829 return(0);
830}
831
832/*
833 * A frame has been uploaded: pass the resulting mbuf chain up to
834 * the higher level protocols.
835 */
836static void
837pcn_rxeof(sc)
838 struct pcn_softc *sc;
839{
840 struct mbuf *m;
841 struct ifnet *ifp;
842 struct pcn_rx_desc *cur_rx;
843 int i;
844
845 PCN_LOCK_ASSERT(sc);
846
847 ifp = sc->pcn_ifp;
848 i = sc->pcn_cdata.pcn_rx_prod;
849
850 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
851 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
852 m = sc->pcn_cdata.pcn_rx_chain[i];
853 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
854
855 /*
856 * If an error occurs, update stats, clear the
857 * status word and leave the mbuf cluster in place:
858 * it should simply get re-used next time this descriptor
859 * comes up in the ring.
860 */
861 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
862 ifp->if_ierrors++;
863 pcn_newbuf(sc, i, m);
864 PCN_INC(i, PCN_RX_LIST_CNT);
865 continue;
866 }
867
868 if (pcn_newbuf(sc, i, NULL)) {
869 /* Ran out of mbufs; recycle this one. */
870 pcn_newbuf(sc, i, m);
871 ifp->if_ierrors++;
872 PCN_INC(i, PCN_RX_LIST_CNT);
873 continue;
874 }
875
876 PCN_INC(i, PCN_RX_LIST_CNT);
877
878 /* No errors; receive the packet. */
879 ifp->if_ipackets++;
880 m->m_len = m->m_pkthdr.len =
881 cur_rx->pcn_rxlen - ETHER_CRC_LEN;
882 m->m_pkthdr.rcvif = ifp;
883
884 PCN_UNLOCK(sc);
885 (*ifp->if_input)(ifp, m);
886 PCN_LOCK(sc);
887 }
888
889 sc->pcn_cdata.pcn_rx_prod = i;
890
891 return;
892}
893
894/*
895 * A frame was downloaded to the chip. It's safe for us to clean up
896 * the list buffers.
897 */
898
899static void
900pcn_txeof(sc)
901 struct pcn_softc *sc;
902{
903 struct pcn_tx_desc *cur_tx = NULL;
904 struct ifnet *ifp;
905 u_int32_t idx;
906
907 ifp = sc->pcn_ifp;
908
909 /*
910 * Go through our tx list and free mbufs for those
911 * frames that have been transmitted.
912 */
913 idx = sc->pcn_cdata.pcn_tx_cons;
914 while (idx != sc->pcn_cdata.pcn_tx_prod) {
915 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
916
917 if (!PCN_OWN_TXDESC(cur_tx))
918 break;
919
920 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
921 sc->pcn_cdata.pcn_tx_cnt--;
922 PCN_INC(idx, PCN_TX_LIST_CNT);
923 continue;
924 }
925
926 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
927 ifp->if_oerrors++;
928 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
929 ifp->if_collisions++;
930 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
931 ifp->if_collisions++;
932 }
933
934 ifp->if_collisions +=
935 cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
936
937 ifp->if_opackets++;
938 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
939 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
940 sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
941 }
942
943 sc->pcn_cdata.pcn_tx_cnt--;
944 PCN_INC(idx, PCN_TX_LIST_CNT);
945 }
946
947 if (idx != sc->pcn_cdata.pcn_tx_cons) {
948 /* Some buffers have been freed. */
949 sc->pcn_cdata.pcn_tx_cons = idx;
950 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
951 }
952 sc->pcn_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
953
954 return;
955}
956
957static void
958pcn_tick(xsc)
959 void *xsc;
960{
961 struct pcn_softc *sc;
962 struct mii_data *mii;
963 struct ifnet *ifp;
964
965 sc = xsc;
966 ifp = sc->pcn_ifp;
967 PCN_LOCK_ASSERT(sc);
968
969 mii = device_get_softc(sc->pcn_miibus);
970 mii_tick(mii);
971
972 /* link just died */
973 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
974 sc->pcn_link = 0;
975
976 /* link just came up, restart */
977 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE &&
978 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
979 sc->pcn_link++;
980 if (ifp->if_snd.ifq_head != NULL)
981 pcn_start_locked(ifp);
982 }
983
984 if (sc->pcn_timer > 0 && --sc->pcn_timer == 0)
985 pcn_watchdog(sc);
986 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc);
987
988 return;
989}
990
991static void
992pcn_intr(arg)
993 void *arg;
994{
995 struct pcn_softc *sc;
996 struct ifnet *ifp;
997 u_int32_t status;
998
999 sc = arg;
1000 ifp = sc->pcn_ifp;
1001
1002 PCN_LOCK(sc);
1003
1004 /* Suppress unwanted interrupts */
1005 if (!(ifp->if_flags & IFF_UP)) {
1006 pcn_stop(sc);
1007 PCN_UNLOCK(sc);
1008 return;
1009 }
1010
1011 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
1012
1013 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
1014 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
1015
1016 if (status & PCN_CSR_RINT)
1017 pcn_rxeof(sc);
1018
1019 if (status & PCN_CSR_TINT)
1020 pcn_txeof(sc);
1021
1022 if (status & PCN_CSR_ERR) {
1023 pcn_init_locked(sc);
1024 break;
1025 }
1026 }
1027
1028 if (ifp->if_snd.ifq_head != NULL)
1029 pcn_start_locked(ifp);
1030
1031 PCN_UNLOCK(sc);
1032 return;
1033}
1034
1035/*
1036 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1037 * pointers to the fragment pointers.
1038 */
1039static int
1040pcn_encap(sc, m_head, txidx)
1041 struct pcn_softc *sc;
1042 struct mbuf *m_head;
1043 u_int32_t *txidx;
1044{
1045 struct pcn_tx_desc *f = NULL;
1046 struct mbuf *m;
1047 int frag, cur, cnt = 0;
1048
1049 /*
1050 * Start packing the mbufs in this chain into
1051 * the fragment pointers. Stop when we run out
1052 * of fragments or hit the end of the mbuf chain.
1053 */
1054 m = m_head;
1055 cur = frag = *txidx;
1056
1057 for (m = m_head; m != NULL; m = m->m_next) {
1058 if (m->m_len == 0)
1059 continue;
1060
1061 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
1062 return(ENOBUFS);
1063 f = &sc->pcn_ldata->pcn_tx_list[frag];
1064 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
1065 f->pcn_txctl |= PCN_TXCTL_MBO;
1066 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
1067 if (cnt == 0)
1068 f->pcn_txctl |= PCN_TXCTL_STP;
1069 else
1070 f->pcn_txctl |= PCN_TXCTL_OWN;
1071 cur = frag;
1072 PCN_INC(frag, PCN_TX_LIST_CNT);
1073 cnt++;
1074 }
1075
1076 if (m != NULL)
1077 return(ENOBUFS);
1078
1079 sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
1080 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
1081 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
1082 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
1083 sc->pcn_cdata.pcn_tx_cnt += cnt;
1084 *txidx = frag;
1085
1086 return(0);
1087}
1088
1089/*
1090 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1091 * to the mbuf data regions directly in the transmit lists. We also save a
1092 * copy of the pointers since the transmit list fragment pointers are
1093 * physical addresses.
1094 */
1095static void
1096pcn_start(ifp)
1097 struct ifnet *ifp;
1098{
1099 struct pcn_softc *sc;
1100
1101 sc = ifp->if_softc;
1102 PCN_LOCK(sc);
1103 pcn_start_locked(ifp);
1104 PCN_UNLOCK(sc);
1105}
1106
1107static void
1108pcn_start_locked(ifp)
1109 struct ifnet *ifp;
1110{
1111 struct pcn_softc *sc;
1112 struct mbuf *m_head = NULL;
1113 u_int32_t idx;
1114
1115 sc = ifp->if_softc;
1116
1117 PCN_LOCK_ASSERT(sc);
1118
1119 if (!sc->pcn_link)
1120 return;
1121
1122 idx = sc->pcn_cdata.pcn_tx_prod;
1123
1124 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1125 return;
1126
1127 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
1128 IF_DEQUEUE(&ifp->if_snd, m_head);
1129 if (m_head == NULL)
1130 break;
1131
1132 if (pcn_encap(sc, m_head, &idx)) {
1133 IF_PREPEND(&ifp->if_snd, m_head);
1134 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1135 break;
1136 }
1137
1138 /*
1139 * If there's a BPF listener, bounce a copy of this frame
1140 * to him.
1141 */
1142 BPF_MTAP(ifp, m_head);
1143
1144 }
1145
1146 /* Transmit */
1147 sc->pcn_cdata.pcn_tx_prod = idx;
1148 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
1149
1150 /*
1151 * Set a timeout in case the chip goes out to lunch.
1152 */
1153 sc->pcn_timer = 5;
1154
1155 return;
1156}
1157
1158static void
1159pcn_setfilt(ifp)
1160 struct ifnet *ifp;
1161{
1162 struct pcn_softc *sc;
1163
1164 sc = ifp->if_softc;
1165
1166 /* If we want promiscuous mode, set the allframes bit. */
1167 if (ifp->if_flags & IFF_PROMISC) {
1168 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1169 } else {
1170 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1171 }
1172
1173 /* Set the capture broadcast bit to capture broadcast frames. */
1174 if (ifp->if_flags & IFF_BROADCAST) {
1175 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1176 } else {
1177 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1178 }
1179
1180 return;
1181}
1182
1183static void
1184pcn_init(xsc)
1185 void *xsc;
1186{
1187 struct pcn_softc *sc = xsc;
1188
1189 PCN_LOCK(sc);
1190 pcn_init_locked(sc);
1191 PCN_UNLOCK(sc);
1192}
1193
1194static void
1195pcn_init_locked(sc)
1196 struct pcn_softc *sc;
1197{
1198 struct ifnet *ifp = sc->pcn_ifp;
1199 struct mii_data *mii = NULL;
1200 struct ifmedia_entry *ife;
1201
1202 PCN_LOCK_ASSERT(sc);
1203
1204 /*
1205 * Cancel pending I/O and free all RX/TX buffers.
1206 */
1207 pcn_stop(sc);
1208 pcn_reset(sc);
1209
1210 mii = device_get_softc(sc->pcn_miibus);
1211 ife = mii->mii_media.ifm_cur;
1212
1213 /* Set MAC address */
1214 pcn_csr_write(sc, PCN_CSR_PAR0,
1215 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[0]);
1216 pcn_csr_write(sc, PCN_CSR_PAR1,
1217 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[1]);
1218 pcn_csr_write(sc, PCN_CSR_PAR2,
1219 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[2]);
1220
1221 /* Init circular RX list. */
1222 if (pcn_list_rx_init(sc) == ENOBUFS) {
1223 if_printf(ifp, "initialization failed: no "
1224 "memory for rx buffers\n");
1225 pcn_stop(sc);
1226 return;
1227 }
1228
1229 /*
1230 * Init tx descriptors.
1231 */
1232 pcn_list_tx_init(sc);
1233
1234 /* Clear PCN_MISC_ASEL so we can set the port via PCN_CSR_MODE. */
1235 PCN_BCR_CLRBIT(sc, PCN_BCR_MISCCFG, PCN_MISC_ASEL);
1236
1237 /*
1238 * Set up the port based on the currently selected media.
1239 * For Am79C978 we've to unconditionally set PCN_PORT_MII and
1240 * set the PHY in PCN_BCR_PHYSEL instead.
1241 */
1242 if (sc->pcn_type != Am79C978 &&
1243 IFM_INST(ife->ifm_media) == sc->pcn_inst_10bt)
1244 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_10BASET);
1245 else
1246 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
1247
1248 /* Set up RX filter. */
1249 pcn_setfilt(ifp);
1250
1251 /*
1252 * Load the multicast filter.
1253 */
1254 pcn_setmulti(sc);
1255
1256 /*
1257 * Load the addresses of the RX and TX lists.
1258 */
1259 pcn_csr_write(sc, PCN_CSR_RXADDR0,
1260 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
1261 pcn_csr_write(sc, PCN_CSR_RXADDR1,
1262 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
1263 pcn_csr_write(sc, PCN_CSR_TXADDR0,
1264 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
1265 pcn_csr_write(sc, PCN_CSR_TXADDR1,
1266 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
1267
1268 /* Set the RX and TX ring sizes. */
1269 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
1270 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
1271
1272 /* We're not using the initialization block. */
1273 pcn_csr_write(sc, PCN_CSR_IAB1, 0);
1274
1275 /* Enable fast suspend mode. */
1276 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1277
1278 /*
1279 * Enable burst read and write. Also set the no underflow
1280 * bit. This will avoid transmit underruns in certain
1281 * conditions while still providing decent performance.
1282 */
1283 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
1284 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
1285
1286 /* Enable graceful recovery from underflow. */
1287 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1288
1289 /* Enable auto-padding of short TX frames. */
1290 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1291
1292 /* Disable MII autoneg (we handle this ourselves). */
1293 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
1294
1295 if (sc->pcn_type == Am79C978)
1296 /* XXX support other PHYs? */
1297 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
1298 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
1299
1300 /* Enable interrupts and start the controller running. */
1301 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
1302
1303 mii_mediachg(mii);
1304
1305 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1306 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1307
1308 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc);
1309
1310 return;
1311}
1312
1313/*
1314 * Set media options.
1315 */
1316static int
1317pcn_ifmedia_upd(ifp)
1318 struct ifnet *ifp;
1319{
1320 struct pcn_softc *sc;
1321
1322 sc = ifp->if_softc;
1323
1324 PCN_LOCK(sc);
1325
1326 /*
1327 * At least Am79C971 with DP83840A can wedge when switching
1328 * from the internal 10baseT PHY to the external PHY without
1329 * issuing pcn_reset(). For setting the port in PCN_CSR_MODE
1330 * the PCnet chip has to be powered down or stopped anyway
1331 * and although documented otherwise it doesn't take effect
1332 * until the next initialization.
1333 */
1334 sc->pcn_link = 0;
1335 pcn_stop(sc);
1336 pcn_reset(sc);
1337 pcn_init_locked(sc);
1338 if (ifp->if_snd.ifq_head != NULL)
1339 pcn_start_locked(ifp);
1340
1341 PCN_UNLOCK(sc);
1342
1343 return(0);
1344}
1345
1346/*
1347 * Report current media status.
1348 */
1349static void
1350pcn_ifmedia_sts(ifp, ifmr)
1351 struct ifnet *ifp;
1352 struct ifmediareq *ifmr;
1353{
1354 struct pcn_softc *sc;
1355 struct mii_data *mii;
1356
1357 sc = ifp->if_softc;
1358
1359 mii = device_get_softc(sc->pcn_miibus);
1360 PCN_LOCK(sc);
1361 mii_pollstat(mii);
1362 ifmr->ifm_active = mii->mii_media_active;
1363 ifmr->ifm_status = mii->mii_media_status;
1364 PCN_UNLOCK(sc);
1365
1366 return;
1367}
1368
1369static int
1370pcn_ioctl(ifp, command, data)
1371 struct ifnet *ifp;
1372 u_long command;
1373 caddr_t data;
1374{
1375 struct pcn_softc *sc = ifp->if_softc;
1376 struct ifreq *ifr = (struct ifreq *) data;
1377 struct mii_data *mii = NULL;
1378 int error = 0;
1379
1380 switch(command) {
1381 case SIOCSIFFLAGS:
1382 PCN_LOCK(sc);
1383 if (ifp->if_flags & IFF_UP) {
1384 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1385 ifp->if_flags & IFF_PROMISC &&
1386 !(sc->pcn_if_flags & IFF_PROMISC)) {
1387 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1388 PCN_EXTCTL1_SPND);
1389 pcn_setfilt(ifp);
1390 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1391 PCN_EXTCTL1_SPND);
1392 pcn_csr_write(sc, PCN_CSR_CSR,
1393 PCN_CSR_INTEN|PCN_CSR_START);
1394 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1395 !(ifp->if_flags & IFF_PROMISC) &&
1396 sc->pcn_if_flags & IFF_PROMISC) {
1397 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1398 PCN_EXTCTL1_SPND);
1399 pcn_setfilt(ifp);
1400 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1401 PCN_EXTCTL1_SPND);
1402 pcn_csr_write(sc, PCN_CSR_CSR,
1403 PCN_CSR_INTEN|PCN_CSR_START);
1404 } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1405 pcn_init_locked(sc);
1406 } else {
1407 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1408 pcn_stop(sc);
1409 }
1410 sc->pcn_if_flags = ifp->if_flags;
1411 PCN_UNLOCK(sc);
1412 error = 0;
1413 break;
1414 case SIOCADDMULTI:
1415 case SIOCDELMULTI:
1416 PCN_LOCK(sc);
1417 pcn_setmulti(sc);
1418 PCN_UNLOCK(sc);
1419 error = 0;
1420 break;
1421 case SIOCGIFMEDIA:
1422 case SIOCSIFMEDIA:
1423 mii = device_get_softc(sc->pcn_miibus);
1424 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1425 break;
1426 default:
1427 error = ether_ioctl(ifp, command, data);
1428 break;
1429 }
1430
1431 return(error);
1432}
1433
1434static void
1435pcn_watchdog(struct pcn_softc *sc)
1436{
1437 struct ifnet *ifp;
1438
1439 PCN_LOCK_ASSERT(sc);
1440 ifp = sc->pcn_ifp;
1441
1442 ifp->if_oerrors++;
1443 if_printf(ifp, "watchdog timeout\n");
1444
1445 pcn_stop(sc);
1446 pcn_reset(sc);
1447 pcn_init_locked(sc);
1448
1449 if (ifp->if_snd.ifq_head != NULL)
1450 pcn_start_locked(ifp);
1451}
1452
1453/*
1454 * Stop the adapter and free any mbufs allocated to the
1455 * RX and TX lists.
1456 */
1457static void
1458pcn_stop(struct pcn_softc *sc)
1459{
1460 register int i;
1461 struct ifnet *ifp;
1462
1463 PCN_LOCK_ASSERT(sc);
1464 ifp = sc->pcn_ifp;
1465 sc->pcn_timer = 0;
1466
1467 callout_stop(&sc->pcn_stat_callout);
1468
1469 /* Turn off interrupts */
1470 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
1471 /* Stop adapter */
1472 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
1473 sc->pcn_link = 0;
1474
1475 /*
1476 * Free data in the RX lists.
1477 */
1478 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
1479 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
1480 m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
1481 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
1482 }
1483 }
1484 bzero((char *)&sc->pcn_ldata->pcn_rx_list,
1485 sizeof(sc->pcn_ldata->pcn_rx_list));
1486
1487 /*
1488 * Free the TX list buffers.
1489 */
1490 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
1491 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
1492 m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
1493 sc->pcn_cdata.pcn_tx_chain[i] = NULL;
1494 }
1495 }
1496
1497 bzero((char *)&sc->pcn_ldata->pcn_tx_list,
1498 sizeof(sc->pcn_ldata->pcn_tx_list));
1499
1500 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1501
1502 return;
1503}
1504
1505/*
1506 * Stop all chip I/O so that the kernel's probe routines don't
1507 * get confused by errant DMAs when rebooting.
1508 */
1509static int
1510pcn_shutdown(device_t dev)
1511{
1512 struct pcn_softc *sc;
1513
1514 sc = device_get_softc(dev);
1515
1516 PCN_LOCK(sc);
1517 pcn_reset(sc);
1518 pcn_stop(sc);
1519 PCN_UNLOCK(sc);
1520
1521 return 0;
1522}
2 * Copyright (c) 2000 Berkeley Software Design, Inc.
3 * Copyright (c) 1997, 1998, 1999, 2000
4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/pcn/if_pcn.c 221407 2011-05-03 19:51:29Z marius $");
36
37/*
38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available
39 * from http://www.amd.com.
40 *
41 * The AMD PCnet/PCI controllers are more advanced and functional
42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
43 * backwards compatibility with the LANCE and thus can be made
44 * to work with older LANCE drivers. This is in fact how the
45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble
46 * is that the PCnet/PCI devices offer several performance enhancements
47 * which can't be exploited in LANCE compatibility mode. Chief among
48 * these enhancements is the ability to perform PCI DMA operations
49 * using 32-bit addressing (which eliminates the need for ISA
50 * bounce-buffering), and special receive buffer alignment (which
51 * allows the receive handler to pass packets to the upper protocol
52 * layers without copying on both the x86 and alpha platforms).
53 */
54
55#include <sys/param.h>
56#include <sys/systm.h>
57#include <sys/sockio.h>
58#include <sys/mbuf.h>
59#include <sys/malloc.h>
60#include <sys/kernel.h>
61#include <sys/module.h>
62#include <sys/socket.h>
63
64#include <net/if.h>
65#include <net/if_arp.h>
66#include <net/ethernet.h>
67#include <net/if_dl.h>
68#include <net/if_media.h>
69#include <net/if_types.h>
70
71#include <net/bpf.h>
72
73#include <vm/vm.h> /* for vtophys */
74#include <vm/pmap.h> /* for vtophys */
75#include <machine/bus.h>
76#include <machine/resource.h>
77#include <sys/bus.h>
78#include <sys/rman.h>
79
80#include <dev/mii/mii.h>
81#include <dev/mii/miivar.h>
82
83#include <dev/pci/pcireg.h>
84#include <dev/pci/pcivar.h>
85
86#define PCN_USEIOSPACE
87
88#include <dev/pcn/if_pcnreg.h>
89
90MODULE_DEPEND(pcn, pci, 1, 1, 1);
91MODULE_DEPEND(pcn, ether, 1, 1, 1);
92MODULE_DEPEND(pcn, miibus, 1, 1, 1);
93
94/* "device miibus" required. See GENERIC if you get errors here. */
95#include "miibus_if.h"
96
97/*
98 * Various supported device vendors/types and their names.
99 */
100static const struct pcn_type pcn_devs[] = {
101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
103 { 0, 0, NULL }
104};
105
106static const struct pcn_chipid {
107 u_int32_t id;
108 const char *name;
109} pcn_chipid[] = {
110 { Am79C971, "Am79C971" },
111 { Am79C972, "Am79C972" },
112 { Am79C973, "Am79C973" },
113 { Am79C978, "Am79C978" },
114 { Am79C975, "Am79C975" },
115 { Am79C976, "Am79C976" },
116 { 0, NULL },
117};
118
119static const char *pcn_chipid_name(u_int32_t);
120static u_int32_t pcn_chip_id(device_t);
121static const struct pcn_type *pcn_match(u_int16_t, u_int16_t);
122
123static u_int32_t pcn_csr_read(struct pcn_softc *, int);
124static u_int16_t pcn_csr_read16(struct pcn_softc *, int);
125static u_int16_t pcn_bcr_read16(struct pcn_softc *, int);
126static void pcn_csr_write(struct pcn_softc *, int, int);
127static u_int32_t pcn_bcr_read(struct pcn_softc *, int);
128static void pcn_bcr_write(struct pcn_softc *, int, int);
129
130static int pcn_probe(device_t);
131static int pcn_attach(device_t);
132static int pcn_detach(device_t);
133
134static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *);
135static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *);
136static void pcn_rxeof(struct pcn_softc *);
137static void pcn_txeof(struct pcn_softc *);
138static void pcn_intr(void *);
139static void pcn_tick(void *);
140static void pcn_start(struct ifnet *);
141static void pcn_start_locked(struct ifnet *);
142static int pcn_ioctl(struct ifnet *, u_long, caddr_t);
143static void pcn_init(void *);
144static void pcn_init_locked(struct pcn_softc *);
145static void pcn_stop(struct pcn_softc *);
146static void pcn_watchdog(struct pcn_softc *);
147static int pcn_shutdown(device_t);
148static int pcn_ifmedia_upd(struct ifnet *);
149static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *);
150
151static int pcn_miibus_readreg(device_t, int, int);
152static int pcn_miibus_writereg(device_t, int, int, int);
153static void pcn_miibus_statchg(device_t);
154
155static void pcn_setfilt(struct ifnet *);
156static void pcn_setmulti(struct pcn_softc *);
157static void pcn_reset(struct pcn_softc *);
158static int pcn_list_rx_init(struct pcn_softc *);
159static int pcn_list_tx_init(struct pcn_softc *);
160
161#ifdef PCN_USEIOSPACE
162#define PCN_RES SYS_RES_IOPORT
163#define PCN_RID PCN_PCI_LOIO
164#else
165#define PCN_RES SYS_RES_MEMORY
166#define PCN_RID PCN_PCI_LOMEM
167#endif
168
169static device_method_t pcn_methods[] = {
170 /* Device interface */
171 DEVMETHOD(device_probe, pcn_probe),
172 DEVMETHOD(device_attach, pcn_attach),
173 DEVMETHOD(device_detach, pcn_detach),
174 DEVMETHOD(device_shutdown, pcn_shutdown),
175
176 /* bus interface */
177 DEVMETHOD(bus_print_child, bus_generic_print_child),
178 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
179
180 /* MII interface */
181 DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
182 DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
183 DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
184
185 { 0, 0 }
186};
187
188static driver_t pcn_driver = {
189 "pcn",
190 pcn_methods,
191 sizeof(struct pcn_softc)
192};
193
194static devclass_t pcn_devclass;
195
196DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0);
197DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
198
199#define PCN_CSR_SETBIT(sc, reg, x) \
200 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
201
202#define PCN_CSR_CLRBIT(sc, reg, x) \
203 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
204
205#define PCN_BCR_SETBIT(sc, reg, x) \
206 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
207
208#define PCN_BCR_CLRBIT(sc, reg, x) \
209 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
210
211static u_int32_t
212pcn_csr_read(sc, reg)
213 struct pcn_softc *sc;
214 int reg;
215{
216 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
217 return(CSR_READ_4(sc, PCN_IO32_RDP));
218}
219
220static u_int16_t
221pcn_csr_read16(sc, reg)
222 struct pcn_softc *sc;
223 int reg;
224{
225 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
226 return(CSR_READ_2(sc, PCN_IO16_RDP));
227}
228
229static void
230pcn_csr_write(sc, reg, val)
231 struct pcn_softc *sc;
232 int reg;
233 int val;
234{
235 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
236 CSR_WRITE_4(sc, PCN_IO32_RDP, val);
237 return;
238}
239
240static u_int32_t
241pcn_bcr_read(sc, reg)
242 struct pcn_softc *sc;
243 int reg;
244{
245 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
246 return(CSR_READ_4(sc, PCN_IO32_BDP));
247}
248
249static u_int16_t
250pcn_bcr_read16(sc, reg)
251 struct pcn_softc *sc;
252 int reg;
253{
254 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
255 return(CSR_READ_2(sc, PCN_IO16_BDP));
256}
257
258static void
259pcn_bcr_write(sc, reg, val)
260 struct pcn_softc *sc;
261 int reg;
262 int val;
263{
264 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
265 CSR_WRITE_4(sc, PCN_IO32_BDP, val);
266 return;
267}
268
269static int
270pcn_miibus_readreg(dev, phy, reg)
271 device_t dev;
272 int phy, reg;
273{
274 struct pcn_softc *sc;
275 int val;
276
277 sc = device_get_softc(dev);
278
279 /*
280 * At least Am79C971 with DP83840A wedge when isolating the
281 * external PHY so we can't allow multiple external PHYs.
282 * There are cards that use Am79C971 with both the internal
283 * and an external PHY though.
284 * For internal PHYs it doesn't really matter whether we can
285 * isolate the remaining internal and the external ones in
286 * the PHY drivers as the internal PHYs have to be enabled
287 * individually in PCN_BCR_PHYSEL, PCN_CSR_MODE, etc.
288 * With Am79C97{3,5,8} we don't support switching beetween
289 * the internal and external PHYs, yet, so we can't allow
290 * multiple PHYs with these either.
291 * Am79C97{2,6} actually only support external PHYs (not
292 * connectable internal ones respond at the usual addresses,
293 * which don't hurt if we let them show up on the bus) and
294 * isolating them works.
295 */
296 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) ||
297 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 ||
298 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr != -1 &&
299 phy != sc->pcn_extphyaddr)
300 return(0);
301
302 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
303 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
304 if (val == 0xFFFF)
305 return(0);
306
307 if (((sc->pcn_type == Am79C971 && phy != PCN_PHYAD_10BT) ||
308 sc->pcn_type == Am79C973 || sc->pcn_type == Am79C975 ||
309 sc->pcn_type == Am79C978) && sc->pcn_extphyaddr == -1)
310 sc->pcn_extphyaddr = phy;
311
312 return(val);
313}
314
315static int
316pcn_miibus_writereg(dev, phy, reg, data)
317 device_t dev;
318 int phy, reg, data;
319{
320 struct pcn_softc *sc;
321
322 sc = device_get_softc(dev);
323
324 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
325 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
326
327 return(0);
328}
329
330static void
331pcn_miibus_statchg(dev)
332 device_t dev;
333{
334 struct pcn_softc *sc;
335 struct mii_data *mii;
336
337 sc = device_get_softc(dev);
338 mii = device_get_softc(sc->pcn_miibus);
339
340 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
341 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
342 } else {
343 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
344 }
345
346 return;
347}
348
349static void
350pcn_setmulti(sc)
351 struct pcn_softc *sc;
352{
353 struct ifnet *ifp;
354 struct ifmultiaddr *ifma;
355 u_int32_t h, i;
356 u_int16_t hashes[4] = { 0, 0, 0, 0 };
357
358 ifp = sc->pcn_ifp;
359
360 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
361
362 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
363 for (i = 0; i < 4; i++)
364 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
365 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
366 return;
367 }
368
369 /* first, zot all the existing hash bits */
370 for (i = 0; i < 4; i++)
371 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
372
373 /* now program new ones */
374 if_maddr_rlock(ifp);
375 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
376 if (ifma->ifma_addr->sa_family != AF_LINK)
377 continue;
378 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
379 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
380 hashes[h >> 4] |= 1 << (h & 0xF);
381 }
382 if_maddr_runlock(ifp);
383
384 for (i = 0; i < 4; i++)
385 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
386
387 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
388
389 return;
390}
391
392static void
393pcn_reset(sc)
394 struct pcn_softc *sc;
395{
396 /*
397 * Issue a reset by reading from the RESET register.
398 * Note that we don't know if the chip is operating in
399 * 16-bit or 32-bit mode at this point, so we attempt
400 * to reset the chip both ways. If one fails, the other
401 * will succeed.
402 */
403 CSR_READ_2(sc, PCN_IO16_RESET);
404 CSR_READ_4(sc, PCN_IO32_RESET);
405
406 /* Wait a little while for the chip to get its brains in order. */
407 DELAY(1000);
408
409 /* Select 32-bit (DWIO) mode */
410 CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
411
412 /* Select software style 3. */
413 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
414
415 return;
416}
417
418static const char *
419pcn_chipid_name(u_int32_t id)
420{
421 const struct pcn_chipid *p;
422
423 p = pcn_chipid;
424 while (p->name) {
425 if (id == p->id)
426 return (p->name);
427 p++;
428 }
429 return ("Unknown");
430}
431
432static u_int32_t
433pcn_chip_id(device_t dev)
434{
435 struct pcn_softc *sc;
436 u_int32_t chip_id;
437
438 sc = device_get_softc(dev);
439 /*
440 * Note: we can *NOT* put the chip into
441 * 32-bit mode yet. The le(4) driver will only
442 * work in 16-bit mode, and once the chip
443 * goes into 32-bit mode, the only way to
444 * get it out again is with a hardware reset.
445 * So if pcn_probe() is called before the
446 * le(4) driver's probe routine, the chip will
447 * be locked into 32-bit operation and the
448 * le(4) driver will be unable to attach to it.
449 * Note II: if the chip happens to already
450 * be in 32-bit mode, we still need to check
451 * the chip ID, but first we have to detect
452 * 32-bit mode using only 16-bit operations.
453 * The safest way to do this is to read the
454 * PCI subsystem ID from BCR23/24 and compare
455 * that with the value read from PCI config
456 * space.
457 */
458 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
459 chip_id <<= 16;
460 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
461 /*
462 * Note III: the test for 0x10001000 is a hack to
463 * pacify VMware, who's pseudo-PCnet interface is
464 * broken. Reading the subsystem register from PCI
465 * config space yields 0x00000000 while reading the
466 * same value from I/O space yields 0x10001000. It's
467 * not supposed to be that way.
468 */
469 if (chip_id == pci_read_config(dev,
470 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
471 /* We're in 16-bit mode. */
472 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
473 chip_id <<= 16;
474 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
475 } else {
476 /* We're in 32-bit mode. */
477 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
478 chip_id <<= 16;
479 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
480 }
481
482 return (chip_id);
483}
484
485static const struct pcn_type *
486pcn_match(u_int16_t vid, u_int16_t did)
487{
488 const struct pcn_type *t;
489
490 t = pcn_devs;
491 while (t->pcn_name != NULL) {
492 if ((vid == t->pcn_vid) && (did == t->pcn_did))
493 return (t);
494 t++;
495 }
496 return (NULL);
497}
498
499/*
500 * Probe for an AMD chip. Check the PCI vendor and device
501 * IDs against our list and return a device name if we find a match.
502 */
503static int
504pcn_probe(dev)
505 device_t dev;
506{
507 const struct pcn_type *t;
508 struct pcn_softc *sc;
509 int rid;
510 u_int32_t chip_id;
511
512 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev));
513 if (t == NULL)
514 return (ENXIO);
515 sc = device_get_softc(dev);
516
517 /*
518 * Temporarily map the I/O space so we can read the chip ID register.
519 */
520 rid = PCN_RID;
521 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
522 if (sc->pcn_res == NULL) {
523 device_printf(dev, "couldn't map ports/memory\n");
524 return(ENXIO);
525 }
526 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
527 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
528
529 chip_id = pcn_chip_id(dev);
530
531 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
532
533 switch((chip_id >> 12) & PART_MASK) {
534 case Am79C971:
535 case Am79C972:
536 case Am79C973:
537 case Am79C975:
538 case Am79C976:
539 case Am79C978:
540 break;
541 default:
542 return(ENXIO);
543 }
544 device_set_desc(dev, t->pcn_name);
545 return(BUS_PROBE_DEFAULT);
546}
547
548/*
549 * Attach the interface. Allocate softc structures, do ifmedia
550 * setup and ethernet/BPF attach.
551 */
552static int
553pcn_attach(dev)
554 device_t dev;
555{
556 u_int32_t eaddr[2];
557 struct pcn_softc *sc;
558 struct mii_data *mii;
559 struct mii_softc *miisc;
560 struct ifnet *ifp;
561 int error = 0, rid;
562
563 sc = device_get_softc(dev);
564
565 /* Initialize our mutex. */
566 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
567 MTX_DEF);
568 /*
569 * Map control/status registers.
570 */
571 pci_enable_busmaster(dev);
572
573 /* Retrieve the chip ID */
574 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK;
575 device_printf(dev, "Chip ID %04x (%s)\n",
576 sc->pcn_type, pcn_chipid_name(sc->pcn_type));
577
578 rid = PCN_RID;
579 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
580
581 if (sc->pcn_res == NULL) {
582 device_printf(dev, "couldn't map ports/memory\n");
583 error = ENXIO;
584 goto fail;
585 }
586
587 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
588 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
589
590 /* Allocate interrupt */
591 rid = 0;
592 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
593 RF_SHAREABLE | RF_ACTIVE);
594
595 if (sc->pcn_irq == NULL) {
596 device_printf(dev, "couldn't map interrupt\n");
597 error = ENXIO;
598 goto fail;
599 }
600
601 /* Reset the adapter. */
602 pcn_reset(sc);
603
604 /*
605 * Get station address from the EEPROM.
606 */
607 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00);
608 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01);
609
610 callout_init_mtx(&sc->pcn_stat_callout, &sc->pcn_mtx, 0);
611
612 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
613 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
614
615 if (sc->pcn_ldata == NULL) {
616 device_printf(dev, "no memory for list buffers!\n");
617 error = ENXIO;
618 goto fail;
619 }
620 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
621
622 ifp = sc->pcn_ifp = if_alloc(IFT_ETHER);
623 if (ifp == NULL) {
624 device_printf(dev, "can not if_alloc()\n");
625 error = ENOSPC;
626 goto fail;
627 }
628 ifp->if_softc = sc;
629 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
630 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
631 ifp->if_ioctl = pcn_ioctl;
632 ifp->if_start = pcn_start;
633 ifp->if_init = pcn_init;
634 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1;
635
636 /*
637 * Do MII setup.
638 * See the comment in pcn_miibus_readreg() for why we can't
639 * universally pass MIIF_NOISOLATE here.
640 */
641 sc->pcn_extphyaddr = -1;
642 error = mii_attach(dev, &sc->pcn_miibus, ifp, pcn_ifmedia_upd,
643 pcn_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
644 if (error != 0) {
645 device_printf(dev, "attaching PHYs failed\n");
646 goto fail;
647 }
648 /*
649 * Record the media instances of internal PHYs, which map the
650 * built-in interfaces to the MII, so we can set the active
651 * PHY/port based on the currently selected media.
652 */
653 sc->pcn_inst_10bt = -1;
654 mii = device_get_softc(sc->pcn_miibus);
655 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
656 switch (miisc->mii_phy) {
657 case PCN_PHYAD_10BT:
658 sc->pcn_inst_10bt = miisc->mii_inst;
659 break;
660 /*
661 * XXX deal with the Am79C97{3,5} internal 100baseT
662 * and the Am79C978 internal HomePNA PHYs.
663 */
664 }
665 }
666
667 /*
668 * Call MI attach routine.
669 */
670 ether_ifattach(ifp, (u_int8_t *) eaddr);
671
672 /* Hook interrupt last to avoid having to lock softc */
673 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET | INTR_MPSAFE,
674 NULL, pcn_intr, sc, &sc->pcn_intrhand);
675
676 if (error) {
677 device_printf(dev, "couldn't set up irq\n");
678 ether_ifdetach(ifp);
679 goto fail;
680 }
681
682fail:
683 if (error)
684 pcn_detach(dev);
685
686 return(error);
687}
688
689/*
690 * Shutdown hardware and free up resources. This can be called any
691 * time after the mutex has been initialized. It is called in both
692 * the error case in attach and the normal detach case so it needs
693 * to be careful about only freeing resources that have actually been
694 * allocated.
695 */
696static int
697pcn_detach(dev)
698 device_t dev;
699{
700 struct pcn_softc *sc;
701 struct ifnet *ifp;
702
703 sc = device_get_softc(dev);
704 ifp = sc->pcn_ifp;
705
706 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized"));
707
708 /* These should only be active if attach succeeded */
709 if (device_is_attached(dev)) {
710 PCN_LOCK(sc);
711 pcn_reset(sc);
712 pcn_stop(sc);
713 PCN_UNLOCK(sc);
714 callout_drain(&sc->pcn_stat_callout);
715 ether_ifdetach(ifp);
716 }
717 if (sc->pcn_miibus)
718 device_delete_child(dev, sc->pcn_miibus);
719 bus_generic_detach(dev);
720
721 if (sc->pcn_intrhand)
722 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
723 if (sc->pcn_irq)
724 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
725 if (sc->pcn_res)
726 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
727
728 if (ifp)
729 if_free(ifp);
730
731 if (sc->pcn_ldata) {
732 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
733 M_DEVBUF);
734 }
735
736 mtx_destroy(&sc->pcn_mtx);
737
738 return(0);
739}
740
741/*
742 * Initialize the transmit descriptors.
743 */
744static int
745pcn_list_tx_init(sc)
746 struct pcn_softc *sc;
747{
748 struct pcn_list_data *ld;
749 struct pcn_ring_data *cd;
750 int i;
751
752 cd = &sc->pcn_cdata;
753 ld = sc->pcn_ldata;
754
755 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
756 cd->pcn_tx_chain[i] = NULL;
757 ld->pcn_tx_list[i].pcn_tbaddr = 0;
758 ld->pcn_tx_list[i].pcn_txctl = 0;
759 ld->pcn_tx_list[i].pcn_txstat = 0;
760 }
761
762 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
763
764 return(0);
765}
766
767
768/*
769 * Initialize the RX descriptors and allocate mbufs for them.
770 */
771static int
772pcn_list_rx_init(sc)
773 struct pcn_softc *sc;
774{
775 struct pcn_ring_data *cd;
776 int i;
777
778 cd = &sc->pcn_cdata;
779
780 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
781 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
782 return(ENOBUFS);
783 }
784
785 cd->pcn_rx_prod = 0;
786
787 return(0);
788}
789
790/*
791 * Initialize an RX descriptor and attach an MBUF cluster.
792 */
793static int
794pcn_newbuf(sc, idx, m)
795 struct pcn_softc *sc;
796 int idx;
797 struct mbuf *m;
798{
799 struct mbuf *m_new = NULL;
800 struct pcn_rx_desc *c;
801
802 c = &sc->pcn_ldata->pcn_rx_list[idx];
803
804 if (m == NULL) {
805 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
806 if (m_new == NULL)
807 return(ENOBUFS);
808
809 MCLGET(m_new, M_DONTWAIT);
810 if (!(m_new->m_flags & M_EXT)) {
811 m_freem(m_new);
812 return(ENOBUFS);
813 }
814 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
815 } else {
816 m_new = m;
817 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
818 m_new->m_data = m_new->m_ext.ext_buf;
819 }
820
821 m_adj(m_new, ETHER_ALIGN);
822
823 sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
824 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
825 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
826 c->pcn_bufsz |= PCN_RXLEN_MBO;
827 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
828
829 return(0);
830}
831
832/*
833 * A frame has been uploaded: pass the resulting mbuf chain up to
834 * the higher level protocols.
835 */
836static void
837pcn_rxeof(sc)
838 struct pcn_softc *sc;
839{
840 struct mbuf *m;
841 struct ifnet *ifp;
842 struct pcn_rx_desc *cur_rx;
843 int i;
844
845 PCN_LOCK_ASSERT(sc);
846
847 ifp = sc->pcn_ifp;
848 i = sc->pcn_cdata.pcn_rx_prod;
849
850 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
851 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
852 m = sc->pcn_cdata.pcn_rx_chain[i];
853 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
854
855 /*
856 * If an error occurs, update stats, clear the
857 * status word and leave the mbuf cluster in place:
858 * it should simply get re-used next time this descriptor
859 * comes up in the ring.
860 */
861 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
862 ifp->if_ierrors++;
863 pcn_newbuf(sc, i, m);
864 PCN_INC(i, PCN_RX_LIST_CNT);
865 continue;
866 }
867
868 if (pcn_newbuf(sc, i, NULL)) {
869 /* Ran out of mbufs; recycle this one. */
870 pcn_newbuf(sc, i, m);
871 ifp->if_ierrors++;
872 PCN_INC(i, PCN_RX_LIST_CNT);
873 continue;
874 }
875
876 PCN_INC(i, PCN_RX_LIST_CNT);
877
878 /* No errors; receive the packet. */
879 ifp->if_ipackets++;
880 m->m_len = m->m_pkthdr.len =
881 cur_rx->pcn_rxlen - ETHER_CRC_LEN;
882 m->m_pkthdr.rcvif = ifp;
883
884 PCN_UNLOCK(sc);
885 (*ifp->if_input)(ifp, m);
886 PCN_LOCK(sc);
887 }
888
889 sc->pcn_cdata.pcn_rx_prod = i;
890
891 return;
892}
893
894/*
895 * A frame was downloaded to the chip. It's safe for us to clean up
896 * the list buffers.
897 */
898
899static void
900pcn_txeof(sc)
901 struct pcn_softc *sc;
902{
903 struct pcn_tx_desc *cur_tx = NULL;
904 struct ifnet *ifp;
905 u_int32_t idx;
906
907 ifp = sc->pcn_ifp;
908
909 /*
910 * Go through our tx list and free mbufs for those
911 * frames that have been transmitted.
912 */
913 idx = sc->pcn_cdata.pcn_tx_cons;
914 while (idx != sc->pcn_cdata.pcn_tx_prod) {
915 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
916
917 if (!PCN_OWN_TXDESC(cur_tx))
918 break;
919
920 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
921 sc->pcn_cdata.pcn_tx_cnt--;
922 PCN_INC(idx, PCN_TX_LIST_CNT);
923 continue;
924 }
925
926 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
927 ifp->if_oerrors++;
928 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
929 ifp->if_collisions++;
930 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
931 ifp->if_collisions++;
932 }
933
934 ifp->if_collisions +=
935 cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
936
937 ifp->if_opackets++;
938 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
939 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
940 sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
941 }
942
943 sc->pcn_cdata.pcn_tx_cnt--;
944 PCN_INC(idx, PCN_TX_LIST_CNT);
945 }
946
947 if (idx != sc->pcn_cdata.pcn_tx_cons) {
948 /* Some buffers have been freed. */
949 sc->pcn_cdata.pcn_tx_cons = idx;
950 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
951 }
952 sc->pcn_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
953
954 return;
955}
956
957static void
958pcn_tick(xsc)
959 void *xsc;
960{
961 struct pcn_softc *sc;
962 struct mii_data *mii;
963 struct ifnet *ifp;
964
965 sc = xsc;
966 ifp = sc->pcn_ifp;
967 PCN_LOCK_ASSERT(sc);
968
969 mii = device_get_softc(sc->pcn_miibus);
970 mii_tick(mii);
971
972 /* link just died */
973 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
974 sc->pcn_link = 0;
975
976 /* link just came up, restart */
977 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE &&
978 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
979 sc->pcn_link++;
980 if (ifp->if_snd.ifq_head != NULL)
981 pcn_start_locked(ifp);
982 }
983
984 if (sc->pcn_timer > 0 && --sc->pcn_timer == 0)
985 pcn_watchdog(sc);
986 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc);
987
988 return;
989}
990
991static void
992pcn_intr(arg)
993 void *arg;
994{
995 struct pcn_softc *sc;
996 struct ifnet *ifp;
997 u_int32_t status;
998
999 sc = arg;
1000 ifp = sc->pcn_ifp;
1001
1002 PCN_LOCK(sc);
1003
1004 /* Suppress unwanted interrupts */
1005 if (!(ifp->if_flags & IFF_UP)) {
1006 pcn_stop(sc);
1007 PCN_UNLOCK(sc);
1008 return;
1009 }
1010
1011 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
1012
1013 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
1014 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
1015
1016 if (status & PCN_CSR_RINT)
1017 pcn_rxeof(sc);
1018
1019 if (status & PCN_CSR_TINT)
1020 pcn_txeof(sc);
1021
1022 if (status & PCN_CSR_ERR) {
1023 pcn_init_locked(sc);
1024 break;
1025 }
1026 }
1027
1028 if (ifp->if_snd.ifq_head != NULL)
1029 pcn_start_locked(ifp);
1030
1031 PCN_UNLOCK(sc);
1032 return;
1033}
1034
1035/*
1036 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1037 * pointers to the fragment pointers.
1038 */
1039static int
1040pcn_encap(sc, m_head, txidx)
1041 struct pcn_softc *sc;
1042 struct mbuf *m_head;
1043 u_int32_t *txidx;
1044{
1045 struct pcn_tx_desc *f = NULL;
1046 struct mbuf *m;
1047 int frag, cur, cnt = 0;
1048
1049 /*
1050 * Start packing the mbufs in this chain into
1051 * the fragment pointers. Stop when we run out
1052 * of fragments or hit the end of the mbuf chain.
1053 */
1054 m = m_head;
1055 cur = frag = *txidx;
1056
1057 for (m = m_head; m != NULL; m = m->m_next) {
1058 if (m->m_len == 0)
1059 continue;
1060
1061 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
1062 return(ENOBUFS);
1063 f = &sc->pcn_ldata->pcn_tx_list[frag];
1064 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
1065 f->pcn_txctl |= PCN_TXCTL_MBO;
1066 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
1067 if (cnt == 0)
1068 f->pcn_txctl |= PCN_TXCTL_STP;
1069 else
1070 f->pcn_txctl |= PCN_TXCTL_OWN;
1071 cur = frag;
1072 PCN_INC(frag, PCN_TX_LIST_CNT);
1073 cnt++;
1074 }
1075
1076 if (m != NULL)
1077 return(ENOBUFS);
1078
1079 sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
1080 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
1081 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
1082 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
1083 sc->pcn_cdata.pcn_tx_cnt += cnt;
1084 *txidx = frag;
1085
1086 return(0);
1087}
1088
1089/*
1090 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1091 * to the mbuf data regions directly in the transmit lists. We also save a
1092 * copy of the pointers since the transmit list fragment pointers are
1093 * physical addresses.
1094 */
1095static void
1096pcn_start(ifp)
1097 struct ifnet *ifp;
1098{
1099 struct pcn_softc *sc;
1100
1101 sc = ifp->if_softc;
1102 PCN_LOCK(sc);
1103 pcn_start_locked(ifp);
1104 PCN_UNLOCK(sc);
1105}
1106
1107static void
1108pcn_start_locked(ifp)
1109 struct ifnet *ifp;
1110{
1111 struct pcn_softc *sc;
1112 struct mbuf *m_head = NULL;
1113 u_int32_t idx;
1114
1115 sc = ifp->if_softc;
1116
1117 PCN_LOCK_ASSERT(sc);
1118
1119 if (!sc->pcn_link)
1120 return;
1121
1122 idx = sc->pcn_cdata.pcn_tx_prod;
1123
1124 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1125 return;
1126
1127 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
1128 IF_DEQUEUE(&ifp->if_snd, m_head);
1129 if (m_head == NULL)
1130 break;
1131
1132 if (pcn_encap(sc, m_head, &idx)) {
1133 IF_PREPEND(&ifp->if_snd, m_head);
1134 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1135 break;
1136 }
1137
1138 /*
1139 * If there's a BPF listener, bounce a copy of this frame
1140 * to him.
1141 */
1142 BPF_MTAP(ifp, m_head);
1143
1144 }
1145
1146 /* Transmit */
1147 sc->pcn_cdata.pcn_tx_prod = idx;
1148 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
1149
1150 /*
1151 * Set a timeout in case the chip goes out to lunch.
1152 */
1153 sc->pcn_timer = 5;
1154
1155 return;
1156}
1157
1158static void
1159pcn_setfilt(ifp)
1160 struct ifnet *ifp;
1161{
1162 struct pcn_softc *sc;
1163
1164 sc = ifp->if_softc;
1165
1166 /* If we want promiscuous mode, set the allframes bit. */
1167 if (ifp->if_flags & IFF_PROMISC) {
1168 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1169 } else {
1170 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1171 }
1172
1173 /* Set the capture broadcast bit to capture broadcast frames. */
1174 if (ifp->if_flags & IFF_BROADCAST) {
1175 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1176 } else {
1177 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1178 }
1179
1180 return;
1181}
1182
1183static void
1184pcn_init(xsc)
1185 void *xsc;
1186{
1187 struct pcn_softc *sc = xsc;
1188
1189 PCN_LOCK(sc);
1190 pcn_init_locked(sc);
1191 PCN_UNLOCK(sc);
1192}
1193
1194static void
1195pcn_init_locked(sc)
1196 struct pcn_softc *sc;
1197{
1198 struct ifnet *ifp = sc->pcn_ifp;
1199 struct mii_data *mii = NULL;
1200 struct ifmedia_entry *ife;
1201
1202 PCN_LOCK_ASSERT(sc);
1203
1204 /*
1205 * Cancel pending I/O and free all RX/TX buffers.
1206 */
1207 pcn_stop(sc);
1208 pcn_reset(sc);
1209
1210 mii = device_get_softc(sc->pcn_miibus);
1211 ife = mii->mii_media.ifm_cur;
1212
1213 /* Set MAC address */
1214 pcn_csr_write(sc, PCN_CSR_PAR0,
1215 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[0]);
1216 pcn_csr_write(sc, PCN_CSR_PAR1,
1217 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[1]);
1218 pcn_csr_write(sc, PCN_CSR_PAR2,
1219 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[2]);
1220
1221 /* Init circular RX list. */
1222 if (pcn_list_rx_init(sc) == ENOBUFS) {
1223 if_printf(ifp, "initialization failed: no "
1224 "memory for rx buffers\n");
1225 pcn_stop(sc);
1226 return;
1227 }
1228
1229 /*
1230 * Init tx descriptors.
1231 */
1232 pcn_list_tx_init(sc);
1233
1234 /* Clear PCN_MISC_ASEL so we can set the port via PCN_CSR_MODE. */
1235 PCN_BCR_CLRBIT(sc, PCN_BCR_MISCCFG, PCN_MISC_ASEL);
1236
1237 /*
1238 * Set up the port based on the currently selected media.
1239 * For Am79C978 we've to unconditionally set PCN_PORT_MII and
1240 * set the PHY in PCN_BCR_PHYSEL instead.
1241 */
1242 if (sc->pcn_type != Am79C978 &&
1243 IFM_INST(ife->ifm_media) == sc->pcn_inst_10bt)
1244 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_10BASET);
1245 else
1246 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
1247
1248 /* Set up RX filter. */
1249 pcn_setfilt(ifp);
1250
1251 /*
1252 * Load the multicast filter.
1253 */
1254 pcn_setmulti(sc);
1255
1256 /*
1257 * Load the addresses of the RX and TX lists.
1258 */
1259 pcn_csr_write(sc, PCN_CSR_RXADDR0,
1260 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
1261 pcn_csr_write(sc, PCN_CSR_RXADDR1,
1262 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
1263 pcn_csr_write(sc, PCN_CSR_TXADDR0,
1264 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
1265 pcn_csr_write(sc, PCN_CSR_TXADDR1,
1266 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
1267
1268 /* Set the RX and TX ring sizes. */
1269 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
1270 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
1271
1272 /* We're not using the initialization block. */
1273 pcn_csr_write(sc, PCN_CSR_IAB1, 0);
1274
1275 /* Enable fast suspend mode. */
1276 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1277
1278 /*
1279 * Enable burst read and write. Also set the no underflow
1280 * bit. This will avoid transmit underruns in certain
1281 * conditions while still providing decent performance.
1282 */
1283 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
1284 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
1285
1286 /* Enable graceful recovery from underflow. */
1287 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1288
1289 /* Enable auto-padding of short TX frames. */
1290 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1291
1292 /* Disable MII autoneg (we handle this ourselves). */
1293 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
1294
1295 if (sc->pcn_type == Am79C978)
1296 /* XXX support other PHYs? */
1297 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
1298 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
1299
1300 /* Enable interrupts and start the controller running. */
1301 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
1302
1303 mii_mediachg(mii);
1304
1305 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1306 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1307
1308 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc);
1309
1310 return;
1311}
1312
1313/*
1314 * Set media options.
1315 */
1316static int
1317pcn_ifmedia_upd(ifp)
1318 struct ifnet *ifp;
1319{
1320 struct pcn_softc *sc;
1321
1322 sc = ifp->if_softc;
1323
1324 PCN_LOCK(sc);
1325
1326 /*
1327 * At least Am79C971 with DP83840A can wedge when switching
1328 * from the internal 10baseT PHY to the external PHY without
1329 * issuing pcn_reset(). For setting the port in PCN_CSR_MODE
1330 * the PCnet chip has to be powered down or stopped anyway
1331 * and although documented otherwise it doesn't take effect
1332 * until the next initialization.
1333 */
1334 sc->pcn_link = 0;
1335 pcn_stop(sc);
1336 pcn_reset(sc);
1337 pcn_init_locked(sc);
1338 if (ifp->if_snd.ifq_head != NULL)
1339 pcn_start_locked(ifp);
1340
1341 PCN_UNLOCK(sc);
1342
1343 return(0);
1344}
1345
1346/*
1347 * Report current media status.
1348 */
1349static void
1350pcn_ifmedia_sts(ifp, ifmr)
1351 struct ifnet *ifp;
1352 struct ifmediareq *ifmr;
1353{
1354 struct pcn_softc *sc;
1355 struct mii_data *mii;
1356
1357 sc = ifp->if_softc;
1358
1359 mii = device_get_softc(sc->pcn_miibus);
1360 PCN_LOCK(sc);
1361 mii_pollstat(mii);
1362 ifmr->ifm_active = mii->mii_media_active;
1363 ifmr->ifm_status = mii->mii_media_status;
1364 PCN_UNLOCK(sc);
1365
1366 return;
1367}
1368
1369static int
1370pcn_ioctl(ifp, command, data)
1371 struct ifnet *ifp;
1372 u_long command;
1373 caddr_t data;
1374{
1375 struct pcn_softc *sc = ifp->if_softc;
1376 struct ifreq *ifr = (struct ifreq *) data;
1377 struct mii_data *mii = NULL;
1378 int error = 0;
1379
1380 switch(command) {
1381 case SIOCSIFFLAGS:
1382 PCN_LOCK(sc);
1383 if (ifp->if_flags & IFF_UP) {
1384 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1385 ifp->if_flags & IFF_PROMISC &&
1386 !(sc->pcn_if_flags & IFF_PROMISC)) {
1387 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1388 PCN_EXTCTL1_SPND);
1389 pcn_setfilt(ifp);
1390 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1391 PCN_EXTCTL1_SPND);
1392 pcn_csr_write(sc, PCN_CSR_CSR,
1393 PCN_CSR_INTEN|PCN_CSR_START);
1394 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1395 !(ifp->if_flags & IFF_PROMISC) &&
1396 sc->pcn_if_flags & IFF_PROMISC) {
1397 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1398 PCN_EXTCTL1_SPND);
1399 pcn_setfilt(ifp);
1400 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1401 PCN_EXTCTL1_SPND);
1402 pcn_csr_write(sc, PCN_CSR_CSR,
1403 PCN_CSR_INTEN|PCN_CSR_START);
1404 } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1405 pcn_init_locked(sc);
1406 } else {
1407 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1408 pcn_stop(sc);
1409 }
1410 sc->pcn_if_flags = ifp->if_flags;
1411 PCN_UNLOCK(sc);
1412 error = 0;
1413 break;
1414 case SIOCADDMULTI:
1415 case SIOCDELMULTI:
1416 PCN_LOCK(sc);
1417 pcn_setmulti(sc);
1418 PCN_UNLOCK(sc);
1419 error = 0;
1420 break;
1421 case SIOCGIFMEDIA:
1422 case SIOCSIFMEDIA:
1423 mii = device_get_softc(sc->pcn_miibus);
1424 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1425 break;
1426 default:
1427 error = ether_ioctl(ifp, command, data);
1428 break;
1429 }
1430
1431 return(error);
1432}
1433
1434static void
1435pcn_watchdog(struct pcn_softc *sc)
1436{
1437 struct ifnet *ifp;
1438
1439 PCN_LOCK_ASSERT(sc);
1440 ifp = sc->pcn_ifp;
1441
1442 ifp->if_oerrors++;
1443 if_printf(ifp, "watchdog timeout\n");
1444
1445 pcn_stop(sc);
1446 pcn_reset(sc);
1447 pcn_init_locked(sc);
1448
1449 if (ifp->if_snd.ifq_head != NULL)
1450 pcn_start_locked(ifp);
1451}
1452
1453/*
1454 * Stop the adapter and free any mbufs allocated to the
1455 * RX and TX lists.
1456 */
1457static void
1458pcn_stop(struct pcn_softc *sc)
1459{
1460 register int i;
1461 struct ifnet *ifp;
1462
1463 PCN_LOCK_ASSERT(sc);
1464 ifp = sc->pcn_ifp;
1465 sc->pcn_timer = 0;
1466
1467 callout_stop(&sc->pcn_stat_callout);
1468
1469 /* Turn off interrupts */
1470 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
1471 /* Stop adapter */
1472 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
1473 sc->pcn_link = 0;
1474
1475 /*
1476 * Free data in the RX lists.
1477 */
1478 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
1479 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
1480 m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
1481 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
1482 }
1483 }
1484 bzero((char *)&sc->pcn_ldata->pcn_rx_list,
1485 sizeof(sc->pcn_ldata->pcn_rx_list));
1486
1487 /*
1488 * Free the TX list buffers.
1489 */
1490 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
1491 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
1492 m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
1493 sc->pcn_cdata.pcn_tx_chain[i] = NULL;
1494 }
1495 }
1496
1497 bzero((char *)&sc->pcn_ldata->pcn_tx_list,
1498 sizeof(sc->pcn_ldata->pcn_tx_list));
1499
1500 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1501
1502 return;
1503}
1504
1505/*
1506 * Stop all chip I/O so that the kernel's probe routines don't
1507 * get confused by errant DMAs when rebooting.
1508 */
1509static int
1510pcn_shutdown(device_t dev)
1511{
1512 struct pcn_softc *sc;
1513
1514 sc = device_get_softc(dev);
1515
1516 PCN_LOCK(sc);
1517 pcn_reset(sc);
1518 pcn_stop(sc);
1519 PCN_UNLOCK(sc);
1520
1521 return 0;
1522}