| pcivar.h (167909) | pcivar.h (169221) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/dev/pci/pcivar.h 167909 2007-03-26 20:18:52Z jhb $ | 26 * $FreeBSD: head/sys/dev/pci/pcivar.h 169221 2007-05-02 17:50:36Z jhb $ |
| 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#include <sys/queue.h> 34 --- 43 unchanged lines hidden (view full) --- 78/* Interesting values for PCI MSI */ 79struct pcicfg_msi { 80 uint16_t msi_ctrl; /* Message Control */ 81 uint8_t msi_location; /* Offset of MSI capability registers. */ 82 uint8_t msi_msgnum; /* Number of messages */ 83 int msi_alloc; /* Number of allocated messages. */ 84 uint64_t msi_addr; /* Contents of address register. */ 85 uint16_t msi_data; /* Contents of data register. */ | 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#include <sys/queue.h> 34 --- 43 unchanged lines hidden (view full) --- 78/* Interesting values for PCI MSI */ 79struct pcicfg_msi { 80 uint16_t msi_ctrl; /* Message Control */ 81 uint8_t msi_location; /* Offset of MSI capability registers. */ 82 uint8_t msi_msgnum; /* Number of messages */ 83 int msi_alloc; /* Number of allocated messages. */ 84 uint64_t msi_addr; /* Contents of address register. */ 85 uint16_t msi_data; /* Contents of data register. */ |
| 86 u_int msi_handlers; |
|
| 86}; 87 88/* Interesting values for PCI MSI-X */ | 87}; 88 89/* Interesting values for PCI MSI-X */ |
| 90struct msix_vector { 91 uint64_t mv_address; /* Contents of address register. */ 92 uint32_t mv_data; /* Contents of data register. */ 93 int mv_irq; 94}; 95 96struct msix_table_entry { 97 u_int mte_vector; /* 1-based index into msix_vectors array. */ 98 u_int mte_handlers; 99}; 100 |
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| 89struct pcicfg_msix { 90 uint16_t msix_ctrl; /* Message Control */ | 101struct pcicfg_msix { 102 uint16_t msix_ctrl; /* Message Control */ |
| 91 uint8_t msix_location; /* Offset of MSI-X capability registers. */ | |
| 92 uint16_t msix_msgnum; /* Number of messages */ | 103 uint16_t msix_msgnum; /* Number of messages */ |
| 93 int msix_alloc; /* Number of allocated messages. */ | 104 uint8_t msix_location; /* Offset of MSI-X capability registers. */ |
| 94 uint8_t msix_table_bar; /* BAR containing vector table. */ 95 uint8_t msix_pba_bar; /* BAR containing PBA. */ 96 uint32_t msix_table_offset; 97 uint32_t msix_pba_offset; | 105 uint8_t msix_table_bar; /* BAR containing vector table. */ 106 uint8_t msix_pba_bar; /* BAR containing PBA. */ 107 uint32_t msix_table_offset; 108 uint32_t msix_pba_offset; |
| 109 int msix_alloc; /* Number of allocated vectors. */ 110 int msix_table_len; /* Length of virtual table. */ 111 struct msix_table_entry *msix_table; /* Virtual table. */ 112 struct msix_vector *msix_vectors; /* Array of allocated vectors. */ |
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| 98 struct resource *msix_table_res; /* Resource containing vector table. */ 99 struct resource *msix_pba_res; /* Resource containing PBA. */ 100}; 101 102/* config header information common to all header types */ 103typedef struct pcicfg { 104 struct device *dev; /* device which owns this */ 105 --- 292 unchanged lines hidden (view full) --- 398 399static __inline int 400pci_alloc_msix(device_t dev, int *count) 401{ 402 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 403} 404 405static __inline int | 113 struct resource *msix_table_res; /* Resource containing vector table. */ 114 struct resource *msix_pba_res; /* Resource containing PBA. */ 115}; 116 117/* config header information common to all header types */ 118typedef struct pcicfg { 119 struct device *dev; /* device which owns this */ 120 --- 292 unchanged lines hidden (view full) --- 413 414static __inline int 415pci_alloc_msix(device_t dev, int *count) 416{ 417 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 418} 419 420static __inline int |
| 406pci_remap_msix(device_t dev, u_int *indices) | 421pci_remap_msix(device_t dev, int count, const u_int *vectors) |
| 407{ | 422{ |
| 408 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, indices)); | 423 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); |
| 409} 410 411static __inline int 412pci_release_msi(device_t dev) 413{ 414 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 415} 416 --- 7 unchanged lines hidden (view full) --- 424pci_msix_count(device_t dev) 425{ 426 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 427} 428 429device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 430device_t pci_find_device(uint16_t, uint16_t); 431 | 424} 425 426static __inline int 427pci_release_msi(device_t dev) 428{ 429 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 430} 431 --- 7 unchanged lines hidden (view full) --- 439pci_msix_count(device_t dev) 440{ 441 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 442} 443 444device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 445device_t pci_find_device(uint16_t, uint16_t); 446 |
| 432/* Used by MD code to program MSI and MSI-X registers. */ 433void pci_enable_msi(device_t dev, uint64_t address, uint16_t data); 434void pci_enable_msix(device_t dev, u_int index, uint64_t address, 435 uint32_t data); 436void pci_mask_msix(device_t dev, u_int index); | 447/* 448 * Can be used by MD code to request the PCI bus to re-map an MSI or 449 * MSI-X message. 450 */ 451int pci_remap_msi_irq(device_t dev, u_int irq); 452 453/* Can be used by drivers to manage the MSI-X table. */ |
| 437int pci_pending_msix(device_t dev, u_int index); | 454int pci_pending_msix(device_t dev, u_int index); |
| 438void pci_unmask_msix(device_t dev, u_int index); | 455 |
| 439int pci_msi_device_blacklisted(device_t dev); 440 441#endif /* _SYS_BUS_H_ */ 442 443/* 444 * cdev switch for control device, initialised in generic PCI code 445 */ 446extern struct cdevsw pcicdev; 447 448/* 449 * List of all PCI devices, generation count for the list. 450 */ 451STAILQ_HEAD(devlist, pci_devinfo); 452 453extern struct devlist pci_devq; 454extern uint32_t pci_generation; 455 456#endif /* _PCIVAR_H_ */ | 456int pci_msi_device_blacklisted(device_t dev); 457 458#endif /* _SYS_BUS_H_ */ 459 460/* 461 * cdev switch for control device, initialised in generic PCI code 462 */ 463extern struct cdevsw pcicdev; 464 465/* 466 * List of all PCI devices, generation count for the list. 467 */ 468STAILQ_HEAD(devlist, pci_devinfo); 469 470extern struct devlist pci_devq; 471extern uint32_t pci_generation; 472 473#endif /* _PCIVAR_H_ */ |