| pcireg.h (69908) | pcireg.h (69953) |
|---|---|
| 1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * | 1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/dev/pci/pcireg.h 69908 2000-12-12 13:20:35Z msmith $ | 26 * $FreeBSD: head/sys/dev/pci/pcireg.h 69953 2000-12-13 01:25:11Z msmith $ |
| 27 * 28 */ 29 30/* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass --- 12 unchanged lines hidden (view full) --- 47/* PCI config header registers for all devices */ 48 49#define PCIR_DEVVENDOR 0x00 50#define PCIR_VENDOR 0x00 51#define PCIR_DEVICE 0x02 52#define PCIR_COMMAND 0x04 53#define PCIM_CMD_PORTEN 0x0001 54#define PCIM_CMD_MEMEN 0x0002 | 27 * 28 */ 29 30/* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass --- 12 unchanged lines hidden (view full) --- 47/* PCI config header registers for all devices */ 48 49#define PCIR_DEVVENDOR 0x00 50#define PCIR_VENDOR 0x00 51#define PCIR_DEVICE 0x02 52#define PCIR_COMMAND 0x04 53#define PCIM_CMD_PORTEN 0x0001 54#define PCIM_CMD_MEMEN 0x0002 |
| 55#define PCIM_CMD_MWRICEN 0x0010 | |
| 56#define PCIM_CMD_BUSMASTEREN 0x0004 | 55#define PCIM_CMD_BUSMASTEREN 0x0004 |
| 56#define PCIM_CMD_SPECIALEN 0x0008 57#define PCIM_CMD_MWRICEN 0x0010 |
|
| 57#define PCIM_CMD_PERRESPEN 0x0040 | 58#define PCIM_CMD_PERRESPEN 0x0040 |
| 59#define PCIM_CMD_SERREN 0x0100 60#define PCIM_CMD_BACKTOBACK 0x0200 |
|
| 58#define PCIR_STATUS 0x06 | 61#define PCIR_STATUS 0x06 |
| 62#define PCIM_STATUS_CAPPRESENT 0x0010 63#define PCIM_STATUS_66CAPABLE 0x0020 64#define PCIM_STATUS_BACKTOBACK 0x0080 65#define PCIM_STATUS_PERRREPORT 0x0100 66#define PCIM_STATUS_SEL_FAST 0x0000 67#define PCIM_STATUS_SEL_MEDIMUM 0x0200 68#define PCIM_STATUS_SEL_SLOW 0x0400 69#define PCIM_STATUS_SEL_MASK 0x0600 70#define PCIM_STATUS_STABORT 0x0800 71#define PCIM_STATUS_RTABORT 0x1000 72#define PCIM_STATUS_RMABORT 0x2000 73#define PCIM_STATUS_SERR 0x4000 74#define PCIM_STATUS_PERR 0x8000 |
|
| 59#define PCIR_REVID 0x08 60#define PCIR_PROGIF 0x09 61#define PCIR_SUBCLASS 0x0a 62#define PCIR_CLASS 0x0b 63#define PCIR_CACHELNSZ 0x0c 64#define PCIR_LATTIMER 0x0d 65#define PCIR_HEADERTYPE 0x0e 66#define PCIM_MFDEV 0x80 --- 9 unchanged lines hidden (view full) --- 76#define PCIM_BIOS_ENABLE 0x01 77#define PCIR_INTLINE 0x3c 78#define PCIR_INTPIN 0x3d 79#define PCIR_MINGNT 0x3e 80#define PCIR_MAXLAT 0x3f 81 82/* config registers for header type 1 devices */ 83 | 75#define PCIR_REVID 0x08 76#define PCIR_PROGIF 0x09 77#define PCIR_SUBCLASS 0x0a 78#define PCIR_CLASS 0x0b 79#define PCIR_CACHELNSZ 0x0c 80#define PCIR_LATTIMER 0x0d 81#define PCIR_HEADERTYPE 0x0e 82#define PCIM_MFDEV 0x80 --- 9 unchanged lines hidden (view full) --- 92#define PCIM_BIOS_ENABLE 0x01 93#define PCIR_INTLINE 0x3c 94#define PCIR_INTPIN 0x3d 95#define PCIR_MINGNT 0x3e 96#define PCIR_MAXLAT 0x3f 97 98/* config registers for header type 1 devices */ 99 |
| 84#define PCIR_SECSTAT_1 0 /**/ | 100#define PCIR_SECSTAT_1 0x1e |
| 85 86#define PCIR_PRIBUS_1 0x18 87#define PCIR_SECBUS_1 0x19 88#define PCIR_SUBBUS_1 0x1a 89#define PCIR_SECLAT_1 0x1b 90 91#define PCIR_IOBASEL_1 0x1c 92#define PCIR_IOLIMITL_1 0x1d --- 129 unchanged lines hidden (view full) --- 222#define PCIS_SERIALBUS_ACCESS 0x01 223#define PCIS_SERIALBUS_SSA 0x02 224#define PCIS_SERIALBUS_USB 0x03 225#define PCIS_SERIALBUS_FC 0x04 226#define PCIS_SERIALBUS_SMBUS 0x05 227 228#define PCIC_OTHER 0xff 229 | 101 102#define PCIR_PRIBUS_1 0x18 103#define PCIR_SECBUS_1 0x19 104#define PCIR_SUBBUS_1 0x1a 105#define PCIR_SECLAT_1 0x1b 106 107#define PCIR_IOBASEL_1 0x1c 108#define PCIR_IOLIMITL_1 0x1d --- 129 unchanged lines hidden (view full) --- 238#define PCIS_SERIALBUS_ACCESS 0x01 239#define PCIS_SERIALBUS_SSA 0x02 240#define PCIS_SERIALBUS_USB 0x03 241#define PCIS_SERIALBUS_FC 0x04 242#define PCIS_SERIALBUS_SMBUS 0x05 243 244#define PCIC_OTHER 0xff 245 |
| 230/* some PCI vendor definitions (only used to identify ancient devices !!! */ | 246/* PCI power manangement */ |
| 231 | 247 |
| 232#define PCIV_INTEL 0x8086 | 248#define PCIR_POWER_CAP 0x2 249#define PCIM_PCAP_SPEC 0x0007 250#define PCIM_PCAP_PMEREQCLK 0x0008 251#define PCIM_PCAP_PMEREQPWR 0x0010 252#define PCIM_PCAP_DEVSPECINIT 0x0020 253#define PCIM_PCAP_DYNCLOCK 0x0040 254#define PCIM_PCAP_SECCLOCK 0x00c0 255#define PCIM_PCAP_CLOCKMASK 0x00c0 256#define PCIM_PCAP_REQFULLCLOCK 0x0100 257#define PCIM_PCAP_D1SUPP 0x0200 258#define PCIM_PCAP_D2SUPP 0x0400 259#define PCIM_PCAP_D0PME 0x1000 260#define PCIM_PCAP_D1PME 0x2000 261#define PCIM_PCAP_D2PME 0x4000 |
| 233 | 262 |
| 234#define PCID_INTEL_SATURN 0x0483 235#define PCID_INTEL_ORION 0x84c4 | 263#define PCIR_POWER_STATUS 0x4 264#define PCIM_PSTAT_D0 0x0000 265#define PCIM_PSTAT_D1 0x0001 266#define PCIM_PSTAT_D2 0x0002 267#define PCIM_PSTAT_D3 0x0003 268#define PCIM_PSTAT_DMASK 0x0003 269#define PCIM_PSTAT_REPENABLE 0x0010 270#define PCIM_PSTAT_PMEENABLE 0x0100 271#define PCIM_PSTAT_D0POWER 0x0000 272#define PCIM_PSTAT_D1POWER 0x0200 273#define PCIM_PSTAT_D2POWER 0x0400 274#define PCIM_PSTAT_D3POWER 0x0600 275#define PCIM_PSTAT_D0HEAT 0x0800 276#define PCIM_PSTAT_D1HEAT 0x1000 277#define PCIM_PSTAT_D2HEAT 0x1200 278#define PCIM_PSTAT_D3HEAT 0x1400 279#define PCIM_PSTAT_DATAUNKN 0x0000 280#define PCIM_PSTAT_DATADIV10 0x2000 281#define PCIM_PSTAT_DATADIV100 0x4000 282#define PCIM_PSTAT_DATADIV1000 0x6000 283#define PCIM_PSTAT_DATADIVMASK 0x6000 284#define PCIM_PSTAT_PME 0x8000 |
| 236 | 285 |
| 237/* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */ | 286#define PCIR_POWER_PMCSR 0x6 287#define PCIM_PMCSR_DCLOCK 0x10 288#define PCIM_PMCSR_B2SUPP 0x20 289#define PCIM_BMCSR_B3SUPP 0x40 290#define PCIM_BMCSR_BPCE 0x80 |
| 238 | 291 |
| 239#if defined(_KERNEL) && !defined(KLD_MODULE) 240#include "opt_compat_oldpci.h" 241#endif | 292#define PCIR_POWER_DATA 0x7 |
| 242 | 293 |
| 243#ifdef COMPAT_OLDPCI | 294#if 0 295/* some PCI vendor definitions (only used to identify ancient devices !!! */ |
| 244 | 296 |
| 245#define PCI_ID_REG 0x00 246#define PCI_COMMAND_STATUS_REG 0x04 247#define PCI_COMMAND_IO_ENABLE 0x00000001 248#define PCI_COMMAND_MEM_ENABLE 0x00000002 249#define PCI_CLASS_REG 0x08 250#define PCI_CLASS_MASK 0xff000000 251#define PCI_SUBCLASS_MASK 0x00ff0000 252#define PCI_REVISION_MASK 0x000000ff 253#define PCI_CLASS_PREHISTORIC 0x00000000 254#define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000 255#define PCI_CLASS_MASS_STORAGE 0x01000000 256#define PCI_CLASS_DISPLAY 0x03000000 257#define PCI_SUBCLASS_DISPLAY_VGA 0x00000000 258#define PCI_CLASS_BRIDGE 0x06000000 259#define PCI_MAP_REG_START 0x10 260#define PCI_MAP_REG_END 0x28 261#define PCI_MAP_IO 0x00000001 262#define PCI_INTERRUPT_REG 0x3c | 297#define PCIV_INTEL 0x8086 |
| 263 | 298 |
| 264#endif /* COMPAT_OLDPCI */ | 299#define PCID_INTEL_SATURN 0x0483 300#define PCID_INTEL_ORION 0x84c4 301#endif |