61 DEVMETHOD(device_shutdown, bus_generic_shutdown),
62 DEVMETHOD(device_suspend, bus_generic_suspend),
63 DEVMETHOD(device_resume, bus_generic_resume),
64
65 /* Bus interface */
66 DEVMETHOD(bus_print_child, bus_generic_print_child),
67 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
68 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
69 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
70 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
71 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
72 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
73 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
74 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
75
76 /* pcib interface */
77 DEVMETHOD(pcib_maxslots, pcib_maxslots),
78 DEVMETHOD(pcib_read_config, pcib_read_config),
79 DEVMETHOD(pcib_write_config, pcib_write_config),
80 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
81
82 { 0, 0 }
83};
84
85static driver_t pcib_driver = {
86 "pcib",
87 pcib_methods,
88 sizeof(struct pcib_softc),
89};
90
91devclass_t pcib_devclass;
92
93DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
94
95/*
96 * Generic device interface
97 */
98static int
99pcib_probe(device_t dev)
100{
101 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
102 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
103 device_set_desc(dev, "PCI-PCI bridge");
104 return(-10000);
105 }
106 return(ENXIO);
107}
108
109void
110pcib_attach_common(device_t dev)
111{
112 struct pcib_softc *sc;
113 uint8_t iolow;
114
115 sc = device_get_softc(dev);
116 sc->dev = dev;
117
118 /*
119 * Get current bridge configuration.
120 */
121 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
122 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
123 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
124 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
125 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
126 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
127
128 /*
129 * Determine current I/O decode.
130 */
131 if (sc->command & PCIM_CMD_PORTEN) {
132 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
133 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
134 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
135 pci_read_config(dev, PCIR_IOBASEL_1, 1));
136 } else {
137 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
138 }
139
140 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
141 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
142 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
143 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
144 } else {
145 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
146 }
147 }
148
149 /*
150 * Determine current memory decode.
151 */
152 if (sc->command & PCIM_CMD_MEMEN) {
153 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
154 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
155 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
156 pci_read_config(dev, PCIR_PMBASEL_1, 2));
157 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
158 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
159 }
160
161 /*
162 * Quirk handling.
163 */
164 switch (pci_get_devid(dev)) {
165 case 0x12258086: /* Intel 82454KX/GX (Orion) */
166 {
167 uint8_t supbus;
168
169 supbus = pci_read_config(dev, 0x41, 1);
170 if (supbus != 0xff) {
171 sc->secbus = supbus + 1;
172 sc->subbus = supbus + 1;
173 }
174 break;
175 }
176
177 /*
178 * The i82380FB mobile docking controller is a PCI-PCI bridge,
179 * and it is a subtractive bridge. However, the ProgIf is wrong
180 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
181 * happen. There's also a Toshiba bridge that behaves this
182 * way.
183 */
184 case 0x124b8086: /* Intel 82380FB Mobile */
185 case 0x060513d7: /* Toshiba ???? */
186 sc->flags |= PCIB_SUBTRACTIVE;
187 break;
188 }
189
190 /*
191 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
192 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
193 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
194 * This means they act as if they were subtractively decoding
195 * bridges and pass all transactions. Mark them and real ProgIf 1
196 * parts as subtractive.
197 */
198 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
199 pci_read_config(dev, PCIR_PROGIF, 1) == 1)
200 sc->flags |= PCIB_SUBTRACTIVE;
201
202 if (bootverbose) {
203 device_printf(dev, " secondary bus %d\n", sc->secbus);
204 device_printf(dev, " subordinate bus %d\n", sc->subbus);
205 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
206 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
207 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
208 if (sc->flags & PCIB_SUBTRACTIVE)
209 device_printf(dev, " Subtractively decoded bridge.\n");
210 }
211
212 /*
213 * XXX If the secondary bus number is zero, we should assign a bus number
214 * since the BIOS hasn't, then initialise the bridge.
215 */
216
217 /*
218 * XXX If the subordinate bus number is less than the secondary bus number,
219 * we should pick a better value. One sensible alternative would be to
220 * pick 255; the only tradeoff here is that configuration transactions
221 * would be more widely routed than absolutely necessary.
222 */
223}
224
225int
226pcib_attach(device_t dev)
227{
228 struct pcib_softc *sc;
229 device_t child;
230
231 pcib_attach_common(dev);
232 sc = device_get_softc(dev);
233 if (sc->secbus != 0) {
234 child = device_add_child(dev, "pci", sc->secbus);
235 if (child != NULL)
236 return(bus_generic_attach(dev));
237 }
238
239 /* no secondary bus; we should have fixed this */
240 return(0);
241}
242
243int
244pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
245{
246 struct pcib_softc *sc = device_get_softc(dev);
247
248 switch (which) {
249 case PCIB_IVAR_BUS:
250 *result = sc->secbus;
251 return(0);
252 }
253 return(ENOENT);
254}
255
256int
257pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
258{
259 struct pcib_softc *sc = device_get_softc(dev);
260
261 switch (which) {
262 case PCIB_IVAR_BUS:
263 sc->secbus = value;
264 break;
265 }
266 return(ENOENT);
267}
268
269/*
270 * Is the prefetch window open (eg, can we allocate memory in it?)
271 */
272static int
273pcib_is_prefetch_open(struct pcib_softc *sc)
274{
275 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
276}
277
278/*
279 * Is the nonprefetch window open (eg, can we allocate memory in it?)
280 */
281static int
282pcib_is_nonprefetch_open(struct pcib_softc *sc)
283{
284 return (sc->membase > 0 && sc->membase < sc->memlimit);
285}
286
287/*
288 * Is the io window open (eg, can we allocate ports in it?)
289 */
290static int
291pcib_is_io_open(struct pcib_softc *sc)
292{
293 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
294}
295
296/*
297 * We have to trap resource allocation requests and ensure that the bridge
298 * is set up to, or capable of handling them.
299 */
300struct resource *
301pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
302 u_long start, u_long end, u_long count, u_int flags)
303{
304 struct pcib_softc *sc = device_get_softc(dev);
305 int ok;
306
307 /*
308 * Fail the allocation for this range if it's not supported.
309 */
310 switch (type) {
311 case SYS_RES_IOPORT:
312 ok = 0;
313 if (!pcib_is_io_open(sc))
314 break;
315 ok = (start >= sc->iobase && end <= sc->iolimit);
316
317 /*
318 * Make sure we allow access to VGA I/O addresses when the
319 * bridge has the "VGA Enable" bit set.
320 */
321 if (!ok && pci_is_vga_ioport_range(start, end))
322 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
323
324 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
325 if (!ok) {
326 if (start < sc->iobase)
327 start = sc->iobase;
328 if (end > sc->iolimit)
329 end = sc->iolimit;
330 if (start < end)
331 ok = 1;
332 }
333 } else {
334 ok = 1;
335#if 1
336 if (start < sc->iobase && end > sc->iolimit) {
337 start = sc->iobase;
338 end = sc->iolimit;
339 }
340#endif
341 }
342 if (end < start) {
343 device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
344 end, start);
345 start = 0;
346 end = 0;
347 ok = 0;
348 }
349 if (!ok) {
350 device_printf(dev, "%s requested unsupported I/O "
351 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
352 device_get_nameunit(child), start, end,
353 sc->iobase, sc->iolimit);
354 return (NULL);
355 }
356 if (bootverbose)
357 device_printf(dev,
358 "%s requested I/O range 0x%lx-0x%lx: in range\n",
359 device_get_nameunit(child), start, end);
360 break;
361
362 case SYS_RES_MEMORY:
363 ok = 0;
364 if (pcib_is_nonprefetch_open(sc))
365 ok = ok || (start >= sc->membase && end <= sc->memlimit);
366 if (pcib_is_prefetch_open(sc))
367 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
368
369 /*
370 * Make sure we allow access to VGA memory addresses when the
371 * bridge has the "VGA Enable" bit set.
372 */
373 if (!ok && pci_is_vga_memory_range(start, end))
374 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
375
376 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
377 if (!ok) {
378 ok = 1;
379 if (flags & RF_PREFETCHABLE) {
380 if (pcib_is_prefetch_open(sc)) {
381 if (start < sc->pmembase)
382 start = sc->pmembase;
383 if (end > sc->pmemlimit)
384 end = sc->pmemlimit;
385 } else {
386 ok = 0;
387 }
388 } else { /* non-prefetchable */
389 if (pcib_is_nonprefetch_open(sc)) {
390 if (start < sc->membase)
391 start = sc->membase;
392 if (end > sc->memlimit)
393 end = sc->memlimit;
394 } else {
395 ok = 0;
396 }
397 }
398 }
399 } else if (!ok) {
400 ok = 1; /* subtractive bridge: always ok */
401#if 1
402 if (pcib_is_nonprefetch_open(sc)) {
403 if (start < sc->membase && end > sc->memlimit) {
404 start = sc->membase;
405 end = sc->memlimit;
406 }
407 }
408 if (pcib_is_prefetch_open(sc)) {
409 if (start < sc->pmembase && end > sc->pmemlimit) {
410 start = sc->pmembase;
411 end = sc->pmemlimit;
412 }
413 }
414#endif
415 }
416 if (end < start) {
417 device_printf(dev, "memory: end (%lx) < start (%lx)\n",
418 end, start);
419 start = 0;
420 end = 0;
421 ok = 0;
422 }
423 if (!ok && bootverbose)
424 device_printf(dev,
425 "%s requested unsupported memory range "
426 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
427 device_get_nameunit(child), start, end,
428 sc->membase, sc->memlimit, sc->pmembase,
429 sc->pmemlimit);
430 if (!ok)
431 return (NULL);
432 if (bootverbose)
433 device_printf(dev,"%s requested memory range "
434 "0x%lx-0x%lx: good\n",
435 device_get_nameunit(child), start, end);
436 break;
437
438 default:
439 break;
440 }
441 /*
442 * Bridge is OK decoding this resource, so pass it up.
443 */
444 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
445 count, flags));
446}
447
448/*
449 * PCIB interface.
450 */
451int
452pcib_maxslots(device_t dev)
453{
454 return(PCI_SLOTMAX);
455}
456
457/*
458 * Since we are a child of a PCI bus, its parent must support the pcib interface.
459 */
460uint32_t
461pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
462{
463 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
464}
465
466void
467pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
468{
469 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
470}
471
472/*
473 * Route an interrupt across a PCI bridge.
474 */
475int
476pcib_route_interrupt(device_t pcib, device_t dev, int pin)
477{
478 device_t bus;
479 int parent_intpin;
480 int intnum;
481
482 /*
483 *
484 * The PCI standard defines a swizzle of the child-side device/intpin to
485 * the parent-side intpin as follows.
486 *
487 * device = device on child bus
488 * child_intpin = intpin on child bus slot (0-3)
489 * parent_intpin = intpin on parent bus slot (0-3)
490 *
491 * parent_intpin = (device + child_intpin) % 4
492 */
493 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
494
495 /*
496 * Our parent is a PCI bus. Its parent must export the pcib interface
497 * which includes the ability to route interrupts.
498 */
499 bus = device_get_parent(pcib);
500 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
501 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
502 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
503 pci_get_slot(dev), 'A' + pin - 1, intnum);
504 }
505 return(intnum);
506}
507
508/*
509 * Try to read the bus number of a host-PCI bridge using appropriate config
510 * registers.
511 */
512int
513host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
514 uint8_t *busnum)
515{
516 uint32_t id;
517
518 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
519 if (id == 0xffffffff)
520 return (0);
521
522 switch (id) {
523 case 0x12258086:
524 /* Intel 824?? */
525 /* XXX This is a guess */
526 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
527 *busnum = bus;
528 break;
529 case 0x84c48086:
530 /* Intel 82454KX/GX (Orion) */
531 *busnum = read_config(bus, slot, func, 0x4a, 1);
532 break;
533 case 0x84ca8086:
534 /*
535 * For the 450nx chipset, there is a whole bundle of
536 * things pretending to be host bridges. The MIOC will
537 * be seen first and isn't really a pci bridge (the
538 * actual busses are attached to the PXB's). We need to
539 * read the registers of the MIOC to figure out the
540 * bus numbers for the PXB channels.
541 *
542 * Since the MIOC doesn't have a pci bus attached, we
543 * pretend it wasn't there.
544 */
545 return (0);
546 case 0x84cb8086:
547 switch (slot) {
548 case 0x12:
549 /* Intel 82454NX PXB#0, Bus#A */
550 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
551 break;
552 case 0x13:
553 /* Intel 82454NX PXB#0, Bus#B */
554 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
555 break;
556 case 0x14:
557 /* Intel 82454NX PXB#1, Bus#A */
558 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
559 break;
560 case 0x15:
561 /* Intel 82454NX PXB#1, Bus#B */
562 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
563 break;
564 }
565 break;
566
567 /* ServerWorks -- vendor 0x1166 */
568 case 0x00051166:
569 case 0x00061166:
570 case 0x00081166:
571 case 0x00091166:
572 case 0x00101166:
573 case 0x00111166:
574 case 0x00171166:
575 case 0x01011166:
576 case 0x010f1014:
577 case 0x02011166:
578 case 0x03021014:
579 *busnum = read_config(bus, slot, func, 0x44, 1);
580 break;
581
582 /* Compaq/HP -- vendor 0x0e11 */
583 case 0x60100e11:
584 *busnum = read_config(bus, slot, func, 0xc8, 1);
585 break;
586 default:
587 /* Don't know how to read bus number. */
588 return 0;
589 }
590
591 return 1;
592}
| 62 DEVMETHOD(device_shutdown, bus_generic_shutdown),
63 DEVMETHOD(device_suspend, bus_generic_suspend),
64 DEVMETHOD(device_resume, bus_generic_resume),
65
66 /* Bus interface */
67 DEVMETHOD(bus_print_child, bus_generic_print_child),
68 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
69 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
70 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
71 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
72 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
73 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
74 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
75 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
76
77 /* pcib interface */
78 DEVMETHOD(pcib_maxslots, pcib_maxslots),
79 DEVMETHOD(pcib_read_config, pcib_read_config),
80 DEVMETHOD(pcib_write_config, pcib_write_config),
81 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
82
83 { 0, 0 }
84};
85
86static driver_t pcib_driver = {
87 "pcib",
88 pcib_methods,
89 sizeof(struct pcib_softc),
90};
91
92devclass_t pcib_devclass;
93
94DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
95
96/*
97 * Generic device interface
98 */
99static int
100pcib_probe(device_t dev)
101{
102 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
103 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
104 device_set_desc(dev, "PCI-PCI bridge");
105 return(-10000);
106 }
107 return(ENXIO);
108}
109
110void
111pcib_attach_common(device_t dev)
112{
113 struct pcib_softc *sc;
114 uint8_t iolow;
115
116 sc = device_get_softc(dev);
117 sc->dev = dev;
118
119 /*
120 * Get current bridge configuration.
121 */
122 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
123 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
124 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
125 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
126 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
127 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
128
129 /*
130 * Determine current I/O decode.
131 */
132 if (sc->command & PCIM_CMD_PORTEN) {
133 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
134 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
135 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
136 pci_read_config(dev, PCIR_IOBASEL_1, 1));
137 } else {
138 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
139 }
140
141 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
142 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
143 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
144 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
145 } else {
146 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
147 }
148 }
149
150 /*
151 * Determine current memory decode.
152 */
153 if (sc->command & PCIM_CMD_MEMEN) {
154 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
155 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
156 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
157 pci_read_config(dev, PCIR_PMBASEL_1, 2));
158 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
159 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
160 }
161
162 /*
163 * Quirk handling.
164 */
165 switch (pci_get_devid(dev)) {
166 case 0x12258086: /* Intel 82454KX/GX (Orion) */
167 {
168 uint8_t supbus;
169
170 supbus = pci_read_config(dev, 0x41, 1);
171 if (supbus != 0xff) {
172 sc->secbus = supbus + 1;
173 sc->subbus = supbus + 1;
174 }
175 break;
176 }
177
178 /*
179 * The i82380FB mobile docking controller is a PCI-PCI bridge,
180 * and it is a subtractive bridge. However, the ProgIf is wrong
181 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
182 * happen. There's also a Toshiba bridge that behaves this
183 * way.
184 */
185 case 0x124b8086: /* Intel 82380FB Mobile */
186 case 0x060513d7: /* Toshiba ???? */
187 sc->flags |= PCIB_SUBTRACTIVE;
188 break;
189 }
190
191 /*
192 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
193 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
194 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
195 * This means they act as if they were subtractively decoding
196 * bridges and pass all transactions. Mark them and real ProgIf 1
197 * parts as subtractive.
198 */
199 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
200 pci_read_config(dev, PCIR_PROGIF, 1) == 1)
201 sc->flags |= PCIB_SUBTRACTIVE;
202
203 if (bootverbose) {
204 device_printf(dev, " secondary bus %d\n", sc->secbus);
205 device_printf(dev, " subordinate bus %d\n", sc->subbus);
206 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
207 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
208 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
209 if (sc->flags & PCIB_SUBTRACTIVE)
210 device_printf(dev, " Subtractively decoded bridge.\n");
211 }
212
213 /*
214 * XXX If the secondary bus number is zero, we should assign a bus number
215 * since the BIOS hasn't, then initialise the bridge.
216 */
217
218 /*
219 * XXX If the subordinate bus number is less than the secondary bus number,
220 * we should pick a better value. One sensible alternative would be to
221 * pick 255; the only tradeoff here is that configuration transactions
222 * would be more widely routed than absolutely necessary.
223 */
224}
225
226int
227pcib_attach(device_t dev)
228{
229 struct pcib_softc *sc;
230 device_t child;
231
232 pcib_attach_common(dev);
233 sc = device_get_softc(dev);
234 if (sc->secbus != 0) {
235 child = device_add_child(dev, "pci", sc->secbus);
236 if (child != NULL)
237 return(bus_generic_attach(dev));
238 }
239
240 /* no secondary bus; we should have fixed this */
241 return(0);
242}
243
244int
245pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
246{
247 struct pcib_softc *sc = device_get_softc(dev);
248
249 switch (which) {
250 case PCIB_IVAR_BUS:
251 *result = sc->secbus;
252 return(0);
253 }
254 return(ENOENT);
255}
256
257int
258pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
259{
260 struct pcib_softc *sc = device_get_softc(dev);
261
262 switch (which) {
263 case PCIB_IVAR_BUS:
264 sc->secbus = value;
265 break;
266 }
267 return(ENOENT);
268}
269
270/*
271 * Is the prefetch window open (eg, can we allocate memory in it?)
272 */
273static int
274pcib_is_prefetch_open(struct pcib_softc *sc)
275{
276 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
277}
278
279/*
280 * Is the nonprefetch window open (eg, can we allocate memory in it?)
281 */
282static int
283pcib_is_nonprefetch_open(struct pcib_softc *sc)
284{
285 return (sc->membase > 0 && sc->membase < sc->memlimit);
286}
287
288/*
289 * Is the io window open (eg, can we allocate ports in it?)
290 */
291static int
292pcib_is_io_open(struct pcib_softc *sc)
293{
294 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
295}
296
297/*
298 * We have to trap resource allocation requests and ensure that the bridge
299 * is set up to, or capable of handling them.
300 */
301struct resource *
302pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
303 u_long start, u_long end, u_long count, u_int flags)
304{
305 struct pcib_softc *sc = device_get_softc(dev);
306 int ok;
307
308 /*
309 * Fail the allocation for this range if it's not supported.
310 */
311 switch (type) {
312 case SYS_RES_IOPORT:
313 ok = 0;
314 if (!pcib_is_io_open(sc))
315 break;
316 ok = (start >= sc->iobase && end <= sc->iolimit);
317
318 /*
319 * Make sure we allow access to VGA I/O addresses when the
320 * bridge has the "VGA Enable" bit set.
321 */
322 if (!ok && pci_is_vga_ioport_range(start, end))
323 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
324
325 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
326 if (!ok) {
327 if (start < sc->iobase)
328 start = sc->iobase;
329 if (end > sc->iolimit)
330 end = sc->iolimit;
331 if (start < end)
332 ok = 1;
333 }
334 } else {
335 ok = 1;
336#if 1
337 if (start < sc->iobase && end > sc->iolimit) {
338 start = sc->iobase;
339 end = sc->iolimit;
340 }
341#endif
342 }
343 if (end < start) {
344 device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
345 end, start);
346 start = 0;
347 end = 0;
348 ok = 0;
349 }
350 if (!ok) {
351 device_printf(dev, "%s requested unsupported I/O "
352 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
353 device_get_nameunit(child), start, end,
354 sc->iobase, sc->iolimit);
355 return (NULL);
356 }
357 if (bootverbose)
358 device_printf(dev,
359 "%s requested I/O range 0x%lx-0x%lx: in range\n",
360 device_get_nameunit(child), start, end);
361 break;
362
363 case SYS_RES_MEMORY:
364 ok = 0;
365 if (pcib_is_nonprefetch_open(sc))
366 ok = ok || (start >= sc->membase && end <= sc->memlimit);
367 if (pcib_is_prefetch_open(sc))
368 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
369
370 /*
371 * Make sure we allow access to VGA memory addresses when the
372 * bridge has the "VGA Enable" bit set.
373 */
374 if (!ok && pci_is_vga_memory_range(start, end))
375 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
376
377 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
378 if (!ok) {
379 ok = 1;
380 if (flags & RF_PREFETCHABLE) {
381 if (pcib_is_prefetch_open(sc)) {
382 if (start < sc->pmembase)
383 start = sc->pmembase;
384 if (end > sc->pmemlimit)
385 end = sc->pmemlimit;
386 } else {
387 ok = 0;
388 }
389 } else { /* non-prefetchable */
390 if (pcib_is_nonprefetch_open(sc)) {
391 if (start < sc->membase)
392 start = sc->membase;
393 if (end > sc->memlimit)
394 end = sc->memlimit;
395 } else {
396 ok = 0;
397 }
398 }
399 }
400 } else if (!ok) {
401 ok = 1; /* subtractive bridge: always ok */
402#if 1
403 if (pcib_is_nonprefetch_open(sc)) {
404 if (start < sc->membase && end > sc->memlimit) {
405 start = sc->membase;
406 end = sc->memlimit;
407 }
408 }
409 if (pcib_is_prefetch_open(sc)) {
410 if (start < sc->pmembase && end > sc->pmemlimit) {
411 start = sc->pmembase;
412 end = sc->pmemlimit;
413 }
414 }
415#endif
416 }
417 if (end < start) {
418 device_printf(dev, "memory: end (%lx) < start (%lx)\n",
419 end, start);
420 start = 0;
421 end = 0;
422 ok = 0;
423 }
424 if (!ok && bootverbose)
425 device_printf(dev,
426 "%s requested unsupported memory range "
427 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
428 device_get_nameunit(child), start, end,
429 sc->membase, sc->memlimit, sc->pmembase,
430 sc->pmemlimit);
431 if (!ok)
432 return (NULL);
433 if (bootverbose)
434 device_printf(dev,"%s requested memory range "
435 "0x%lx-0x%lx: good\n",
436 device_get_nameunit(child), start, end);
437 break;
438
439 default:
440 break;
441 }
442 /*
443 * Bridge is OK decoding this resource, so pass it up.
444 */
445 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
446 count, flags));
447}
448
449/*
450 * PCIB interface.
451 */
452int
453pcib_maxslots(device_t dev)
454{
455 return(PCI_SLOTMAX);
456}
457
458/*
459 * Since we are a child of a PCI bus, its parent must support the pcib interface.
460 */
461uint32_t
462pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
463{
464 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
465}
466
467void
468pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
469{
470 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
471}
472
473/*
474 * Route an interrupt across a PCI bridge.
475 */
476int
477pcib_route_interrupt(device_t pcib, device_t dev, int pin)
478{
479 device_t bus;
480 int parent_intpin;
481 int intnum;
482
483 /*
484 *
485 * The PCI standard defines a swizzle of the child-side device/intpin to
486 * the parent-side intpin as follows.
487 *
488 * device = device on child bus
489 * child_intpin = intpin on child bus slot (0-3)
490 * parent_intpin = intpin on parent bus slot (0-3)
491 *
492 * parent_intpin = (device + child_intpin) % 4
493 */
494 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
495
496 /*
497 * Our parent is a PCI bus. Its parent must export the pcib interface
498 * which includes the ability to route interrupts.
499 */
500 bus = device_get_parent(pcib);
501 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
502 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
503 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
504 pci_get_slot(dev), 'A' + pin - 1, intnum);
505 }
506 return(intnum);
507}
508
509/*
510 * Try to read the bus number of a host-PCI bridge using appropriate config
511 * registers.
512 */
513int
514host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
515 uint8_t *busnum)
516{
517 uint32_t id;
518
519 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
520 if (id == 0xffffffff)
521 return (0);
522
523 switch (id) {
524 case 0x12258086:
525 /* Intel 824?? */
526 /* XXX This is a guess */
527 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
528 *busnum = bus;
529 break;
530 case 0x84c48086:
531 /* Intel 82454KX/GX (Orion) */
532 *busnum = read_config(bus, slot, func, 0x4a, 1);
533 break;
534 case 0x84ca8086:
535 /*
536 * For the 450nx chipset, there is a whole bundle of
537 * things pretending to be host bridges. The MIOC will
538 * be seen first and isn't really a pci bridge (the
539 * actual busses are attached to the PXB's). We need to
540 * read the registers of the MIOC to figure out the
541 * bus numbers for the PXB channels.
542 *
543 * Since the MIOC doesn't have a pci bus attached, we
544 * pretend it wasn't there.
545 */
546 return (0);
547 case 0x84cb8086:
548 switch (slot) {
549 case 0x12:
550 /* Intel 82454NX PXB#0, Bus#A */
551 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
552 break;
553 case 0x13:
554 /* Intel 82454NX PXB#0, Bus#B */
555 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
556 break;
557 case 0x14:
558 /* Intel 82454NX PXB#1, Bus#A */
559 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
560 break;
561 case 0x15:
562 /* Intel 82454NX PXB#1, Bus#B */
563 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
564 break;
565 }
566 break;
567
568 /* ServerWorks -- vendor 0x1166 */
569 case 0x00051166:
570 case 0x00061166:
571 case 0x00081166:
572 case 0x00091166:
573 case 0x00101166:
574 case 0x00111166:
575 case 0x00171166:
576 case 0x01011166:
577 case 0x010f1014:
578 case 0x02011166:
579 case 0x03021014:
580 *busnum = read_config(bus, slot, func, 0x44, 1);
581 break;
582
583 /* Compaq/HP -- vendor 0x0e11 */
584 case 0x60100e11:
585 *busnum = read_config(bus, slot, func, 0xc8, 1);
586 break;
587 default:
588 /* Don't know how to read bus number. */
589 return 0;
590 }
591
592 return 1;
593}
|