1/*-
2 * Copyright (C) 2013 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
| 1/*-
2 * Copyright (C) 2013 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
|
| 39/* $FreeBSD: head/sys/dev/oce/oce_mbox.c 257007 2013-10-23 18:58:38Z delphij $ */
|
39
| 40
|
40
41/* $FreeBSD: head/sys/dev/oce/oce_mbox.c 252869 2013-07-06 08:30:45Z delphij $ */
42
43
| |
44#include "oce_if.h"
45extern uint32_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_NUM_ELE];
46
47/**
48 * @brief Reset (firmware) common function
49 * @param sc software handle to the device
50 * @returns 0 on success, ETIMEDOUT on failure
51 */
52int
53oce_reset_fun(POCE_SOFTC sc)
54{
55 struct oce_mbx *mbx;
56 struct oce_bmbx *mb;
57 struct ioctl_common_function_reset *fwcmd;
58 int rc = 0;
59
60 if (sc->flags & OCE_FLAGS_FUNCRESET_RQD) {
61 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
62 mbx = &mb->mbx;
63 bzero(mbx, sizeof(struct oce_mbx));
64
65 fwcmd = (struct ioctl_common_function_reset *)&mbx->payload;
66 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
67 MBX_SUBSYSTEM_COMMON,
68 OPCODE_COMMON_FUNCTION_RESET,
69 10, /* MBX_TIMEOUT_SEC */
70 sizeof(struct
71 ioctl_common_function_reset),
72 OCE_MBX_VER_V0);
73
74 mbx->u0.s.embedded = 1;
75 mbx->payload_length =
76 sizeof(struct ioctl_common_function_reset);
77
78 rc = oce_mbox_dispatch(sc, 2);
79 }
80
81 return rc;
82}
83
84
85/**
86 * @brief This funtions tells firmware we are
87 * done with commands.
88 * @param sc software handle to the device
89 * @returns 0 on success, ETIMEDOUT on failure
90 */
91int
92oce_fw_clean(POCE_SOFTC sc)
93{
94 struct oce_bmbx *mbx;
95 uint8_t *ptr;
96 int ret = 0;
97
98 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
99 ptr = (uint8_t *) &mbx->mbx;
100
101 /* Endian Signature */
102 *ptr++ = 0xff;
103 *ptr++ = 0xaa;
104 *ptr++ = 0xbb;
105 *ptr++ = 0xff;
106 *ptr++ = 0xff;
107 *ptr++ = 0xcc;
108 *ptr++ = 0xdd;
109 *ptr = 0xff;
110
111 ret = oce_mbox_dispatch(sc, 2);
112
113 return ret;
114}
115
116
117/**
118 * @brief Mailbox wait
119 * @param sc software handle to the device
120 * @param tmo_sec timeout in seconds
121 */
122static int
123oce_mbox_wait(POCE_SOFTC sc, uint32_t tmo_sec)
124{
125 tmo_sec *= 10000;
126 pd_mpu_mbox_db_t mbox_db;
127
128 for (;;) {
129 if (tmo_sec != 0) {
130 if (--tmo_sec == 0)
131 break;
132 }
133
134 mbox_db.dw0 = OCE_READ_REG32(sc, db, PD_MPU_MBOX_DB);
135
136 if (mbox_db.bits.ready)
137 return 0;
138
139 DELAY(100);
140 }
141
142 device_printf(sc->dev, "Mailbox timed out\n");
143
144 return ETIMEDOUT;
145}
146
147
148/**
149 * @brief Mailbox dispatch
150 * @param sc software handle to the device
151 * @param tmo_sec timeout in seconds
152 */
153int
154oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec)
155{
156 pd_mpu_mbox_db_t mbox_db;
157 uint32_t pa;
158 int rc;
159
160 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_PREWRITE);
161 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 34);
162 bzero(&mbox_db, sizeof(pd_mpu_mbox_db_t));
163 mbox_db.bits.ready = 0;
164 mbox_db.bits.hi = 1;
165 mbox_db.bits.address = pa;
166
167 rc = oce_mbox_wait(sc, tmo_sec);
168 if (rc == 0) {
169 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
170
171 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 4) & 0x3fffffff;
172 mbox_db.bits.ready = 0;
173 mbox_db.bits.hi = 0;
174 mbox_db.bits.address = pa;
175
176 rc = oce_mbox_wait(sc, tmo_sec);
177
178 if (rc == 0) {
179 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
180
181 rc = oce_mbox_wait(sc, tmo_sec);
182
183 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_POSTWRITE);
184 }
185 }
186
187 return rc;
188}
189
190
191
192/**
193 * @brief Mailbox common request header initialization
194 * @param hdr mailbox header
195 * @param dom domain
196 * @param port port
197 * @param subsys subsystem
198 * @param opcode opcode
199 * @param timeout timeout
200 * @param pyld_len payload length
201 */
202void
203mbx_common_req_hdr_init(struct mbx_hdr *hdr,
204 uint8_t dom, uint8_t port,
205 uint8_t subsys, uint8_t opcode,
206 uint32_t timeout, uint32_t pyld_len,
207 uint8_t version)
208{
209 hdr->u0.req.opcode = opcode;
210 hdr->u0.req.subsystem = subsys;
211 hdr->u0.req.port_number = port;
212 hdr->u0.req.domain = dom;
213
214 hdr->u0.req.timeout = timeout;
215 hdr->u0.req.request_length = pyld_len - sizeof(struct mbx_hdr);
216 hdr->u0.req.version = version;
217}
218
219
220
221/**
222 * @brief Function to initialize the hw with host endian information
223 * @param sc software handle to the device
224 * @returns 0 on success, ETIMEDOUT on failure
225 */
226int
227oce_mbox_init(POCE_SOFTC sc)
228{
229 struct oce_bmbx *mbx;
230 uint8_t *ptr;
231 int ret = 0;
232
233 if (sc->flags & OCE_FLAGS_MBOX_ENDIAN_RQD) {
234 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
235 ptr = (uint8_t *) &mbx->mbx;
236
237 /* Endian Signature */
238 *ptr++ = 0xff;
239 *ptr++ = 0x12;
240 *ptr++ = 0x34;
241 *ptr++ = 0xff;
242 *ptr++ = 0xff;
243 *ptr++ = 0x56;
244 *ptr++ = 0x78;
245 *ptr = 0xff;
246
247 ret = oce_mbox_dispatch(sc, 0);
248 }
249
250 return ret;
251}
252
253
254/**
255 * @brief Function to get the firmware version
256 * @param sc software handle to the device
257 * @returns 0 on success, EIO on failure
258 */
259int
260oce_get_fw_version(POCE_SOFTC sc)
261{
262 struct oce_mbx mbx;
263 struct mbx_get_common_fw_version *fwcmd;
264 int ret = 0;
265
266 bzero(&mbx, sizeof(struct oce_mbx));
267
268 fwcmd = (struct mbx_get_common_fw_version *)&mbx.payload;
269 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
270 MBX_SUBSYSTEM_COMMON,
271 OPCODE_COMMON_GET_FW_VERSION,
272 MBX_TIMEOUT_SEC,
273 sizeof(struct mbx_get_common_fw_version),
274 OCE_MBX_VER_V0);
275
276 mbx.u0.s.embedded = 1;
277 mbx.payload_length = sizeof(struct mbx_get_common_fw_version);
278 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
279
280 ret = oce_mbox_post(sc, &mbx, NULL);
281 if (!ret)
282 ret = fwcmd->hdr.u0.rsp.status;
283 if (ret) {
| 41#include "oce_if.h"
42extern uint32_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_NUM_ELE];
43
44/**
45 * @brief Reset (firmware) common function
46 * @param sc software handle to the device
47 * @returns 0 on success, ETIMEDOUT on failure
48 */
49int
50oce_reset_fun(POCE_SOFTC sc)
51{
52 struct oce_mbx *mbx;
53 struct oce_bmbx *mb;
54 struct ioctl_common_function_reset *fwcmd;
55 int rc = 0;
56
57 if (sc->flags & OCE_FLAGS_FUNCRESET_RQD) {
58 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
59 mbx = &mb->mbx;
60 bzero(mbx, sizeof(struct oce_mbx));
61
62 fwcmd = (struct ioctl_common_function_reset *)&mbx->payload;
63 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
64 MBX_SUBSYSTEM_COMMON,
65 OPCODE_COMMON_FUNCTION_RESET,
66 10, /* MBX_TIMEOUT_SEC */
67 sizeof(struct
68 ioctl_common_function_reset),
69 OCE_MBX_VER_V0);
70
71 mbx->u0.s.embedded = 1;
72 mbx->payload_length =
73 sizeof(struct ioctl_common_function_reset);
74
75 rc = oce_mbox_dispatch(sc, 2);
76 }
77
78 return rc;
79}
80
81
82/**
83 * @brief This funtions tells firmware we are
84 * done with commands.
85 * @param sc software handle to the device
86 * @returns 0 on success, ETIMEDOUT on failure
87 */
88int
89oce_fw_clean(POCE_SOFTC sc)
90{
91 struct oce_bmbx *mbx;
92 uint8_t *ptr;
93 int ret = 0;
94
95 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
96 ptr = (uint8_t *) &mbx->mbx;
97
98 /* Endian Signature */
99 *ptr++ = 0xff;
100 *ptr++ = 0xaa;
101 *ptr++ = 0xbb;
102 *ptr++ = 0xff;
103 *ptr++ = 0xff;
104 *ptr++ = 0xcc;
105 *ptr++ = 0xdd;
106 *ptr = 0xff;
107
108 ret = oce_mbox_dispatch(sc, 2);
109
110 return ret;
111}
112
113
114/**
115 * @brief Mailbox wait
116 * @param sc software handle to the device
117 * @param tmo_sec timeout in seconds
118 */
119static int
120oce_mbox_wait(POCE_SOFTC sc, uint32_t tmo_sec)
121{
122 tmo_sec *= 10000;
123 pd_mpu_mbox_db_t mbox_db;
124
125 for (;;) {
126 if (tmo_sec != 0) {
127 if (--tmo_sec == 0)
128 break;
129 }
130
131 mbox_db.dw0 = OCE_READ_REG32(sc, db, PD_MPU_MBOX_DB);
132
133 if (mbox_db.bits.ready)
134 return 0;
135
136 DELAY(100);
137 }
138
139 device_printf(sc->dev, "Mailbox timed out\n");
140
141 return ETIMEDOUT;
142}
143
144
145/**
146 * @brief Mailbox dispatch
147 * @param sc software handle to the device
148 * @param tmo_sec timeout in seconds
149 */
150int
151oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec)
152{
153 pd_mpu_mbox_db_t mbox_db;
154 uint32_t pa;
155 int rc;
156
157 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_PREWRITE);
158 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 34);
159 bzero(&mbox_db, sizeof(pd_mpu_mbox_db_t));
160 mbox_db.bits.ready = 0;
161 mbox_db.bits.hi = 1;
162 mbox_db.bits.address = pa;
163
164 rc = oce_mbox_wait(sc, tmo_sec);
165 if (rc == 0) {
166 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
167
168 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 4) & 0x3fffffff;
169 mbox_db.bits.ready = 0;
170 mbox_db.bits.hi = 0;
171 mbox_db.bits.address = pa;
172
173 rc = oce_mbox_wait(sc, tmo_sec);
174
175 if (rc == 0) {
176 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
177
178 rc = oce_mbox_wait(sc, tmo_sec);
179
180 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_POSTWRITE);
181 }
182 }
183
184 return rc;
185}
186
187
188
189/**
190 * @brief Mailbox common request header initialization
191 * @param hdr mailbox header
192 * @param dom domain
193 * @param port port
194 * @param subsys subsystem
195 * @param opcode opcode
196 * @param timeout timeout
197 * @param pyld_len payload length
198 */
199void
200mbx_common_req_hdr_init(struct mbx_hdr *hdr,
201 uint8_t dom, uint8_t port,
202 uint8_t subsys, uint8_t opcode,
203 uint32_t timeout, uint32_t pyld_len,
204 uint8_t version)
205{
206 hdr->u0.req.opcode = opcode;
207 hdr->u0.req.subsystem = subsys;
208 hdr->u0.req.port_number = port;
209 hdr->u0.req.domain = dom;
210
211 hdr->u0.req.timeout = timeout;
212 hdr->u0.req.request_length = pyld_len - sizeof(struct mbx_hdr);
213 hdr->u0.req.version = version;
214}
215
216
217
218/**
219 * @brief Function to initialize the hw with host endian information
220 * @param sc software handle to the device
221 * @returns 0 on success, ETIMEDOUT on failure
222 */
223int
224oce_mbox_init(POCE_SOFTC sc)
225{
226 struct oce_bmbx *mbx;
227 uint8_t *ptr;
228 int ret = 0;
229
230 if (sc->flags & OCE_FLAGS_MBOX_ENDIAN_RQD) {
231 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
232 ptr = (uint8_t *) &mbx->mbx;
233
234 /* Endian Signature */
235 *ptr++ = 0xff;
236 *ptr++ = 0x12;
237 *ptr++ = 0x34;
238 *ptr++ = 0xff;
239 *ptr++ = 0xff;
240 *ptr++ = 0x56;
241 *ptr++ = 0x78;
242 *ptr = 0xff;
243
244 ret = oce_mbox_dispatch(sc, 0);
245 }
246
247 return ret;
248}
249
250
251/**
252 * @brief Function to get the firmware version
253 * @param sc software handle to the device
254 * @returns 0 on success, EIO on failure
255 */
256int
257oce_get_fw_version(POCE_SOFTC sc)
258{
259 struct oce_mbx mbx;
260 struct mbx_get_common_fw_version *fwcmd;
261 int ret = 0;
262
263 bzero(&mbx, sizeof(struct oce_mbx));
264
265 fwcmd = (struct mbx_get_common_fw_version *)&mbx.payload;
266 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
267 MBX_SUBSYSTEM_COMMON,
268 OPCODE_COMMON_GET_FW_VERSION,
269 MBX_TIMEOUT_SEC,
270 sizeof(struct mbx_get_common_fw_version),
271 OCE_MBX_VER_V0);
272
273 mbx.u0.s.embedded = 1;
274 mbx.payload_length = sizeof(struct mbx_get_common_fw_version);
275 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
276
277 ret = oce_mbox_post(sc, &mbx, NULL);
278 if (!ret)
279 ret = fwcmd->hdr.u0.rsp.status;
280 if (ret) {
|
284 device_printf(sc->dev,"%s failed - cmd status: %d\n",
285 __FUNCTION__, ret);
| 281 device_printf(sc->dev,
282 "%s failed - cmd status: %d addi status: %d\n",
283 __FUNCTION__, ret,
284 fwcmd->hdr.u0.rsp.additional_status);
|
286 goto error;
287 }
288
289 bcopy(fwcmd->params.rsp.fw_ver_str, sc->fw_version, 32);
290error:
291 return ret;
292}
293
294
295/**
296 * @brief Firmware will send gracious notifications during
297 * attach only after sending first mcc commnad. We
298 * use MCC queue only for getting async and mailbox
299 * for sending cmds. So to get gracious notifications
300 * atleast send one dummy command on mcc.
301 */
302int
303oce_first_mcc_cmd(POCE_SOFTC sc)
304{
305 struct oce_mbx *mbx;
306 struct oce_mq *mq = sc->mq;
307 struct mbx_get_common_fw_version *fwcmd;
308 uint32_t reg_value;
309
310 mbx = RING_GET_PRODUCER_ITEM_VA(mq->ring, struct oce_mbx);
311 bzero(mbx, sizeof(struct oce_mbx));
312
313 fwcmd = (struct mbx_get_common_fw_version *)&mbx->payload;
314 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
315 MBX_SUBSYSTEM_COMMON,
316 OPCODE_COMMON_GET_FW_VERSION,
317 MBX_TIMEOUT_SEC,
318 sizeof(struct mbx_get_common_fw_version),
319 OCE_MBX_VER_V0);
320 mbx->u0.s.embedded = 1;
321 mbx->payload_length = sizeof(struct mbx_get_common_fw_version);
322 bus_dmamap_sync(mq->ring->dma.tag, mq->ring->dma.map,
323 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
324 RING_PUT(mq->ring, 1);
325 reg_value = (1 << 16) | mq->mq_id;
326 OCE_WRITE_REG32(sc, db, PD_MQ_DB, reg_value);
327
328 return 0;
329}
330
331/**
332 * @brief Function to post a MBX to the mbox
333 * @param sc software handle to the device
334 * @param mbx pointer to the MBX to send
335 * @param mbxctx pointer to the mbx context structure
336 * @returns 0 on success, error on failure
337 */
338int
339oce_mbox_post(POCE_SOFTC sc, struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx)
340{
341 struct oce_mbx *mb_mbx = NULL;
342 struct oce_mq_cqe *mb_cqe = NULL;
343 struct oce_bmbx *mb = NULL;
344 int rc = 0;
345 uint32_t tmo = 0;
346 uint32_t cstatus = 0;
347 uint32_t xstatus = 0;
348
349 LOCK(&sc->bmbx_lock);
350
351 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
352 mb_mbx = &mb->mbx;
353
354 /* get the tmo */
355 tmo = mbx->tag[0];
356 mbx->tag[0] = 0;
357
358 /* copy mbx into mbox */
359 bcopy(mbx, mb_mbx, sizeof(struct oce_mbx));
360
361 /* now dispatch */
362 rc = oce_mbox_dispatch(sc, tmo);
363 if (rc == 0) {
364 /*
365 * the command completed successfully. Now get the
366 * completion queue entry
367 */
368 mb_cqe = &mb->cqe;
369 DW_SWAP(u32ptr(&mb_cqe->u0.dw[0]), sizeof(struct oce_mq_cqe));
370
371 /* copy mbox mbx back */
372 bcopy(mb_mbx, mbx, sizeof(struct oce_mbx));
373
374 /* pick up the mailbox status */
375 cstatus = mb_cqe->u0.s.completion_status;
376 xstatus = mb_cqe->u0.s.extended_status;
377
378 /*
379 * store the mbx context in the cqe tag section so that
380 * the upper layer handling the cqe can associate the mbx
381 * with the response
382 */
383 if (cstatus == 0 && mbxctx) {
384 /* save context */
385 mbxctx->mbx = mb_mbx;
386 bcopy(&mbxctx, mb_cqe->u0.s.mq_tag,
387 sizeof(struct oce_mbx_ctx *));
388 }
389 }
390
391 UNLOCK(&sc->bmbx_lock);
392
393 return rc;
394}
395
396/**
397 * @brief Function to read the mac address associated with an interface
398 * @param sc software handle to the device
399 * @param if_id interface id to read the address from
400 * @param perm set to 1 if reading the factory mac address.
401 * In this case if_id is ignored
402 * @param type type of the mac address, whether network or storage
403 * @param[out] mac [OUTPUT] pointer to a buffer containing the
404 * mac address when the command succeeds.
405 * @returns 0 on success, EIO on failure
406 */
407int
408oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id,
409 uint8_t perm, uint8_t type, struct mac_address_format *mac)
410{
411 struct oce_mbx mbx;
412 struct mbx_query_common_iface_mac *fwcmd;
413 int ret = 0;
414
415 bzero(&mbx, sizeof(struct oce_mbx));
416
417 fwcmd = (struct mbx_query_common_iface_mac *)&mbx.payload;
418 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
419 MBX_SUBSYSTEM_COMMON,
420 OPCODE_COMMON_QUERY_IFACE_MAC,
421 MBX_TIMEOUT_SEC,
422 sizeof(struct mbx_query_common_iface_mac),
423 OCE_MBX_VER_V0);
424
425 fwcmd->params.req.permanent = perm;
426 if (!perm)
427 fwcmd->params.req.if_id = (uint16_t) if_id;
428 else
429 fwcmd->params.req.if_id = 0;
430
431 fwcmd->params.req.type = type;
432
433 mbx.u0.s.embedded = 1;
434 mbx.payload_length = sizeof(struct mbx_query_common_iface_mac);
435 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
436
437 ret = oce_mbox_post(sc, &mbx, NULL);
438 if (!ret)
439 ret = fwcmd->hdr.u0.rsp.status;
440 if (ret) {
| 285 goto error;
286 }
287
288 bcopy(fwcmd->params.rsp.fw_ver_str, sc->fw_version, 32);
289error:
290 return ret;
291}
292
293
294/**
295 * @brief Firmware will send gracious notifications during
296 * attach only after sending first mcc commnad. We
297 * use MCC queue only for getting async and mailbox
298 * for sending cmds. So to get gracious notifications
299 * atleast send one dummy command on mcc.
300 */
301int
302oce_first_mcc_cmd(POCE_SOFTC sc)
303{
304 struct oce_mbx *mbx;
305 struct oce_mq *mq = sc->mq;
306 struct mbx_get_common_fw_version *fwcmd;
307 uint32_t reg_value;
308
309 mbx = RING_GET_PRODUCER_ITEM_VA(mq->ring, struct oce_mbx);
310 bzero(mbx, sizeof(struct oce_mbx));
311
312 fwcmd = (struct mbx_get_common_fw_version *)&mbx->payload;
313 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
314 MBX_SUBSYSTEM_COMMON,
315 OPCODE_COMMON_GET_FW_VERSION,
316 MBX_TIMEOUT_SEC,
317 sizeof(struct mbx_get_common_fw_version),
318 OCE_MBX_VER_V0);
319 mbx->u0.s.embedded = 1;
320 mbx->payload_length = sizeof(struct mbx_get_common_fw_version);
321 bus_dmamap_sync(mq->ring->dma.tag, mq->ring->dma.map,
322 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
323 RING_PUT(mq->ring, 1);
324 reg_value = (1 << 16) | mq->mq_id;
325 OCE_WRITE_REG32(sc, db, PD_MQ_DB, reg_value);
326
327 return 0;
328}
329
330/**
331 * @brief Function to post a MBX to the mbox
332 * @param sc software handle to the device
333 * @param mbx pointer to the MBX to send
334 * @param mbxctx pointer to the mbx context structure
335 * @returns 0 on success, error on failure
336 */
337int
338oce_mbox_post(POCE_SOFTC sc, struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx)
339{
340 struct oce_mbx *mb_mbx = NULL;
341 struct oce_mq_cqe *mb_cqe = NULL;
342 struct oce_bmbx *mb = NULL;
343 int rc = 0;
344 uint32_t tmo = 0;
345 uint32_t cstatus = 0;
346 uint32_t xstatus = 0;
347
348 LOCK(&sc->bmbx_lock);
349
350 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
351 mb_mbx = &mb->mbx;
352
353 /* get the tmo */
354 tmo = mbx->tag[0];
355 mbx->tag[0] = 0;
356
357 /* copy mbx into mbox */
358 bcopy(mbx, mb_mbx, sizeof(struct oce_mbx));
359
360 /* now dispatch */
361 rc = oce_mbox_dispatch(sc, tmo);
362 if (rc == 0) {
363 /*
364 * the command completed successfully. Now get the
365 * completion queue entry
366 */
367 mb_cqe = &mb->cqe;
368 DW_SWAP(u32ptr(&mb_cqe->u0.dw[0]), sizeof(struct oce_mq_cqe));
369
370 /* copy mbox mbx back */
371 bcopy(mb_mbx, mbx, sizeof(struct oce_mbx));
372
373 /* pick up the mailbox status */
374 cstatus = mb_cqe->u0.s.completion_status;
375 xstatus = mb_cqe->u0.s.extended_status;
376
377 /*
378 * store the mbx context in the cqe tag section so that
379 * the upper layer handling the cqe can associate the mbx
380 * with the response
381 */
382 if (cstatus == 0 && mbxctx) {
383 /* save context */
384 mbxctx->mbx = mb_mbx;
385 bcopy(&mbxctx, mb_cqe->u0.s.mq_tag,
386 sizeof(struct oce_mbx_ctx *));
387 }
388 }
389
390 UNLOCK(&sc->bmbx_lock);
391
392 return rc;
393}
394
395/**
396 * @brief Function to read the mac address associated with an interface
397 * @param sc software handle to the device
398 * @param if_id interface id to read the address from
399 * @param perm set to 1 if reading the factory mac address.
400 * In this case if_id is ignored
401 * @param type type of the mac address, whether network or storage
402 * @param[out] mac [OUTPUT] pointer to a buffer containing the
403 * mac address when the command succeeds.
404 * @returns 0 on success, EIO on failure
405 */
406int
407oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id,
408 uint8_t perm, uint8_t type, struct mac_address_format *mac)
409{
410 struct oce_mbx mbx;
411 struct mbx_query_common_iface_mac *fwcmd;
412 int ret = 0;
413
414 bzero(&mbx, sizeof(struct oce_mbx));
415
416 fwcmd = (struct mbx_query_common_iface_mac *)&mbx.payload;
417 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
418 MBX_SUBSYSTEM_COMMON,
419 OPCODE_COMMON_QUERY_IFACE_MAC,
420 MBX_TIMEOUT_SEC,
421 sizeof(struct mbx_query_common_iface_mac),
422 OCE_MBX_VER_V0);
423
424 fwcmd->params.req.permanent = perm;
425 if (!perm)
426 fwcmd->params.req.if_id = (uint16_t) if_id;
427 else
428 fwcmd->params.req.if_id = 0;
429
430 fwcmd->params.req.type = type;
431
432 mbx.u0.s.embedded = 1;
433 mbx.payload_length = sizeof(struct mbx_query_common_iface_mac);
434 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
435
436 ret = oce_mbox_post(sc, &mbx, NULL);
437 if (!ret)
438 ret = fwcmd->hdr.u0.rsp.status;
439 if (ret) {
|
441 device_printf(sc->dev,"%s failed - cmd status: %d\n",
442 __FUNCTION__, ret);
| 440 device_printf(sc->dev,
441 "%s failed - cmd status: %d addi status: %d\n",
442 __FUNCTION__, ret,
443 fwcmd->hdr.u0.rsp.additional_status);
|
443 goto error;
444 }
445
446 /* copy the mac addres in the output parameter */
447 mac->size_of_struct = fwcmd->params.rsp.mac.size_of_struct;
448 bcopy(&fwcmd->params.rsp.mac.mac_addr[0], &mac->mac_addr[0],
449 mac->size_of_struct);
450error:
451 return ret;
452}
453
454/**
455 * @brief Function to query the fw attributes from the hw
456 * @param sc software handle to the device
457 * @returns 0 on success, EIO on failure
458 */
459int
460oce_get_fw_config(POCE_SOFTC sc)
461{
462 struct oce_mbx mbx;
463 struct mbx_common_query_fw_config *fwcmd;
464 int ret = 0;
465
466 bzero(&mbx, sizeof(struct oce_mbx));
467
468 fwcmd = (struct mbx_common_query_fw_config *)&mbx.payload;
469 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
470 MBX_SUBSYSTEM_COMMON,
471 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
472 MBX_TIMEOUT_SEC,
473 sizeof(struct mbx_common_query_fw_config),
474 OCE_MBX_VER_V0);
475
476 mbx.u0.s.embedded = 1;
477 mbx.payload_length = sizeof(struct mbx_common_query_fw_config);
478 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
479
480 ret = oce_mbox_post(sc, &mbx, NULL);
481 if (!ret)
482 ret = fwcmd->hdr.u0.rsp.status;
483 if (ret) {
| 444 goto error;
445 }
446
447 /* copy the mac addres in the output parameter */
448 mac->size_of_struct = fwcmd->params.rsp.mac.size_of_struct;
449 bcopy(&fwcmd->params.rsp.mac.mac_addr[0], &mac->mac_addr[0],
450 mac->size_of_struct);
451error:
452 return ret;
453}
454
455/**
456 * @brief Function to query the fw attributes from the hw
457 * @param sc software handle to the device
458 * @returns 0 on success, EIO on failure
459 */
460int
461oce_get_fw_config(POCE_SOFTC sc)
462{
463 struct oce_mbx mbx;
464 struct mbx_common_query_fw_config *fwcmd;
465 int ret = 0;
466
467 bzero(&mbx, sizeof(struct oce_mbx));
468
469 fwcmd = (struct mbx_common_query_fw_config *)&mbx.payload;
470 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
471 MBX_SUBSYSTEM_COMMON,
472 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
473 MBX_TIMEOUT_SEC,
474 sizeof(struct mbx_common_query_fw_config),
475 OCE_MBX_VER_V0);
476
477 mbx.u0.s.embedded = 1;
478 mbx.payload_length = sizeof(struct mbx_common_query_fw_config);
479 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
480
481 ret = oce_mbox_post(sc, &mbx, NULL);
482 if (!ret)
483 ret = fwcmd->hdr.u0.rsp.status;
484 if (ret) {
|
484 device_printf(sc->dev,"%s failed - cmd status: %d\n",
485 __FUNCTION__, ret);
| 485 device_printf(sc->dev,
486 "%s failed - cmd status: %d addi status: %d\n",
487 __FUNCTION__, ret,
488 fwcmd->hdr.u0.rsp.additional_status);
|
486 goto error;
487 }
488
489 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config));
490
| 489 goto error;
490 }
491
492 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config));
493
|
491 sc->config_number = fwcmd->params.rsp.config_number;
492 sc->asic_revision = fwcmd->params.rsp.asic_revision;
493 sc->port_id = fwcmd->params.rsp.port_id;
494 sc->function_mode = fwcmd->params.rsp.function_mode;
495 sc->function_caps = fwcmd->params.rsp.function_caps;
| 494 sc->config_number = HOST_32(fwcmd->params.rsp.config_number);
495 sc->asic_revision = HOST_32(fwcmd->params.rsp.asic_revision);
496 sc->port_id = HOST_32(fwcmd->params.rsp.port_id);
497 sc->function_mode = HOST_32(fwcmd->params.rsp.function_mode);
498 sc->function_caps = HOST_32(fwcmd->params.rsp.function_caps);
|
496
497 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) {
| 499
500 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) {
|
498 sc->max_tx_rings = fwcmd->params.rsp.ulp[0].nic_wq_tot;
499 sc->max_rx_rings = fwcmd->params.rsp.ulp[0].lro_rqid_tot;
| 501 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[0].nic_wq_tot);
502 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[0].lro_rqid_tot);
|
500 } else {
| 503 } else {
|
501 sc->max_tx_rings = fwcmd->params.rsp.ulp[1].nic_wq_tot;
502 sc->max_rx_rings = fwcmd->params.rsp.ulp[1].lro_rqid_tot;
| 504 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[1].nic_wq_tot);
505 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[1].lro_rqid_tot);
|
503 }
504
505error:
506 return ret;
507
508}
509
510/**
511 *
512 * @brief function to create a device interface
513 * @param sc software handle to the device
514 * @param cap_flags capability flags
515 * @param en_flags enable capability flags
516 * @param vlan_tag optional vlan tag to associate with the if
517 * @param mac_addr pointer to a buffer containing the mac address
518 * @param[out] if_id [OUTPUT] pointer to an integer to hold the ID of the
519 interface created
520 * @returns 0 on success, EIO on failure
521 */
522int
523oce_if_create(POCE_SOFTC sc,
524 uint32_t cap_flags,
525 uint32_t en_flags,
526 uint16_t vlan_tag,
527 uint8_t *mac_addr,
528 uint32_t *if_id)
529{
530 struct oce_mbx mbx;
531 struct mbx_create_common_iface *fwcmd;
532 int rc = 0;
533
534 bzero(&mbx, sizeof(struct oce_mbx));
535
536 fwcmd = (struct mbx_create_common_iface *)&mbx.payload;
537 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
538 MBX_SUBSYSTEM_COMMON,
539 OPCODE_COMMON_CREATE_IFACE,
540 MBX_TIMEOUT_SEC,
541 sizeof(struct mbx_create_common_iface),
542 OCE_MBX_VER_V0);
543 DW_SWAP(u32ptr(&fwcmd->hdr), sizeof(struct mbx_hdr));
544
545 fwcmd->params.req.version = 0;
546 fwcmd->params.req.cap_flags = LE_32(cap_flags);
547 fwcmd->params.req.enable_flags = LE_32(en_flags);
548 if (mac_addr != NULL) {
549 bcopy(mac_addr, &fwcmd->params.req.mac_addr[0], 6);
550 fwcmd->params.req.vlan_tag.u0.normal.vtag = LE_16(vlan_tag);
551 fwcmd->params.req.mac_invalid = 0;
552 } else {
553 fwcmd->params.req.mac_invalid = 1;
554 }
555
556 mbx.u0.s.embedded = 1;
557 mbx.payload_length = sizeof(struct mbx_create_common_iface);
558 DW_SWAP(u32ptr(&mbx), OCE_BMBX_RHDR_SZ);
559
560 rc = oce_mbox_post(sc, &mbx, NULL);
561 if (!rc)
562 rc = fwcmd->hdr.u0.rsp.status;
563 if (rc) {
| 506 }
507
508error:
509 return ret;
510
511}
512
513/**
514 *
515 * @brief function to create a device interface
516 * @param sc software handle to the device
517 * @param cap_flags capability flags
518 * @param en_flags enable capability flags
519 * @param vlan_tag optional vlan tag to associate with the if
520 * @param mac_addr pointer to a buffer containing the mac address
521 * @param[out] if_id [OUTPUT] pointer to an integer to hold the ID of the
522 interface created
523 * @returns 0 on success, EIO on failure
524 */
525int
526oce_if_create(POCE_SOFTC sc,
527 uint32_t cap_flags,
528 uint32_t en_flags,
529 uint16_t vlan_tag,
530 uint8_t *mac_addr,
531 uint32_t *if_id)
532{
533 struct oce_mbx mbx;
534 struct mbx_create_common_iface *fwcmd;
535 int rc = 0;
536
537 bzero(&mbx, sizeof(struct oce_mbx));
538
539 fwcmd = (struct mbx_create_common_iface *)&mbx.payload;
540 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
541 MBX_SUBSYSTEM_COMMON,
542 OPCODE_COMMON_CREATE_IFACE,
543 MBX_TIMEOUT_SEC,
544 sizeof(struct mbx_create_common_iface),
545 OCE_MBX_VER_V0);
546 DW_SWAP(u32ptr(&fwcmd->hdr), sizeof(struct mbx_hdr));
547
548 fwcmd->params.req.version = 0;
549 fwcmd->params.req.cap_flags = LE_32(cap_flags);
550 fwcmd->params.req.enable_flags = LE_32(en_flags);
551 if (mac_addr != NULL) {
552 bcopy(mac_addr, &fwcmd->params.req.mac_addr[0], 6);
553 fwcmd->params.req.vlan_tag.u0.normal.vtag = LE_16(vlan_tag);
554 fwcmd->params.req.mac_invalid = 0;
555 } else {
556 fwcmd->params.req.mac_invalid = 1;
557 }
558
559 mbx.u0.s.embedded = 1;
560 mbx.payload_length = sizeof(struct mbx_create_common_iface);
561 DW_SWAP(u32ptr(&mbx), OCE_BMBX_RHDR_SZ);
562
563 rc = oce_mbox_post(sc, &mbx, NULL);
564 if (!rc)
565 rc = fwcmd->hdr.u0.rsp.status;
566 if (rc) {
|
564 device_printf(sc->dev,"%s failed - cmd status: %d\n",
565 __FUNCTION__, rc);
| 567 device_printf(sc->dev,
568 "%s failed - cmd status: %d addi status: %d\n",
569 __FUNCTION__, rc,
570 fwcmd->hdr.u0.rsp.additional_status);
|
566 goto error;
567 }
568
| 571 goto error;
572 }
573
|
569 *if_id = LE_32(fwcmd->params.rsp.if_id);
| 574 *if_id = HOST_32(fwcmd->params.rsp.if_id);
|
570
571 if (mac_addr != NULL)
| 575
576 if (mac_addr != NULL)
|
572 sc->pmac_id = LE_32(fwcmd->params.rsp.pmac_id);
| 577 sc->pmac_id = HOST_32(fwcmd->params.rsp.pmac_id);
|
573error:
574 return rc;
575}
576
577/**
578 * @brief Function to delete an interface
579 * @param sc software handle to the device
580 * @param if_id ID of the interface to delete
581 * @returns 0 on success, EIO on failure
582 */
583int
584oce_if_del(POCE_SOFTC sc, uint32_t if_id)
585{
586 struct oce_mbx mbx;
587 struct mbx_destroy_common_iface *fwcmd;
588 int rc = 0;
589
590 bzero(&mbx, sizeof(struct oce_mbx));
591
592 fwcmd = (struct mbx_destroy_common_iface *)&mbx.payload;
593 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
594 MBX_SUBSYSTEM_COMMON,
595 OPCODE_COMMON_DESTROY_IFACE,
596 MBX_TIMEOUT_SEC,
597 sizeof(struct mbx_destroy_common_iface),
598 OCE_MBX_VER_V0);
599
600 fwcmd->params.req.if_id = if_id;
601
602 mbx.u0.s.embedded = 1;
603 mbx.payload_length = sizeof(struct mbx_destroy_common_iface);
604 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
605
606 rc = oce_mbox_post(sc, &mbx, NULL);
607 if (!rc)
608 rc = fwcmd->hdr.u0.rsp.status;
609 if (rc)
| 578error:
579 return rc;
580}
581
582/**
583 * @brief Function to delete an interface
584 * @param sc software handle to the device
585 * @param if_id ID of the interface to delete
586 * @returns 0 on success, EIO on failure
587 */
588int
589oce_if_del(POCE_SOFTC sc, uint32_t if_id)
590{
591 struct oce_mbx mbx;
592 struct mbx_destroy_common_iface *fwcmd;
593 int rc = 0;
594
595 bzero(&mbx, sizeof(struct oce_mbx));
596
597 fwcmd = (struct mbx_destroy_common_iface *)&mbx.payload;
598 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
599 MBX_SUBSYSTEM_COMMON,
600 OPCODE_COMMON_DESTROY_IFACE,
601 MBX_TIMEOUT_SEC,
602 sizeof(struct mbx_destroy_common_iface),
603 OCE_MBX_VER_V0);
604
605 fwcmd->params.req.if_id = if_id;
606
607 mbx.u0.s.embedded = 1;
608 mbx.payload_length = sizeof(struct mbx_destroy_common_iface);
609 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
610
611 rc = oce_mbox_post(sc, &mbx, NULL);
612 if (!rc)
613 rc = fwcmd->hdr.u0.rsp.status;
614 if (rc)
|
610 device_printf(sc->dev,"%s failed - cmd status: %d\n",
611 __FUNCTION__, rc);
| 615 device_printf(sc->dev,
616 "%s failed - cmd status: %d addi status: %d\n",
617 __FUNCTION__, rc,
618 fwcmd->hdr.u0.rsp.additional_status);
|
612 return rc;
613}
614
615/**
616 * @brief Function to send the mbx command to configure vlan
617 * @param sc software handle to the device
618 * @param if_id interface identifier index
619 * @param vtag_arr array of vlan tags
620 * @param vtag_cnt number of elements in array
621 * @param untagged boolean TRUE/FLASE
622 * @param enable_promisc flag to enable/disable VLAN promiscuous mode
623 * @returns 0 on success, EIO on failure
624 */
625int
626oce_config_vlan(POCE_SOFTC sc,
627 uint32_t if_id,
628 struct normal_vlan *vtag_arr,
629 uint8_t vtag_cnt, uint32_t untagged, uint32_t enable_promisc)
630{
631 struct oce_mbx mbx;
632 struct mbx_common_config_vlan *fwcmd;
| 619 return rc;
620}
621
622/**
623 * @brief Function to send the mbx command to configure vlan
624 * @param sc software handle to the device
625 * @param if_id interface identifier index
626 * @param vtag_arr array of vlan tags
627 * @param vtag_cnt number of elements in array
628 * @param untagged boolean TRUE/FLASE
629 * @param enable_promisc flag to enable/disable VLAN promiscuous mode
630 * @returns 0 on success, EIO on failure
631 */
632int
633oce_config_vlan(POCE_SOFTC sc,
634 uint32_t if_id,
635 struct normal_vlan *vtag_arr,
636 uint8_t vtag_cnt, uint32_t untagged, uint32_t enable_promisc)
637{
638 struct oce_mbx mbx;
639 struct mbx_common_config_vlan *fwcmd;
|
633 int rc;
| 640 int rc = 0;
|
634
| 641
|
| 642 if (sc->vlans_added > sc->max_vlans)
643 goto vlan_promisc;
644
|
635 bzero(&mbx, sizeof(struct oce_mbx));
636 fwcmd = (struct mbx_common_config_vlan *)&mbx.payload;
637
638 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
639 MBX_SUBSYSTEM_COMMON,
640 OPCODE_COMMON_CONFIG_IFACE_VLAN,
641 MBX_TIMEOUT_SEC,
642 sizeof(struct mbx_common_config_vlan),
643 OCE_MBX_VER_V0);
644
645 fwcmd->params.req.if_id = (uint8_t) if_id;
646 fwcmd->params.req.promisc = (uint8_t) enable_promisc;
647 fwcmd->params.req.untagged = (uint8_t) untagged;
648 fwcmd->params.req.num_vlans = vtag_cnt;
649
650 if (!enable_promisc) {
651 bcopy(vtag_arr, fwcmd->params.req.tags.normal_vlans,
652 vtag_cnt * sizeof(struct normal_vlan));
653 }
654 mbx.u0.s.embedded = 1;
655 mbx.payload_length = sizeof(struct mbx_common_config_vlan);
656 DW_SWAP(u32ptr(&mbx), (OCE_BMBX_RHDR_SZ + mbx.payload_length));
657
658 rc = oce_mbox_post(sc, &mbx, NULL);
659 if (!rc)
660 rc = fwcmd->hdr.u0.rsp.status;
661 if (rc)
| 645 bzero(&mbx, sizeof(struct oce_mbx));
646 fwcmd = (struct mbx_common_config_vlan *)&mbx.payload;
647
648 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
649 MBX_SUBSYSTEM_COMMON,
650 OPCODE_COMMON_CONFIG_IFACE_VLAN,
651 MBX_TIMEOUT_SEC,
652 sizeof(struct mbx_common_config_vlan),
653 OCE_MBX_VER_V0);
654
655 fwcmd->params.req.if_id = (uint8_t) if_id;
656 fwcmd->params.req.promisc = (uint8_t) enable_promisc;
657 fwcmd->params.req.untagged = (uint8_t) untagged;
658 fwcmd->params.req.num_vlans = vtag_cnt;
659
660 if (!enable_promisc) {
661 bcopy(vtag_arr, fwcmd->params.req.tags.normal_vlans,
662 vtag_cnt * sizeof(struct normal_vlan));
663 }
664 mbx.u0.s.embedded = 1;
665 mbx.payload_length = sizeof(struct mbx_common_config_vlan);
666 DW_SWAP(u32ptr(&mbx), (OCE_BMBX_RHDR_SZ + mbx.payload_length));
667
668 rc = oce_mbox_post(sc, &mbx, NULL);
669 if (!rc)
670 rc = fwcmd->hdr.u0.rsp.status;
671 if (rc)
|
662 device_printf(sc->dev,"%s failed - cmd status: %d\n",
663 __FUNCTION__, rc);
664 return 0;
| 672 device_printf(sc->dev,
673 "%s failed - cmd status: %d addi status: %d\n",
674 __FUNCTION__, rc,
675 fwcmd->hdr.u0.rsp.additional_status);
|
665
| 676
|
| 677 goto done;
678
679vlan_promisc:
680 /* Enable Vlan Promis */
681 oce_rxf_set_promiscuous(sc, (1 << 1));
682 device_printf(sc->dev,"Enabling Vlan Promisc Mode\n");
683done:
684 return rc;
685
|
666}
667
668/**
669 * @brief Function to set flow control capability in the hardware
670 * @param sc software handle to the device
671 * @param flow_control flow control flags to set
672 * @returns 0 on success, EIO on failure
673 */
674int
675oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control)
676{
677 struct oce_mbx mbx;
678 struct mbx_common_get_set_flow_control *fwcmd =
679 (struct mbx_common_get_set_flow_control *)&mbx.payload;
680 int rc;
681
682 bzero(&mbx, sizeof(struct oce_mbx));
683
684 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
685 MBX_SUBSYSTEM_COMMON,
686 OPCODE_COMMON_SET_FLOW_CONTROL,
687 MBX_TIMEOUT_SEC,
688 sizeof(struct mbx_common_get_set_flow_control),
689 OCE_MBX_VER_V0);
690
691 if (flow_control & OCE_FC_TX)
692 fwcmd->tx_flow_control = 1;
693
694 if (flow_control & OCE_FC_RX)
695 fwcmd->rx_flow_control = 1;
696
697 mbx.u0.s.embedded = 1;
698 mbx.payload_length = sizeof(struct mbx_common_get_set_flow_control);
699 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
700
701 rc = oce_mbox_post(sc, &mbx, NULL);
702 if (!rc)
703 rc = fwcmd->hdr.u0.rsp.status;
704 if (rc)
| 686}
687
688/**
689 * @brief Function to set flow control capability in the hardware
690 * @param sc software handle to the device
691 * @param flow_control flow control flags to set
692 * @returns 0 on success, EIO on failure
693 */
694int
695oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control)
696{
697 struct oce_mbx mbx;
698 struct mbx_common_get_set_flow_control *fwcmd =
699 (struct mbx_common_get_set_flow_control *)&mbx.payload;
700 int rc;
701
702 bzero(&mbx, sizeof(struct oce_mbx));
703
704 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
705 MBX_SUBSYSTEM_COMMON,
706 OPCODE_COMMON_SET_FLOW_CONTROL,
707 MBX_TIMEOUT_SEC,
708 sizeof(struct mbx_common_get_set_flow_control),
709 OCE_MBX_VER_V0);
710
711 if (flow_control & OCE_FC_TX)
712 fwcmd->tx_flow_control = 1;
713
714 if (flow_control & OCE_FC_RX)
715 fwcmd->rx_flow_control = 1;
716
717 mbx.u0.s.embedded = 1;
718 mbx.payload_length = sizeof(struct mbx_common_get_set_flow_control);
719 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
720
721 rc = oce_mbox_post(sc, &mbx, NULL);
722 if (!rc)
723 rc = fwcmd->hdr.u0.rsp.status;
724 if (rc)
|
705 device_printf(sc->dev,"%s failed - cmd status: %d\n",
706 __FUNCTION__, rc);
| 725 device_printf(sc->dev,
726 "%s failed - cmd status: %d addi status: %d\n",
727 __FUNCTION__, rc,
728 fwcmd->hdr.u0.rsp.additional_status);
|
707 return rc;
708}
709
710/**
711 * @brief Initialize the RSS CPU indirection table
712 *
713 * The table is used to choose the queue to place the incomming packets.
714 * Incomming packets are hashed. The lowest bits in the hash result
715 * are used as the index into the CPU indirection table.
716 * Each entry in the table contains the RSS CPU-ID returned by the NIC
717 * create. Based on the CPU ID, the receive completion is routed to
718 * the corresponding RSS CQs. (Non-RSS packets are always completed
719 * on the default (0) CQ).
720 *
721 * @param sc software handle to the device
722 * @param *fwcmd pointer to the rss mbox command
723 * @returns none
724 */
725static int
726oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd)
727{
728 int i = 0, j = 0, rc = 0;
729 uint8_t *tbl = fwcmd->params.req.cputable;
730 struct oce_rq *rq = NULL;
731
732
733 for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) {
734 for_all_rss_queues(sc, rq, i) {
735 if ((j + i) >= INDIRECTION_TABLE_ENTRIES)
736 break;
737 tbl[j + i] = rq->rss_cpuid;
738 }
739 }
740 if (i == 0) {
741 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n");
742 rc = ENXIO;
743
744 }
745
746 /* fill log2 value indicating the size of the CPU table */
747 if (rc == 0)
748 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(i));
749
750 return rc;
751}
752
753/**
754 * @brief Function to set flow control capability in the hardware
755 * @param sc software handle to the device
756 * @param if_id interface id to read the address from
757 * @param enable_rss 0=disable, RSS_ENABLE_xxx flags otherwise
758 * @returns 0 on success, EIO on failure
759 */
760int
761oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss)
762{
763 int rc;
764 struct oce_mbx mbx;
765 struct mbx_config_nic_rss *fwcmd =
766 (struct mbx_config_nic_rss *)&mbx.payload;
767 int version;
768
769 bzero(&mbx, sizeof(struct oce_mbx));
770
771 if (IS_XE201(sc) || IS_SH(sc)) {
772 version = OCE_MBX_VER_V1;
773 fwcmd->params.req.enable_rss = RSS_ENABLE_UDP_IPV4 |
774 RSS_ENABLE_UDP_IPV6;
775 } else
776 version = OCE_MBX_VER_V0;
777
778 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
779 MBX_SUBSYSTEM_NIC,
780 NIC_CONFIG_RSS,
781 MBX_TIMEOUT_SEC,
782 sizeof(struct mbx_config_nic_rss),
783 version);
784 if (enable_rss)
785 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 |
786 RSS_ENABLE_TCP_IPV4 |
787 RSS_ENABLE_IPV6 |
788 RSS_ENABLE_TCP_IPV6);
789 fwcmd->params.req.flush = OCE_FLUSH;
790 fwcmd->params.req.if_id = LE_32(if_id);
791
792 srandom(arc4random()); /* random entropy seed */
793 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash));
794
795 rc = oce_rss_itbl_init(sc, fwcmd);
796 if (rc == 0) {
797 mbx.u0.s.embedded = 1;
798 mbx.payload_length = sizeof(struct mbx_config_nic_rss);
799 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
800
801 rc = oce_mbox_post(sc, &mbx, NULL);
802 if (!rc)
803 rc = fwcmd->hdr.u0.rsp.status;
804 if (rc)
| 729 return rc;
730}
731
732/**
733 * @brief Initialize the RSS CPU indirection table
734 *
735 * The table is used to choose the queue to place the incomming packets.
736 * Incomming packets are hashed. The lowest bits in the hash result
737 * are used as the index into the CPU indirection table.
738 * Each entry in the table contains the RSS CPU-ID returned by the NIC
739 * create. Based on the CPU ID, the receive completion is routed to
740 * the corresponding RSS CQs. (Non-RSS packets are always completed
741 * on the default (0) CQ).
742 *
743 * @param sc software handle to the device
744 * @param *fwcmd pointer to the rss mbox command
745 * @returns none
746 */
747static int
748oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd)
749{
750 int i = 0, j = 0, rc = 0;
751 uint8_t *tbl = fwcmd->params.req.cputable;
752 struct oce_rq *rq = NULL;
753
754
755 for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) {
756 for_all_rss_queues(sc, rq, i) {
757 if ((j + i) >= INDIRECTION_TABLE_ENTRIES)
758 break;
759 tbl[j + i] = rq->rss_cpuid;
760 }
761 }
762 if (i == 0) {
763 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n");
764 rc = ENXIO;
765
766 }
767
768 /* fill log2 value indicating the size of the CPU table */
769 if (rc == 0)
770 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(i));
771
772 return rc;
773}
774
775/**
776 * @brief Function to set flow control capability in the hardware
777 * @param sc software handle to the device
778 * @param if_id interface id to read the address from
779 * @param enable_rss 0=disable, RSS_ENABLE_xxx flags otherwise
780 * @returns 0 on success, EIO on failure
781 */
782int
783oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss)
784{
785 int rc;
786 struct oce_mbx mbx;
787 struct mbx_config_nic_rss *fwcmd =
788 (struct mbx_config_nic_rss *)&mbx.payload;
789 int version;
790
791 bzero(&mbx, sizeof(struct oce_mbx));
792
793 if (IS_XE201(sc) || IS_SH(sc)) {
794 version = OCE_MBX_VER_V1;
795 fwcmd->params.req.enable_rss = RSS_ENABLE_UDP_IPV4 |
796 RSS_ENABLE_UDP_IPV6;
797 } else
798 version = OCE_MBX_VER_V0;
799
800 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
801 MBX_SUBSYSTEM_NIC,
802 NIC_CONFIG_RSS,
803 MBX_TIMEOUT_SEC,
804 sizeof(struct mbx_config_nic_rss),
805 version);
806 if (enable_rss)
807 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 |
808 RSS_ENABLE_TCP_IPV4 |
809 RSS_ENABLE_IPV6 |
810 RSS_ENABLE_TCP_IPV6);
811 fwcmd->params.req.flush = OCE_FLUSH;
812 fwcmd->params.req.if_id = LE_32(if_id);
813
814 srandom(arc4random()); /* random entropy seed */
815 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash));
816
817 rc = oce_rss_itbl_init(sc, fwcmd);
818 if (rc == 0) {
819 mbx.u0.s.embedded = 1;
820 mbx.payload_length = sizeof(struct mbx_config_nic_rss);
821 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
822
823 rc = oce_mbox_post(sc, &mbx, NULL);
824 if (!rc)
825 rc = fwcmd->hdr.u0.rsp.status;
826 if (rc)
|
805 device_printf(sc->dev,"%s failed - cmd status: %d\n",
806 __FUNCTION__, rc);
| 827 device_printf(sc->dev,
828 "%s failed - cmd status: %d addi status: %d\n",
829 __FUNCTION__, rc,
830 fwcmd->hdr.u0.rsp.additional_status);
|
807 }
808 return rc;
809}
810
811/**
812 * @brief RXF function to enable/disable device promiscuous mode
813 * @param sc software handle to the device
814 * @param enable enable/disable flag
815 * @returns 0 on success, EIO on failure
816 * @note
817 * The NIC_CONFIG_PROMISCUOUS command deprecated for Lancer.
818 * This function uses the COMMON_SET_IFACE_RX_FILTER command instead.
819 */
820int
| 831 }
832 return rc;
833}
834
835/**
836 * @brief RXF function to enable/disable device promiscuous mode
837 * @param sc software handle to the device
838 * @param enable enable/disable flag
839 * @returns 0 on success, EIO on failure
840 * @note
841 * The NIC_CONFIG_PROMISCUOUS command deprecated for Lancer.
842 * This function uses the COMMON_SET_IFACE_RX_FILTER command instead.
843 */
844int
|
821oce_rxf_set_promiscuous(POCE_SOFTC sc, uint32_t enable)
| 845oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable)
|
822{
823 struct mbx_set_common_iface_rx_filter *fwcmd;
824 int sz = sizeof(struct mbx_set_common_iface_rx_filter);
825 iface_rx_filter_ctx_t *req;
826 OCE_DMA_MEM sgl;
827 int rc;
828
829 /* allocate mbx payload's dma scatter/gather memory */
830 rc = oce_dma_alloc(sc, sz, &sgl, 0);
831 if (rc)
832 return rc;
833
834 fwcmd = OCE_DMAPTR(&sgl, struct mbx_set_common_iface_rx_filter);
835
836 req = &fwcmd->params.req;
837 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS |
838 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
| 846{
847 struct mbx_set_common_iface_rx_filter *fwcmd;
848 int sz = sizeof(struct mbx_set_common_iface_rx_filter);
849 iface_rx_filter_ctx_t *req;
850 OCE_DMA_MEM sgl;
851 int rc;
852
853 /* allocate mbx payload's dma scatter/gather memory */
854 rc = oce_dma_alloc(sc, sz, &sgl, 0);
855 if (rc)
856 return rc;
857
858 fwcmd = OCE_DMAPTR(&sgl, struct mbx_set_common_iface_rx_filter);
859
860 req = &fwcmd->params.req;
861 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS |
862 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
|
839 if (enable) {
840 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS |
841 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
842 }
| 863 /* Bit 0 Mac promisc, Bit 1 Vlan promisc */
864 if (enable & 0x01)
865 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS;
866
867 if (enable & 0x02)
868 req->iface_flags = MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
869
|
843 req->if_id = sc->if_id;
844
845 rc = oce_set_common_iface_rx_filter(sc, &sgl);
846 oce_dma_free(sc, &sgl);
847
848 return rc;
849}
850
851
852/**
853 * @brief Function modify and select rx filter options
854 * @param sc software handle to the device
855 * @param sgl scatter/gather request/response
856 * @returns 0 on success, error code on failure
857 */
858int
859oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl)
860{
861 struct oce_mbx mbx;
862 int mbx_sz = sizeof(struct mbx_set_common_iface_rx_filter);
863 struct mbx_set_common_iface_rx_filter *fwcmd;
864 int rc;
865
866 bzero(&mbx, sizeof(struct oce_mbx));
867 fwcmd = OCE_DMAPTR(sgl, struct mbx_set_common_iface_rx_filter);
868
869 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
870 MBX_SUBSYSTEM_COMMON,
871 OPCODE_COMMON_SET_IFACE_RX_FILTER,
872 MBX_TIMEOUT_SEC,
873 mbx_sz,
874 OCE_MBX_VER_V0);
875
876 oce_dma_sync(sgl, BUS_DMASYNC_PREWRITE);
877 mbx.u0.s.embedded = 0;
878 mbx.u0.s.sge_count = 1;
879 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(sgl->paddr);
880 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(sgl->paddr);
881 mbx.payload.u0.u1.sgl[0].length = mbx_sz;
882 mbx.payload_length = mbx_sz;
883 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
884
885 rc = oce_mbox_post(sc, &mbx, NULL);
886 if (!rc)
887 rc = fwcmd->hdr.u0.rsp.status;
888 if (rc)
| 870 req->if_id = sc->if_id;
871
872 rc = oce_set_common_iface_rx_filter(sc, &sgl);
873 oce_dma_free(sc, &sgl);
874
875 return rc;
876}
877
878
879/**
880 * @brief Function modify and select rx filter options
881 * @param sc software handle to the device
882 * @param sgl scatter/gather request/response
883 * @returns 0 on success, error code on failure
884 */
885int
886oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl)
887{
888 struct oce_mbx mbx;
889 int mbx_sz = sizeof(struct mbx_set_common_iface_rx_filter);
890 struct mbx_set_common_iface_rx_filter *fwcmd;
891 int rc;
892
893 bzero(&mbx, sizeof(struct oce_mbx));
894 fwcmd = OCE_DMAPTR(sgl, struct mbx_set_common_iface_rx_filter);
895
896 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
897 MBX_SUBSYSTEM_COMMON,
898 OPCODE_COMMON_SET_IFACE_RX_FILTER,
899 MBX_TIMEOUT_SEC,
900 mbx_sz,
901 OCE_MBX_VER_V0);
902
903 oce_dma_sync(sgl, BUS_DMASYNC_PREWRITE);
904 mbx.u0.s.embedded = 0;
905 mbx.u0.s.sge_count = 1;
906 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(sgl->paddr);
907 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(sgl->paddr);
908 mbx.payload.u0.u1.sgl[0].length = mbx_sz;
909 mbx.payload_length = mbx_sz;
910 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
911
912 rc = oce_mbox_post(sc, &mbx, NULL);
913 if (!rc)
914 rc = fwcmd->hdr.u0.rsp.status;
915 if (rc)
|
889 device_printf(sc->dev,"%s failed - cmd status: %d\n",
890 __FUNCTION__, rc);
891 return 0;
| 916 device_printf(sc->dev,
917 "%s failed - cmd status: %d addi status: %d\n",
918 __FUNCTION__, rc,
919 fwcmd->hdr.u0.rsp.additional_status);
920 return rc;
|
892}
893
894/**
895 * @brief Function to query the link status from the hardware
896 * @param sc software handle to the device
897 * @param[out] link pointer to the structure returning link attributes
898 * @returns 0 on success, EIO on failure
899 */
900int
901oce_get_link_status(POCE_SOFTC sc, struct link_status *link)
902{
903 struct oce_mbx mbx;
904 struct mbx_query_common_link_config *fwcmd;
905 int rc = 0, version;
906
907 bzero(&mbx, sizeof(struct oce_mbx));
908
909 IS_XE201(sc) ? (version = OCE_MBX_VER_V1) : (version = OCE_MBX_VER_V0);
910
911 fwcmd = (struct mbx_query_common_link_config *)&mbx.payload;
912 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
913 MBX_SUBSYSTEM_COMMON,
914 OPCODE_COMMON_QUERY_LINK_CONFIG,
915 MBX_TIMEOUT_SEC,
916 sizeof(struct mbx_query_common_link_config),
917 version);
918
919 mbx.u0.s.embedded = 1;
920 mbx.payload_length = sizeof(struct mbx_query_common_link_config);
921 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
922
923 rc = oce_mbox_post(sc, &mbx, NULL);
924
925 if (!rc)
926 rc = fwcmd->hdr.u0.rsp.status;
927 if (rc) {
| 921}
922
923/**
924 * @brief Function to query the link status from the hardware
925 * @param sc software handle to the device
926 * @param[out] link pointer to the structure returning link attributes
927 * @returns 0 on success, EIO on failure
928 */
929int
930oce_get_link_status(POCE_SOFTC sc, struct link_status *link)
931{
932 struct oce_mbx mbx;
933 struct mbx_query_common_link_config *fwcmd;
934 int rc = 0, version;
935
936 bzero(&mbx, sizeof(struct oce_mbx));
937
938 IS_XE201(sc) ? (version = OCE_MBX_VER_V1) : (version = OCE_MBX_VER_V0);
939
940 fwcmd = (struct mbx_query_common_link_config *)&mbx.payload;
941 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
942 MBX_SUBSYSTEM_COMMON,
943 OPCODE_COMMON_QUERY_LINK_CONFIG,
944 MBX_TIMEOUT_SEC,
945 sizeof(struct mbx_query_common_link_config),
946 version);
947
948 mbx.u0.s.embedded = 1;
949 mbx.payload_length = sizeof(struct mbx_query_common_link_config);
950 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
951
952 rc = oce_mbox_post(sc, &mbx, NULL);
953
954 if (!rc)
955 rc = fwcmd->hdr.u0.rsp.status;
956 if (rc) {
|
928 device_printf(sc->dev,"%s failed - cmd status: %d\n",
929 __FUNCTION__, rc);
| 957 device_printf(sc->dev,
958 "%s failed - cmd status: %d addi status: %d\n",
959 __FUNCTION__, rc,
960 fwcmd->hdr.u0.rsp.additional_status);
|
930 goto error;
931 }
932 /* interpret response */
933 bcopy(&fwcmd->params.rsp, link, sizeof(struct link_status));
| 961 goto error;
962 }
963 /* interpret response */
964 bcopy(&fwcmd->params.rsp, link, sizeof(struct link_status));
|
934 link->logical_link_status = LE_32(link->logical_link_status);
935 link->qos_link_speed = LE_16(link->qos_link_speed);
| 965 link->logical_link_status = HOST_32(link->logical_link_status);
966 link->qos_link_speed = HOST_16(link->qos_link_speed);
|
936error:
937 return rc;
938}
939
940
941
942int
943oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem)
944{
945 struct oce_mbx mbx;
946 struct mbx_get_nic_stats_v0 *fwcmd;
947 int rc = 0;
948
949 bzero(&mbx, sizeof(struct oce_mbx));
950
951 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v0);
952 bzero(fwcmd, sizeof(struct mbx_get_nic_stats_v0));
953
954 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
955 MBX_SUBSYSTEM_NIC,
956 NIC_GET_STATS,
957 MBX_TIMEOUT_SEC,
958 sizeof(struct mbx_get_nic_stats_v0),
959 OCE_MBX_VER_V0);
960
961 mbx.u0.s.embedded = 0;
962 mbx.u0.s.sge_count = 1;
963
964 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
965
966 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
967 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
968 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_nic_stats_v0);
969
970 mbx.payload_length = sizeof(struct mbx_get_nic_stats_v0);
971
972 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
973
974 rc = oce_mbox_post(sc, &mbx, NULL);
975
976 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
977
978 if (!rc)
979 rc = fwcmd->hdr.u0.rsp.status;
980 if (rc)
| 967error:
968 return rc;
969}
970
971
972
973int
974oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem)
975{
976 struct oce_mbx mbx;
977 struct mbx_get_nic_stats_v0 *fwcmd;
978 int rc = 0;
979
980 bzero(&mbx, sizeof(struct oce_mbx));
981
982 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v0);
983 bzero(fwcmd, sizeof(struct mbx_get_nic_stats_v0));
984
985 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
986 MBX_SUBSYSTEM_NIC,
987 NIC_GET_STATS,
988 MBX_TIMEOUT_SEC,
989 sizeof(struct mbx_get_nic_stats_v0),
990 OCE_MBX_VER_V0);
991
992 mbx.u0.s.embedded = 0;
993 mbx.u0.s.sge_count = 1;
994
995 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
996
997 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
998 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
999 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_nic_stats_v0);
1000
1001 mbx.payload_length = sizeof(struct mbx_get_nic_stats_v0);
1002
1003 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1004
1005 rc = oce_mbox_post(sc, &mbx, NULL);
1006
1007 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1008
1009 if (!rc)
1010 rc = fwcmd->hdr.u0.rsp.status;
1011 if (rc)
|
981 device_printf(sc->dev,"%s failed - cmd status: %d\n",
982 __FUNCTION__, rc);
| 1012 device_printf(sc->dev,
1013 "%s failed - cmd status: %d addi status: %d\n",
1014 __FUNCTION__, rc,
1015 fwcmd->hdr.u0.rsp.additional_status);
|
983 return rc;
984}
985
986
987
988/**
989 * @brief Function to get NIC statistics
990 * @param sc software handle to the device
991 * @param *stats pointer to where to store statistics
992 * @param reset_stats resets statistics of set
993 * @returns 0 on success, EIO on failure
994 * @note command depricated in Lancer
995 */
996int
997oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem)
998{
999 struct oce_mbx mbx;
1000 struct mbx_get_nic_stats *fwcmd;
1001 int rc = 0;
1002
1003 bzero(&mbx, sizeof(struct oce_mbx));
1004 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats);
1005 bzero(fwcmd, sizeof(struct mbx_get_nic_stats));
1006
1007 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1008 MBX_SUBSYSTEM_NIC,
1009 NIC_GET_STATS,
1010 MBX_TIMEOUT_SEC,
1011 sizeof(struct mbx_get_nic_stats),
1012 OCE_MBX_VER_V1);
1013
1014
1015 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1016 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1017
1018 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1019 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1020 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1021 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_nic_stats);
1022
1023 mbx.payload_length = sizeof(struct mbx_get_nic_stats);
1024 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1025
1026 rc = oce_mbox_post(sc, &mbx, NULL);
1027 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1028 if (!rc)
1029 rc = fwcmd->hdr.u0.rsp.status;
1030 if (rc)
| 1016 return rc;
1017}
1018
1019
1020
1021/**
1022 * @brief Function to get NIC statistics
1023 * @param sc software handle to the device
1024 * @param *stats pointer to where to store statistics
1025 * @param reset_stats resets statistics of set
1026 * @returns 0 on success, EIO on failure
1027 * @note command depricated in Lancer
1028 */
1029int
1030oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem)
1031{
1032 struct oce_mbx mbx;
1033 struct mbx_get_nic_stats *fwcmd;
1034 int rc = 0;
1035
1036 bzero(&mbx, sizeof(struct oce_mbx));
1037 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats);
1038 bzero(fwcmd, sizeof(struct mbx_get_nic_stats));
1039
1040 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1041 MBX_SUBSYSTEM_NIC,
1042 NIC_GET_STATS,
1043 MBX_TIMEOUT_SEC,
1044 sizeof(struct mbx_get_nic_stats),
1045 OCE_MBX_VER_V1);
1046
1047
1048 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1049 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1050
1051 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1052 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1053 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1054 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_nic_stats);
1055
1056 mbx.payload_length = sizeof(struct mbx_get_nic_stats);
1057 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1058
1059 rc = oce_mbox_post(sc, &mbx, NULL);
1060 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1061 if (!rc)
1062 rc = fwcmd->hdr.u0.rsp.status;
1063 if (rc)
|
1031 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1032 __FUNCTION__, rc);
| 1064 device_printf(sc->dev,
1065 "%s failed - cmd status: %d addi status: %d\n",
1066 __FUNCTION__, rc,
1067 fwcmd->hdr.u0.rsp.additional_status);
|
1033 return rc;
1034}
1035
1036
1037/**
1038 * @brief Function to get pport (physical port) statistics
1039 * @param sc software handle to the device
1040 * @param *stats pointer to where to store statistics
1041 * @param reset_stats resets statistics of set
1042 * @returns 0 on success, EIO on failure
1043 */
1044int
1045oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1046 uint32_t reset_stats)
1047{
1048 struct oce_mbx mbx;
1049 struct mbx_get_pport_stats *fwcmd;
1050 int rc = 0;
1051
1052 bzero(&mbx, sizeof(struct oce_mbx));
1053 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_pport_stats);
1054 bzero(fwcmd, sizeof(struct mbx_get_pport_stats));
1055
1056 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1057 MBX_SUBSYSTEM_NIC,
1058 NIC_GET_PPORT_STATS,
1059 MBX_TIMEOUT_SEC,
1060 sizeof(struct mbx_get_pport_stats),
1061 OCE_MBX_VER_V0);
1062
1063 fwcmd->params.req.reset_stats = reset_stats;
1064 fwcmd->params.req.port_number = sc->port_id;
1065
1066 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1067 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1068
1069 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1070 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1071 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1072 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_pport_stats);
1073
1074 mbx.payload_length = sizeof(struct mbx_get_pport_stats);
1075 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1076
1077 rc = oce_mbox_post(sc, &mbx, NULL);
1078 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1079
1080 if (!rc)
1081 rc = fwcmd->hdr.u0.rsp.status;
1082 if (rc)
| 1068 return rc;
1069}
1070
1071
1072/**
1073 * @brief Function to get pport (physical port) statistics
1074 * @param sc software handle to the device
1075 * @param *stats pointer to where to store statistics
1076 * @param reset_stats resets statistics of set
1077 * @returns 0 on success, EIO on failure
1078 */
1079int
1080oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1081 uint32_t reset_stats)
1082{
1083 struct oce_mbx mbx;
1084 struct mbx_get_pport_stats *fwcmd;
1085 int rc = 0;
1086
1087 bzero(&mbx, sizeof(struct oce_mbx));
1088 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_pport_stats);
1089 bzero(fwcmd, sizeof(struct mbx_get_pport_stats));
1090
1091 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1092 MBX_SUBSYSTEM_NIC,
1093 NIC_GET_PPORT_STATS,
1094 MBX_TIMEOUT_SEC,
1095 sizeof(struct mbx_get_pport_stats),
1096 OCE_MBX_VER_V0);
1097
1098 fwcmd->params.req.reset_stats = reset_stats;
1099 fwcmd->params.req.port_number = sc->port_id;
1100
1101 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1102 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1103
1104 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1105 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1106 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1107 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_pport_stats);
1108
1109 mbx.payload_length = sizeof(struct mbx_get_pport_stats);
1110 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1111
1112 rc = oce_mbox_post(sc, &mbx, NULL);
1113 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1114
1115 if (!rc)
1116 rc = fwcmd->hdr.u0.rsp.status;
1117 if (rc)
|
1083 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1084 __FUNCTION__, rc);
| 1118 device_printf(sc->dev,
1119 "%s failed - cmd status: %d addi status: %d\n",
1120 __FUNCTION__, rc,
1121 fwcmd->hdr.u0.rsp.additional_status);
|
1085 return rc;
1086}
1087
1088
1089/**
1090 * @brief Function to get vport (virtual port) statistics
1091 * @param sc software handle to the device
1092 * @param *stats pointer to where to store statistics
1093 * @param reset_stats resets statistics of set
1094 * @returns 0 on success, EIO on failure
1095 */
1096int
1097oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1098 uint32_t req_size, uint32_t reset_stats)
1099{
1100 struct oce_mbx mbx;
1101 struct mbx_get_vport_stats *fwcmd;
1102 int rc = 0;
1103
1104 bzero(&mbx, sizeof(struct oce_mbx));
1105
1106 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_vport_stats);
1107 bzero(fwcmd, sizeof(struct mbx_get_vport_stats));
1108
1109 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1110 MBX_SUBSYSTEM_NIC,
1111 NIC_GET_VPORT_STATS,
1112 MBX_TIMEOUT_SEC,
1113 sizeof(struct mbx_get_vport_stats),
1114 OCE_MBX_VER_V0);
1115
1116 fwcmd->params.req.reset_stats = reset_stats;
1117 fwcmd->params.req.vport_number = sc->if_id;
1118
1119 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1120 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1121
1122 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1123 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1124 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1125 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_vport_stats);
1126
1127 mbx.payload_length = sizeof(struct mbx_get_vport_stats);
1128 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1129
1130 rc = oce_mbox_post(sc, &mbx, NULL);
1131 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1132
1133 if (!rc)
1134 rc = fwcmd->hdr.u0.rsp.status;
1135 if (rc)
| 1122 return rc;
1123}
1124
1125
1126/**
1127 * @brief Function to get vport (virtual port) statistics
1128 * @param sc software handle to the device
1129 * @param *stats pointer to where to store statistics
1130 * @param reset_stats resets statistics of set
1131 * @returns 0 on success, EIO on failure
1132 */
1133int
1134oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1135 uint32_t req_size, uint32_t reset_stats)
1136{
1137 struct oce_mbx mbx;
1138 struct mbx_get_vport_stats *fwcmd;
1139 int rc = 0;
1140
1141 bzero(&mbx, sizeof(struct oce_mbx));
1142
1143 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_vport_stats);
1144 bzero(fwcmd, sizeof(struct mbx_get_vport_stats));
1145
1146 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1147 MBX_SUBSYSTEM_NIC,
1148 NIC_GET_VPORT_STATS,
1149 MBX_TIMEOUT_SEC,
1150 sizeof(struct mbx_get_vport_stats),
1151 OCE_MBX_VER_V0);
1152
1153 fwcmd->params.req.reset_stats = reset_stats;
1154 fwcmd->params.req.vport_number = sc->if_id;
1155
1156 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1157 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1158
1159 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1160 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1161 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1162 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_vport_stats);
1163
1164 mbx.payload_length = sizeof(struct mbx_get_vport_stats);
1165 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1166
1167 rc = oce_mbox_post(sc, &mbx, NULL);
1168 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1169
1170 if (!rc)
1171 rc = fwcmd->hdr.u0.rsp.status;
1172 if (rc)
|
1136 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1137 __FUNCTION__, rc);
| 1173 device_printf(sc->dev,
1174 "%s failed - cmd status: %d addi status: %d\n",
1175 __FUNCTION__, rc,
1176 fwcmd->hdr.u0.rsp.additional_status);
|
1138 return rc;
1139}
1140
1141
1142/**
1143 * @brief Function to update the muticast filter with
1144 * values in dma_mem
1145 * @param sc software handle to the device
1146 * @param dma_mem pointer to dma memory region
1147 * @returns 0 on success, EIO on failure
1148 */
1149int
1150oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem)
1151{
1152 struct oce_mbx mbx;
1153 struct oce_mq_sge *sgl;
1154 struct mbx_set_common_iface_multicast *req = NULL;
1155 int rc = 0;
1156
1157 req = OCE_DMAPTR(pdma_mem, struct mbx_set_common_iface_multicast);
1158 mbx_common_req_hdr_init(&req->hdr, 0, 0,
1159 MBX_SUBSYSTEM_COMMON,
1160 OPCODE_COMMON_SET_IFACE_MULTICAST,
1161 MBX_TIMEOUT_SEC,
1162 sizeof(struct mbx_set_common_iface_multicast),
1163 OCE_MBX_VER_V0);
1164
1165 bzero(&mbx, sizeof(struct oce_mbx));
1166
1167 mbx.u0.s.embedded = 0; /*Non embeded*/
1168 mbx.payload_length = sizeof(struct mbx_set_common_iface_multicast);
1169 mbx.u0.s.sge_count = 1;
1170 sgl = &mbx.payload.u0.u1.sgl[0];
1171 sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr));
1172 sgl->pa_lo = htole32((pdma_mem->paddr) & 0xFFFFFFFF);
1173 sgl->length = htole32(mbx.payload_length);
1174
1175 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1176
1177 rc = oce_mbox_post(sc, &mbx, NULL);
1178 if (!rc)
1179 rc = req->hdr.u0.rsp.status;
1180 if (rc)
| 1177 return rc;
1178}
1179
1180
1181/**
1182 * @brief Function to update the muticast filter with
1183 * values in dma_mem
1184 * @param sc software handle to the device
1185 * @param dma_mem pointer to dma memory region
1186 * @returns 0 on success, EIO on failure
1187 */
1188int
1189oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem)
1190{
1191 struct oce_mbx mbx;
1192 struct oce_mq_sge *sgl;
1193 struct mbx_set_common_iface_multicast *req = NULL;
1194 int rc = 0;
1195
1196 req = OCE_DMAPTR(pdma_mem, struct mbx_set_common_iface_multicast);
1197 mbx_common_req_hdr_init(&req->hdr, 0, 0,
1198 MBX_SUBSYSTEM_COMMON,
1199 OPCODE_COMMON_SET_IFACE_MULTICAST,
1200 MBX_TIMEOUT_SEC,
1201 sizeof(struct mbx_set_common_iface_multicast),
1202 OCE_MBX_VER_V0);
1203
1204 bzero(&mbx, sizeof(struct oce_mbx));
1205
1206 mbx.u0.s.embedded = 0; /*Non embeded*/
1207 mbx.payload_length = sizeof(struct mbx_set_common_iface_multicast);
1208 mbx.u0.s.sge_count = 1;
1209 sgl = &mbx.payload.u0.u1.sgl[0];
1210 sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr));
1211 sgl->pa_lo = htole32((pdma_mem->paddr) & 0xFFFFFFFF);
1212 sgl->length = htole32(mbx.payload_length);
1213
1214 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1215
1216 rc = oce_mbox_post(sc, &mbx, NULL);
1217 if (!rc)
1218 rc = req->hdr.u0.rsp.status;
1219 if (rc)
|
1181 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1182 __FUNCTION__, rc);
| 1220 device_printf(sc->dev,
1221 "%s failed - cmd status: %d addi status: %d\n",
1222 __FUNCTION__, rc,
1223 req->hdr.u0.rsp.additional_status);
|
1183 return rc;
1184}
1185
1186
1187/**
1188 * @brief Function to send passthrough Ioctls
1189 * @param sc software handle to the device
1190 * @param dma_mem pointer to dma memory region
1191 * @param req_size size of dma_mem
1192 * @returns 0 on success, EIO on failure
1193 */
1194int
1195oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size)
1196{
1197 struct oce_mbx mbx;
1198 struct oce_mq_sge *sgl;
1199 int rc = 0;
1200
1201 bzero(&mbx, sizeof(struct oce_mbx));
1202
1203 mbx.u0.s.embedded = 0; /*Non embeded*/
1204 mbx.payload_length = req_size;
1205 mbx.u0.s.sge_count = 1;
1206 sgl = &mbx.payload.u0.u1.sgl[0];
1207 sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr));
1208 sgl->pa_lo = htole32((dma_mem->paddr) & 0xFFFFFFFF);
1209 sgl->length = htole32(req_size);
1210
1211 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1212
1213 rc = oce_mbox_post(sc, &mbx, NULL);
1214 return rc;
1215}
1216
1217
1218int
1219oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1220 uint32_t if_id, uint32_t *pmac_id)
1221{
1222 struct oce_mbx mbx;
1223 struct mbx_add_common_iface_mac *fwcmd;
1224 int rc = 0;
1225
1226 bzero(&mbx, sizeof(struct oce_mbx));
1227
1228 fwcmd = (struct mbx_add_common_iface_mac *)&mbx.payload;
1229 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1230 MBX_SUBSYSTEM_COMMON,
1231 OPCODE_COMMON_ADD_IFACE_MAC,
1232 MBX_TIMEOUT_SEC,
1233 sizeof(struct mbx_add_common_iface_mac),
1234 OCE_MBX_VER_V0);
1235
1236 fwcmd->params.req.if_id = (uint16_t) if_id;
1237 bcopy(mac_addr, fwcmd->params.req.mac_address, 6);
1238
1239 mbx.u0.s.embedded = 1;
1240 mbx.payload_length = sizeof(struct mbx_add_common_iface_mac);
1241 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1242 rc = oce_mbox_post(sc, &mbx, NULL);
1243 if (!rc)
1244 rc = fwcmd->hdr.u0.rsp.status;
1245 if (rc) {
| 1224 return rc;
1225}
1226
1227
1228/**
1229 * @brief Function to send passthrough Ioctls
1230 * @param sc software handle to the device
1231 * @param dma_mem pointer to dma memory region
1232 * @param req_size size of dma_mem
1233 * @returns 0 on success, EIO on failure
1234 */
1235int
1236oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size)
1237{
1238 struct oce_mbx mbx;
1239 struct oce_mq_sge *sgl;
1240 int rc = 0;
1241
1242 bzero(&mbx, sizeof(struct oce_mbx));
1243
1244 mbx.u0.s.embedded = 0; /*Non embeded*/
1245 mbx.payload_length = req_size;
1246 mbx.u0.s.sge_count = 1;
1247 sgl = &mbx.payload.u0.u1.sgl[0];
1248 sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr));
1249 sgl->pa_lo = htole32((dma_mem->paddr) & 0xFFFFFFFF);
1250 sgl->length = htole32(req_size);
1251
1252 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1253
1254 rc = oce_mbox_post(sc, &mbx, NULL);
1255 return rc;
1256}
1257
1258
1259int
1260oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1261 uint32_t if_id, uint32_t *pmac_id)
1262{
1263 struct oce_mbx mbx;
1264 struct mbx_add_common_iface_mac *fwcmd;
1265 int rc = 0;
1266
1267 bzero(&mbx, sizeof(struct oce_mbx));
1268
1269 fwcmd = (struct mbx_add_common_iface_mac *)&mbx.payload;
1270 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1271 MBX_SUBSYSTEM_COMMON,
1272 OPCODE_COMMON_ADD_IFACE_MAC,
1273 MBX_TIMEOUT_SEC,
1274 sizeof(struct mbx_add_common_iface_mac),
1275 OCE_MBX_VER_V0);
1276
1277 fwcmd->params.req.if_id = (uint16_t) if_id;
1278 bcopy(mac_addr, fwcmd->params.req.mac_address, 6);
1279
1280 mbx.u0.s.embedded = 1;
1281 mbx.payload_length = sizeof(struct mbx_add_common_iface_mac);
1282 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1283 rc = oce_mbox_post(sc, &mbx, NULL);
1284 if (!rc)
1285 rc = fwcmd->hdr.u0.rsp.status;
1286 if (rc) {
|
1246 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1247 __FUNCTION__, rc);
| 1287 device_printf(sc->dev,
1288 "%s failed - cmd status: %d addi status: %d\n",
1289 __FUNCTION__, rc,
1290 fwcmd->hdr.u0.rsp.additional_status);
|
1248 goto error;
1249 }
1250 *pmac_id = fwcmd->params.rsp.pmac_id;
1251error:
1252 return rc;
1253}
1254
1255
1256int
1257oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id)
1258{
1259 struct oce_mbx mbx;
1260 struct mbx_del_common_iface_mac *fwcmd;
1261 int rc = 0;
1262
1263 bzero(&mbx, sizeof(struct oce_mbx));
1264
1265 fwcmd = (struct mbx_del_common_iface_mac *)&mbx.payload;
1266 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1267 MBX_SUBSYSTEM_COMMON,
1268 OPCODE_COMMON_DEL_IFACE_MAC,
1269 MBX_TIMEOUT_SEC,
1270 sizeof(struct mbx_del_common_iface_mac),
1271 OCE_MBX_VER_V0);
1272
1273 fwcmd->params.req.if_id = (uint16_t)if_id;
1274 fwcmd->params.req.pmac_id = pmac_id;
1275
1276 mbx.u0.s.embedded = 1;
1277 mbx.payload_length = sizeof(struct mbx_del_common_iface_mac);
1278 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1279
1280 rc = oce_mbox_post(sc, &mbx, NULL);
1281 if (!rc)
1282 rc = fwcmd->hdr.u0.rsp.status;
1283 if (rc)
| 1291 goto error;
1292 }
1293 *pmac_id = fwcmd->params.rsp.pmac_id;
1294error:
1295 return rc;
1296}
1297
1298
1299int
1300oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id)
1301{
1302 struct oce_mbx mbx;
1303 struct mbx_del_common_iface_mac *fwcmd;
1304 int rc = 0;
1305
1306 bzero(&mbx, sizeof(struct oce_mbx));
1307
1308 fwcmd = (struct mbx_del_common_iface_mac *)&mbx.payload;
1309 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1310 MBX_SUBSYSTEM_COMMON,
1311 OPCODE_COMMON_DEL_IFACE_MAC,
1312 MBX_TIMEOUT_SEC,
1313 sizeof(struct mbx_del_common_iface_mac),
1314 OCE_MBX_VER_V0);
1315
1316 fwcmd->params.req.if_id = (uint16_t)if_id;
1317 fwcmd->params.req.pmac_id = pmac_id;
1318
1319 mbx.u0.s.embedded = 1;
1320 mbx.payload_length = sizeof(struct mbx_del_common_iface_mac);
1321 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1322
1323 rc = oce_mbox_post(sc, &mbx, NULL);
1324 if (!rc)
1325 rc = fwcmd->hdr.u0.rsp.status;
1326 if (rc)
|
1284 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1285 __FUNCTION__, rc);
| 1327 device_printf(sc->dev,
1328 "%s failed - cmd status: %d addi status: %d\n",
1329 __FUNCTION__, rc,
1330 fwcmd->hdr.u0.rsp.additional_status);
|
1286 return rc;
1287}
1288
1289
1290
1291int
1292oce_mbox_check_native_mode(POCE_SOFTC sc)
1293{
1294 struct oce_mbx mbx;
1295 struct mbx_common_set_function_cap *fwcmd;
1296 int rc = 0;
1297
1298 bzero(&mbx, sizeof(struct oce_mbx));
1299
1300 fwcmd = (struct mbx_common_set_function_cap *)&mbx.payload;
1301 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1302 MBX_SUBSYSTEM_COMMON,
1303 OPCODE_COMMON_SET_FUNCTIONAL_CAPS,
1304 MBX_TIMEOUT_SEC,
1305 sizeof(struct mbx_common_set_function_cap),
1306 OCE_MBX_VER_V0);
1307
1308 fwcmd->params.req.valid_capability_flags = CAP_SW_TIMESTAMPS |
1309 CAP_BE3_NATIVE_ERX_API;
1310
1311 fwcmd->params.req.capability_flags = CAP_BE3_NATIVE_ERX_API;
1312
1313 mbx.u0.s.embedded = 1;
1314 mbx.payload_length = sizeof(struct mbx_common_set_function_cap);
1315 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1316
1317 rc = oce_mbox_post(sc, &mbx, NULL);
1318 if (!rc)
1319 rc = fwcmd->hdr.u0.rsp.status;
1320 if (rc) {
| 1331 return rc;
1332}
1333
1334
1335
1336int
1337oce_mbox_check_native_mode(POCE_SOFTC sc)
1338{
1339 struct oce_mbx mbx;
1340 struct mbx_common_set_function_cap *fwcmd;
1341 int rc = 0;
1342
1343 bzero(&mbx, sizeof(struct oce_mbx));
1344
1345 fwcmd = (struct mbx_common_set_function_cap *)&mbx.payload;
1346 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1347 MBX_SUBSYSTEM_COMMON,
1348 OPCODE_COMMON_SET_FUNCTIONAL_CAPS,
1349 MBX_TIMEOUT_SEC,
1350 sizeof(struct mbx_common_set_function_cap),
1351 OCE_MBX_VER_V0);
1352
1353 fwcmd->params.req.valid_capability_flags = CAP_SW_TIMESTAMPS |
1354 CAP_BE3_NATIVE_ERX_API;
1355
1356 fwcmd->params.req.capability_flags = CAP_BE3_NATIVE_ERX_API;
1357
1358 mbx.u0.s.embedded = 1;
1359 mbx.payload_length = sizeof(struct mbx_common_set_function_cap);
1360 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1361
1362 rc = oce_mbox_post(sc, &mbx, NULL);
1363 if (!rc)
1364 rc = fwcmd->hdr.u0.rsp.status;
1365 if (rc) {
|
1321 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1322 __FUNCTION__, rc);
| 1366 device_printf(sc->dev,
1367 "%s failed - cmd status: %d addi status: %d\n",
1368 __FUNCTION__, rc,
1369 fwcmd->hdr.u0.rsp.additional_status);
|
1323 goto error;
1324 }
| 1370 goto error;
1371 }
|
1325 sc->be3_native = fwcmd->params.rsp.capability_flags
| 1372 sc->be3_native = HOST_32(fwcmd->params.rsp.capability_flags)
|
1326 & CAP_BE3_NATIVE_ERX_API;
1327
1328error:
1329 return 0;
1330}
1331
1332
1333
1334int
1335oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1336 uint8_t loopback_type, uint8_t enable)
1337{
1338 struct oce_mbx mbx;
1339 struct mbx_lowlevel_set_loopback_mode *fwcmd;
1340 int rc = 0;
1341
1342
1343 bzero(&mbx, sizeof(struct oce_mbx));
1344
1345 fwcmd = (struct mbx_lowlevel_set_loopback_mode *)&mbx.payload;
1346 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1347 MBX_SUBSYSTEM_LOWLEVEL,
1348 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1349 MBX_TIMEOUT_SEC,
1350 sizeof(struct mbx_lowlevel_set_loopback_mode),
1351 OCE_MBX_VER_V0);
1352
1353 fwcmd->params.req.src_port = port_num;
1354 fwcmd->params.req.dest_port = port_num;
1355 fwcmd->params.req.loopback_type = loopback_type;
1356 fwcmd->params.req.loopback_state = enable;
1357
1358 mbx.u0.s.embedded = 1;
1359 mbx.payload_length = sizeof(struct mbx_lowlevel_set_loopback_mode);
1360 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1361
1362 rc = oce_mbox_post(sc, &mbx, NULL);
1363 if (!rc)
1364 rc = fwcmd->hdr.u0.rsp.status;
1365 if (rc)
| 1373 & CAP_BE3_NATIVE_ERX_API;
1374
1375error:
1376 return 0;
1377}
1378
1379
1380
1381int
1382oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1383 uint8_t loopback_type, uint8_t enable)
1384{
1385 struct oce_mbx mbx;
1386 struct mbx_lowlevel_set_loopback_mode *fwcmd;
1387 int rc = 0;
1388
1389
1390 bzero(&mbx, sizeof(struct oce_mbx));
1391
1392 fwcmd = (struct mbx_lowlevel_set_loopback_mode *)&mbx.payload;
1393 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1394 MBX_SUBSYSTEM_LOWLEVEL,
1395 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1396 MBX_TIMEOUT_SEC,
1397 sizeof(struct mbx_lowlevel_set_loopback_mode),
1398 OCE_MBX_VER_V0);
1399
1400 fwcmd->params.req.src_port = port_num;
1401 fwcmd->params.req.dest_port = port_num;
1402 fwcmd->params.req.loopback_type = loopback_type;
1403 fwcmd->params.req.loopback_state = enable;
1404
1405 mbx.u0.s.embedded = 1;
1406 mbx.payload_length = sizeof(struct mbx_lowlevel_set_loopback_mode);
1407 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1408
1409 rc = oce_mbox_post(sc, &mbx, NULL);
1410 if (!rc)
1411 rc = fwcmd->hdr.u0.rsp.status;
1412 if (rc)
|
1366 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1367 __FUNCTION__, rc);
| 1413 device_printf(sc->dev,
1414 "%s failed - cmd status: %d addi status: %d\n",
1415 __FUNCTION__, rc,
1416 fwcmd->hdr.u0.rsp.additional_status);
|
1368
1369 return rc;
1370
1371}
1372
1373int
1374oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1375 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1376 uint64_t pattern)
1377{
1378
1379 struct oce_mbx mbx;
1380 struct mbx_lowlevel_test_loopback_mode *fwcmd;
1381 int rc = 0;
1382
1383
1384 bzero(&mbx, sizeof(struct oce_mbx));
1385
1386 fwcmd = (struct mbx_lowlevel_test_loopback_mode *)&mbx.payload;
1387 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1388 MBX_SUBSYSTEM_LOWLEVEL,
1389 OPCODE_LOWLEVEL_TEST_LOOPBACK,
1390 MBX_TIMEOUT_SEC,
1391 sizeof(struct mbx_lowlevel_test_loopback_mode),
1392 OCE_MBX_VER_V0);
1393
1394 fwcmd->params.req.pattern = pattern;
1395 fwcmd->params.req.src_port = port_num;
1396 fwcmd->params.req.dest_port = port_num;
1397 fwcmd->params.req.pkt_size = pkt_size;
1398 fwcmd->params.req.num_pkts = num_pkts;
1399 fwcmd->params.req.loopback_type = loopback_type;
1400
1401 mbx.u0.s.embedded = 1;
1402 mbx.payload_length = sizeof(struct mbx_lowlevel_test_loopback_mode);
1403 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1404
1405 rc = oce_mbox_post(sc, &mbx, NULL);
1406 if (!rc)
1407 rc = fwcmd->hdr.u0.rsp.status;
1408 if (rc)
| 1417
1418 return rc;
1419
1420}
1421
1422int
1423oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1424 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1425 uint64_t pattern)
1426{
1427
1428 struct oce_mbx mbx;
1429 struct mbx_lowlevel_test_loopback_mode *fwcmd;
1430 int rc = 0;
1431
1432
1433 bzero(&mbx, sizeof(struct oce_mbx));
1434
1435 fwcmd = (struct mbx_lowlevel_test_loopback_mode *)&mbx.payload;
1436 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1437 MBX_SUBSYSTEM_LOWLEVEL,
1438 OPCODE_LOWLEVEL_TEST_LOOPBACK,
1439 MBX_TIMEOUT_SEC,
1440 sizeof(struct mbx_lowlevel_test_loopback_mode),
1441 OCE_MBX_VER_V0);
1442
1443 fwcmd->params.req.pattern = pattern;
1444 fwcmd->params.req.src_port = port_num;
1445 fwcmd->params.req.dest_port = port_num;
1446 fwcmd->params.req.pkt_size = pkt_size;
1447 fwcmd->params.req.num_pkts = num_pkts;
1448 fwcmd->params.req.loopback_type = loopback_type;
1449
1450 mbx.u0.s.embedded = 1;
1451 mbx.payload_length = sizeof(struct mbx_lowlevel_test_loopback_mode);
1452 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1453
1454 rc = oce_mbox_post(sc, &mbx, NULL);
1455 if (!rc)
1456 rc = fwcmd->hdr.u0.rsp.status;
1457 if (rc)
|
1409 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1410 __FUNCTION__, rc);
| 1458 device_printf(sc->dev,
1459 "%s failed - cmd status: %d addi status: %d\n",
1460 __FUNCTION__, rc,
1461 fwcmd->hdr.u0.rsp.additional_status);
|
1411
1412 return rc;
1413}
1414
1415int
1416oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1417 POCE_DMA_MEM pdma_mem, uint32_t num_bytes)
1418{
1419
1420 struct oce_mbx mbx;
1421 struct oce_mq_sge *sgl = NULL;
1422 struct mbx_common_read_write_flashrom *fwcmd = NULL;
1423 int rc = 0, payload_len = 0;
1424
1425 bzero(&mbx, sizeof(struct oce_mbx));
1426 fwcmd = OCE_DMAPTR(pdma_mem, struct mbx_common_read_write_flashrom);
1427 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 32*1024;
1428
1429 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1430 MBX_SUBSYSTEM_COMMON,
1431 OPCODE_COMMON_WRITE_FLASHROM,
1432 LONG_TIMEOUT,
1433 payload_len,
1434 OCE_MBX_VER_V0);
1435
| 1462
1463 return rc;
1464}
1465
1466int
1467oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1468 POCE_DMA_MEM pdma_mem, uint32_t num_bytes)
1469{
1470
1471 struct oce_mbx mbx;
1472 struct oce_mq_sge *sgl = NULL;
1473 struct mbx_common_read_write_flashrom *fwcmd = NULL;
1474 int rc = 0, payload_len = 0;
1475
1476 bzero(&mbx, sizeof(struct oce_mbx));
1477 fwcmd = OCE_DMAPTR(pdma_mem, struct mbx_common_read_write_flashrom);
1478 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 32*1024;
1479
1480 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1481 MBX_SUBSYSTEM_COMMON,
1482 OPCODE_COMMON_WRITE_FLASHROM,
1483 LONG_TIMEOUT,
1484 payload_len,
1485 OCE_MBX_VER_V0);
1486
|
1436 fwcmd->flash_op_type = optype;
1437 fwcmd->flash_op_code = opcode;
1438 fwcmd->data_buffer_size = num_bytes;
| 1487 fwcmd->flash_op_type = LE_32(optype);
1488 fwcmd->flash_op_code = LE_32(opcode);
1489 fwcmd->data_buffer_size = LE_32(num_bytes);
|
1439
1440 mbx.u0.s.embedded = 0; /*Non embeded*/
1441 mbx.payload_length = payload_len;
1442 mbx.u0.s.sge_count = 1;
1443
1444 sgl = &mbx.payload.u0.u1.sgl[0];
1445 sgl->pa_hi = upper_32_bits(pdma_mem->paddr);
1446 sgl->pa_lo = pdma_mem->paddr & 0xFFFFFFFF;
1447 sgl->length = payload_len;
1448
1449 /* post the command */
1450 rc = oce_mbox_post(sc, &mbx, NULL);
1451 if (!rc)
1452 rc = fwcmd->hdr.u0.rsp.status;
1453 if (rc)
| 1490
1491 mbx.u0.s.embedded = 0; /*Non embeded*/
1492 mbx.payload_length = payload_len;
1493 mbx.u0.s.sge_count = 1;
1494
1495 sgl = &mbx.payload.u0.u1.sgl[0];
1496 sgl->pa_hi = upper_32_bits(pdma_mem->paddr);
1497 sgl->pa_lo = pdma_mem->paddr & 0xFFFFFFFF;
1498 sgl->length = payload_len;
1499
1500 /* post the command */
1501 rc = oce_mbox_post(sc, &mbx, NULL);
1502 if (!rc)
1503 rc = fwcmd->hdr.u0.rsp.status;
1504 if (rc)
|
1454 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1455 __FUNCTION__, rc);
| 1505 device_printf(sc->dev,
1506 "%s failed - cmd status: %d addi status: %d\n",
1507 __FUNCTION__, rc,
1508 fwcmd->hdr.u0.rsp.additional_status);
|
1456
1457 return rc;
1458
1459}
1460
1461int
1462oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1463 uint32_t offset, uint32_t optype)
1464{
1465
1466 int rc = 0, payload_len = 0;
1467 struct oce_mbx mbx;
1468 struct mbx_common_read_write_flashrom *fwcmd;
1469
1470 bzero(&mbx, sizeof(struct oce_mbx));
1471
1472 fwcmd = (struct mbx_common_read_write_flashrom *)&mbx.payload;
1473
1474 /* Firmware requires extra 4 bytes with this ioctl. Since there
1475 is enough room in the mbx payload it should be good enough
1476 Reference: Bug 14853
1477 */
1478 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 4;
1479
1480 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1481 MBX_SUBSYSTEM_COMMON,
1482 OPCODE_COMMON_READ_FLASHROM,
1483 MBX_TIMEOUT_SEC,
1484 payload_len,
1485 OCE_MBX_VER_V0);
1486
1487 fwcmd->flash_op_type = optype;
1488 fwcmd->flash_op_code = FLASHROM_OPER_REPORT;
1489 fwcmd->data_offset = offset;
1490 fwcmd->data_buffer_size = 0x4;
1491
1492 mbx.u0.s.embedded = 1;
1493 mbx.payload_length = payload_len;
1494
1495 /* post the command */
1496 rc = oce_mbox_post(sc, &mbx, NULL);
1497 if (!rc)
1498 rc = fwcmd->hdr.u0.rsp.status;
1499 if (rc) {
| 1509
1510 return rc;
1511
1512}
1513
1514int
1515oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1516 uint32_t offset, uint32_t optype)
1517{
1518
1519 int rc = 0, payload_len = 0;
1520 struct oce_mbx mbx;
1521 struct mbx_common_read_write_flashrom *fwcmd;
1522
1523 bzero(&mbx, sizeof(struct oce_mbx));
1524
1525 fwcmd = (struct mbx_common_read_write_flashrom *)&mbx.payload;
1526
1527 /* Firmware requires extra 4 bytes with this ioctl. Since there
1528 is enough room in the mbx payload it should be good enough
1529 Reference: Bug 14853
1530 */
1531 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 4;
1532
1533 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1534 MBX_SUBSYSTEM_COMMON,
1535 OPCODE_COMMON_READ_FLASHROM,
1536 MBX_TIMEOUT_SEC,
1537 payload_len,
1538 OCE_MBX_VER_V0);
1539
1540 fwcmd->flash_op_type = optype;
1541 fwcmd->flash_op_code = FLASHROM_OPER_REPORT;
1542 fwcmd->data_offset = offset;
1543 fwcmd->data_buffer_size = 0x4;
1544
1545 mbx.u0.s.embedded = 1;
1546 mbx.payload_length = payload_len;
1547
1548 /* post the command */
1549 rc = oce_mbox_post(sc, &mbx, NULL);
1550 if (!rc)
1551 rc = fwcmd->hdr.u0.rsp.status;
1552 if (rc) {
|
1500 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1501 __FUNCTION__, rc);
| 1553 device_printf(sc->dev,
1554 "%s failed - cmd status: %d addi status: %d\n",
1555 __FUNCTION__, rc,
1556 fwcmd->hdr.u0.rsp.additional_status);
|
1502 goto error;
1503 }
1504 bcopy(fwcmd->data_buffer, flash_crc, 4);
1505error:
1506 return rc;
1507}
1508
1509int
1510oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info)
1511{
1512
1513 struct oce_mbx mbx;
1514 struct mbx_common_phy_info *fwcmd;
1515 int rc = 0;
1516
1517 bzero(&mbx, sizeof(struct oce_mbx));
1518
1519 fwcmd = (struct mbx_common_phy_info *)&mbx.payload;
1520 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1521 MBX_SUBSYSTEM_COMMON,
1522 OPCODE_COMMON_GET_PHY_CONFIG,
1523 MBX_TIMEOUT_SEC,
1524 sizeof(struct mbx_common_phy_info),
1525 OCE_MBX_VER_V0);
1526
1527 mbx.u0.s.embedded = 1;
1528 mbx.payload_length = sizeof(struct mbx_common_phy_info);
1529
1530 /* now post the command */
1531 rc = oce_mbox_post(sc, &mbx, NULL);
1532 if (!rc)
1533 rc = fwcmd->hdr.u0.rsp.status;
1534 if (rc) {
| 1557 goto error;
1558 }
1559 bcopy(fwcmd->data_buffer, flash_crc, 4);
1560error:
1561 return rc;
1562}
1563
1564int
1565oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info)
1566{
1567
1568 struct oce_mbx mbx;
1569 struct mbx_common_phy_info *fwcmd;
1570 int rc = 0;
1571
1572 bzero(&mbx, sizeof(struct oce_mbx));
1573
1574 fwcmd = (struct mbx_common_phy_info *)&mbx.payload;
1575 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1576 MBX_SUBSYSTEM_COMMON,
1577 OPCODE_COMMON_GET_PHY_CONFIG,
1578 MBX_TIMEOUT_SEC,
1579 sizeof(struct mbx_common_phy_info),
1580 OCE_MBX_VER_V0);
1581
1582 mbx.u0.s.embedded = 1;
1583 mbx.payload_length = sizeof(struct mbx_common_phy_info);
1584
1585 /* now post the command */
1586 rc = oce_mbox_post(sc, &mbx, NULL);
1587 if (!rc)
1588 rc = fwcmd->hdr.u0.rsp.status;
1589 if (rc) {
|
1535 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1536 __FUNCTION__, rc);
| 1590 device_printf(sc->dev,
1591 "%s failed - cmd status: %d addi status: %d\n",
1592 __FUNCTION__, rc,
1593 fwcmd->hdr.u0.rsp.additional_status);
|
1537 goto error;
1538 }
| 1594 goto error;
1595 }
|
1539 phy_info->phy_type = fwcmd->params.rsp.phy_info.phy_type;
| 1596 phy_info->phy_type = HOST_16(fwcmd->params.rsp.phy_info.phy_type);
|
1540 phy_info->interface_type =
| 1597 phy_info->interface_type =
|
1541 fwcmd->params.rsp.phy_info.interface_type;
| 1598 HOST_16(fwcmd->params.rsp.phy_info.interface_type);
|
1542 phy_info->auto_speeds_supported =
| 1599 phy_info->auto_speeds_supported =
|
1543 fwcmd->params.rsp.phy_info.auto_speeds_supported;
| 1600 HOST_16(fwcmd->params.rsp.phy_info.auto_speeds_supported);
|
1544 phy_info->fixed_speeds_supported =
| 1601 phy_info->fixed_speeds_supported =
|
1545 fwcmd->params.rsp.phy_info.fixed_speeds_supported;
1546 phy_info->misc_params =fwcmd->params.rsp.phy_info.misc_params;
| 1602 HOST_16(fwcmd->params.rsp.phy_info.fixed_speeds_supported);
1603 phy_info->misc_params = HOST_32(fwcmd->params.rsp.phy_info.misc_params);
|
1547error:
1548 return rc;
1549
1550}
1551
1552
1553int
1554oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1555 uint32_t data_offset, POCE_DMA_MEM pdma_mem,
1556 uint32_t *written_data, uint32_t *additional_status)
1557{
1558
1559 struct oce_mbx mbx;
1560 struct mbx_lancer_common_write_object *fwcmd = NULL;
1561 int rc = 0, payload_len = 0;
1562
1563 bzero(&mbx, sizeof(struct oce_mbx));
1564 payload_len = sizeof(struct mbx_lancer_common_write_object);
1565
1566 mbx.u0.s.embedded = 1;/* Embedded */
1567 mbx.payload_length = payload_len;
1568 fwcmd = (struct mbx_lancer_common_write_object *)&mbx.payload;
1569
1570 /* initialize the ioctl header */
1571 mbx_common_req_hdr_init(&fwcmd->params.req.hdr, 0, 0,
1572 MBX_SUBSYSTEM_COMMON,
1573 OPCODE_COMMON_WRITE_OBJECT,
1574 LONG_TIMEOUT,
1575 payload_len,
1576 OCE_MBX_VER_V0);
1577
1578 fwcmd->params.req.write_length = data_size;
1579 if (data_size == 0)
1580 fwcmd->params.req.eof = 1;
1581 else
1582 fwcmd->params.req.eof = 0;
1583
1584 strcpy(fwcmd->params.req.object_name, "/prg");
1585 fwcmd->params.req.descriptor_count = 1;
1586 fwcmd->params.req.write_offset = data_offset;
1587 fwcmd->params.req.buffer_length = data_size;
1588 fwcmd->params.req.address_lower = pdma_mem->paddr & 0xFFFFFFFF;
1589 fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr);
1590
1591 /* post the command */
1592 rc = oce_mbox_post(sc, &mbx, NULL);
1593 if (!rc)
1594 rc = fwcmd->params.rsp.status;
1595 if (rc) {
| 1604error:
1605 return rc;
1606
1607}
1608
1609
1610int
1611oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1612 uint32_t data_offset, POCE_DMA_MEM pdma_mem,
1613 uint32_t *written_data, uint32_t *additional_status)
1614{
1615
1616 struct oce_mbx mbx;
1617 struct mbx_lancer_common_write_object *fwcmd = NULL;
1618 int rc = 0, payload_len = 0;
1619
1620 bzero(&mbx, sizeof(struct oce_mbx));
1621 payload_len = sizeof(struct mbx_lancer_common_write_object);
1622
1623 mbx.u0.s.embedded = 1;/* Embedded */
1624 mbx.payload_length = payload_len;
1625 fwcmd = (struct mbx_lancer_common_write_object *)&mbx.payload;
1626
1627 /* initialize the ioctl header */
1628 mbx_common_req_hdr_init(&fwcmd->params.req.hdr, 0, 0,
1629 MBX_SUBSYSTEM_COMMON,
1630 OPCODE_COMMON_WRITE_OBJECT,
1631 LONG_TIMEOUT,
1632 payload_len,
1633 OCE_MBX_VER_V0);
1634
1635 fwcmd->params.req.write_length = data_size;
1636 if (data_size == 0)
1637 fwcmd->params.req.eof = 1;
1638 else
1639 fwcmd->params.req.eof = 0;
1640
1641 strcpy(fwcmd->params.req.object_name, "/prg");
1642 fwcmd->params.req.descriptor_count = 1;
1643 fwcmd->params.req.write_offset = data_offset;
1644 fwcmd->params.req.buffer_length = data_size;
1645 fwcmd->params.req.address_lower = pdma_mem->paddr & 0xFFFFFFFF;
1646 fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr);
1647
1648 /* post the command */
1649 rc = oce_mbox_post(sc, &mbx, NULL);
1650 if (!rc)
1651 rc = fwcmd->params.rsp.status;
1652 if (rc) {
|
1596 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1597 __FUNCTION__, rc);
| 1653 device_printf(sc->dev,
1654 "%s failed - cmd status: %d addi status: %d\n",
1655 __FUNCTION__, rc,
1656 fwcmd->params.rsp.additional_status);
|
1598 goto error;
1599 }
| 1657 goto error;
1658 }
|
1600 *written_data = fwcmd->params.rsp.actual_write_length;
| 1659 *written_data = HOST_32(fwcmd->params.rsp.actual_write_length);
|
1601 *additional_status = fwcmd->params.rsp.additional_status;
1602error:
1603 return rc;
1604
1605}
1606
1607
1608
1609int
1610oce_mbox_create_rq(struct oce_rq *rq)
1611{
1612
1613 struct oce_mbx mbx;
1614 struct mbx_create_nic_rq *fwcmd;
1615 POCE_SOFTC sc = rq->parent;
1616 int rc, num_pages = 0;
1617
1618 if (rq->qstate == QCREATED)
1619 return 0;
1620
1621 bzero(&mbx, sizeof(struct oce_mbx));
1622
1623 fwcmd = (struct mbx_create_nic_rq *)&mbx.payload;
1624 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1625 MBX_SUBSYSTEM_NIC,
1626 NIC_CREATE_RQ, MBX_TIMEOUT_SEC,
1627 sizeof(struct mbx_create_nic_rq),
1628 OCE_MBX_VER_V0);
1629
1630 /* oce_page_list will also prepare pages */
1631 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
1632
1633 if (IS_XE201(sc)) {
1634 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
1635 fwcmd->params.req.page_size = 1;
1636 fwcmd->hdr.u0.req.version = OCE_MBX_VER_V1;
1637 } else
1638 fwcmd->params.req.frag_size = OCE_LOG2(rq->cfg.frag_size);
1639 fwcmd->params.req.num_pages = num_pages;
1640 fwcmd->params.req.cq_id = rq->cq->cq_id;
1641 fwcmd->params.req.if_id = sc->if_id;
1642 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
1643 fwcmd->params.req.is_rss_queue = rq->cfg.is_rss_queue;
1644
1645 mbx.u0.s.embedded = 1;
1646 mbx.payload_length = sizeof(struct mbx_create_nic_rq);
1647
1648 rc = oce_mbox_post(sc, &mbx, NULL);
1649 if (!rc)
1650 rc = fwcmd->hdr.u0.rsp.status;
1651 if (rc) {
| 1660 *additional_status = fwcmd->params.rsp.additional_status;
1661error:
1662 return rc;
1663
1664}
1665
1666
1667
1668int
1669oce_mbox_create_rq(struct oce_rq *rq)
1670{
1671
1672 struct oce_mbx mbx;
1673 struct mbx_create_nic_rq *fwcmd;
1674 POCE_SOFTC sc = rq->parent;
1675 int rc, num_pages = 0;
1676
1677 if (rq->qstate == QCREATED)
1678 return 0;
1679
1680 bzero(&mbx, sizeof(struct oce_mbx));
1681
1682 fwcmd = (struct mbx_create_nic_rq *)&mbx.payload;
1683 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1684 MBX_SUBSYSTEM_NIC,
1685 NIC_CREATE_RQ, MBX_TIMEOUT_SEC,
1686 sizeof(struct mbx_create_nic_rq),
1687 OCE_MBX_VER_V0);
1688
1689 /* oce_page_list will also prepare pages */
1690 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
1691
1692 if (IS_XE201(sc)) {
1693 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
1694 fwcmd->params.req.page_size = 1;
1695 fwcmd->hdr.u0.req.version = OCE_MBX_VER_V1;
1696 } else
1697 fwcmd->params.req.frag_size = OCE_LOG2(rq->cfg.frag_size);
1698 fwcmd->params.req.num_pages = num_pages;
1699 fwcmd->params.req.cq_id = rq->cq->cq_id;
1700 fwcmd->params.req.if_id = sc->if_id;
1701 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
1702 fwcmd->params.req.is_rss_queue = rq->cfg.is_rss_queue;
1703
1704 mbx.u0.s.embedded = 1;
1705 mbx.payload_length = sizeof(struct mbx_create_nic_rq);
1706
1707 rc = oce_mbox_post(sc, &mbx, NULL);
1708 if (!rc)
1709 rc = fwcmd->hdr.u0.rsp.status;
1710 if (rc) {
|
1652 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1653 __FUNCTION__, rc);
| 1711 device_printf(sc->dev,
1712 "%s failed - cmd status: %d addi status: %d\n",
1713 __FUNCTION__, rc,
1714 fwcmd->hdr.u0.rsp.additional_status);
|
1654 goto error;
1655 }
| 1715 goto error;
1716 }
|
1656 rq->rq_id = fwcmd->params.rsp.rq_id;
| 1717 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id);
|
1657 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;
1658error:
1659 return rc;
1660
1661}
1662
1663
1664
1665int
1666oce_mbox_create_wq(struct oce_wq *wq)
1667{
1668 struct oce_mbx mbx;
1669 struct mbx_create_nic_wq *fwcmd;
1670 POCE_SOFTC sc = wq->parent;
1671 int rc = 0, version, num_pages;
1672
1673 bzero(&mbx, sizeof(struct oce_mbx));
1674
1675 fwcmd = (struct mbx_create_nic_wq *)&mbx.payload;
| 1718 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;
1719error:
1720 return rc;
1721
1722}
1723
1724
1725
1726int
1727oce_mbox_create_wq(struct oce_wq *wq)
1728{
1729 struct oce_mbx mbx;
1730 struct mbx_create_nic_wq *fwcmd;
1731 POCE_SOFTC sc = wq->parent;
1732 int rc = 0, version, num_pages;
1733
1734 bzero(&mbx, sizeof(struct oce_mbx));
1735
1736 fwcmd = (struct mbx_create_nic_wq *)&mbx.payload;
|
1676 if (IS_XE201(sc)) {
| 1737 if (IS_XE201(sc))
|
1677 version = OCE_MBX_VER_V1;
| 1738 version = OCE_MBX_VER_V1;
|
1678 fwcmd->params.req.if_id = sc->if_id;
1679 } else if(IS_BE(sc))
| 1739 else if(IS_BE(sc))
|
1680 IS_PROFILE_SUPER_NIC(sc) ? (version = OCE_MBX_VER_V2)
1681 : (version = OCE_MBX_VER_V0);
1682 else
1683 version = OCE_MBX_VER_V2;
1684
| 1740 IS_PROFILE_SUPER_NIC(sc) ? (version = OCE_MBX_VER_V2)
1741 : (version = OCE_MBX_VER_V0);
1742 else
1743 version = OCE_MBX_VER_V2;
1744
|
| 1745 if (version > OCE_MBX_VER_V0)
1746 fwcmd->params.req.if_id = sc->if_id;
1747
|
1685 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1686 MBX_SUBSYSTEM_NIC,
1687 NIC_CREATE_WQ, MBX_TIMEOUT_SEC,
1688 sizeof(struct mbx_create_nic_wq),
1689 version);
1690
1691 num_pages = oce_page_list(wq->ring, &fwcmd->params.req.pages[0]);
1692
1693 fwcmd->params.req.nic_wq_type = wq->cfg.wq_type;
1694 fwcmd->params.req.num_pages = num_pages;
1695 fwcmd->params.req.wq_size = OCE_LOG2(wq->cfg.q_len) + 1;
1696 fwcmd->params.req.cq_id = wq->cq->cq_id;
1697 fwcmd->params.req.ulp_num = 1;
1698
1699 mbx.u0.s.embedded = 1;
1700 mbx.payload_length = sizeof(struct mbx_create_nic_wq);
1701
1702 rc = oce_mbox_post(sc, &mbx, NULL);
1703 if (!rc)
1704 rc = fwcmd->hdr.u0.rsp.status;
1705 if (rc) {
| 1748 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1749 MBX_SUBSYSTEM_NIC,
1750 NIC_CREATE_WQ, MBX_TIMEOUT_SEC,
1751 sizeof(struct mbx_create_nic_wq),
1752 version);
1753
1754 num_pages = oce_page_list(wq->ring, &fwcmd->params.req.pages[0]);
1755
1756 fwcmd->params.req.nic_wq_type = wq->cfg.wq_type;
1757 fwcmd->params.req.num_pages = num_pages;
1758 fwcmd->params.req.wq_size = OCE_LOG2(wq->cfg.q_len) + 1;
1759 fwcmd->params.req.cq_id = wq->cq->cq_id;
1760 fwcmd->params.req.ulp_num = 1;
1761
1762 mbx.u0.s.embedded = 1;
1763 mbx.payload_length = sizeof(struct mbx_create_nic_wq);
1764
1765 rc = oce_mbox_post(sc, &mbx, NULL);
1766 if (!rc)
1767 rc = fwcmd->hdr.u0.rsp.status;
1768 if (rc) {
|
1706 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1707 __FUNCTION__, rc);
| 1769 device_printf(sc->dev,
1770 "%s failed - cmd status: %d addi status: %d\n",
1771 __FUNCTION__, rc,
1772 fwcmd->hdr.u0.rsp.additional_status);
|
1708 goto error;
1709 }
| 1773 goto error;
1774 }
|
1710 wq->wq_id = LE_16(fwcmd->params.rsp.wq_id);
| 1775 wq->wq_id = HOST_16(fwcmd->params.rsp.wq_id);
|
1711 if (version == OCE_MBX_VER_V2)
| 1776 if (version == OCE_MBX_VER_V2)
|
1712 wq->db_offset = LE_32(fwcmd->params.rsp.db_offset);
| 1777 wq->db_offset = HOST_32(fwcmd->params.rsp.db_offset);
|
1713 else
1714 wq->db_offset = PD_TXULP_DB;
1715error:
1716 return rc;
1717
1718}
1719
1720
1721
1722int
1723oce_mbox_create_eq(struct oce_eq *eq)
1724{
1725 struct oce_mbx mbx;
1726 struct mbx_create_common_eq *fwcmd;
1727 POCE_SOFTC sc = eq->parent;
1728 int rc = 0;
1729 uint32_t num_pages;
1730
1731 bzero(&mbx, sizeof(struct oce_mbx));
1732
1733 fwcmd = (struct mbx_create_common_eq *)&mbx.payload;
1734
1735 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1736 MBX_SUBSYSTEM_COMMON,
1737 OPCODE_COMMON_CREATE_EQ, MBX_TIMEOUT_SEC,
1738 sizeof(struct mbx_create_common_eq),
1739 OCE_MBX_VER_V0);
1740
1741 num_pages = oce_page_list(eq->ring, &fwcmd->params.req.pages[0]);
1742 fwcmd->params.req.ctx.num_pages = num_pages;
1743 fwcmd->params.req.ctx.valid = 1;
1744 fwcmd->params.req.ctx.size = (eq->eq_cfg.item_size == 4) ? 0 : 1;
1745 fwcmd->params.req.ctx.count = OCE_LOG2(eq->eq_cfg.q_len / 256);
1746 fwcmd->params.req.ctx.armed = 0;
1747 fwcmd->params.req.ctx.delay_mult = eq->eq_cfg.cur_eqd;
1748
1749
1750 mbx.u0.s.embedded = 1;
1751 mbx.payload_length = sizeof(struct mbx_create_common_eq);
1752
1753 rc = oce_mbox_post(sc, &mbx, NULL);
1754 if (!rc)
1755 rc = fwcmd->hdr.u0.rsp.status;
1756 if (rc) {
| 1778 else
1779 wq->db_offset = PD_TXULP_DB;
1780error:
1781 return rc;
1782
1783}
1784
1785
1786
1787int
1788oce_mbox_create_eq(struct oce_eq *eq)
1789{
1790 struct oce_mbx mbx;
1791 struct mbx_create_common_eq *fwcmd;
1792 POCE_SOFTC sc = eq->parent;
1793 int rc = 0;
1794 uint32_t num_pages;
1795
1796 bzero(&mbx, sizeof(struct oce_mbx));
1797
1798 fwcmd = (struct mbx_create_common_eq *)&mbx.payload;
1799
1800 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1801 MBX_SUBSYSTEM_COMMON,
1802 OPCODE_COMMON_CREATE_EQ, MBX_TIMEOUT_SEC,
1803 sizeof(struct mbx_create_common_eq),
1804 OCE_MBX_VER_V0);
1805
1806 num_pages = oce_page_list(eq->ring, &fwcmd->params.req.pages[0]);
1807 fwcmd->params.req.ctx.num_pages = num_pages;
1808 fwcmd->params.req.ctx.valid = 1;
1809 fwcmd->params.req.ctx.size = (eq->eq_cfg.item_size == 4) ? 0 : 1;
1810 fwcmd->params.req.ctx.count = OCE_LOG2(eq->eq_cfg.q_len / 256);
1811 fwcmd->params.req.ctx.armed = 0;
1812 fwcmd->params.req.ctx.delay_mult = eq->eq_cfg.cur_eqd;
1813
1814
1815 mbx.u0.s.embedded = 1;
1816 mbx.payload_length = sizeof(struct mbx_create_common_eq);
1817
1818 rc = oce_mbox_post(sc, &mbx, NULL);
1819 if (!rc)
1820 rc = fwcmd->hdr.u0.rsp.status;
1821 if (rc) {
|
1757 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1758 __FUNCTION__, rc);
| 1822 device_printf(sc->dev,
1823 "%s failed - cmd status: %d addi status: %d\n",
1824 __FUNCTION__, rc,
1825 fwcmd->hdr.u0.rsp.additional_status);
|
1759 goto error;
1760 }
| 1826 goto error;
1827 }
|
1761 eq->eq_id = LE_16(fwcmd->params.rsp.eq_id);
| 1828 eq->eq_id = HOST_16(fwcmd->params.rsp.eq_id);
|
1762error:
1763 return rc;
1764}
1765
1766
1767
1768int
1769oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable)
1770{
1771 struct oce_mbx mbx;
1772 struct mbx_create_common_cq *fwcmd;
1773 POCE_SOFTC sc = cq->parent;
1774 uint8_t version;
1775 oce_cq_ctx_t *ctx;
1776 uint32_t num_pages, page_size;
1777 int rc = 0;
1778
1779
1780 bzero(&mbx, sizeof(struct oce_mbx));
1781
1782 fwcmd = (struct mbx_create_common_cq *)&mbx.payload;
1783
1784 if (IS_XE201(sc))
1785 version = OCE_MBX_VER_V2;
1786 else
1787 version = OCE_MBX_VER_V0;
1788
1789 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1790 MBX_SUBSYSTEM_COMMON,
1791 OPCODE_COMMON_CREATE_CQ,
1792 MBX_TIMEOUT_SEC,
1793 sizeof(struct mbx_create_common_cq),
1794 version);
1795
1796 ctx = &fwcmd->params.req.cq_ctx;
1797
1798 num_pages = oce_page_list(cq->ring, &fwcmd->params.req.pages[0]);
1799 page_size = 1; /* 1 for 4K */
1800
1801 if (version == OCE_MBX_VER_V2) {
1802 ctx->v2.num_pages = LE_16(num_pages);
1803 ctx->v2.page_size = page_size;
1804 ctx->v2.eventable = is_eventable;
1805 ctx->v2.valid = 1;
1806 ctx->v2.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1807 ctx->v2.nodelay = cq->cq_cfg.nodelay;
1808 ctx->v2.coalesce_wm = ncoalesce;
1809 ctx->v2.armed = 0;
1810 ctx->v2.eq_id = cq->eq->eq_id;
1811 if (ctx->v2.count == 3) {
1812 if (cq->cq_cfg.q_len > (4*1024)-1)
1813 ctx->v2.cqe_count = (4*1024)-1;
1814 else
1815 ctx->v2.cqe_count = cq->cq_cfg.q_len;
1816 }
1817 } else {
1818 ctx->v0.num_pages = LE_16(num_pages);
1819 ctx->v0.eventable = is_eventable;
1820 ctx->v0.valid = 1;
1821 ctx->v0.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1822 ctx->v0.nodelay = cq->cq_cfg.nodelay;
1823 ctx->v0.coalesce_wm = ncoalesce;
1824 ctx->v0.armed = 0;
1825 ctx->v0.eq_id = cq->eq->eq_id;
1826 }
1827
1828 mbx.u0.s.embedded = 1;
1829 mbx.payload_length = sizeof(struct mbx_create_common_cq);
1830
1831 rc = oce_mbox_post(sc, &mbx, NULL);
1832 if (!rc)
1833 rc = fwcmd->hdr.u0.rsp.status;
1834 if (rc) {
| 1829error:
1830 return rc;
1831}
1832
1833
1834
1835int
1836oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable)
1837{
1838 struct oce_mbx mbx;
1839 struct mbx_create_common_cq *fwcmd;
1840 POCE_SOFTC sc = cq->parent;
1841 uint8_t version;
1842 oce_cq_ctx_t *ctx;
1843 uint32_t num_pages, page_size;
1844 int rc = 0;
1845
1846
1847 bzero(&mbx, sizeof(struct oce_mbx));
1848
1849 fwcmd = (struct mbx_create_common_cq *)&mbx.payload;
1850
1851 if (IS_XE201(sc))
1852 version = OCE_MBX_VER_V2;
1853 else
1854 version = OCE_MBX_VER_V0;
1855
1856 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1857 MBX_SUBSYSTEM_COMMON,
1858 OPCODE_COMMON_CREATE_CQ,
1859 MBX_TIMEOUT_SEC,
1860 sizeof(struct mbx_create_common_cq),
1861 version);
1862
1863 ctx = &fwcmd->params.req.cq_ctx;
1864
1865 num_pages = oce_page_list(cq->ring, &fwcmd->params.req.pages[0]);
1866 page_size = 1; /* 1 for 4K */
1867
1868 if (version == OCE_MBX_VER_V2) {
1869 ctx->v2.num_pages = LE_16(num_pages);
1870 ctx->v2.page_size = page_size;
1871 ctx->v2.eventable = is_eventable;
1872 ctx->v2.valid = 1;
1873 ctx->v2.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1874 ctx->v2.nodelay = cq->cq_cfg.nodelay;
1875 ctx->v2.coalesce_wm = ncoalesce;
1876 ctx->v2.armed = 0;
1877 ctx->v2.eq_id = cq->eq->eq_id;
1878 if (ctx->v2.count == 3) {
1879 if (cq->cq_cfg.q_len > (4*1024)-1)
1880 ctx->v2.cqe_count = (4*1024)-1;
1881 else
1882 ctx->v2.cqe_count = cq->cq_cfg.q_len;
1883 }
1884 } else {
1885 ctx->v0.num_pages = LE_16(num_pages);
1886 ctx->v0.eventable = is_eventable;
1887 ctx->v0.valid = 1;
1888 ctx->v0.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1889 ctx->v0.nodelay = cq->cq_cfg.nodelay;
1890 ctx->v0.coalesce_wm = ncoalesce;
1891 ctx->v0.armed = 0;
1892 ctx->v0.eq_id = cq->eq->eq_id;
1893 }
1894
1895 mbx.u0.s.embedded = 1;
1896 mbx.payload_length = sizeof(struct mbx_create_common_cq);
1897
1898 rc = oce_mbox_post(sc, &mbx, NULL);
1899 if (!rc)
1900 rc = fwcmd->hdr.u0.rsp.status;
1901 if (rc) {
|
1835 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1836 __FUNCTION__, rc);
| 1902 device_printf(sc->dev,
1903 "%s failed - cmd status: %d addi status: %d\n",
1904 __FUNCTION__, rc,
1905 fwcmd->hdr.u0.rsp.additional_status);
|
1837 goto error;
1838 }
| 1906 goto error;
1907 }
|
1839 cq->cq_id = LE_16(fwcmd->params.rsp.cq_id);
| 1908 cq->cq_id = HOST_16(fwcmd->params.rsp.cq_id);
|
1840error:
1841 return rc;
1842
1843}
1844
1845int
1846oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num)
1847{
1848 int rc = 0;
1849 struct oce_mbx mbx;
1850 struct mbx_read_common_transrecv_data *fwcmd;
1851 struct oce_mq_sge *sgl;
1852 OCE_DMA_MEM dma;
1853
1854 /* Allocate DMA mem*/
1855 if (oce_dma_alloc(sc, sizeof(struct mbx_read_common_transrecv_data),
1856 &dma, 0))
1857 return ENOMEM;
1858
1859 fwcmd = OCE_DMAPTR(&dma, struct mbx_read_common_transrecv_data);
1860 bzero(fwcmd, sizeof(struct mbx_read_common_transrecv_data));
1861
1862 bzero(&mbx, sizeof(struct oce_mbx));
1863 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1864 MBX_SUBSYSTEM_COMMON,
1865 OPCODE_COMMON_READ_TRANSRECEIVER_DATA,
1866 MBX_TIMEOUT_SEC,
1867 sizeof(struct mbx_read_common_transrecv_data),
1868 OCE_MBX_VER_V0);
1869
1870 /* fill rest of mbx */
1871 mbx.u0.s.embedded = 0;
1872 mbx.payload_length = sizeof(struct mbx_read_common_transrecv_data);
1873 mbx.u0.s.sge_count = 1;
1874 sgl = &mbx.payload.u0.u1.sgl[0];
1875 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
1876 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
1877 sgl->length = htole32(mbx.payload_length);
1878 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1879
1880 fwcmd->params.req.port = LE_32(sc->port_id);
1881 fwcmd->params.req.page_num = LE_32(page_num);
1882
1883 /* command post */
1884 rc = oce_mbox_post(sc, &mbx, NULL);
1885 if (!rc)
1886 rc = fwcmd->hdr.u0.rsp.status;
1887 if (rc) {
| 1909error:
1910 return rc;
1911
1912}
1913
1914int
1915oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num)
1916{
1917 int rc = 0;
1918 struct oce_mbx mbx;
1919 struct mbx_read_common_transrecv_data *fwcmd;
1920 struct oce_mq_sge *sgl;
1921 OCE_DMA_MEM dma;
1922
1923 /* Allocate DMA mem*/
1924 if (oce_dma_alloc(sc, sizeof(struct mbx_read_common_transrecv_data),
1925 &dma, 0))
1926 return ENOMEM;
1927
1928 fwcmd = OCE_DMAPTR(&dma, struct mbx_read_common_transrecv_data);
1929 bzero(fwcmd, sizeof(struct mbx_read_common_transrecv_data));
1930
1931 bzero(&mbx, sizeof(struct oce_mbx));
1932 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1933 MBX_SUBSYSTEM_COMMON,
1934 OPCODE_COMMON_READ_TRANSRECEIVER_DATA,
1935 MBX_TIMEOUT_SEC,
1936 sizeof(struct mbx_read_common_transrecv_data),
1937 OCE_MBX_VER_V0);
1938
1939 /* fill rest of mbx */
1940 mbx.u0.s.embedded = 0;
1941 mbx.payload_length = sizeof(struct mbx_read_common_transrecv_data);
1942 mbx.u0.s.sge_count = 1;
1943 sgl = &mbx.payload.u0.u1.sgl[0];
1944 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
1945 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
1946 sgl->length = htole32(mbx.payload_length);
1947 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1948
1949 fwcmd->params.req.port = LE_32(sc->port_id);
1950 fwcmd->params.req.page_num = LE_32(page_num);
1951
1952 /* command post */
1953 rc = oce_mbox_post(sc, &mbx, NULL);
1954 if (!rc)
1955 rc = fwcmd->hdr.u0.rsp.status;
1956 if (rc) {
|
1888 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1889 __FUNCTION__, rc);
| 1957 device_printf(sc->dev,
1958 "%s failed - cmd status: %d addi status: %d\n",
1959 __FUNCTION__, rc,
1960 fwcmd->hdr.u0.rsp.additional_status);
|
1890 goto error;
1891 }
1892 if(fwcmd->params.rsp.page_num == PAGE_NUM_A0)
1893 {
1894 bcopy((char *)fwcmd->params.rsp.page_data,
1895 (char *)&sfp_vpd_dump_buffer[0],
1896 TRANSCEIVER_A0_SIZE);
1897 }
1898
1899 if(fwcmd->params.rsp.page_num == PAGE_NUM_A2)
1900 {
1901 bcopy((char *)fwcmd->params.rsp.page_data,
1902 (char *)&sfp_vpd_dump_buffer[32],
1903 TRANSCEIVER_A2_SIZE);
1904 }
1905error:
1906 oce_dma_free(sc, &dma);
1907 return rc;
1908}
1909
1910void
1911oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1912 int num)
1913{
1914 struct oce_mbx mbx;
1915 struct mbx_modify_common_eq_delay *fwcmd;
1916 int rc = 0;
1917 int i = 0;
1918
1919 bzero(&mbx, sizeof(struct oce_mbx));
1920
1921 /* Initialize MODIFY_EQ_DELAY ioctl header */
1922 fwcmd = (struct mbx_modify_common_eq_delay *)&mbx.payload;
1923 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1924 MBX_SUBSYSTEM_COMMON,
1925 OPCODE_COMMON_MODIFY_EQ_DELAY,
1926 MBX_TIMEOUT_SEC,
1927 sizeof(struct mbx_modify_common_eq_delay),
1928 OCE_MBX_VER_V0);
1929 /* fill rest of mbx */
1930 mbx.u0.s.embedded = 1;
1931 mbx.payload_length = sizeof(struct mbx_modify_common_eq_delay);
1932 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1933
1934 fwcmd->params.req.num_eq = num;
1935 for (i = 0; i < num; i++) {
1936 fwcmd->params.req.delay[i].eq_id =
1937 htole32(set_eqd[i].eq_id);
1938 fwcmd->params.req.delay[i].phase = 0;
1939 fwcmd->params.req.delay[i].dm =
1940 htole32(set_eqd[i].delay_multiplier);
1941 }
1942
1943
1944 /* command post */
1945 rc = oce_mbox_post(sc, &mbx, NULL);
1946
1947 if (!rc)
1948 rc = fwcmd->hdr.u0.rsp.status;
1949 if (rc)
| 1961 goto error;
1962 }
1963 if(fwcmd->params.rsp.page_num == PAGE_NUM_A0)
1964 {
1965 bcopy((char *)fwcmd->params.rsp.page_data,
1966 (char *)&sfp_vpd_dump_buffer[0],
1967 TRANSCEIVER_A0_SIZE);
1968 }
1969
1970 if(fwcmd->params.rsp.page_num == PAGE_NUM_A2)
1971 {
1972 bcopy((char *)fwcmd->params.rsp.page_data,
1973 (char *)&sfp_vpd_dump_buffer[32],
1974 TRANSCEIVER_A2_SIZE);
1975 }
1976error:
1977 oce_dma_free(sc, &dma);
1978 return rc;
1979}
1980
1981void
1982oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1983 int num)
1984{
1985 struct oce_mbx mbx;
1986 struct mbx_modify_common_eq_delay *fwcmd;
1987 int rc = 0;
1988 int i = 0;
1989
1990 bzero(&mbx, sizeof(struct oce_mbx));
1991
1992 /* Initialize MODIFY_EQ_DELAY ioctl header */
1993 fwcmd = (struct mbx_modify_common_eq_delay *)&mbx.payload;
1994 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1995 MBX_SUBSYSTEM_COMMON,
1996 OPCODE_COMMON_MODIFY_EQ_DELAY,
1997 MBX_TIMEOUT_SEC,
1998 sizeof(struct mbx_modify_common_eq_delay),
1999 OCE_MBX_VER_V0);
2000 /* fill rest of mbx */
2001 mbx.u0.s.embedded = 1;
2002 mbx.payload_length = sizeof(struct mbx_modify_common_eq_delay);
2003 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2004
2005 fwcmd->params.req.num_eq = num;
2006 for (i = 0; i < num; i++) {
2007 fwcmd->params.req.delay[i].eq_id =
2008 htole32(set_eqd[i].eq_id);
2009 fwcmd->params.req.delay[i].phase = 0;
2010 fwcmd->params.req.delay[i].dm =
2011 htole32(set_eqd[i].delay_multiplier);
2012 }
2013
2014
2015 /* command post */
2016 rc = oce_mbox_post(sc, &mbx, NULL);
2017
2018 if (!rc)
2019 rc = fwcmd->hdr.u0.rsp.status;
2020 if (rc)
|
1950 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1951 __FUNCTION__, rc);
| 2021 device_printf(sc->dev,
2022 "%s failed - cmd status: %d addi status: %d\n",
2023 __FUNCTION__, rc,
2024 fwcmd->hdr.u0.rsp.additional_status);
|
1952}
1953
1954int
1955oce_get_profile_config(POCE_SOFTC sc)
1956{
1957 struct oce_mbx mbx;
1958 struct mbx_common_get_profile_config *fwcmd;
1959 int rc = 0;
1960 int version = 0;
1961 struct oce_mq_sge *sgl;
1962 OCE_DMA_MEM dma;
1963 uint32_t desc_count = 0;
1964 struct oce_nic_resc_desc *nic_desc = NULL;
1965 int i;
1966 boolean_t nic_desc_valid = FALSE;
1967
1968 if (IS_BE2(sc))
1969 return -1;
1970
1971 /* Allocate DMA mem*/
1972 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_profile_config),
1973 &dma, 0))
1974 return ENOMEM;
1975
1976 /* Initialize MODIFY_EQ_DELAY ioctl header */
1977 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_profile_config);
1978 bzero(fwcmd, sizeof(struct mbx_common_get_profile_config));
1979
1980 if (IS_BE3(sc))
1981 version = OCE_MBX_VER_V1;
1982 else
1983 version = OCE_MBX_VER_V0;
1984
1985 bzero(&mbx, sizeof(struct oce_mbx));
1986 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1987 MBX_SUBSYSTEM_COMMON,
1988 OPCODE_COMMON_GET_PROFILE_CONFIG,
1989 MBX_TIMEOUT_SEC,
1990 sizeof(struct mbx_common_get_profile_config),
1991 version);
1992 /* fill rest of mbx */
1993 mbx.u0.s.embedded = 0;
1994 mbx.payload_length = sizeof(struct mbx_common_get_profile_config);
1995 mbx.u0.s.sge_count = 1;
1996 sgl = &mbx.payload.u0.u1.sgl[0];
1997 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
1998 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
1999 sgl->length = htole32(mbx.payload_length);
2000 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2001
2002 fwcmd->params.req.type = ACTIVE_PROFILE;
2003
2004 /* command post */
2005 rc = oce_mbox_post(sc, &mbx, NULL);
2006 if (!rc)
2007 rc = fwcmd->hdr.u0.rsp.status;
2008 if (rc) {
| 2025}
2026
2027int
2028oce_get_profile_config(POCE_SOFTC sc)
2029{
2030 struct oce_mbx mbx;
2031 struct mbx_common_get_profile_config *fwcmd;
2032 int rc = 0;
2033 int version = 0;
2034 struct oce_mq_sge *sgl;
2035 OCE_DMA_MEM dma;
2036 uint32_t desc_count = 0;
2037 struct oce_nic_resc_desc *nic_desc = NULL;
2038 int i;
2039 boolean_t nic_desc_valid = FALSE;
2040
2041 if (IS_BE2(sc))
2042 return -1;
2043
2044 /* Allocate DMA mem*/
2045 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_profile_config),
2046 &dma, 0))
2047 return ENOMEM;
2048
2049 /* Initialize MODIFY_EQ_DELAY ioctl header */
2050 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_profile_config);
2051 bzero(fwcmd, sizeof(struct mbx_common_get_profile_config));
2052
2053 if (IS_BE3(sc))
2054 version = OCE_MBX_VER_V1;
2055 else
2056 version = OCE_MBX_VER_V0;
2057
2058 bzero(&mbx, sizeof(struct oce_mbx));
2059 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2060 MBX_SUBSYSTEM_COMMON,
2061 OPCODE_COMMON_GET_PROFILE_CONFIG,
2062 MBX_TIMEOUT_SEC,
2063 sizeof(struct mbx_common_get_profile_config),
2064 version);
2065 /* fill rest of mbx */
2066 mbx.u0.s.embedded = 0;
2067 mbx.payload_length = sizeof(struct mbx_common_get_profile_config);
2068 mbx.u0.s.sge_count = 1;
2069 sgl = &mbx.payload.u0.u1.sgl[0];
2070 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2071 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2072 sgl->length = htole32(mbx.payload_length);
2073 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2074
2075 fwcmd->params.req.type = ACTIVE_PROFILE;
2076
2077 /* command post */
2078 rc = oce_mbox_post(sc, &mbx, NULL);
2079 if (!rc)
2080 rc = fwcmd->hdr.u0.rsp.status;
2081 if (rc) {
|
2009 device_printf(sc->dev,"%s failed - cmd status: %d\n",
2010 __FUNCTION__, rc);
| 2082 device_printf(sc->dev,
2083 "%s failed - cmd status: %d addi status: %d\n",
2084 __FUNCTION__, rc,
2085 fwcmd->hdr.u0.rsp.additional_status);
|
2011 goto error;
2012 }
2013
2014 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2015 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2016 for (i = 0; i < desc_count; i++) {
2017 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2018 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2019 nic_desc_valid = TRUE;
2020 break;
2021 }
2022 nic_desc = (struct oce_nic_resc_desc *) \
2023 ((char *)nic_desc + nic_desc->desc_len);
2024 }
2025 if (!nic_desc_valid) {
2026 rc = -1;
2027 goto error;
2028 }
2029 else {
| 2086 goto error;
2087 }
2088
2089 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2090 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2091 for (i = 0; i < desc_count; i++) {
2092 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2093 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2094 nic_desc_valid = TRUE;
2095 break;
2096 }
2097 nic_desc = (struct oce_nic_resc_desc *) \
2098 ((char *)nic_desc + nic_desc->desc_len);
2099 }
2100 if (!nic_desc_valid) {
2101 rc = -1;
2102 goto error;
2103 }
2104 else {
|
| 2105 sc->max_vlans = nic_desc->vlan_count;
|
2030 sc->nwqs = HOST_32(nic_desc->txq_count);
2031 if (sc->nwqs)
2032 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2033 else
2034 sc->nwqs = OCE_MAX_WQ;
2035
2036 }
2037error:
2038 oce_dma_free(sc, &dma);
2039 return rc;
2040
2041}
2042
2043int
2044oce_get_func_config(POCE_SOFTC sc)
2045{
2046 struct oce_mbx mbx;
2047 struct mbx_common_get_func_config *fwcmd;
2048 int rc = 0;
2049 int version = 0;
2050 struct oce_mq_sge *sgl;
2051 OCE_DMA_MEM dma;
2052 uint32_t desc_count = 0;
2053 struct oce_nic_resc_desc *nic_desc = NULL;
2054 int i;
2055 boolean_t nic_desc_valid = FALSE;
2056 uint32_t max_rss = 0;
2057
2058 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native))
2059 max_rss = OCE_LEGACY_MODE_RSS;
2060 else
2061 max_rss = OCE_MAX_RSS;
2062
2063 /* Allocate DMA mem*/
2064 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_func_config),
2065 &dma, 0))
2066 return ENOMEM;
2067
2068 /* Initialize MODIFY_EQ_DELAY ioctl header */
2069 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_func_config);
2070 bzero(fwcmd, sizeof(struct mbx_common_get_func_config));
2071
2072 if (IS_SH(sc))
2073 version = OCE_MBX_VER_V1;
2074 else
2075 version = OCE_MBX_VER_V0;
2076
2077 bzero(&mbx, sizeof(struct oce_mbx));
2078 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2079 MBX_SUBSYSTEM_COMMON,
2080 OPCODE_COMMON_GET_FUNCTION_CONFIG,
2081 MBX_TIMEOUT_SEC,
2082 sizeof(struct mbx_common_get_func_config),
2083 version);
2084 /* fill rest of mbx */
2085 mbx.u0.s.embedded = 0;
2086 mbx.payload_length = sizeof(struct mbx_common_get_func_config);
2087 mbx.u0.s.sge_count = 1;
2088 sgl = &mbx.payload.u0.u1.sgl[0];
2089 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2090 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2091 sgl->length = htole32(mbx.payload_length);
2092 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2093
2094 /* command post */
2095 rc = oce_mbox_post(sc, &mbx, NULL);
2096 if (!rc)
2097 rc = fwcmd->hdr.u0.rsp.status;
2098 if (rc) {
| 2106 sc->nwqs = HOST_32(nic_desc->txq_count);
2107 if (sc->nwqs)
2108 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2109 else
2110 sc->nwqs = OCE_MAX_WQ;
2111
2112 }
2113error:
2114 oce_dma_free(sc, &dma);
2115 return rc;
2116
2117}
2118
2119int
2120oce_get_func_config(POCE_SOFTC sc)
2121{
2122 struct oce_mbx mbx;
2123 struct mbx_common_get_func_config *fwcmd;
2124 int rc = 0;
2125 int version = 0;
2126 struct oce_mq_sge *sgl;
2127 OCE_DMA_MEM dma;
2128 uint32_t desc_count = 0;
2129 struct oce_nic_resc_desc *nic_desc = NULL;
2130 int i;
2131 boolean_t nic_desc_valid = FALSE;
2132 uint32_t max_rss = 0;
2133
2134 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native))
2135 max_rss = OCE_LEGACY_MODE_RSS;
2136 else
2137 max_rss = OCE_MAX_RSS;
2138
2139 /* Allocate DMA mem*/
2140 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_func_config),
2141 &dma, 0))
2142 return ENOMEM;
2143
2144 /* Initialize MODIFY_EQ_DELAY ioctl header */
2145 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_func_config);
2146 bzero(fwcmd, sizeof(struct mbx_common_get_func_config));
2147
2148 if (IS_SH(sc))
2149 version = OCE_MBX_VER_V1;
2150 else
2151 version = OCE_MBX_VER_V0;
2152
2153 bzero(&mbx, sizeof(struct oce_mbx));
2154 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
2155 MBX_SUBSYSTEM_COMMON,
2156 OPCODE_COMMON_GET_FUNCTION_CONFIG,
2157 MBX_TIMEOUT_SEC,
2158 sizeof(struct mbx_common_get_func_config),
2159 version);
2160 /* fill rest of mbx */
2161 mbx.u0.s.embedded = 0;
2162 mbx.payload_length = sizeof(struct mbx_common_get_func_config);
2163 mbx.u0.s.sge_count = 1;
2164 sgl = &mbx.payload.u0.u1.sgl[0];
2165 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
2166 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
2167 sgl->length = htole32(mbx.payload_length);
2168 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
2169
2170 /* command post */
2171 rc = oce_mbox_post(sc, &mbx, NULL);
2172 if (!rc)
2173 rc = fwcmd->hdr.u0.rsp.status;
2174 if (rc) {
|
2099 device_printf(sc->dev,"%s failed - cmd status: %d\n",
2100 __FUNCTION__, rc);
| 2175 device_printf(sc->dev,
2176 "%s failed - cmd status: %d addi status: %d\n",
2177 __FUNCTION__, rc,
2178 fwcmd->hdr.u0.rsp.additional_status);
|
2101 goto error;
2102 }
2103
2104 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2105 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2106 for (i = 0; i < desc_count; i++) {
2107 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2108 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2109 nic_desc_valid = TRUE;
2110 break;
2111 }
2112 nic_desc = (struct oce_nic_resc_desc *) \
2113 ((char *)nic_desc + nic_desc->desc_len);
2114 }
2115 if (!nic_desc_valid) {
2116 rc = -1;
2117 goto error;
2118 }
2119 else {
| 2179 goto error;
2180 }
2181
2182 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources;
2183 desc_count = HOST_32(fwcmd->params.rsp.desc_count);
2184 for (i = 0; i < desc_count; i++) {
2185 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) ||
2186 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) {
2187 nic_desc_valid = TRUE;
2188 break;
2189 }
2190 nic_desc = (struct oce_nic_resc_desc *) \
2191 ((char *)nic_desc + nic_desc->desc_len);
2192 }
2193 if (!nic_desc_valid) {
2194 rc = -1;
2195 goto error;
2196 }
2197 else {
|
| 2198 sc->max_vlans = nic_desc->vlan_count;
|
2120 sc->nwqs = HOST_32(nic_desc->txq_count);
2121 if (sc->nwqs)
2122 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2123 else
2124 sc->nwqs = OCE_MAX_WQ;
2125
2126 sc->nrssqs = HOST_32(nic_desc->rssq_count);
2127 if (sc->nrssqs)
2128 sc->nrssqs = MIN(sc->nrssqs, max_rss);
2129 else
2130 sc->nrssqs = max_rss;
2131 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */;
2132 }
2133error:
2134 oce_dma_free(sc, &dma);
2135 return rc;
2136
2137}
| 2199 sc->nwqs = HOST_32(nic_desc->txq_count);
2200 if (sc->nwqs)
2201 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ);
2202 else
2203 sc->nwqs = OCE_MAX_WQ;
2204
2205 sc->nrssqs = HOST_32(nic_desc->rssq_count);
2206 if (sc->nrssqs)
2207 sc->nrssqs = MIN(sc->nrssqs, max_rss);
2208 else
2209 sc->nrssqs = max_rss;
2210 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */;
2211 }
2212error:
2213 oce_dma_free(sc, &dma);
2214 return rc;
2215
2216}
|