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oce_if.h (252869) oce_if.h (257007)
1/*-
2 * Copyright (C) 2013 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,

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31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
1/*-
2 * Copyright (C) 2013 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,

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31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
39/* $FreeBSD: head/sys/dev/oce/oce_if.h 257007 2013-10-23 18:58:38Z delphij $ */
39
40
40/* $FreeBSD: head/sys/dev/oce/oce_if.h 252869 2013-07-06 08:30:45Z delphij $ */
41
42#include <sys/param.h>
43#include <sys/endian.h>
44#include <sys/module.h>
45#include <sys/kernel.h>
46#include <sys/bus.h>
47#include <sys/mbuf.h>
48#include <sys/rman.h>
49#include <sys/socket.h>

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83#include <netinet/tcp.h>
84#include <netinet/sctp.h>
85#include <netinet/tcp_lro.h>
86
87#include <machine/bus.h>
88
89#include "oce_hw.h"
90
41#include <sys/param.h>
42#include <sys/endian.h>
43#include <sys/module.h>
44#include <sys/kernel.h>
45#include <sys/bus.h>
46#include <sys/mbuf.h>
47#include <sys/rman.h>
48#include <sys/socket.h>

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82#include <netinet/tcp.h>
83#include <netinet/sctp.h>
84#include <netinet/tcp_lro.h>
85
86#include <machine/bus.h>
87
88#include "oce_hw.h"
89
91#define COMPONENT_REVISION "4.6.95.0"
90/* OCE device driver module component revision informaiton */
91#define COMPONENT_REVISION "10.0.664.0"
92
93/* OCE devices supported by this driver */
94#define PCI_VENDOR_EMULEX 0x10df /* Emulex */
95#define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */
96#define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */
97#define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */
98#define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */
99#define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */

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145#define OCE_MAX_JUMBO_FRAME_SIZE 9018
146#define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \
147 ETHER_VLAN_ENCAP_LEN - \
148 ETHER_HDR_LEN)
149
150#define OCE_MAX_TX_ELEMENTS 29
151#define OCE_MAX_TX_DESC 1024
152#define OCE_MAX_TX_SIZE 65535
92
93/* OCE devices supported by this driver */
94#define PCI_VENDOR_EMULEX 0x10df /* Emulex */
95#define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */
96#define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */
97#define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */
98#define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */
99#define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */

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145#define OCE_MAX_JUMBO_FRAME_SIZE 9018
146#define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \
147 ETHER_VLAN_ENCAP_LEN - \
148 ETHER_HDR_LEN)
149
150#define OCE_MAX_TX_ELEMENTS 29
151#define OCE_MAX_TX_DESC 1024
152#define OCE_MAX_TX_SIZE 65535
153#define OCE_MAX_TSO_SIZE (65535 - ETHER_HDR_LEN)
153#define OCE_MAX_RX_SIZE 4096
154#define OCE_MAX_RQ_POSTS 255
155#define OCE_DEFAULT_PROMISCUOUS 0
156
157
158#define RSS_ENABLE_IPV4 0x1
159#define RSS_ENABLE_TCP_IPV4 0x2
160#define RSS_ENABLE_IPV6 0x4

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168#define OCE_FC_RX 0x00000002
169#define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX)
170
171
172/* Interface capabilities to give device when creating interface */
173#define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \
174 MBX_RX_IFACE_FLAGS_UNTAGGED | \
175 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \
154#define OCE_MAX_RX_SIZE 4096
155#define OCE_MAX_RQ_POSTS 255
156#define OCE_DEFAULT_PROMISCUOUS 0
157
158
159#define RSS_ENABLE_IPV4 0x1
160#define RSS_ENABLE_TCP_IPV4 0x2
161#define RSS_ENABLE_IPV6 0x4

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169#define OCE_FC_RX 0x00000002
170#define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX)
171
172
173/* Interface capabilities to give device when creating interface */
174#define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \
175 MBX_RX_IFACE_FLAGS_UNTAGGED | \
176 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \
177 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS | \
176 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \
177 MBX_RX_IFACE_FLAGS_RSS | \
178 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
179
180/* Interface capabilities to enable by default (others set dynamically) */
181#define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \
182 MBX_RX_IFACE_FLAGS_UNTAGGED | \
183 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)

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858
859 uint32_t if_id; /* interface ID */
860 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */
861 uint32_t pmac_id; /* PMAC id */
862
863 uint32_t if_cap_flags;
864
865 uint32_t flow_control;
178 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \
179 MBX_RX_IFACE_FLAGS_RSS | \
180 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
181
182/* Interface capabilities to enable by default (others set dynamically) */
183#define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \
184 MBX_RX_IFACE_FLAGS_UNTAGGED | \
185 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)

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860
861 uint32_t if_id; /* interface ID */
862 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */
863 uint32_t pmac_id; /* PMAC id */
864
865 uint32_t if_cap_flags;
866
867 uint32_t flow_control;
866 uint32_t promisc;
868 uint8_t promisc;
867
868 struct oce_aic_obj aic_obj[OCE_MAX_EQ];
869
870 /*Vlan Filtering related */
871 eventhandler_tag vlan_attach;
872 eventhandler_tag vlan_detach;
873 uint16_t vlans_added;
874 uint8_t vlan_tag[MAX_VLANS];
875 /*stats */
876 OCE_DMA_MEM stats_mem;
877 struct oce_drv_stats oce_stats_info;
878 struct callout timer;
879 int8_t be3_native;
869
870 struct oce_aic_obj aic_obj[OCE_MAX_EQ];
871
872 /*Vlan Filtering related */
873 eventhandler_tag vlan_attach;
874 eventhandler_tag vlan_detach;
875 uint16_t vlans_added;
876 uint8_t vlan_tag[MAX_VLANS];
877 /*stats */
878 OCE_DMA_MEM stats_mem;
879 struct oce_drv_stats oce_stats_info;
880 struct callout timer;
881 int8_t be3_native;
882 uint8_t hw_error;
880 uint16_t qnq_debug_event;
881 uint16_t qnqid;
882 uint16_t pvid;
883 uint16_t qnq_debug_event;
884 uint16_t qnqid;
885 uint16_t pvid;
886 uint16_t max_vlans;
883
884} OCE_SOFTC, *POCE_SOFTC;
885
886
887
888/**************************************************
889 * BUS memory read/write macros
890 * BE3: accesses three BAR spaces (CFG, CSR, DB)

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1005int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags,
1006 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id);
1007int oce_if_del(POCE_SOFTC sc, uint32_t if_id);
1008int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id,
1009 struct normal_vlan *vtag_arr, uint8_t vtag_cnt,
1010 uint32_t untagged, uint32_t enable_promisc);
1011int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control);
1012int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss);
887
888} OCE_SOFTC, *POCE_SOFTC;
889
890
891
892/**************************************************
893 * BUS memory read/write macros
894 * BE3: accesses three BAR spaces (CFG, CSR, DB)

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1009int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags,
1010 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id);
1011int oce_if_del(POCE_SOFTC sc, uint32_t if_id);
1012int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id,
1013 struct normal_vlan *vtag_arr, uint8_t vtag_cnt,
1014 uint32_t untagged, uint32_t enable_promisc);
1015int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control);
1016int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss);
1013int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint32_t enable);
1017int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable);
1014int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl);
1015int oce_get_link_status(POCE_SOFTC sc, struct link_status *link);
1016int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1017int oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1018int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1019 uint32_t reset_stats);
1020int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1021 uint32_t req_size, uint32_t reset_stats);

--- 136 unchanged lines hidden --- 		1018int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl);
1019int oce_get_link_status(POCE_SOFTC sc, struct link_status *link);
1020int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1021int oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1022int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1023 uint32_t reset_stats);
1024int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1025 uint32_t req_size, uint32_t reset_stats);

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