1/*-
2 * Copyright (C) 2013 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
39
40/* $FreeBSD: head/sys/dev/oce/oce_if.h 252869 2013-07-06 08:30:45Z delphij $ */
41
42#include <sys/param.h>
43#include <sys/endian.h>
44#include <sys/module.h>
45#include <sys/kernel.h>
46#include <sys/bus.h>
47#include <sys/mbuf.h>
48#include <sys/rman.h>
49#include <sys/socket.h>
50#include <sys/sockio.h>
51#include <sys/sockopt.h>
52#include <sys/queue.h>
53#include <sys/taskqueue.h>
54#include <sys/lock.h>
55#include <sys/mutex.h>
56#include <sys/sysctl.h>
57#include <sys/random.h>
58#include <sys/firmware.h>
59#include <sys/systm.h>
60#include <sys/proc.h>
61
62#include <dev/pci/pcireg.h>
63#include <dev/pci/pcivar.h>
64
65#include <net/bpf.h>
66#include <net/ethernet.h>
67#include <net/if.h>
68#include <net/if_types.h>
69#include <net/if_media.h>
70#include <net/if_vlan_var.h>
71#include <net/if_dl.h>
72
73#include <netinet/in.h>
74#include <netinet/in_systm.h>
75#include <netinet/in_var.h>
76#include <netinet/if_ether.h>
77#include <netinet/ip.h>
78#include <netinet/ip6.h>
79#include <netinet6/in6_var.h>
80#include <netinet6/ip6_mroute.h>
81
82#include <netinet/udp.h>
83#include <netinet/tcp.h>
84#include <netinet/sctp.h>
85#include <netinet/tcp_lro.h>
86
87#include <machine/bus.h>
88
89#include "oce_hw.h"
90
91#define COMPONENT_REVISION "4.6.95.0"
92
93/* OCE devices supported by this driver */
94#define PCI_VENDOR_EMULEX 0x10df /* Emulex */
95#define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */
96#define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */
97#define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */
98#define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */
99#define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */
100#define PCI_PRODUCT_SH 0x0720 /* Skyhawk network adapter */
101
102#define IS_BE(sc) (((sc->flags & OCE_FLAGS_BE3) | \
103 (sc->flags & OCE_FLAGS_BE2))? 1:0)
104#define IS_BE3(sc) (sc->flags & OCE_FLAGS_BE3)
105#define IS_BE2(sc) (sc->flags & OCE_FLAGS_BE2)
106#define IS_XE201(sc) ((sc->flags & OCE_FLAGS_XE201) ? 1:0)
107#define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0)
108#define IS_SH(sc) ((sc->flags & OCE_FLAGS_SH) ? 1 : 0)
109
110#define is_be_mode_mc(sc) ((sc->function_mode & FNM_FLEX10_MODE) || \
111 (sc->function_mode & FNM_UMC_MODE) || \
112 (sc->function_mode & FNM_VNIC_MODE))
113#define OCE_FUNCTION_CAPS_SUPER_NIC 0x40
114#define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC)
115
116
117/* proportion Service Level Interface queues */
118#define OCE_MAX_UNITS 2
119#define OCE_MAX_PPORT OCE_MAX_UNITS
120#define OCE_MAX_VPORT OCE_MAX_UNITS
121
122extern int mp_ncpus; /* system's total active cpu cores */
123#define OCE_NCPUS mp_ncpus
124
125/* This should be powers of 2. Like 2,4,8 & 16 */
126#define OCE_MAX_RSS 8
127#define OCE_LEGACY_MODE_RSS 4 /* For BE3 Legacy mode*/
128#define is_rss_enabled(sc) ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc))
129
130#define OCE_MIN_RQ 1
131#define OCE_MIN_WQ 1
132
133#define OCE_MAX_RQ OCE_MAX_RSS + 1 /* one default queue */
134#define OCE_MAX_WQ 8
135
136#define OCE_MAX_EQ 32
137#define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */
138#define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */
139
140#define OCE_DEFAULT_WQ_EQD 16
141#define OCE_MAX_PACKET_Q 16
142#define OCE_RQ_BUF_SIZE 2048
143#define OCE_LSO_MAX_SIZE (64 * 1024)
144#define LONG_TIMEOUT 30
145#define OCE_MAX_JUMBO_FRAME_SIZE 9018
146#define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \
147 ETHER_VLAN_ENCAP_LEN - \
148 ETHER_HDR_LEN)
149
150#define OCE_MAX_TX_ELEMENTS 29
151#define OCE_MAX_TX_DESC 1024
152#define OCE_MAX_TX_SIZE 65535
153#define OCE_MAX_RX_SIZE 4096
154#define OCE_MAX_RQ_POSTS 255
155#define OCE_DEFAULT_PROMISCUOUS 0
156
157
158#define RSS_ENABLE_IPV4 0x1
159#define RSS_ENABLE_TCP_IPV4 0x2
160#define RSS_ENABLE_IPV6 0x4
161#define RSS_ENABLE_TCP_IPV6 0x8
162
163#define INDIRECTION_TABLE_ENTRIES 128
164
165/* flow control definitions */
166#define OCE_FC_NONE 0x00000000
167#define OCE_FC_TX 0x00000001
168#define OCE_FC_RX 0x00000002
169#define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX)
170
171
172/* Interface capabilities to give device when creating interface */
173#define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \
174 MBX_RX_IFACE_FLAGS_UNTAGGED | \
175 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \
176 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \
177 MBX_RX_IFACE_FLAGS_RSS | \
178 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
179
180/* Interface capabilities to enable by default (others set dynamically) */
181#define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \
182 MBX_RX_IFACE_FLAGS_UNTAGGED | \
183 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
184
185#define OCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP)
186#define OCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
187 IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \
188 IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU)
189#define OCE_IF_HWASSIST_NONE 0
190#define OCE_IF_CAPABILITIES_NONE 0
191
192
193#define ETH_ADDR_LEN 6
194#define MAX_VLANFILTER_SIZE 64
195#define MAX_VLANS 4096
196
197#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
198#define BSWAP_8(x) ((x) & 0xff)
199#define BSWAP_16(x) ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8))
200#define BSWAP_32(x) ((BSWAP_16(x) << 16) | \
201 BSWAP_16((x) >> 16))
202#define BSWAP_64(x) ((BSWAP_32(x) << 32) | \
203 BSWAP_32((x) >> 32))
204
205#define for_all_wq_queues(sc, wq, i) \
206 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i])
207#define for_all_rq_queues(sc, rq, i) \
208 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i])
209#define for_all_rss_queues(sc, rq, i) \
210 for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \
211 i++, rq = sc->rq[i + 1])
212#define for_all_evnt_queues(sc, eq, i) \
213 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i])
214#define for_all_cq_queues(sc, cq, i) \
215 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i])
216
217
218/* Flash specific */
219#define IOCTL_COOKIE "SERVERENGINES CORP"
220#define MAX_FLASH_COMP 32
221
222#define IMG_ISCSI 160
223#define IMG_REDBOOT 224
224#define IMG_BIOS 34
225#define IMG_PXEBIOS 32
226#define IMG_FCOEBIOS 33
227#define IMG_ISCSI_BAK 176
228#define IMG_FCOE 162
229#define IMG_FCOE_BAK 178
230#define IMG_NCSI 16
231#define IMG_PHY 192
232#define FLASHROM_OPER_FLASH 1
233#define FLASHROM_OPER_SAVE 2
234#define FLASHROM_OPER_REPORT 4
235#define FLASHROM_OPER_FLASH_PHY 9
236#define FLASHROM_OPER_SAVE_PHY 10
237#define TN_8022 13
238
239enum {
240 PHY_TYPE_CX4_10GB = 0,
241 PHY_TYPE_XFP_10GB,
242 PHY_TYPE_SFP_1GB,
243 PHY_TYPE_SFP_PLUS_10GB,
244 PHY_TYPE_KR_10GB,
245 PHY_TYPE_KX4_10GB,
246 PHY_TYPE_BASET_10GB,
247 PHY_TYPE_BASET_1GB,
248 PHY_TYPE_BASEX_1GB,
249 PHY_TYPE_SGMII,
250 PHY_TYPE_DISABLED = 255
251};
252
253/**
254 * @brief Define and hold all necessary info for a single interrupt
255 */
256#define OCE_MAX_MSI 32 /* Message Signaled Interrupts */
257#define OCE_MAX_MSIX 2048 /* PCI Express MSI Interrrupts */
258
259typedef struct oce_intr_info {
260 void *tag; /* cookie returned by bus_setup_intr */
261 struct resource *intr_res; /* PCI resource container */
262 int irq_rr; /* resource id for the interrupt */
263 struct oce_softc *sc; /* pointer to the parent soft c */
264 struct oce_eq *eq; /* pointer to the connected EQ */
265 struct taskqueue *tq; /* Associated task queue */
266 struct task task; /* task queue task */
267 char task_name[32]; /* task name */
268 int vector; /* interrupt vector number */
269} OCE_INTR_INFO, *POCE_INTR_INFO;
270
271
272/* Ring related */
273#define GET_Q_NEXT(_START, _STEP, _END) \
274 (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \
275 : (((_START) + (_STEP)) - (_END)))
276
277#define DBUF_PA(obj) ((obj)->addr)
278#define DBUF_VA(obj) ((obj)->ptr)
279#define DBUF_TAG(obj) ((obj)->tag)
280#define DBUF_MAP(obj) ((obj)->map)
281#define DBUF_SYNC(obj, flags) \
282 (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags))
283
284#define RING_NUM_PENDING(ring) ring->num_used
285#define RING_FULL(ring) (ring->num_used == ring->num_items)
286#define RING_EMPTY(ring) (ring->num_used == 0)
287#define RING_NUM_FREE(ring) \
288 (uint32_t)(ring->num_items - ring->num_used)
289#define RING_GET(ring, n) \
290 ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items)
291#define RING_PUT(ring, n) \
292 ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items)
293
294#define RING_GET_CONSUMER_ITEM_VA(ring, type) \
295 (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx)
296#define RING_GET_CONSUMER_ITEM_PA(ring, type) \
297 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx)
298#define RING_GET_PRODUCER_ITEM_VA(ring, type) \
299 (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx)
300#define RING_GET_PRODUCER_ITEM_PA(ring, type) \
301 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx)
302
303#define OCE_DMAPTR(o, c) ((c *)(o)->ptr)
304
305struct oce_packet_desc {
306 struct mbuf *mbuf;
307 bus_dmamap_t map;
308 int nsegs;
309 uint32_t wqe_idx;
310};
311
312typedef struct oce_dma_mem {
313 bus_dma_tag_t tag;
314 bus_dmamap_t map;
315 void *ptr;
316 bus_addr_t paddr;
317} OCE_DMA_MEM, *POCE_DMA_MEM;
318
319typedef struct oce_ring_buffer_s {
320 uint16_t cidx; /* Get ptr */
321 uint16_t pidx; /* Put Ptr */
322 size_t item_size;
323 size_t num_items;
324 uint32_t num_used;
325 OCE_DMA_MEM dma;
326} oce_ring_buffer_t;
327
328/* Stats */
329#define OCE_UNICAST_PACKET 0
330#define OCE_MULTICAST_PACKET 1
331#define OCE_BROADCAST_PACKET 2
332#define OCE_RSVD_PACKET 3
333
334struct oce_rx_stats {
335 /* Total Receive Stats*/
336 uint64_t t_rx_pkts;
337 uint64_t t_rx_bytes;
338 uint32_t t_rx_frags;
339 uint32_t t_rx_mcast_pkts;
340 uint32_t t_rx_ucast_pkts;
341 uint32_t t_rxcp_errs;
342};
343struct oce_tx_stats {
344 /*Total Transmit Stats */
345 uint64_t t_tx_pkts;
346 uint64_t t_tx_bytes;
347 uint32_t t_tx_reqs;
348 uint32_t t_tx_stops;
349 uint32_t t_tx_wrbs;
350 uint32_t t_tx_compl;
351 uint32_t t_ipv6_ext_hdr_tx_drop;
352};
353
354struct oce_be_stats {
355 uint8_t be_on_die_temperature;
356 uint32_t be_tx_events;
357 uint32_t eth_red_drops;
358 uint32_t rx_drops_no_pbuf;
359 uint32_t rx_drops_no_txpb;
360 uint32_t rx_drops_no_erx_descr;
361 uint32_t rx_drops_no_tpre_descr;
362 uint32_t rx_drops_too_many_frags;
363 uint32_t rx_drops_invalid_ring;
364 uint32_t forwarded_packets;
365 uint32_t rx_drops_mtu;
366 uint32_t rx_crc_errors;
367 uint32_t rx_alignment_symbol_errors;
368 uint32_t rx_pause_frames;
369 uint32_t rx_priority_pause_frames;
370 uint32_t rx_control_frames;
371 uint32_t rx_in_range_errors;
372 uint32_t rx_out_range_errors;
373 uint32_t rx_frame_too_long;
374 uint32_t rx_address_match_errors;
375 uint32_t rx_dropped_too_small;
376 uint32_t rx_dropped_too_short;
377 uint32_t rx_dropped_header_too_small;
378 uint32_t rx_dropped_tcp_length;
379 uint32_t rx_dropped_runt;
380 uint32_t rx_ip_checksum_errs;
381 uint32_t rx_tcp_checksum_errs;
382 uint32_t rx_udp_checksum_errs;
383 uint32_t rx_switched_unicast_packets;
384 uint32_t rx_switched_multicast_packets;
385 uint32_t rx_switched_broadcast_packets;
386 uint32_t tx_pauseframes;
387 uint32_t tx_priority_pauseframes;
388 uint32_t tx_controlframes;
389 uint32_t rxpp_fifo_overflow_drop;
390 uint32_t rx_input_fifo_overflow_drop;
391 uint32_t pmem_fifo_overflow_drop;
392 uint32_t jabber_events;
393};
394
395struct oce_xe201_stats {
396 uint64_t tx_pkts;
397 uint64_t tx_unicast_pkts;
398 uint64_t tx_multicast_pkts;
399 uint64_t tx_broadcast_pkts;
400 uint64_t tx_bytes;
401 uint64_t tx_unicast_bytes;
402 uint64_t tx_multicast_bytes;
403 uint64_t tx_broadcast_bytes;
404 uint64_t tx_discards;
405 uint64_t tx_errors;
406 uint64_t tx_pause_frames;
407 uint64_t tx_pause_on_frames;
408 uint64_t tx_pause_off_frames;
409 uint64_t tx_internal_mac_errors;
410 uint64_t tx_control_frames;
411 uint64_t tx_pkts_64_bytes;
412 uint64_t tx_pkts_65_to_127_bytes;
413 uint64_t tx_pkts_128_to_255_bytes;
414 uint64_t tx_pkts_256_to_511_bytes;
415 uint64_t tx_pkts_512_to_1023_bytes;
416 uint64_t tx_pkts_1024_to_1518_bytes;
417 uint64_t tx_pkts_1519_to_2047_bytes;
418 uint64_t tx_pkts_2048_to_4095_bytes;
419 uint64_t tx_pkts_4096_to_8191_bytes;
420 uint64_t tx_pkts_8192_to_9216_bytes;
421 uint64_t tx_lso_pkts;
422 uint64_t rx_pkts;
423 uint64_t rx_unicast_pkts;
424 uint64_t rx_multicast_pkts;
425 uint64_t rx_broadcast_pkts;
426 uint64_t rx_bytes;
427 uint64_t rx_unicast_bytes;
428 uint64_t rx_multicast_bytes;
429 uint64_t rx_broadcast_bytes;
430 uint32_t rx_unknown_protos;
431 uint64_t rx_discards;
432 uint64_t rx_errors;
433 uint64_t rx_crc_errors;
434 uint64_t rx_alignment_errors;
435 uint64_t rx_symbol_errors;
436 uint64_t rx_pause_frames;
437 uint64_t rx_pause_on_frames;
438 uint64_t rx_pause_off_frames;
439 uint64_t rx_frames_too_long;
440 uint64_t rx_internal_mac_errors;
441 uint32_t rx_undersize_pkts;
442 uint32_t rx_oversize_pkts;
443 uint32_t rx_fragment_pkts;
444 uint32_t rx_jabbers;
445 uint64_t rx_control_frames;
446 uint64_t rx_control_frames_unknown_opcode;
447 uint32_t rx_in_range_errors;
448 uint32_t rx_out_of_range_errors;
449 uint32_t rx_address_match_errors;
450 uint32_t rx_vlan_mismatch_errors;
451 uint32_t rx_dropped_too_small;
452 uint32_t rx_dropped_too_short;
453 uint32_t rx_dropped_header_too_small;
454 uint32_t rx_dropped_invalid_tcp_length;
455 uint32_t rx_dropped_runt;
456 uint32_t rx_ip_checksum_errors;
457 uint32_t rx_tcp_checksum_errors;
458 uint32_t rx_udp_checksum_errors;
459 uint32_t rx_non_rss_pkts;
460 uint64_t rx_ipv4_pkts;
461 uint64_t rx_ipv6_pkts;
462 uint64_t rx_ipv4_bytes;
463 uint64_t rx_ipv6_bytes;
464 uint64_t rx_nic_pkts;
465 uint64_t rx_tcp_pkts;
466 uint64_t rx_iscsi_pkts;
467 uint64_t rx_management_pkts;
468 uint64_t rx_switched_unicast_pkts;
469 uint64_t rx_switched_multicast_pkts;
470 uint64_t rx_switched_broadcast_pkts;
471 uint64_t num_forwards;
472 uint32_t rx_fifo_overflow;
473 uint32_t rx_input_fifo_overflow;
474 uint64_t rx_drops_too_many_frags;
475 uint32_t rx_drops_invalid_queue;
476 uint64_t rx_drops_mtu;
477 uint64_t rx_pkts_64_bytes;
478 uint64_t rx_pkts_65_to_127_bytes;
479 uint64_t rx_pkts_128_to_255_bytes;
480 uint64_t rx_pkts_256_to_511_bytes;
481 uint64_t rx_pkts_512_to_1023_bytes;
482 uint64_t rx_pkts_1024_to_1518_bytes;
483 uint64_t rx_pkts_1519_to_2047_bytes;
484 uint64_t rx_pkts_2048_to_4095_bytes;
485 uint64_t rx_pkts_4096_to_8191_bytes;
486 uint64_t rx_pkts_8192_to_9216_bytes;
487};
488
489struct oce_drv_stats {
490 struct oce_rx_stats rx;
491 struct oce_tx_stats tx;
492 union {
493 struct oce_be_stats be;
494 struct oce_xe201_stats xe201;
495 } u0;
496};
497
498#define INTR_RATE_HWM 15000
499#define INTR_RATE_LWM 10000
500
501#define OCE_MAX_EQD 128u
502#define OCE_MIN_EQD 50u
503
504struct oce_set_eqd {
505 uint32_t eq_id;
506 uint32_t phase;
507 uint32_t delay_multiplier;
508};
509
510struct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
511 boolean_t enable;
512 uint32_t min_eqd; /* in usecs */
513 uint32_t max_eqd; /* in usecs */
514 uint32_t cur_eqd; /* in usecs */
515 uint32_t et_eqd; /* configured value when aic is off */
516 uint64_t ticks;
517 uint64_t intr_prev;
518};
519
520#define MAX_LOCK_DESC_LEN 32
521struct oce_lock {
522 struct mtx mutex;
523 char name[MAX_LOCK_DESC_LEN+1];
524};
525#define OCE_LOCK struct oce_lock
526
527#define LOCK_CREATE(lock, desc) { \
528 strncpy((lock)->name, (desc), MAX_LOCK_DESC_LEN); \
529 (lock)->name[MAX_LOCK_DESC_LEN] = '\0'; \
530 mtx_init(&(lock)->mutex, (lock)->name, NULL, MTX_DEF); \
531}
532#define LOCK_DESTROY(lock) \
533 if (mtx_initialized(&(lock)->mutex))\
534 mtx_destroy(&(lock)->mutex)
535#define TRY_LOCK(lock) mtx_trylock(&(lock)->mutex)
536#define LOCK(lock) mtx_lock(&(lock)->mutex)
537#define LOCKED(lock) mtx_owned(&(lock)->mutex)
538#define UNLOCK(lock) mtx_unlock(&(lock)->mutex)
539
540#define DEFAULT_MQ_MBOX_TIMEOUT (5 * 1000 * 1000)
541#define MBX_READY_TIMEOUT (1 * 1000 * 1000)
542#define DEFAULT_DRAIN_TIME 200
543#define MBX_TIMEOUT_SEC 5
544#define STAT_TIMEOUT 2000000
545
546/* size of the packet descriptor array in a transmit queue */
547#define OCE_TX_RING_SIZE 2048
548#define OCE_RX_RING_SIZE 1024
549#define OCE_WQ_PACKET_ARRAY_SIZE (OCE_TX_RING_SIZE/2)
550#define OCE_RQ_PACKET_ARRAY_SIZE (OCE_RX_RING_SIZE)
551
552struct oce_dev;
553
554enum eq_len {
555 EQ_LEN_256 = 256,
556 EQ_LEN_512 = 512,
557 EQ_LEN_1024 = 1024,
558 EQ_LEN_2048 = 2048,
559 EQ_LEN_4096 = 4096
560};
561
562enum eqe_size {
563 EQE_SIZE_4 = 4,
564 EQE_SIZE_16 = 16
565};
566
567enum qtype {
568 QTYPE_EQ,
569 QTYPE_MQ,
570 QTYPE_WQ,
571 QTYPE_RQ,
572 QTYPE_CQ,
573 QTYPE_RSS
574};
575
576typedef enum qstate_e {
577 QDELETED = 0x0,
578 QCREATED = 0x1
579} qstate_t;
580
581struct eq_config {
582 enum eq_len q_len;
583 enum eqe_size item_size;
584 uint32_t q_vector_num;
585 uint8_t min_eqd;
586 uint8_t max_eqd;
587 uint8_t cur_eqd;
588 uint8_t pad;
589};
590
591struct oce_eq {
592 uint32_t eq_id;
593 void *parent;
594 void *cb_context;
595 oce_ring_buffer_t *ring;
596 uint32_t ref_count;
597 qstate_t qstate;
598 struct oce_cq *cq[OCE_MAX_CQ_EQ];
599 int cq_valid;
600 struct eq_config eq_cfg;
601 int vector;
602 uint64_t intr;
603};
604
605enum cq_len {
606 CQ_LEN_256 = 256,
607 CQ_LEN_512 = 512,
608 CQ_LEN_1024 = 1024
609};
610
611struct cq_config {
612 enum cq_len q_len;
613 uint32_t item_size;
614 boolean_t is_eventable;
615 boolean_t sol_eventable;
616 boolean_t nodelay;
617 uint16_t dma_coalescing;
618};
619
620typedef uint16_t(*cq_handler_t) (void *arg1);
621
622struct oce_cq {
623 uint32_t cq_id;
624 void *parent;
625 struct oce_eq *eq;
626 cq_handler_t cq_handler;
627 void *cb_arg;
628 oce_ring_buffer_t *ring;
629 qstate_t qstate;
630 struct cq_config cq_cfg;
631 uint32_t ref_count;
632};
633
634
635struct mq_config {
636 uint32_t eqd;
637 uint8_t q_len;
638 uint8_t pad[3];
639};
640
641
642struct oce_mq {
643 void *parent;
644 oce_ring_buffer_t *ring;
645 uint32_t mq_id;
646 struct oce_cq *cq;
647 struct oce_cq *async_cq;
648 uint32_t mq_free;
649 qstate_t qstate;
650 struct mq_config cfg;
651};
652
653struct oce_mbx_ctx {
654 struct oce_mbx *mbx;
655 void (*cb) (void *ctx);
656 void *cb_ctx;
657};
658
659struct wq_config {
660 uint8_t wq_type;
661 uint16_t buf_size;
662 uint8_t pad[1];
663 uint32_t q_len;
664 uint16_t pd_id;
665 uint16_t pci_fn_num;
666 uint32_t eqd; /* interrupt delay */
667 uint32_t nbufs;
668 uint32_t nhdl;
669};
670
671struct oce_tx_queue_stats {
672 uint64_t tx_pkts;
673 uint64_t tx_bytes;
674 uint32_t tx_reqs;
675 uint32_t tx_stops; /* number of times TX Q was stopped */
676 uint32_t tx_wrbs;
677 uint32_t tx_compl;
678 uint32_t tx_rate;
679 uint32_t ipv6_ext_hdr_tx_drop;
680};
681
682struct oce_wq {
683 OCE_LOCK tx_lock;
684 void *parent;
685 oce_ring_buffer_t *ring;
686 struct oce_cq *cq;
687 bus_dma_tag_t tag;
688 struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE];
689 uint32_t pkt_desc_tail;
690 uint32_t pkt_desc_head;
691 uint32_t wqm_used;
692 boolean_t resched;
693 uint32_t wq_free;
694 uint32_t tx_deferd;
695 uint32_t pkt_drops;
696 qstate_t qstate;
697 uint16_t wq_id;
698 struct wq_config cfg;
699 int queue_index;
700 struct oce_tx_queue_stats tx_stats;
701 struct buf_ring *br;
702 struct task txtask;
703 uint32_t db_offset;
704};
705
706struct rq_config {
707 uint32_t q_len;
708 uint32_t frag_size;
709 uint32_t mtu;
710 uint32_t if_id;
711 uint32_t is_rss_queue;
712 uint32_t eqd;
713 uint32_t nbufs;
714};
715
716struct oce_rx_queue_stats {
717 uint32_t rx_post_fail;
718 uint32_t rx_ucast_pkts;
719 uint32_t rx_compl;
720 uint64_t rx_bytes;
721 uint64_t rx_bytes_prev;
722 uint64_t rx_pkts;
723 uint32_t rx_rate;
724 uint32_t rx_mcast_pkts;
725 uint32_t rxcp_err;
726 uint32_t rx_frags;
727 uint32_t prev_rx_frags;
728 uint32_t rx_fps;
729};
730
731
732struct oce_rq {
733 struct rq_config cfg;
734 uint32_t rq_id;
735 int queue_index;
736 uint32_t rss_cpuid;
737 void *parent;
738 oce_ring_buffer_t *ring;
739 struct oce_cq *cq;
740 void *pad1;
741 bus_dma_tag_t tag;
742 struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE];
743 uint32_t packets_in;
744 uint32_t packets_out;
745 uint32_t pending;
746#ifdef notdef
747 struct mbuf *head;
748 struct mbuf *tail;
749 int fragsleft;
750#endif
751 qstate_t qstate;
752 OCE_LOCK rx_lock;
753 struct oce_rx_queue_stats rx_stats;
754 struct lro_ctrl lro;
755 int lro_pkts_queued;
756
757};
758
759struct link_status {
760 uint8_t physical_port;
761 uint8_t mac_duplex;
762 uint8_t mac_speed;
763 uint8_t mac_fault;
764 uint8_t mgmt_mac_duplex;
765 uint8_t mgmt_mac_speed;
766 uint16_t qos_link_speed;
767 uint32_t logical_link_status;
768};
769
770
771
772#define OCE_FLAGS_PCIX 0x00000001
773#define OCE_FLAGS_PCIE 0x00000002
774#define OCE_FLAGS_MSI_CAPABLE 0x00000004
775#define OCE_FLAGS_MSIX_CAPABLE 0x00000008
776#define OCE_FLAGS_USING_MSI 0x00000010
777#define OCE_FLAGS_USING_MSIX 0x00000020
778#define OCE_FLAGS_FUNCRESET_RQD 0x00000040
779#define OCE_FLAGS_VIRTUAL_PORT 0x00000080
780#define OCE_FLAGS_MBOX_ENDIAN_RQD 0x00000100
781#define OCE_FLAGS_BE3 0x00000200
782#define OCE_FLAGS_XE201 0x00000400
783#define OCE_FLAGS_BE2 0x00000800
784#define OCE_FLAGS_SH 0x00001000
785
786#define OCE_DEV_BE2_CFG_BAR 1
787#define OCE_DEV_CFG_BAR 0
788#define OCE_PCI_CSR_BAR 2
789#define OCE_PCI_DB_BAR 4
790
791typedef struct oce_softc {
792 device_t dev;
793 OCE_LOCK dev_lock;
794
795 uint32_t flags;
796
797 uint32_t pcie_link_speed;
798 uint32_t pcie_link_width;
799
800 uint8_t fn; /* PCI function number */
801
802 struct resource *devcfg_res;
803 bus_space_tag_t devcfg_btag;
804 bus_space_handle_t devcfg_bhandle;
805 void *devcfg_vhandle;
806
807 struct resource *csr_res;
808 bus_space_tag_t csr_btag;
809 bus_space_handle_t csr_bhandle;
810 void *csr_vhandle;
811
812 struct resource *db_res;
813 bus_space_tag_t db_btag;
814 bus_space_handle_t db_bhandle;
815 void *db_vhandle;
816
817 OCE_INTR_INFO intrs[OCE_MAX_EQ];
818 int intr_count;
819
820 struct ifnet *ifp;
821
822 struct ifmedia media;
823 uint8_t link_status;
824 uint8_t link_speed;
825 uint8_t duplex;
826 uint32_t qos_link_speed;
827 uint32_t speed;
828
829 char fw_version[32];
830 struct mac_address_format macaddr;
831
832 OCE_DMA_MEM bsmbx;
833 OCE_LOCK bmbx_lock;
834
835 uint32_t config_number;
836 uint32_t asic_revision;
837 uint32_t port_id;
838 uint32_t function_mode;
839 uint32_t function_caps;
840 uint32_t max_tx_rings;
841 uint32_t max_rx_rings;
842
843 struct oce_wq *wq[OCE_MAX_WQ]; /* TX work queues */
844 struct oce_rq *rq[OCE_MAX_RQ]; /* RX work queues */
845 struct oce_cq *cq[OCE_MAX_CQ]; /* Completion queues */
846 struct oce_eq *eq[OCE_MAX_EQ]; /* Event queues */
847 struct oce_mq *mq; /* Mailbox queue */
848
849 uint32_t neqs;
850 uint32_t ncqs;
851 uint32_t nrqs;
852 uint32_t nwqs;
853 uint32_t nrssqs;
854
855 uint32_t tx_ring_size;
856 uint32_t rx_ring_size;
857 uint32_t rq_frag_size;
858
859 uint32_t if_id; /* interface ID */
860 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */
861 uint32_t pmac_id; /* PMAC id */
862
863 uint32_t if_cap_flags;
864
865 uint32_t flow_control;
866 uint32_t promisc;
867
868 struct oce_aic_obj aic_obj[OCE_MAX_EQ];
869
870 /*Vlan Filtering related */
871 eventhandler_tag vlan_attach;
872 eventhandler_tag vlan_detach;
873 uint16_t vlans_added;
874 uint8_t vlan_tag[MAX_VLANS];
875 /*stats */
876 OCE_DMA_MEM stats_mem;
877 struct oce_drv_stats oce_stats_info;
878 struct callout timer;
879 int8_t be3_native;
880 uint16_t qnq_debug_event;
881 uint16_t qnqid;
882 uint16_t pvid;
883
884} OCE_SOFTC, *POCE_SOFTC;
885
886
887
888/**************************************************
889 * BUS memory read/write macros
890 * BE3: accesses three BAR spaces (CFG, CSR, DB)
891 * Lancer: accesses one BAR space (CFG)
892 **************************************************/
893#define OCE_READ_CSR_MPU(sc, space, o) \
894 ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \
895 (sc)->space##_bhandle,o)) \
896 : (bus_space_read_4((sc)->devcfg_btag, \
897 (sc)->devcfg_bhandle,o)))
898#define OCE_READ_REG32(sc, space, o) \
899 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \
900 (sc)->space##_bhandle,o)) \
901 : (bus_space_read_4((sc)->devcfg_btag, \
902 (sc)->devcfg_bhandle,o)))
903#define OCE_READ_REG16(sc, space, o) \
904 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \
905 (sc)->space##_bhandle,o)) \
906 : (bus_space_read_2((sc)->devcfg_btag, \
907 (sc)->devcfg_bhandle,o)))
908#define OCE_READ_REG8(sc, space, o) \
909 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \
910 (sc)->space##_bhandle,o)) \
911 : (bus_space_read_1((sc)->devcfg_btag, \
912 (sc)->devcfg_bhandle,o)))
913
914#define OCE_WRITE_CSR_MPU(sc, space, o, v) \
915 ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \
916 (sc)->space##_bhandle,o,v)) \
917 : (bus_space_write_4((sc)->devcfg_btag, \
918 (sc)->devcfg_bhandle,o,v)))
919#define OCE_WRITE_REG32(sc, space, o, v) \
920 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \
921 (sc)->space##_bhandle,o,v)) \
922 : (bus_space_write_4((sc)->devcfg_btag, \
923 (sc)->devcfg_bhandle,o,v)))
924#define OCE_WRITE_REG16(sc, space, o, v) \
925 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \
926 (sc)->space##_bhandle,o,v)) \
927 : (bus_space_write_2((sc)->devcfg_btag, \
928 (sc)->devcfg_bhandle,o,v)))
929#define OCE_WRITE_REG8(sc, space, o, v) \
930 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \
931 (sc)->space##_bhandle,o,v)) \
932 : (bus_space_write_1((sc)->devcfg_btag, \
933 (sc)->devcfg_bhandle,o,v)))
934
935
936/***********************************************************
937 * DMA memory functions
938 ***********************************************************/
939#define oce_dma_sync(d, f) bus_dmamap_sync((d)->tag, (d)->map, f)
940int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags);
941void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma);
942void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error);
943void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring);
944oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc,
945 uint32_t q_len, uint32_t num_entries);
946/************************************************************
947 * oce_hw_xxx functions
948 ************************************************************/
949int oce_clear_rx_buf(struct oce_rq *rq);
950int oce_hw_pci_alloc(POCE_SOFTC sc);
951int oce_hw_init(POCE_SOFTC sc);
952int oce_hw_start(POCE_SOFTC sc);
953int oce_create_nw_interface(POCE_SOFTC sc);
954int oce_pci_soft_reset(POCE_SOFTC sc);
955int oce_hw_update_multicast(POCE_SOFTC sc);
956void oce_delete_nw_interface(POCE_SOFTC sc);
957void oce_hw_shutdown(POCE_SOFTC sc);
958void oce_hw_intr_enable(POCE_SOFTC sc);
959void oce_hw_intr_disable(POCE_SOFTC sc);
960void oce_hw_pci_free(POCE_SOFTC sc);
961
962/***********************************************************
963 * oce_queue_xxx functions
964 ***********************************************************/
965int oce_queue_init_all(POCE_SOFTC sc);
966int oce_start_rq(struct oce_rq *rq);
967int oce_start_wq(struct oce_wq *wq);
968int oce_start_mq(struct oce_mq *mq);
969int oce_start_rx(POCE_SOFTC sc);
970void oce_arm_eq(POCE_SOFTC sc,
971 int16_t qid, int npopped, uint32_t rearm, uint32_t clearint);
972void oce_queue_release_all(POCE_SOFTC sc);
973void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm);
974void oce_drain_eq(struct oce_eq *eq);
975void oce_drain_mq_cq(void *arg);
976void oce_drain_rq_cq(struct oce_rq *rq);
977void oce_drain_wq_cq(struct oce_wq *wq);
978
979uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list);
980
981/***********************************************************
982 * cleanup functions
983 ***********************************************************/
984void oce_stop_rx(POCE_SOFTC sc);
985void oce_intr_free(POCE_SOFTC sc);
986void oce_free_posted_rxbuf(struct oce_rq *rq);
987#if defined(INET6) || defined(INET)
988void oce_free_lro(POCE_SOFTC sc);
989#endif
990
991
992/************************************************************
993 * Mailbox functions
994 ************************************************************/
995int oce_fw_clean(POCE_SOFTC sc);
996int oce_reset_fun(POCE_SOFTC sc);
997int oce_mbox_init(POCE_SOFTC sc);
998int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec);
999int oce_get_fw_version(POCE_SOFTC sc);
1000int oce_first_mcc_cmd(POCE_SOFTC sc);
1001
1002int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm,
1003 uint8_t type, struct mac_address_format *mac);
1004int oce_get_fw_config(POCE_SOFTC sc);
1005int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags,
1006 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id);
1007int oce_if_del(POCE_SOFTC sc, uint32_t if_id);
1008int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id,
1009 struct normal_vlan *vtag_arr, uint8_t vtag_cnt,
1010 uint32_t untagged, uint32_t enable_promisc);
1011int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control);
1012int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss);
1013int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint32_t enable);
1014int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl);
1015int oce_get_link_status(POCE_SOFTC sc, struct link_status *link);
1016int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1017int oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1018int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1019 uint32_t reset_stats);
1020int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1021 uint32_t req_size, uint32_t reset_stats);
1022int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem);
1023int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size);
1024int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id);
1025int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1026 uint32_t if_id, uint32_t *pmac_id);
1027int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1028 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1029 uint64_t pattern);
1030
1031int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1032 uint8_t loopback_type, uint8_t enable);
1033
1034int oce_mbox_check_native_mode(POCE_SOFTC sc);
1035int oce_mbox_post(POCE_SOFTC sc,
1036 struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx);
1037int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1038 POCE_DMA_MEM pdma_mem, uint32_t num_bytes);
1039int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1040 uint32_t data_offset,POCE_DMA_MEM pdma_mem,
1041 uint32_t *written_data, uint32_t *additional_status);
1042
1043int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1044 uint32_t offset, uint32_t optype);
1045int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info);
1046int oce_mbox_create_rq(struct oce_rq *rq);
1047int oce_mbox_create_wq(struct oce_wq *wq);
1048int oce_mbox_create_eq(struct oce_eq *eq);
1049int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce,
1050 uint32_t is_eventable);
1051int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num);
1052void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1053 int num);
1054int oce_get_profile_config(POCE_SOFTC sc);
1055int oce_get_func_config(POCE_SOFTC sc);
1056void mbx_common_req_hdr_init(struct mbx_hdr *hdr,
1057 uint8_t dom,
1058 uint8_t port,
1059 uint8_t subsys,
1060 uint8_t opcode,
1061 uint32_t timeout, uint32_t pyld_len,
1062 uint8_t version);
1063
1064
1065uint16_t oce_mq_handler(void *arg);
1066
1067/************************************************************
1068 * Transmit functions
1069 ************************************************************/
1070uint16_t oce_wq_handler(void *arg);
1071void oce_start(struct ifnet *ifp);
1072void oce_tx_task(void *arg, int npending);
1073
1074/************************************************************
1075 * Receive functions
1076 ************************************************************/
1077int oce_alloc_rx_bufs(struct oce_rq *rq, int count);
1078uint16_t oce_rq_handler(void *arg);
1079
1080
1081/* Sysctl functions */
1082void oce_add_sysctls(POCE_SOFTC sc);
1083void oce_refresh_queue_stats(POCE_SOFTC sc);
1084int oce_refresh_nic_stats(POCE_SOFTC sc);
1085int oce_stats_init(POCE_SOFTC sc);
1086void oce_stats_free(POCE_SOFTC sc);
1087
1088/* Capabilities */
1089#define OCE_MODCAP_RSS 1
1090#define OCE_MAX_RSP_HANDLED 64
1091extern uint32_t oce_max_rsp_handled; /* max responses */
1092
1093#define OCE_MAC_LOOPBACK 0x0
1094#define OCE_PHY_LOOPBACK 0x1
1095#define OCE_ONE_PORT_EXT_LOOPBACK 0x2
1096#define OCE_NO_LOOPBACK 0xff
1097
1098#define atomic_inc_32(x) atomic_add_32(x, 1)
1099#define atomic_dec_32(x) atomic_subtract_32(x, 1)
1100
1101#define LE_64(x) htole64(x)
1102#define LE_32(x) htole32(x)
1103#define LE_16(x) htole16(x)
1104#define HOST_64(x) le64toh(x)
1105#define HOST_32(x) le32toh(x)
1106#define HOST_16(x) le16toh(x)
1107#define DW_SWAP(x, l)
1108#define IS_ALIGNED(x,a) ((x % a) == 0)
1109#define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32))
1110#define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff));
1111
1112#define IF_LRO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0)
1113#define IF_LSO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0)
1114#define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0)
1115
1116#define OCE_LOG2(x) (oce_highbit(x))
1117static inline uint32_t oce_highbit(uint32_t x)
1118{
1119 int i;
1120 int c;
1121 int b;
1122
1123 c = 0;
1124 b = 0;
1125
1126 for (i = 0; i < 32; i++) {
1127 if ((1 << i) & x) {
1128 c++;
1129 b = i;
1130 }
1131 }
1132
1133 if (c == 1)
1134 return b;
1135
1136 return 0;
1137}
1138
1139static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc)
1140{
1141 if (IS_BE(sc))
1142 return MPU_EP_SEMAPHORE_BE3;
1143 else if (IS_SH(sc))
1144 return MPU_EP_SEMAPHORE_SH;
1145 else
1146 return MPU_EP_SEMAPHORE_XE201;
1147}
1148
1149#define TRANSCEIVER_DATA_NUM_ELE 64
1150#define TRANSCEIVER_DATA_SIZE 256
1151#define TRANSCEIVER_A0_SIZE 128
1152#define TRANSCEIVER_A2_SIZE 128
1153#define PAGE_NUM_A0 0xa0
1154#define PAGE_NUM_A2 0xa2
1155#define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\
1156 || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE)))
1157
2 * Copyright (C) 2013 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
39
40/* $FreeBSD: head/sys/dev/oce/oce_if.h 252869 2013-07-06 08:30:45Z delphij $ */
41
42#include <sys/param.h>
43#include <sys/endian.h>
44#include <sys/module.h>
45#include <sys/kernel.h>
46#include <sys/bus.h>
47#include <sys/mbuf.h>
48#include <sys/rman.h>
49#include <sys/socket.h>
50#include <sys/sockio.h>
51#include <sys/sockopt.h>
52#include <sys/queue.h>
53#include <sys/taskqueue.h>
54#include <sys/lock.h>
55#include <sys/mutex.h>
56#include <sys/sysctl.h>
57#include <sys/random.h>
58#include <sys/firmware.h>
59#include <sys/systm.h>
60#include <sys/proc.h>
61
62#include <dev/pci/pcireg.h>
63#include <dev/pci/pcivar.h>
64
65#include <net/bpf.h>
66#include <net/ethernet.h>
67#include <net/if.h>
68#include <net/if_types.h>
69#include <net/if_media.h>
70#include <net/if_vlan_var.h>
71#include <net/if_dl.h>
72
73#include <netinet/in.h>
74#include <netinet/in_systm.h>
75#include <netinet/in_var.h>
76#include <netinet/if_ether.h>
77#include <netinet/ip.h>
78#include <netinet/ip6.h>
79#include <netinet6/in6_var.h>
80#include <netinet6/ip6_mroute.h>
81
82#include <netinet/udp.h>
83#include <netinet/tcp.h>
84#include <netinet/sctp.h>
85#include <netinet/tcp_lro.h>
86
87#include <machine/bus.h>
88
89#include "oce_hw.h"
90
91#define COMPONENT_REVISION "4.6.95.0"
92
93/* OCE devices supported by this driver */
94#define PCI_VENDOR_EMULEX 0x10df /* Emulex */
95#define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */
96#define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */
97#define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */
98#define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */
99#define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */
100#define PCI_PRODUCT_SH 0x0720 /* Skyhawk network adapter */
101
102#define IS_BE(sc) (((sc->flags & OCE_FLAGS_BE3) | \
103 (sc->flags & OCE_FLAGS_BE2))? 1:0)
104#define IS_BE3(sc) (sc->flags & OCE_FLAGS_BE3)
105#define IS_BE2(sc) (sc->flags & OCE_FLAGS_BE2)
106#define IS_XE201(sc) ((sc->flags & OCE_FLAGS_XE201) ? 1:0)
107#define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0)
108#define IS_SH(sc) ((sc->flags & OCE_FLAGS_SH) ? 1 : 0)
109
110#define is_be_mode_mc(sc) ((sc->function_mode & FNM_FLEX10_MODE) || \
111 (sc->function_mode & FNM_UMC_MODE) || \
112 (sc->function_mode & FNM_VNIC_MODE))
113#define OCE_FUNCTION_CAPS_SUPER_NIC 0x40
114#define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC)
115
116
117/* proportion Service Level Interface queues */
118#define OCE_MAX_UNITS 2
119#define OCE_MAX_PPORT OCE_MAX_UNITS
120#define OCE_MAX_VPORT OCE_MAX_UNITS
121
122extern int mp_ncpus; /* system's total active cpu cores */
123#define OCE_NCPUS mp_ncpus
124
125/* This should be powers of 2. Like 2,4,8 & 16 */
126#define OCE_MAX_RSS 8
127#define OCE_LEGACY_MODE_RSS 4 /* For BE3 Legacy mode*/
128#define is_rss_enabled(sc) ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc))
129
130#define OCE_MIN_RQ 1
131#define OCE_MIN_WQ 1
132
133#define OCE_MAX_RQ OCE_MAX_RSS + 1 /* one default queue */
134#define OCE_MAX_WQ 8
135
136#define OCE_MAX_EQ 32
137#define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */
138#define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */
139
140#define OCE_DEFAULT_WQ_EQD 16
141#define OCE_MAX_PACKET_Q 16
142#define OCE_RQ_BUF_SIZE 2048
143#define OCE_LSO_MAX_SIZE (64 * 1024)
144#define LONG_TIMEOUT 30
145#define OCE_MAX_JUMBO_FRAME_SIZE 9018
146#define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \
147 ETHER_VLAN_ENCAP_LEN - \
148 ETHER_HDR_LEN)
149
150#define OCE_MAX_TX_ELEMENTS 29
151#define OCE_MAX_TX_DESC 1024
152#define OCE_MAX_TX_SIZE 65535
153#define OCE_MAX_RX_SIZE 4096
154#define OCE_MAX_RQ_POSTS 255
155#define OCE_DEFAULT_PROMISCUOUS 0
156
157
158#define RSS_ENABLE_IPV4 0x1
159#define RSS_ENABLE_TCP_IPV4 0x2
160#define RSS_ENABLE_IPV6 0x4
161#define RSS_ENABLE_TCP_IPV6 0x8
162
163#define INDIRECTION_TABLE_ENTRIES 128
164
165/* flow control definitions */
166#define OCE_FC_NONE 0x00000000
167#define OCE_FC_TX 0x00000001
168#define OCE_FC_RX 0x00000002
169#define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX)
170
171
172/* Interface capabilities to give device when creating interface */
173#define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \
174 MBX_RX_IFACE_FLAGS_UNTAGGED | \
175 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \
176 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \
177 MBX_RX_IFACE_FLAGS_RSS | \
178 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
179
180/* Interface capabilities to enable by default (others set dynamically) */
181#define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \
182 MBX_RX_IFACE_FLAGS_UNTAGGED | \
183 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
184
185#define OCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP)
186#define OCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
187 IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \
188 IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU)
189#define OCE_IF_HWASSIST_NONE 0
190#define OCE_IF_CAPABILITIES_NONE 0
191
192
193#define ETH_ADDR_LEN 6
194#define MAX_VLANFILTER_SIZE 64
195#define MAX_VLANS 4096
196
197#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
198#define BSWAP_8(x) ((x) & 0xff)
199#define BSWAP_16(x) ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8))
200#define BSWAP_32(x) ((BSWAP_16(x) << 16) | \
201 BSWAP_16((x) >> 16))
202#define BSWAP_64(x) ((BSWAP_32(x) << 32) | \
203 BSWAP_32((x) >> 32))
204
205#define for_all_wq_queues(sc, wq, i) \
206 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i])
207#define for_all_rq_queues(sc, rq, i) \
208 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i])
209#define for_all_rss_queues(sc, rq, i) \
210 for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \
211 i++, rq = sc->rq[i + 1])
212#define for_all_evnt_queues(sc, eq, i) \
213 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i])
214#define for_all_cq_queues(sc, cq, i) \
215 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i])
216
217
218/* Flash specific */
219#define IOCTL_COOKIE "SERVERENGINES CORP"
220#define MAX_FLASH_COMP 32
221
222#define IMG_ISCSI 160
223#define IMG_REDBOOT 224
224#define IMG_BIOS 34
225#define IMG_PXEBIOS 32
226#define IMG_FCOEBIOS 33
227#define IMG_ISCSI_BAK 176
228#define IMG_FCOE 162
229#define IMG_FCOE_BAK 178
230#define IMG_NCSI 16
231#define IMG_PHY 192
232#define FLASHROM_OPER_FLASH 1
233#define FLASHROM_OPER_SAVE 2
234#define FLASHROM_OPER_REPORT 4
235#define FLASHROM_OPER_FLASH_PHY 9
236#define FLASHROM_OPER_SAVE_PHY 10
237#define TN_8022 13
238
239enum {
240 PHY_TYPE_CX4_10GB = 0,
241 PHY_TYPE_XFP_10GB,
242 PHY_TYPE_SFP_1GB,
243 PHY_TYPE_SFP_PLUS_10GB,
244 PHY_TYPE_KR_10GB,
245 PHY_TYPE_KX4_10GB,
246 PHY_TYPE_BASET_10GB,
247 PHY_TYPE_BASET_1GB,
248 PHY_TYPE_BASEX_1GB,
249 PHY_TYPE_SGMII,
250 PHY_TYPE_DISABLED = 255
251};
252
253/**
254 * @brief Define and hold all necessary info for a single interrupt
255 */
256#define OCE_MAX_MSI 32 /* Message Signaled Interrupts */
257#define OCE_MAX_MSIX 2048 /* PCI Express MSI Interrrupts */
258
259typedef struct oce_intr_info {
260 void *tag; /* cookie returned by bus_setup_intr */
261 struct resource *intr_res; /* PCI resource container */
262 int irq_rr; /* resource id for the interrupt */
263 struct oce_softc *sc; /* pointer to the parent soft c */
264 struct oce_eq *eq; /* pointer to the connected EQ */
265 struct taskqueue *tq; /* Associated task queue */
266 struct task task; /* task queue task */
267 char task_name[32]; /* task name */
268 int vector; /* interrupt vector number */
269} OCE_INTR_INFO, *POCE_INTR_INFO;
270
271
272/* Ring related */
273#define GET_Q_NEXT(_START, _STEP, _END) \
274 (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \
275 : (((_START) + (_STEP)) - (_END)))
276
277#define DBUF_PA(obj) ((obj)->addr)
278#define DBUF_VA(obj) ((obj)->ptr)
279#define DBUF_TAG(obj) ((obj)->tag)
280#define DBUF_MAP(obj) ((obj)->map)
281#define DBUF_SYNC(obj, flags) \
282 (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags))
283
284#define RING_NUM_PENDING(ring) ring->num_used
285#define RING_FULL(ring) (ring->num_used == ring->num_items)
286#define RING_EMPTY(ring) (ring->num_used == 0)
287#define RING_NUM_FREE(ring) \
288 (uint32_t)(ring->num_items - ring->num_used)
289#define RING_GET(ring, n) \
290 ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items)
291#define RING_PUT(ring, n) \
292 ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items)
293
294#define RING_GET_CONSUMER_ITEM_VA(ring, type) \
295 (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx)
296#define RING_GET_CONSUMER_ITEM_PA(ring, type) \
297 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx)
298#define RING_GET_PRODUCER_ITEM_VA(ring, type) \
299 (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx)
300#define RING_GET_PRODUCER_ITEM_PA(ring, type) \
301 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx)
302
303#define OCE_DMAPTR(o, c) ((c *)(o)->ptr)
304
305struct oce_packet_desc {
306 struct mbuf *mbuf;
307 bus_dmamap_t map;
308 int nsegs;
309 uint32_t wqe_idx;
310};
311
312typedef struct oce_dma_mem {
313 bus_dma_tag_t tag;
314 bus_dmamap_t map;
315 void *ptr;
316 bus_addr_t paddr;
317} OCE_DMA_MEM, *POCE_DMA_MEM;
318
319typedef struct oce_ring_buffer_s {
320 uint16_t cidx; /* Get ptr */
321 uint16_t pidx; /* Put Ptr */
322 size_t item_size;
323 size_t num_items;
324 uint32_t num_used;
325 OCE_DMA_MEM dma;
326} oce_ring_buffer_t;
327
328/* Stats */
329#define OCE_UNICAST_PACKET 0
330#define OCE_MULTICAST_PACKET 1
331#define OCE_BROADCAST_PACKET 2
332#define OCE_RSVD_PACKET 3
333
334struct oce_rx_stats {
335 /* Total Receive Stats*/
336 uint64_t t_rx_pkts;
337 uint64_t t_rx_bytes;
338 uint32_t t_rx_frags;
339 uint32_t t_rx_mcast_pkts;
340 uint32_t t_rx_ucast_pkts;
341 uint32_t t_rxcp_errs;
342};
343struct oce_tx_stats {
344 /*Total Transmit Stats */
345 uint64_t t_tx_pkts;
346 uint64_t t_tx_bytes;
347 uint32_t t_tx_reqs;
348 uint32_t t_tx_stops;
349 uint32_t t_tx_wrbs;
350 uint32_t t_tx_compl;
351 uint32_t t_ipv6_ext_hdr_tx_drop;
352};
353
354struct oce_be_stats {
355 uint8_t be_on_die_temperature;
356 uint32_t be_tx_events;
357 uint32_t eth_red_drops;
358 uint32_t rx_drops_no_pbuf;
359 uint32_t rx_drops_no_txpb;
360 uint32_t rx_drops_no_erx_descr;
361 uint32_t rx_drops_no_tpre_descr;
362 uint32_t rx_drops_too_many_frags;
363 uint32_t rx_drops_invalid_ring;
364 uint32_t forwarded_packets;
365 uint32_t rx_drops_mtu;
366 uint32_t rx_crc_errors;
367 uint32_t rx_alignment_symbol_errors;
368 uint32_t rx_pause_frames;
369 uint32_t rx_priority_pause_frames;
370 uint32_t rx_control_frames;
371 uint32_t rx_in_range_errors;
372 uint32_t rx_out_range_errors;
373 uint32_t rx_frame_too_long;
374 uint32_t rx_address_match_errors;
375 uint32_t rx_dropped_too_small;
376 uint32_t rx_dropped_too_short;
377 uint32_t rx_dropped_header_too_small;
378 uint32_t rx_dropped_tcp_length;
379 uint32_t rx_dropped_runt;
380 uint32_t rx_ip_checksum_errs;
381 uint32_t rx_tcp_checksum_errs;
382 uint32_t rx_udp_checksum_errs;
383 uint32_t rx_switched_unicast_packets;
384 uint32_t rx_switched_multicast_packets;
385 uint32_t rx_switched_broadcast_packets;
386 uint32_t tx_pauseframes;
387 uint32_t tx_priority_pauseframes;
388 uint32_t tx_controlframes;
389 uint32_t rxpp_fifo_overflow_drop;
390 uint32_t rx_input_fifo_overflow_drop;
391 uint32_t pmem_fifo_overflow_drop;
392 uint32_t jabber_events;
393};
394
395struct oce_xe201_stats {
396 uint64_t tx_pkts;
397 uint64_t tx_unicast_pkts;
398 uint64_t tx_multicast_pkts;
399 uint64_t tx_broadcast_pkts;
400 uint64_t tx_bytes;
401 uint64_t tx_unicast_bytes;
402 uint64_t tx_multicast_bytes;
403 uint64_t tx_broadcast_bytes;
404 uint64_t tx_discards;
405 uint64_t tx_errors;
406 uint64_t tx_pause_frames;
407 uint64_t tx_pause_on_frames;
408 uint64_t tx_pause_off_frames;
409 uint64_t tx_internal_mac_errors;
410 uint64_t tx_control_frames;
411 uint64_t tx_pkts_64_bytes;
412 uint64_t tx_pkts_65_to_127_bytes;
413 uint64_t tx_pkts_128_to_255_bytes;
414 uint64_t tx_pkts_256_to_511_bytes;
415 uint64_t tx_pkts_512_to_1023_bytes;
416 uint64_t tx_pkts_1024_to_1518_bytes;
417 uint64_t tx_pkts_1519_to_2047_bytes;
418 uint64_t tx_pkts_2048_to_4095_bytes;
419 uint64_t tx_pkts_4096_to_8191_bytes;
420 uint64_t tx_pkts_8192_to_9216_bytes;
421 uint64_t tx_lso_pkts;
422 uint64_t rx_pkts;
423 uint64_t rx_unicast_pkts;
424 uint64_t rx_multicast_pkts;
425 uint64_t rx_broadcast_pkts;
426 uint64_t rx_bytes;
427 uint64_t rx_unicast_bytes;
428 uint64_t rx_multicast_bytes;
429 uint64_t rx_broadcast_bytes;
430 uint32_t rx_unknown_protos;
431 uint64_t rx_discards;
432 uint64_t rx_errors;
433 uint64_t rx_crc_errors;
434 uint64_t rx_alignment_errors;
435 uint64_t rx_symbol_errors;
436 uint64_t rx_pause_frames;
437 uint64_t rx_pause_on_frames;
438 uint64_t rx_pause_off_frames;
439 uint64_t rx_frames_too_long;
440 uint64_t rx_internal_mac_errors;
441 uint32_t rx_undersize_pkts;
442 uint32_t rx_oversize_pkts;
443 uint32_t rx_fragment_pkts;
444 uint32_t rx_jabbers;
445 uint64_t rx_control_frames;
446 uint64_t rx_control_frames_unknown_opcode;
447 uint32_t rx_in_range_errors;
448 uint32_t rx_out_of_range_errors;
449 uint32_t rx_address_match_errors;
450 uint32_t rx_vlan_mismatch_errors;
451 uint32_t rx_dropped_too_small;
452 uint32_t rx_dropped_too_short;
453 uint32_t rx_dropped_header_too_small;
454 uint32_t rx_dropped_invalid_tcp_length;
455 uint32_t rx_dropped_runt;
456 uint32_t rx_ip_checksum_errors;
457 uint32_t rx_tcp_checksum_errors;
458 uint32_t rx_udp_checksum_errors;
459 uint32_t rx_non_rss_pkts;
460 uint64_t rx_ipv4_pkts;
461 uint64_t rx_ipv6_pkts;
462 uint64_t rx_ipv4_bytes;
463 uint64_t rx_ipv6_bytes;
464 uint64_t rx_nic_pkts;
465 uint64_t rx_tcp_pkts;
466 uint64_t rx_iscsi_pkts;
467 uint64_t rx_management_pkts;
468 uint64_t rx_switched_unicast_pkts;
469 uint64_t rx_switched_multicast_pkts;
470 uint64_t rx_switched_broadcast_pkts;
471 uint64_t num_forwards;
472 uint32_t rx_fifo_overflow;
473 uint32_t rx_input_fifo_overflow;
474 uint64_t rx_drops_too_many_frags;
475 uint32_t rx_drops_invalid_queue;
476 uint64_t rx_drops_mtu;
477 uint64_t rx_pkts_64_bytes;
478 uint64_t rx_pkts_65_to_127_bytes;
479 uint64_t rx_pkts_128_to_255_bytes;
480 uint64_t rx_pkts_256_to_511_bytes;
481 uint64_t rx_pkts_512_to_1023_bytes;
482 uint64_t rx_pkts_1024_to_1518_bytes;
483 uint64_t rx_pkts_1519_to_2047_bytes;
484 uint64_t rx_pkts_2048_to_4095_bytes;
485 uint64_t rx_pkts_4096_to_8191_bytes;
486 uint64_t rx_pkts_8192_to_9216_bytes;
487};
488
489struct oce_drv_stats {
490 struct oce_rx_stats rx;
491 struct oce_tx_stats tx;
492 union {
493 struct oce_be_stats be;
494 struct oce_xe201_stats xe201;
495 } u0;
496};
497
498#define INTR_RATE_HWM 15000
499#define INTR_RATE_LWM 10000
500
501#define OCE_MAX_EQD 128u
502#define OCE_MIN_EQD 50u
503
504struct oce_set_eqd {
505 uint32_t eq_id;
506 uint32_t phase;
507 uint32_t delay_multiplier;
508};
509
510struct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
511 boolean_t enable;
512 uint32_t min_eqd; /* in usecs */
513 uint32_t max_eqd; /* in usecs */
514 uint32_t cur_eqd; /* in usecs */
515 uint32_t et_eqd; /* configured value when aic is off */
516 uint64_t ticks;
517 uint64_t intr_prev;
518};
519
520#define MAX_LOCK_DESC_LEN 32
521struct oce_lock {
522 struct mtx mutex;
523 char name[MAX_LOCK_DESC_LEN+1];
524};
525#define OCE_LOCK struct oce_lock
526
527#define LOCK_CREATE(lock, desc) { \
528 strncpy((lock)->name, (desc), MAX_LOCK_DESC_LEN); \
529 (lock)->name[MAX_LOCK_DESC_LEN] = '\0'; \
530 mtx_init(&(lock)->mutex, (lock)->name, NULL, MTX_DEF); \
531}
532#define LOCK_DESTROY(lock) \
533 if (mtx_initialized(&(lock)->mutex))\
534 mtx_destroy(&(lock)->mutex)
535#define TRY_LOCK(lock) mtx_trylock(&(lock)->mutex)
536#define LOCK(lock) mtx_lock(&(lock)->mutex)
537#define LOCKED(lock) mtx_owned(&(lock)->mutex)
538#define UNLOCK(lock) mtx_unlock(&(lock)->mutex)
539
540#define DEFAULT_MQ_MBOX_TIMEOUT (5 * 1000 * 1000)
541#define MBX_READY_TIMEOUT (1 * 1000 * 1000)
542#define DEFAULT_DRAIN_TIME 200
543#define MBX_TIMEOUT_SEC 5
544#define STAT_TIMEOUT 2000000
545
546/* size of the packet descriptor array in a transmit queue */
547#define OCE_TX_RING_SIZE 2048
548#define OCE_RX_RING_SIZE 1024
549#define OCE_WQ_PACKET_ARRAY_SIZE (OCE_TX_RING_SIZE/2)
550#define OCE_RQ_PACKET_ARRAY_SIZE (OCE_RX_RING_SIZE)
551
552struct oce_dev;
553
554enum eq_len {
555 EQ_LEN_256 = 256,
556 EQ_LEN_512 = 512,
557 EQ_LEN_1024 = 1024,
558 EQ_LEN_2048 = 2048,
559 EQ_LEN_4096 = 4096
560};
561
562enum eqe_size {
563 EQE_SIZE_4 = 4,
564 EQE_SIZE_16 = 16
565};
566
567enum qtype {
568 QTYPE_EQ,
569 QTYPE_MQ,
570 QTYPE_WQ,
571 QTYPE_RQ,
572 QTYPE_CQ,
573 QTYPE_RSS
574};
575
576typedef enum qstate_e {
577 QDELETED = 0x0,
578 QCREATED = 0x1
579} qstate_t;
580
581struct eq_config {
582 enum eq_len q_len;
583 enum eqe_size item_size;
584 uint32_t q_vector_num;
585 uint8_t min_eqd;
586 uint8_t max_eqd;
587 uint8_t cur_eqd;
588 uint8_t pad;
589};
590
591struct oce_eq {
592 uint32_t eq_id;
593 void *parent;
594 void *cb_context;
595 oce_ring_buffer_t *ring;
596 uint32_t ref_count;
597 qstate_t qstate;
598 struct oce_cq *cq[OCE_MAX_CQ_EQ];
599 int cq_valid;
600 struct eq_config eq_cfg;
601 int vector;
602 uint64_t intr;
603};
604
605enum cq_len {
606 CQ_LEN_256 = 256,
607 CQ_LEN_512 = 512,
608 CQ_LEN_1024 = 1024
609};
610
611struct cq_config {
612 enum cq_len q_len;
613 uint32_t item_size;
614 boolean_t is_eventable;
615 boolean_t sol_eventable;
616 boolean_t nodelay;
617 uint16_t dma_coalescing;
618};
619
620typedef uint16_t(*cq_handler_t) (void *arg1);
621
622struct oce_cq {
623 uint32_t cq_id;
624 void *parent;
625 struct oce_eq *eq;
626 cq_handler_t cq_handler;
627 void *cb_arg;
628 oce_ring_buffer_t *ring;
629 qstate_t qstate;
630 struct cq_config cq_cfg;
631 uint32_t ref_count;
632};
633
634
635struct mq_config {
636 uint32_t eqd;
637 uint8_t q_len;
638 uint8_t pad[3];
639};
640
641
642struct oce_mq {
643 void *parent;
644 oce_ring_buffer_t *ring;
645 uint32_t mq_id;
646 struct oce_cq *cq;
647 struct oce_cq *async_cq;
648 uint32_t mq_free;
649 qstate_t qstate;
650 struct mq_config cfg;
651};
652
653struct oce_mbx_ctx {
654 struct oce_mbx *mbx;
655 void (*cb) (void *ctx);
656 void *cb_ctx;
657};
658
659struct wq_config {
660 uint8_t wq_type;
661 uint16_t buf_size;
662 uint8_t pad[1];
663 uint32_t q_len;
664 uint16_t pd_id;
665 uint16_t pci_fn_num;
666 uint32_t eqd; /* interrupt delay */
667 uint32_t nbufs;
668 uint32_t nhdl;
669};
670
671struct oce_tx_queue_stats {
672 uint64_t tx_pkts;
673 uint64_t tx_bytes;
674 uint32_t tx_reqs;
675 uint32_t tx_stops; /* number of times TX Q was stopped */
676 uint32_t tx_wrbs;
677 uint32_t tx_compl;
678 uint32_t tx_rate;
679 uint32_t ipv6_ext_hdr_tx_drop;
680};
681
682struct oce_wq {
683 OCE_LOCK tx_lock;
684 void *parent;
685 oce_ring_buffer_t *ring;
686 struct oce_cq *cq;
687 bus_dma_tag_t tag;
688 struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE];
689 uint32_t pkt_desc_tail;
690 uint32_t pkt_desc_head;
691 uint32_t wqm_used;
692 boolean_t resched;
693 uint32_t wq_free;
694 uint32_t tx_deferd;
695 uint32_t pkt_drops;
696 qstate_t qstate;
697 uint16_t wq_id;
698 struct wq_config cfg;
699 int queue_index;
700 struct oce_tx_queue_stats tx_stats;
701 struct buf_ring *br;
702 struct task txtask;
703 uint32_t db_offset;
704};
705
706struct rq_config {
707 uint32_t q_len;
708 uint32_t frag_size;
709 uint32_t mtu;
710 uint32_t if_id;
711 uint32_t is_rss_queue;
712 uint32_t eqd;
713 uint32_t nbufs;
714};
715
716struct oce_rx_queue_stats {
717 uint32_t rx_post_fail;
718 uint32_t rx_ucast_pkts;
719 uint32_t rx_compl;
720 uint64_t rx_bytes;
721 uint64_t rx_bytes_prev;
722 uint64_t rx_pkts;
723 uint32_t rx_rate;
724 uint32_t rx_mcast_pkts;
725 uint32_t rxcp_err;
726 uint32_t rx_frags;
727 uint32_t prev_rx_frags;
728 uint32_t rx_fps;
729};
730
731
732struct oce_rq {
733 struct rq_config cfg;
734 uint32_t rq_id;
735 int queue_index;
736 uint32_t rss_cpuid;
737 void *parent;
738 oce_ring_buffer_t *ring;
739 struct oce_cq *cq;
740 void *pad1;
741 bus_dma_tag_t tag;
742 struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE];
743 uint32_t packets_in;
744 uint32_t packets_out;
745 uint32_t pending;
746#ifdef notdef
747 struct mbuf *head;
748 struct mbuf *tail;
749 int fragsleft;
750#endif
751 qstate_t qstate;
752 OCE_LOCK rx_lock;
753 struct oce_rx_queue_stats rx_stats;
754 struct lro_ctrl lro;
755 int lro_pkts_queued;
756
757};
758
759struct link_status {
760 uint8_t physical_port;
761 uint8_t mac_duplex;
762 uint8_t mac_speed;
763 uint8_t mac_fault;
764 uint8_t mgmt_mac_duplex;
765 uint8_t mgmt_mac_speed;
766 uint16_t qos_link_speed;
767 uint32_t logical_link_status;
768};
769
770
771
772#define OCE_FLAGS_PCIX 0x00000001
773#define OCE_FLAGS_PCIE 0x00000002
774#define OCE_FLAGS_MSI_CAPABLE 0x00000004
775#define OCE_FLAGS_MSIX_CAPABLE 0x00000008
776#define OCE_FLAGS_USING_MSI 0x00000010
777#define OCE_FLAGS_USING_MSIX 0x00000020
778#define OCE_FLAGS_FUNCRESET_RQD 0x00000040
779#define OCE_FLAGS_VIRTUAL_PORT 0x00000080
780#define OCE_FLAGS_MBOX_ENDIAN_RQD 0x00000100
781#define OCE_FLAGS_BE3 0x00000200
782#define OCE_FLAGS_XE201 0x00000400
783#define OCE_FLAGS_BE2 0x00000800
784#define OCE_FLAGS_SH 0x00001000
785
786#define OCE_DEV_BE2_CFG_BAR 1
787#define OCE_DEV_CFG_BAR 0
788#define OCE_PCI_CSR_BAR 2
789#define OCE_PCI_DB_BAR 4
790
791typedef struct oce_softc {
792 device_t dev;
793 OCE_LOCK dev_lock;
794
795 uint32_t flags;
796
797 uint32_t pcie_link_speed;
798 uint32_t pcie_link_width;
799
800 uint8_t fn; /* PCI function number */
801
802 struct resource *devcfg_res;
803 bus_space_tag_t devcfg_btag;
804 bus_space_handle_t devcfg_bhandle;
805 void *devcfg_vhandle;
806
807 struct resource *csr_res;
808 bus_space_tag_t csr_btag;
809 bus_space_handle_t csr_bhandle;
810 void *csr_vhandle;
811
812 struct resource *db_res;
813 bus_space_tag_t db_btag;
814 bus_space_handle_t db_bhandle;
815 void *db_vhandle;
816
817 OCE_INTR_INFO intrs[OCE_MAX_EQ];
818 int intr_count;
819
820 struct ifnet *ifp;
821
822 struct ifmedia media;
823 uint8_t link_status;
824 uint8_t link_speed;
825 uint8_t duplex;
826 uint32_t qos_link_speed;
827 uint32_t speed;
828
829 char fw_version[32];
830 struct mac_address_format macaddr;
831
832 OCE_DMA_MEM bsmbx;
833 OCE_LOCK bmbx_lock;
834
835 uint32_t config_number;
836 uint32_t asic_revision;
837 uint32_t port_id;
838 uint32_t function_mode;
839 uint32_t function_caps;
840 uint32_t max_tx_rings;
841 uint32_t max_rx_rings;
842
843 struct oce_wq *wq[OCE_MAX_WQ]; /* TX work queues */
844 struct oce_rq *rq[OCE_MAX_RQ]; /* RX work queues */
845 struct oce_cq *cq[OCE_MAX_CQ]; /* Completion queues */
846 struct oce_eq *eq[OCE_MAX_EQ]; /* Event queues */
847 struct oce_mq *mq; /* Mailbox queue */
848
849 uint32_t neqs;
850 uint32_t ncqs;
851 uint32_t nrqs;
852 uint32_t nwqs;
853 uint32_t nrssqs;
854
855 uint32_t tx_ring_size;
856 uint32_t rx_ring_size;
857 uint32_t rq_frag_size;
858
859 uint32_t if_id; /* interface ID */
860 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */
861 uint32_t pmac_id; /* PMAC id */
862
863 uint32_t if_cap_flags;
864
865 uint32_t flow_control;
866 uint32_t promisc;
867
868 struct oce_aic_obj aic_obj[OCE_MAX_EQ];
869
870 /*Vlan Filtering related */
871 eventhandler_tag vlan_attach;
872 eventhandler_tag vlan_detach;
873 uint16_t vlans_added;
874 uint8_t vlan_tag[MAX_VLANS];
875 /*stats */
876 OCE_DMA_MEM stats_mem;
877 struct oce_drv_stats oce_stats_info;
878 struct callout timer;
879 int8_t be3_native;
880 uint16_t qnq_debug_event;
881 uint16_t qnqid;
882 uint16_t pvid;
883
884} OCE_SOFTC, *POCE_SOFTC;
885
886
887
888/**************************************************
889 * BUS memory read/write macros
890 * BE3: accesses three BAR spaces (CFG, CSR, DB)
891 * Lancer: accesses one BAR space (CFG)
892 **************************************************/
893#define OCE_READ_CSR_MPU(sc, space, o) \
894 ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \
895 (sc)->space##_bhandle,o)) \
896 : (bus_space_read_4((sc)->devcfg_btag, \
897 (sc)->devcfg_bhandle,o)))
898#define OCE_READ_REG32(sc, space, o) \
899 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \
900 (sc)->space##_bhandle,o)) \
901 : (bus_space_read_4((sc)->devcfg_btag, \
902 (sc)->devcfg_bhandle,o)))
903#define OCE_READ_REG16(sc, space, o) \
904 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \
905 (sc)->space##_bhandle,o)) \
906 : (bus_space_read_2((sc)->devcfg_btag, \
907 (sc)->devcfg_bhandle,o)))
908#define OCE_READ_REG8(sc, space, o) \
909 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \
910 (sc)->space##_bhandle,o)) \
911 : (bus_space_read_1((sc)->devcfg_btag, \
912 (sc)->devcfg_bhandle,o)))
913
914#define OCE_WRITE_CSR_MPU(sc, space, o, v) \
915 ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \
916 (sc)->space##_bhandle,o,v)) \
917 : (bus_space_write_4((sc)->devcfg_btag, \
918 (sc)->devcfg_bhandle,o,v)))
919#define OCE_WRITE_REG32(sc, space, o, v) \
920 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \
921 (sc)->space##_bhandle,o,v)) \
922 : (bus_space_write_4((sc)->devcfg_btag, \
923 (sc)->devcfg_bhandle,o,v)))
924#define OCE_WRITE_REG16(sc, space, o, v) \
925 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \
926 (sc)->space##_bhandle,o,v)) \
927 : (bus_space_write_2((sc)->devcfg_btag, \
928 (sc)->devcfg_bhandle,o,v)))
929#define OCE_WRITE_REG8(sc, space, o, v) \
930 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \
931 (sc)->space##_bhandle,o,v)) \
932 : (bus_space_write_1((sc)->devcfg_btag, \
933 (sc)->devcfg_bhandle,o,v)))
934
935
936/***********************************************************
937 * DMA memory functions
938 ***********************************************************/
939#define oce_dma_sync(d, f) bus_dmamap_sync((d)->tag, (d)->map, f)
940int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags);
941void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma);
942void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error);
943void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring);
944oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc,
945 uint32_t q_len, uint32_t num_entries);
946/************************************************************
947 * oce_hw_xxx functions
948 ************************************************************/
949int oce_clear_rx_buf(struct oce_rq *rq);
950int oce_hw_pci_alloc(POCE_SOFTC sc);
951int oce_hw_init(POCE_SOFTC sc);
952int oce_hw_start(POCE_SOFTC sc);
953int oce_create_nw_interface(POCE_SOFTC sc);
954int oce_pci_soft_reset(POCE_SOFTC sc);
955int oce_hw_update_multicast(POCE_SOFTC sc);
956void oce_delete_nw_interface(POCE_SOFTC sc);
957void oce_hw_shutdown(POCE_SOFTC sc);
958void oce_hw_intr_enable(POCE_SOFTC sc);
959void oce_hw_intr_disable(POCE_SOFTC sc);
960void oce_hw_pci_free(POCE_SOFTC sc);
961
962/***********************************************************
963 * oce_queue_xxx functions
964 ***********************************************************/
965int oce_queue_init_all(POCE_SOFTC sc);
966int oce_start_rq(struct oce_rq *rq);
967int oce_start_wq(struct oce_wq *wq);
968int oce_start_mq(struct oce_mq *mq);
969int oce_start_rx(POCE_SOFTC sc);
970void oce_arm_eq(POCE_SOFTC sc,
971 int16_t qid, int npopped, uint32_t rearm, uint32_t clearint);
972void oce_queue_release_all(POCE_SOFTC sc);
973void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm);
974void oce_drain_eq(struct oce_eq *eq);
975void oce_drain_mq_cq(void *arg);
976void oce_drain_rq_cq(struct oce_rq *rq);
977void oce_drain_wq_cq(struct oce_wq *wq);
978
979uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list);
980
981/***********************************************************
982 * cleanup functions
983 ***********************************************************/
984void oce_stop_rx(POCE_SOFTC sc);
985void oce_intr_free(POCE_SOFTC sc);
986void oce_free_posted_rxbuf(struct oce_rq *rq);
987#if defined(INET6) || defined(INET)
988void oce_free_lro(POCE_SOFTC sc);
989#endif
990
991
992/************************************************************
993 * Mailbox functions
994 ************************************************************/
995int oce_fw_clean(POCE_SOFTC sc);
996int oce_reset_fun(POCE_SOFTC sc);
997int oce_mbox_init(POCE_SOFTC sc);
998int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec);
999int oce_get_fw_version(POCE_SOFTC sc);
1000int oce_first_mcc_cmd(POCE_SOFTC sc);
1001
1002int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm,
1003 uint8_t type, struct mac_address_format *mac);
1004int oce_get_fw_config(POCE_SOFTC sc);
1005int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags,
1006 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id);
1007int oce_if_del(POCE_SOFTC sc, uint32_t if_id);
1008int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id,
1009 struct normal_vlan *vtag_arr, uint8_t vtag_cnt,
1010 uint32_t untagged, uint32_t enable_promisc);
1011int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control);
1012int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss);
1013int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint32_t enable);
1014int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl);
1015int oce_get_link_status(POCE_SOFTC sc, struct link_status *link);
1016int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1017int oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1018int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1019 uint32_t reset_stats);
1020int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1021 uint32_t req_size, uint32_t reset_stats);
1022int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem);
1023int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size);
1024int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id);
1025int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1026 uint32_t if_id, uint32_t *pmac_id);
1027int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1028 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1029 uint64_t pattern);
1030
1031int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1032 uint8_t loopback_type, uint8_t enable);
1033
1034int oce_mbox_check_native_mode(POCE_SOFTC sc);
1035int oce_mbox_post(POCE_SOFTC sc,
1036 struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx);
1037int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1038 POCE_DMA_MEM pdma_mem, uint32_t num_bytes);
1039int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1040 uint32_t data_offset,POCE_DMA_MEM pdma_mem,
1041 uint32_t *written_data, uint32_t *additional_status);
1042
1043int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1044 uint32_t offset, uint32_t optype);
1045int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info);
1046int oce_mbox_create_rq(struct oce_rq *rq);
1047int oce_mbox_create_wq(struct oce_wq *wq);
1048int oce_mbox_create_eq(struct oce_eq *eq);
1049int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce,
1050 uint32_t is_eventable);
1051int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num);
1052void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1053 int num);
1054int oce_get_profile_config(POCE_SOFTC sc);
1055int oce_get_func_config(POCE_SOFTC sc);
1056void mbx_common_req_hdr_init(struct mbx_hdr *hdr,
1057 uint8_t dom,
1058 uint8_t port,
1059 uint8_t subsys,
1060 uint8_t opcode,
1061 uint32_t timeout, uint32_t pyld_len,
1062 uint8_t version);
1063
1064
1065uint16_t oce_mq_handler(void *arg);
1066
1067/************************************************************
1068 * Transmit functions
1069 ************************************************************/
1070uint16_t oce_wq_handler(void *arg);
1071void oce_start(struct ifnet *ifp);
1072void oce_tx_task(void *arg, int npending);
1073
1074/************************************************************
1075 * Receive functions
1076 ************************************************************/
1077int oce_alloc_rx_bufs(struct oce_rq *rq, int count);
1078uint16_t oce_rq_handler(void *arg);
1079
1080
1081/* Sysctl functions */
1082void oce_add_sysctls(POCE_SOFTC sc);
1083void oce_refresh_queue_stats(POCE_SOFTC sc);
1084int oce_refresh_nic_stats(POCE_SOFTC sc);
1085int oce_stats_init(POCE_SOFTC sc);
1086void oce_stats_free(POCE_SOFTC sc);
1087
1088/* Capabilities */
1089#define OCE_MODCAP_RSS 1
1090#define OCE_MAX_RSP_HANDLED 64
1091extern uint32_t oce_max_rsp_handled; /* max responses */
1092
1093#define OCE_MAC_LOOPBACK 0x0
1094#define OCE_PHY_LOOPBACK 0x1
1095#define OCE_ONE_PORT_EXT_LOOPBACK 0x2
1096#define OCE_NO_LOOPBACK 0xff
1097
1098#define atomic_inc_32(x) atomic_add_32(x, 1)
1099#define atomic_dec_32(x) atomic_subtract_32(x, 1)
1100
1101#define LE_64(x) htole64(x)
1102#define LE_32(x) htole32(x)
1103#define LE_16(x) htole16(x)
1104#define HOST_64(x) le64toh(x)
1105#define HOST_32(x) le32toh(x)
1106#define HOST_16(x) le16toh(x)
1107#define DW_SWAP(x, l)
1108#define IS_ALIGNED(x,a) ((x % a) == 0)
1109#define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32))
1110#define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff));
1111
1112#define IF_LRO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0)
1113#define IF_LSO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0)
1114#define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0)
1115
1116#define OCE_LOG2(x) (oce_highbit(x))
1117static inline uint32_t oce_highbit(uint32_t x)
1118{
1119 int i;
1120 int c;
1121 int b;
1122
1123 c = 0;
1124 b = 0;
1125
1126 for (i = 0; i < 32; i++) {
1127 if ((1 << i) & x) {
1128 c++;
1129 b = i;
1130 }
1131 }
1132
1133 if (c == 1)
1134 return b;
1135
1136 return 0;
1137}
1138
1139static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc)
1140{
1141 if (IS_BE(sc))
1142 return MPU_EP_SEMAPHORE_BE3;
1143 else if (IS_SH(sc))
1144 return MPU_EP_SEMAPHORE_SH;
1145 else
1146 return MPU_EP_SEMAPHORE_XE201;
1147}
1148
1149#define TRANSCEIVER_DATA_NUM_ELE 64
1150#define TRANSCEIVER_DATA_SIZE 256
1151#define TRANSCEIVER_A0_SIZE 128
1152#define TRANSCEIVER_A2_SIZE 128
1153#define PAGE_NUM_A0 0xa0
1154#define PAGE_NUM_A2 0xa2
1155#define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\
1156 || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE)))
1157