38a39
> /* $FreeBSD: head/sys/dev/oce/oce_if.c 257007 2013-10-23 18:58:38Z delphij $ */
40,41d40
< /* $FreeBSD: head/sys/dev/oce/oce_if.c 252869 2013-07-06 08:30:45Z delphij $ */
<
46a46,80
> /* UE Status Low CSR */
> static char *ue_status_low_desc[] = {
> "CEV",
> "CTX",
> "DBUF",
> "ERX",
> "Host",
> "MPU",
> "NDMA",
> "PTC ",
> "RDMA ",
> "RXF ",
> "RXIPS ",
> "RXULP0 ",
> "RXULP1 ",
> "RXULP2 ",
> "TIM ",
> "TPOST ",
> "TPRE ",
> "TXIPS ",
> "TXULP0 ",
> "TXULP1 ",
> "UC ",
> "WDMA ",
> "TXULP2 ",
> "HOST1 ",
> "P0_OB_LINK ",
> "P1_OB_LINK ",
> "HOST_GPIO ",
> "MBOX ",
> "AXGMAC0",
> "AXGMAC1",
> "JTAG",
> "MPU_INTPEND"
> };
47a82,118
> /* UE Status High CSR */
> static char *ue_status_hi_desc[] = {
> "LPCMEMHOST",
> "MGMT_MAC",
> "PCS0ONLINE",
> "MPU_IRAM",
> "PCS1ONLINE",
> "PCTL0",
> "PCTL1",
> "PMEM",
> "RR",
> "TXPB",
> "RXPP",
> "XAUI",
> "TXP",
> "ARM",
> "IPC",
> "HOST2",
> "HOST3",
> "HOST4",
> "HOST5",
> "HOST6",
> "HOST7",
> "HOST8",
> "HOST9",
> "NETC",
> "Unknown",
> "Unknown",
> "Unknown",
> "Unknown",
> "Unknown",
> "Unknown",
> "Unknown",
> "Unknown"
> };
>
>
391,392c462,463
< sc->promisc = TRUE;
< oce_rxf_set_promiscuous(sc, sc->promisc);
---
> if (!oce_rxf_set_promiscuous(sc, (1 | (1 << 1))))
> sc->promisc = TRUE;
394,395c465,466
< sc->promisc = FALSE;
< oce_rxf_set_promiscuous(sc, sc->promisc);
---
> if (!oce_rxf_set_promiscuous(sc, 0))
> sc->promisc = FALSE;
864a936
>
868a941
>
1158a1232,1243
> #if __FreeBSD_version >= 1000000
> static __inline void
> drbr_stats_update(struct ifnet *ifp, int len, int mflags)
> {
> #ifndef NO_SLOW_STATS
> ifp->if_obytes += len;
> if (mflags & M_MCAST)
> ifp->if_omcasts++;
> #endif
> }
> #endif
>
1177c1262
< if (m != NULL) {
---
> if (m != NULL) {
1648a1734,1737
> #if __FreeBSD_version >= 1000000
> sc->ifp->if_hw_tsomax = OCE_MAX_TSO_SIZE;
> #endif
>
1667c1756,1757
< oce_vid_config(sc);
---
> if (sc->vlans_added <= (sc->max_vlans + 1))
> oce_vid_config(sc);
1868a1959,2021
> static void oce_detect_hw_error(POCE_SOFTC sc)
> {
>
> uint32_t ue_low = 0, ue_high = 0, ue_low_mask = 0, ue_high_mask = 0;
> uint32_t sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
> uint32_t i;
>
> if (sc->hw_error)
> return;
>
> if (IS_XE201(sc)) {
> sliport_status = OCE_READ_REG32(sc, db, SLIPORT_STATUS_OFFSET);
> if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
> sliport_err1 = OCE_READ_REG32(sc, db, SLIPORT_ERROR1_OFFSET);
> sliport_err2 = OCE_READ_REG32(sc, db, SLIPORT_ERROR2_OFFSET);
> }
> } else {
> ue_low = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_LOW);
> ue_high = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_HIGH);
> ue_low_mask = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_LOW_MASK);
> ue_high_mask = OCE_READ_REG32(sc, devcfg, PCICFG_UE_STATUS_HI_MASK);
>
> ue_low = (ue_low & ~ue_low_mask);
> ue_high = (ue_high & ~ue_high_mask);
> }
>
> /* On certain platforms BE hardware can indicate spurious UEs.
> * Allow the h/w to stop working completely in case of a real UE.
> * Hence not setting the hw_error for UE detection.
> */
> if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
> sc->hw_error = TRUE;
> device_printf(sc->dev, "Error detected in the card\n");
> }
>
> if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
> device_printf(sc->dev,
> "ERR: sliport status 0x%x\n", sliport_status);
> device_printf(sc->dev,
> "ERR: sliport error1 0x%x\n", sliport_err1);
> device_printf(sc->dev,
> "ERR: sliport error2 0x%x\n", sliport_err2);
> }
>
> if (ue_low) {
> for (i = 0; ue_low; ue_low >>= 1, i++) {
> if (ue_low & 1)
> device_printf(sc->dev, "UE: %s bit set\n",
> ue_status_low_desc[i]);
> }
> }
>
> if (ue_high) {
> for (i = 0; ue_high; ue_high >>= 1, i++) {
> if (ue_high & 1)
> device_printf(sc->dev, "UE: %s bit set\n",
> ue_status_hi_desc[i]);
> }
> }
>
> }
>
>
1874a2028
> oce_detect_hw_error(sc);
1893c2047
< */
---
> */
2082a2237,2239
> } else {
> sc->nrqs = MIN(OCE_NCPUS, sc->nrssqs) + 1;
> sc->nwqs = MIN(OCE_NCPUS, sc->nrssqs);