| oce_hw.h (252869) | oce_hw.h (257007) |
|---|---|
| 1/*- 2 * Copyright (C) 2013 Emulex 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, --- 22 unchanged lines hidden (view full) --- 31 * Contact Information: 32 * freebsd-drivers@emulex.com 33 * 34 * Emulex 35 * 3333 Susan Street 36 * Costa Mesa, CA 92626 37 */ 38 | 1/*- 2 * Copyright (C) 2013 Emulex 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, --- 22 unchanged lines hidden (view full) --- 31 * Contact Information: 32 * freebsd-drivers@emulex.com 33 * 34 * Emulex 35 * 3333 Susan Street 36 * Costa Mesa, CA 92626 37 */ 38 |
| 39/* $FreeBSD: head/sys/dev/oce/oce_hw.h 252869 2013-07-06 08:30:45Z delphij $ */ | 39/* $FreeBSD: head/sys/dev/oce/oce_hw.h 257007 2013-10-23 18:58:38Z delphij $ */ |
| 40 41#include <sys/types.h> 42 43#undef _BIG_ENDIAN /* TODO */ 44#pragma pack(1) 45 46#define OC_CNA_GEN2 0x2 47#define OC_CNA_GEN3 0x3 --- 6 unchanged lines hidden (view full) --- 54#define PCICFG_SOFT_RESET 0x5c 55#define PCICFG_UE_STATUS_HI_MASK 0xac 56#define PCICFG_UE_STATUS_LO_MASK 0xa8 57#define PCICFG_ONLINE0 0xb0 58#define PCICFG_ONLINE1 0xb4 59#define INTR_EN 0x20000000 60#define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */ 61 | 40 41#include <sys/types.h> 42 43#undef _BIG_ENDIAN /* TODO */ 44#pragma pack(1) 45 46#define OC_CNA_GEN2 0x2 47#define OC_CNA_GEN3 0x3 --- 6 unchanged lines hidden (view full) --- 54#define PCICFG_SOFT_RESET 0x5c 55#define PCICFG_UE_STATUS_HI_MASK 0xac 56#define PCICFG_UE_STATUS_LO_MASK 0xa8 57#define PCICFG_ONLINE0 0xb0 58#define PCICFG_ONLINE1 0xb4 59#define INTR_EN 0x20000000 60#define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */ 61 |
| 62 63/********* UE Status and Mask Registers ***/ 64#define PCICFG_UE_STATUS_LOW 0xA0 65#define PCICFG_UE_STATUS_HIGH 0xA4 66#define PCICFG_UE_STATUS_LOW_MASK 0xA8 67 68/* Lancer SLIPORT registers */ 69#define SLIPORT_STATUS_OFFSET 0x404 70#define SLIPORT_CONTROL_OFFSET 0x408 71#define SLIPORT_ERROR1_OFFSET 0x40C 72#define SLIPORT_ERROR2_OFFSET 0x410 73#define PHYSDEV_CONTROL_OFFSET 0x414 74 75#define SLIPORT_STATUS_ERR_MASK 0x80000000 76#define SLIPORT_STATUS_DIP_MASK 0x02000000 77#define SLIPORT_STATUS_RN_MASK 0x01000000 78#define SLIPORT_STATUS_RDY_MASK 0x00800000 79#define SLI_PORT_CONTROL_IP_MASK 0x08000000 80#define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002 81#define PHYSDEV_CONTROL_DD_MASK 0x00000004 82#define PHYSDEV_CONTROL_INP_MASK 0x40000000 83 84#define SLIPORT_ERROR_NO_RESOURCE1 0x2 85#define SLIPORT_ERROR_NO_RESOURCE2 0x9 |
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| 62/* CSR register offsets */ 63#define MPU_EP_CONTROL 0 64#define MPU_EP_SEMAPHORE_BE3 0xac 65#define MPU_EP_SEMAPHORE_XE201 0x400 66#define MPU_EP_SEMAPHORE_SH 0x94 67#define PCICFG_INTR_CTRL 0xfc 68#define HOSTINTR_MASK (1 << 29) 69#define HOSTINTR_PFUNC_SHIFT 26 --- 2004 unchanged lines hidden (view full) --- 2074struct flash_file_hdr { 2075 uint8_t sign[52]; 2076 uint8_t ufi_version[4]; 2077 uint32_t file_len; 2078 uint32_t cksum; 2079 uint32_t antidote; 2080 uint32_t num_imgs; 2081 uint8_t build[24]; | 86/* CSR register offsets */ 87#define MPU_EP_CONTROL 0 88#define MPU_EP_SEMAPHORE_BE3 0xac 89#define MPU_EP_SEMAPHORE_XE201 0x400 90#define MPU_EP_SEMAPHORE_SH 0x94 91#define PCICFG_INTR_CTRL 0xfc 92#define HOSTINTR_MASK (1 << 29) 93#define HOSTINTR_PFUNC_SHIFT 26 --- 2004 unchanged lines hidden (view full) --- 2098struct flash_file_hdr { 2099 uint8_t sign[52]; 2100 uint8_t ufi_version[4]; 2101 uint32_t file_len; 2102 uint32_t cksum; 2103 uint32_t antidote; 2104 uint32_t num_imgs; 2105 uint8_t build[24]; |
| 2082 uint8_t rsvd[32]; | 2106 uint8_t asic_type_rev; 2107 uint8_t rsvd[31]; |
| 2083}; 2084 2085struct image_hdr { 2086 uint32_t imageid; 2087 uint32_t imageoffset; 2088 uint32_t imagelength; 2089 uint32_t image_checksum; 2090 uint8_t image_version[32]; --- 1585 unchanged lines hidden (view full) --- 3676enum OCE_QUEUE_RX_STATS { 3677 QUEUE_RX_PKTS = 0, 3678 QUEUE_RX_BYTES = 2, 3679 QUEUE_RX_ERRORS = 4, 3680 QUEUE_RX_DROPS = 6, 3681 QUEUE_RX_BUFFER_ERRORS = 8, 3682 QUEUE_RX_N_WORDS = 10 3683}; | 2108}; 2109 2110struct image_hdr { 2111 uint32_t imageid; 2112 uint32_t imageoffset; 2113 uint32_t imagelength; 2114 uint32_t image_checksum; 2115 uint8_t image_version[32]; --- 1585 unchanged lines hidden (view full) --- 3701enum OCE_QUEUE_RX_STATS { 3702 QUEUE_RX_PKTS = 0, 3703 QUEUE_RX_BYTES = 2, 3704 QUEUE_RX_ERRORS = 4, 3705 QUEUE_RX_DROPS = 6, 3706 QUEUE_RX_BUFFER_ERRORS = 8, 3707 QUEUE_RX_N_WORDS = 10 3708}; |
| 3684 | |