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oce_hw.h (231437) oce_hw.h (231879)
1/*-
2 * Copyright (C) 2012 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,

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31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
1/*-
2 * Copyright (C) 2012 Emulex
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,

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31 * Contact Information:
32 * freebsd-drivers@emulex.com
33 *
34 * Emulex
35 * 3333 Susan Street
36 * Costa Mesa, CA 92626
37 */
38
39/* $FreeBSD: head/sys/dev/oce/oce_hw.h 231437 2012-02-10 21:03:04Z luigi $ */
39/* $FreeBSD: head/sys/dev/oce/oce_hw.h 231879 2012-02-17 13:55:17Z luigi $ */
40
41#include <sys/types.h>
42
43#undef _BIG_ENDIAN /* TODO */
44#pragma pack(1)
45
46#define OC_CNA_GEN2 0x2
47#define OC_CNA_GEN3 0x3

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149#define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */
150#define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */
151
152#define MBX_DB_READY_BIT 0x1
153#define MBX_DB_HI_BIT 0x2
154#define ASYNC_EVENT_CODE_LINK_STATE 0x1
155#define ASYNC_EVENT_LINK_UP 0x1
156#define ASYNC_EVENT_LINK_DOWN 0x0
40
41#include <sys/types.h>
42
43#undef _BIG_ENDIAN /* TODO */
44#pragma pack(1)
45
46#define OC_CNA_GEN2 0x2
47#define OC_CNA_GEN3 0x3

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149#define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */
150#define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */
151
152#define MBX_DB_READY_BIT 0x1
153#define MBX_DB_HI_BIT 0x2
154#define ASYNC_EVENT_CODE_LINK_STATE 0x1
155#define ASYNC_EVENT_LINK_UP 0x1
156#define ASYNC_EVENT_LINK_DOWN 0x0
157#define ASYNC_EVENT_GRP5 0x5
158#define ASYNC_EVENT_PVID_STATE 0x3
159#define VLAN_VID_MASK 0x0FFF
157
158/* port link_status */
159#define ASYNC_EVENT_LOGICAL 0x02
160
161/* Logical Link Status */
162#define NTWK_LOGICAL_LINK_DOWN 0
163#define NTWK_LOGICAL_LINK_UP 1
164

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605 /* dw1 dw2 */
606 uint32_t mq_tag[2];
607 /* dw3 */
608 uint32_t valid:1;
609 uint32_t async_event:1;
610 uint32_t hpi_buffer_cmpl:1;
611 uint32_t completed:1;
612 uint32_t consumed:1;
160
161/* port link_status */
162#define ASYNC_EVENT_LOGICAL 0x02
163
164/* Logical Link Status */
165#define NTWK_LOGICAL_LINK_DOWN 0
166#define NTWK_LOGICAL_LINK_UP 1
167

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608 /* dw1 dw2 */
609 uint32_t mq_tag[2];
610 /* dw3 */
611 uint32_t valid:1;
612 uint32_t async_event:1;
613 uint32_t hpi_buffer_cmpl:1;
614 uint32_t completed:1;
615 uint32_t consumed:1;
613 uint32_t rsvd0:27;
616 uint32_t rsvd0:3;
617 uint32_t async_type:8;
618 uint32_t event_type:8;
619 uint32_t rsvd1:8;
614#else
615 /* dw0 */
616 uint32_t completion_status:16;
617 uint32_t extended_status:16;
618 /* dw1 dw2 */
619 uint32_t mq_tag[2];
620 /* dw3 */
620#else
621 /* dw0 */
622 uint32_t completion_status:16;
623 uint32_t extended_status:16;
624 /* dw1 dw2 */
625 uint32_t mq_tag[2];
626 /* dw3 */
621 uint32_t rsvd0:27;
627 uint32_t rsvd1:8;
628 uint32_t event_type:8;
629 uint32_t async_type:8;
630 uint32_t rsvd0:3;
622 uint32_t consumed:1;
623 uint32_t completed:1;
624 uint32_t hpi_buffer_cmpl:1;
625 uint32_t async_event:1;
626 uint32_t valid:1;
627#endif
628 } s;
629 uint32_t dw[4];

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682 uint32_t async_event:1;
683 uint32_t valid:1;
684#endif
685 } s;
686 uint32_t dw[4];
687 } u0;
688};
689
631 uint32_t consumed:1;
632 uint32_t completed:1;
633 uint32_t hpi_buffer_cmpl:1;
634 uint32_t async_event:1;
635 uint32_t valid:1;
636#endif
637 } s;
638 uint32_t dw[4];

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691 uint32_t async_event:1;
692 uint32_t valid:1;
693#endif
694 } s;
695 uint32_t dw[4];
696 } u0;
697};
698
699
700/* PVID aync event */
701struct oce_async_event_grp5_pvid_state {
702 uint8_t enabled;
703 uint8_t rsvd0;
704 uint16_t tag;
705 uint32_t event_tag;
706 uint32_t rsvd1;
707 uint32_t code;
708};
709
710typedef union oce_mq_ext_ctx_u {
711 uint32_t dw[6];
712 struct {
713 #ifdef _BIG_ENDIAN
714 /* dw0 */
715 uint32_t dw4rsvd1:16;
716 uint32_t num_pages:16;
717 /* dw1 */
718 uint32_t async_evt_bitmap;
719 /* dw2 */
720 uint32_t cq_id:10;
721 uint32_t dw5rsvd2:2;
722 uint32_t ring_size:4;
723 uint32_t dw5rsvd1:16;
724 /* dw3 */
725 uint32_t valid:1;
726 uint32_t dw6rsvd1:31;
727 /* dw4 */
728 uint32_t dw7rsvd1:21;
729 uint32_t async_cq_id:10;
730 uint32_t async_cq_valid:1;
731 #else
732 /* dw0 */
733 uint32_t num_pages:16;
734 uint32_t dw4rsvd1:16;
735 /* dw1 */
736 uint32_t async_evt_bitmap;
737 /* dw2 */
738 uint32_t dw5rsvd1:16;
739 uint32_t ring_size:4;
740 uint32_t dw5rsvd2:2;
741 uint32_t cq_id:10;
742 /* dw3 */
743 uint32_t dw6rsvd1:31;
744 uint32_t valid:1;
745 /* dw4 */
746 uint32_t async_cq_valid:1;
747 uint32_t async_cq_id:10;
748 uint32_t dw7rsvd1:21;
749 #endif
750 /* dw5 */
751 uint32_t dw8rsvd1;
752 } v0;
753} oce_mq_ext_ctx_t;
754
755
690/* MQ mailbox structure */
691struct oce_bmbx {
692 struct oce_mbx mbx;
693 struct oce_mq_cqe cqe;
694};
695
696/* ---[ MBXs start here ]---------------------------------------------- */
697/* MBXs sub system codes */

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1337
1338 struct {
1339 uint32_t mq_id:16;
1340 uint32_t rsvd0:16;
1341 } rsp;
1342 } params;
1343};
1344
756/* MQ mailbox structure */
757struct oce_bmbx {
758 struct oce_mbx mbx;
759 struct oce_mq_cqe cqe;
760};
761
762/* ---[ MBXs start here ]---------------------------------------------- */
763/* MBXs sub system codes */

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1403
1404 struct {
1405 uint32_t mq_id:16;
1406 uint32_t rsvd0:16;
1407 } rsp;
1408 } params;
1409};
1410
1411struct mbx_create_common_mq_ex {
1412 struct mbx_hdr hdr;
1413 union {
1414 struct {
1415 oce_mq_ext_ctx_t context;
1416 struct phys_addr pages[8];
1417 } req;
1418
1419 struct {
1420 uint32_t mq_id:16;
1421 uint32_t rsvd0:16;
1422 } rsp;
1423 } params;
1424};
1425
1426
1427
1345/* [53] OPCODE_COMMON_DESTROY_MQ */
1346struct mbx_destroy_common_mq {
1347 struct mbx_hdr hdr;
1348 union {
1349 struct {
1350#ifdef _BIG_ENDIAN
1351 uint16_t rsvd0;
1352 uint16_t id;

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1579 FNM_FLEX10_MODE = 0x400, /* QinQ, FLEX-10 or VNIC */
1580 FNM_NCSI_MODE = 0x800, /* NCSI supported */
1581 FNM_IPV6_MODE = 0x1000, /* IPV6 stack enabled */
1582 FNM_BE2_COMPAT_MODE = 0x2000, /* BE2 compatibility (BE3 disable)*/
1583 FNM_INVALID_MODE = 0x8000, /* Invalid */
1584 FNM_BE3_COMPAT_MODE = 0x10000, /* BE3 features */
1585 FNM_VNIC_MODE = 0x20000, /* Set when IBM vNIC mode is set */
1586 FNM_VNTAG_MODE = 0x40000, /* Set when VNTAG mode is set */
1428/* [53] OPCODE_COMMON_DESTROY_MQ */
1429struct mbx_destroy_common_mq {
1430 struct mbx_hdr hdr;
1431 union {
1432 struct {
1433#ifdef _BIG_ENDIAN
1434 uint16_t rsvd0;
1435 uint16_t id;

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1662 FNM_FLEX10_MODE = 0x400, /* QinQ, FLEX-10 or VNIC */
1663 FNM_NCSI_MODE = 0x800, /* NCSI supported */
1664 FNM_IPV6_MODE = 0x1000, /* IPV6 stack enabled */
1665 FNM_BE2_COMPAT_MODE = 0x2000, /* BE2 compatibility (BE3 disable)*/
1666 FNM_INVALID_MODE = 0x8000, /* Invalid */
1667 FNM_BE3_COMPAT_MODE = 0x10000, /* BE3 features */
1668 FNM_VNIC_MODE = 0x20000, /* Set when IBM vNIC mode is set */
1669 FNM_VNTAG_MODE = 0x40000, /* Set when VNTAG mode is set */
1587 FNM_UMC_MODE = 0x80000, /* Set when UMC mode is set */
1670 FNM_UMC_MODE = 0x1000000, /* Set when UMC mode is set */
1588 FNM_UMC_DEF_EN = 0x100000, /* Set when UMC Default is set */
1589 FNM_ONE_GB_EN = 0x200000, /* Set when 1GB Default is set */
1590 FNM_VNIC_DEF_VALID = 0x400000, /* Set when VNIC_DEF_EN is valid */
1591 FNM_VNIC_DEF_EN = 0x800000 /* Set when VNIC Default enabled */
1592};
1593
1594
1595struct mbx_common_config_vlan {

--- 1786 unchanged lines hidden --- 		1671 FNM_UMC_DEF_EN = 0x100000, /* Set when UMC Default is set */
1672 FNM_ONE_GB_EN = 0x200000, /* Set when 1GB Default is set */
1673 FNM_VNIC_DEF_VALID = 0x400000, /* Set when VNIC_DEF_EN is valid */
1674 FNM_VNIC_DEF_EN = 0x800000 /* Set when VNIC Default enabled */
1675};
1676
1677
1678struct mbx_common_config_vlan {

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