| oce_hw.c (231603) | oce_hw.c (231879) |
|---|---|
| 1/*- 2 * Copyright (C) 2012 Emulex 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, --- 22 unchanged lines hidden (view full) --- 31 * Contact Information: 32 * freebsd-drivers@emulex.com 33 * 34 * Emulex 35 * 3333 Susan Street 36 * Costa Mesa, CA 92626 37 */ 38 | 1/*- 2 * Copyright (C) 2012 Emulex 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, --- 22 unchanged lines hidden (view full) --- 31 * Contact Information: 32 * freebsd-drivers@emulex.com 33 * 34 * Emulex 35 * 3333 Susan Street 36 * Costa Mesa, CA 92626 37 */ 38 |
| 39/* $FreeBSD: head/sys/dev/oce/oce_hw.c 231603 2012-02-13 19:35:35Z jhb $ */ | 39/* $FreeBSD: head/sys/dev/oce/oce_hw.c 231879 2012-02-17 13:55:17Z luigi $ */ |
| 40 41#include "oce_if.h" 42 43static int oce_POST(POCE_SOFTC sc); 44 45/** 46 * @brief Function to post status 47 * @param sc software handle to the device --- 287 unchanged lines hidden (view full) --- 335 */ 336void 337oce_hw_shutdown(POCE_SOFTC sc) 338{ 339 340 oce_stats_free(sc); 341 /* disable hardware interrupts */ 342 oce_hw_intr_disable(sc); | 40 41#include "oce_if.h" 42 43static int oce_POST(POCE_SOFTC sc); 44 45/** 46 * @brief Function to post status 47 * @param sc software handle to the device --- 287 unchanged lines hidden (view full) --- 335 */ 336void 337oce_hw_shutdown(POCE_SOFTC sc) 338{ 339 340 oce_stats_free(sc); 341 /* disable hardware interrupts */ 342 oce_hw_intr_disable(sc); |
| 343#if defined(INET6) || defined(INET) |
|
| 343 /* Free LRO resources */ 344 oce_free_lro(sc); | 344 /* Free LRO resources */ 345 oce_free_lro(sc); |
| 346#endif |
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| 345 /* Release queue*/ 346 oce_queue_release_all(sc); 347 /*Delete Network Interface*/ 348 oce_delete_nw_interface(sc); 349 /* After fw clean we dont send any cmds to fw.*/ 350 oce_fw_clean(sc); 351 /* release intr resources */ 352 oce_intr_free(sc); --- 136 unchanged lines hidden (view full) --- 489 sc->link_speed = link.mac_speed; 490 else 491 sc->link_speed = 0; 492 493 sc->qos_link_speed = (uint32_t )link.qos_link_speed * 10; 494 495 rc = oce_start_mq(sc->mq); 496 | 347 /* Release queue*/ 348 oce_queue_release_all(sc); 349 /*Delete Network Interface*/ 350 oce_delete_nw_interface(sc); 351 /* After fw clean we dont send any cmds to fw.*/ 352 oce_fw_clean(sc); 353 /* release intr resources */ 354 oce_intr_free(sc); --- 136 unchanged lines hidden (view full) --- 491 sc->link_speed = link.mac_speed; 492 else 493 sc->link_speed = 0; 494 495 sc->qos_link_speed = (uint32_t )link.qos_link_speed * 10; 496 497 rc = oce_start_mq(sc->mq); 498 |
| 497 /* we need to get MCC aync events. 498 So enable intrs and also arm first EQ | 499 /* we need to get MCC aync events. So enable intrs and arm 500 first EQ, Other EQs will be armed after interface is UP |
| 499 */ 500 oce_hw_intr_enable(sc); 501 oce_arm_eq(sc, sc->eq[0]->eq_id, 0, TRUE, FALSE); 502 | 501 */ 502 oce_hw_intr_enable(sc); 503 oce_arm_eq(sc, sc->eq[0]->eq_id, 0, TRUE, FALSE); 504 |
| 505 /* Send first mcc cmd and after that we get gracious 506 MCC notifications from FW 507 */ 508 oce_first_mcc_cmd(sc); 509 |
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| 503 return rc; 504} 505 506 507/** 508 * @brief Function for hardware enable interupts. 509 * @param sc software handle to the device 510 */ --- 21 unchanged lines hidden (view full) --- 532 reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL); 533 reg &= ~HOSTINTR_MASK; 534 OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg); 535} 536 537 538 539/** | 510 return rc; 511} 512 513 514/** 515 * @brief Function for hardware enable interupts. 516 * @param sc software handle to the device 517 */ --- 21 unchanged lines hidden (view full) --- 539 reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL); 540 reg &= ~HOSTINTR_MASK; 541 OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg); 542} 543 544 545 546/** |
| 540 * @brief Function for hardware update multicast filter 541 * @param sc software handle to the device | 547 * @brief Function for hardware update multicast filter 548 * @param sc software handle to the device |
| 542 */ 543int 544oce_hw_update_multicast(POCE_SOFTC sc) 545{ 546 struct ifnet *ifp = sc->ifp; 547 struct ifmultiaddr *ifma; 548 struct mbx_set_common_iface_multicast *req = NULL; 549 OCE_DMA_MEM dma; --- 39 unchanged lines hidden --- | 549 */ 550int 551oce_hw_update_multicast(POCE_SOFTC sc) 552{ 553 struct ifnet *ifp = sc->ifp; 554 struct ifmultiaddr *ifma; 555 struct mbx_set_common_iface_multicast *req = NULL; 556 OCE_DMA_MEM dma; --- 39 unchanged lines hidden --- |