36
37/*
38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
39 * for FreeBSD. Datasheets are available from:
40 *
41 * http://www.national.com/ds/DP/DP83820.pdf
42 * http://www.national.com/ds/DP/DP83821.pdf
43 *
44 * These chips are used on several low cost gigabit ethernet NICs
45 * sold by D-Link, Addtron, SMC and Asante. Both parts are
46 * virtually the same, except the 83820 is a 64-bit/32-bit part,
47 * while the 83821 is 32-bit only.
48 *
49 * Many cards also use National gigE transceivers, such as the
50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
51 * contains a full register description that applies to all of these
52 * components:
53 *
54 * http://www.national.com/ds/DP/DP83861.pdf
55 *
56 * Written by Bill Paul <wpaul@bsdi.com>
57 * BSDi Open Source Solutions
58 */
59
60/*
61 * The NatSemi DP83820 and 83821 controllers are enhanced versions
62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
67 * matching buffers, one perfect address filter buffer and interrupt
68 * moderation. The 83820 supports both 64-bit and 32-bit addressing
69 * and data transfers: the 64-bit support can be toggled on or off
70 * via software. This affects the size of certain fields in the DMA
71 * descriptors.
72 *
73 * There are two bugs/misfeatures in the 83820/83821 that I have
74 * discovered so far:
75 *
76 * - Receive buffers must be aligned on 64-bit boundaries, which means
77 * you must resort to copying data in order to fix up the payload
78 * alignment.
79 *
80 * - In order to transmit jumbo frames larger than 8170 bytes, you have
81 * to turn off transmit checksum offloading, because the chip can't
82 * compute the checksum on an outgoing frame unless it fits entirely
83 * within the TX FIFO, which is only 8192 bytes in size. If you have
84 * TX checksum offload enabled and you transmit attempt to transmit a
85 * frame larger than 8170 bytes, the transmitter will wedge.
86 *
87 * To work around the latter problem, TX checksum offload is disabled
88 * if the user selects an MTU larger than 8152 (8170 - 18).
89 */
90
91#include <sys/param.h>
92#include <sys/systm.h>
93#include <sys/sockio.h>
94#include <sys/mbuf.h>
95#include <sys/malloc.h>
96#include <sys/module.h>
97#include <sys/kernel.h>
98#include <sys/socket.h>
99
100#include <net/if.h>
101#include <net/if_arp.h>
102#include <net/ethernet.h>
103#include <net/if_dl.h>
104#include <net/if_media.h>
105#include <net/if_types.h>
106#include <net/if_vlan_var.h>
107
108#include <net/bpf.h>
109
110#include <vm/vm.h> /* for vtophys */
111#include <vm/pmap.h> /* for vtophys */
112#include <machine/clock.h> /* for DELAY */
113#include <machine/bus.h>
114#include <machine/resource.h>
115#include <sys/bus.h>
116#include <sys/rman.h>
117
118#include <dev/mii/mii.h>
119#include <dev/mii/miivar.h>
120
121#include <dev/pci/pcireg.h>
122#include <dev/pci/pcivar.h>
123
124#define NGE_USEIOSPACE
125
126#include <dev/nge/if_ngereg.h>
127
128MODULE_DEPEND(nge, pci, 1, 1, 1);
129MODULE_DEPEND(nge, ether, 1, 1, 1);
130MODULE_DEPEND(nge, miibus, 1, 1, 1);
131
132/* "controller miibus0" required. See GENERIC if you get errors here. */
133#include "miibus_if.h"
134
135#define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
136
137/*
138 * Various supported device vendors/types and their names.
139 */
140static struct nge_type nge_devs[] = {
141 { NGE_VENDORID, NGE_DEVICEID,
142 "National Semiconductor Gigabit Ethernet" },
143 { 0, 0, NULL }
144};
145
146static int nge_probe(device_t);
147static int nge_attach(device_t);
148static int nge_detach(device_t);
149
150static int nge_newbuf(struct nge_softc *, struct nge_desc *, struct mbuf *);
151static int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *);
152#ifdef NGE_FIXUP_RX
153static __inline void nge_fixup_rx (struct mbuf *);
154#endif
155static void nge_rxeof(struct nge_softc *);
156static void nge_txeof(struct nge_softc *);
157static void nge_intr(void *);
158static void nge_tick(void *);
159static void nge_tick_locked(struct nge_softc *);
160static void nge_start(struct ifnet *);
161static void nge_start_locked(struct ifnet *);
162static int nge_ioctl(struct ifnet *, u_long, caddr_t);
163static void nge_init(void *);
164static void nge_init_locked(struct nge_softc *);
165static void nge_stop(struct nge_softc *);
166static void nge_watchdog(struct ifnet *);
167static void nge_shutdown(device_t);
168static int nge_ifmedia_upd(struct ifnet *);
169static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
170
171static void nge_delay(struct nge_softc *);
172static void nge_eeprom_idle(struct nge_softc *);
173static void nge_eeprom_putbyte(struct nge_softc *, int);
174static void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *);
175static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int);
176
177static void nge_mii_sync(struct nge_softc *);
178static void nge_mii_send(struct nge_softc *, u_int32_t, int);
179static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
180static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
181
182static int nge_miibus_readreg(device_t, int, int);
183static int nge_miibus_writereg(device_t, int, int, int);
184static void nge_miibus_statchg(device_t);
185
186static void nge_setmulti(struct nge_softc *);
187static void nge_reset(struct nge_softc *);
188static int nge_list_rx_init(struct nge_softc *);
189static int nge_list_tx_init(struct nge_softc *);
190
191#ifdef NGE_USEIOSPACE
192#define NGE_RES SYS_RES_IOPORT
193#define NGE_RID NGE_PCI_LOIO
194#else
195#define NGE_RES SYS_RES_MEMORY
196#define NGE_RID NGE_PCI_LOMEM
197#endif
198
199static device_method_t nge_methods[] = {
200 /* Device interface */
201 DEVMETHOD(device_probe, nge_probe),
202 DEVMETHOD(device_attach, nge_attach),
203 DEVMETHOD(device_detach, nge_detach),
204 DEVMETHOD(device_shutdown, nge_shutdown),
205
206 /* bus interface */
207 DEVMETHOD(bus_print_child, bus_generic_print_child),
208 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
209
210 /* MII interface */
211 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
212 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
213 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
214
215 { 0, 0 }
216};
217
218static driver_t nge_driver = {
219 "nge",
220 nge_methods,
221 sizeof(struct nge_softc)
222};
223
224static devclass_t nge_devclass;
225
226DRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0);
227DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
228
229#define NGE_SETBIT(sc, reg, x) \
230 CSR_WRITE_4(sc, reg, \
231 CSR_READ_4(sc, reg) | (x))
232
233#define NGE_CLRBIT(sc, reg, x) \
234 CSR_WRITE_4(sc, reg, \
235 CSR_READ_4(sc, reg) & ~(x))
236
237#define SIO_SET(x) \
238 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
239
240#define SIO_CLR(x) \
241 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
242
243static void
244nge_delay(sc)
245 struct nge_softc *sc;
246{
247 int idx;
248
249 for (idx = (300 / 33) + 1; idx > 0; idx--)
250 CSR_READ_4(sc, NGE_CSR);
251
252 return;
253}
254
255static void
256nge_eeprom_idle(sc)
257 struct nge_softc *sc;
258{
259 register int i;
260
261 SIO_SET(NGE_MEAR_EE_CSEL);
262 nge_delay(sc);
263 SIO_SET(NGE_MEAR_EE_CLK);
264 nge_delay(sc);
265
266 for (i = 0; i < 25; i++) {
267 SIO_CLR(NGE_MEAR_EE_CLK);
268 nge_delay(sc);
269 SIO_SET(NGE_MEAR_EE_CLK);
270 nge_delay(sc);
271 }
272
273 SIO_CLR(NGE_MEAR_EE_CLK);
274 nge_delay(sc);
275 SIO_CLR(NGE_MEAR_EE_CSEL);
276 nge_delay(sc);
277 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
278
279 return;
280}
281
282/*
283 * Send a read command and address to the EEPROM, check for ACK.
284 */
285static void
286nge_eeprom_putbyte(sc, addr)
287 struct nge_softc *sc;
288 int addr;
289{
290 register int d, i;
291
292 d = addr | NGE_EECMD_READ;
293
294 /*
295 * Feed in each bit and stobe the clock.
296 */
297 for (i = 0x400; i; i >>= 1) {
298 if (d & i) {
299 SIO_SET(NGE_MEAR_EE_DIN);
300 } else {
301 SIO_CLR(NGE_MEAR_EE_DIN);
302 }
303 nge_delay(sc);
304 SIO_SET(NGE_MEAR_EE_CLK);
305 nge_delay(sc);
306 SIO_CLR(NGE_MEAR_EE_CLK);
307 nge_delay(sc);
308 }
309
310 return;
311}
312
313/*
314 * Read a word of data stored in the EEPROM at address 'addr.'
315 */
316static void
317nge_eeprom_getword(sc, addr, dest)
318 struct nge_softc *sc;
319 int addr;
320 u_int16_t *dest;
321{
322 register int i;
323 u_int16_t word = 0;
324
325 /* Force EEPROM to idle state. */
326 nge_eeprom_idle(sc);
327
328 /* Enter EEPROM access mode. */
329 nge_delay(sc);
330 SIO_CLR(NGE_MEAR_EE_CLK);
331 nge_delay(sc);
332 SIO_SET(NGE_MEAR_EE_CSEL);
333 nge_delay(sc);
334
335 /*
336 * Send address of word we want to read.
337 */
338 nge_eeprom_putbyte(sc, addr);
339
340 /*
341 * Start reading bits from EEPROM.
342 */
343 for (i = 0x8000; i; i >>= 1) {
344 SIO_SET(NGE_MEAR_EE_CLK);
345 nge_delay(sc);
346 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
347 word |= i;
348 nge_delay(sc);
349 SIO_CLR(NGE_MEAR_EE_CLK);
350 nge_delay(sc);
351 }
352
353 /* Turn off EEPROM access mode. */
354 nge_eeprom_idle(sc);
355
356 *dest = word;
357
358 return;
359}
360
361/*
362 * Read a sequence of words from the EEPROM.
363 */
364static void
365nge_read_eeprom(sc, dest, off, cnt, swap)
366 struct nge_softc *sc;
367 caddr_t dest;
368 int off;
369 int cnt;
370 int swap;
371{
372 int i;
373 u_int16_t word = 0, *ptr;
374
375 for (i = 0; i < cnt; i++) {
376 nge_eeprom_getword(sc, off + i, &word);
377 ptr = (u_int16_t *)(dest + (i * 2));
378 if (swap)
379 *ptr = ntohs(word);
380 else
381 *ptr = word;
382 }
383
384 return;
385}
386
387/*
388 * Sync the PHYs by setting data bit and strobing the clock 32 times.
389 */
390static void
391nge_mii_sync(sc)
392 struct nge_softc *sc;
393{
394 register int i;
395
396 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA);
397
398 for (i = 0; i < 32; i++) {
399 SIO_SET(NGE_MEAR_MII_CLK);
400 DELAY(1);
401 SIO_CLR(NGE_MEAR_MII_CLK);
402 DELAY(1);
403 }
404
405 return;
406}
407
408/*
409 * Clock a series of bits through the MII.
410 */
411static void
412nge_mii_send(sc, bits, cnt)
413 struct nge_softc *sc;
414 u_int32_t bits;
415 int cnt;
416{
417 int i;
418
419 SIO_CLR(NGE_MEAR_MII_CLK);
420
421 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
422 if (bits & i) {
423 SIO_SET(NGE_MEAR_MII_DATA);
424 } else {
425 SIO_CLR(NGE_MEAR_MII_DATA);
426 }
427 DELAY(1);
428 SIO_CLR(NGE_MEAR_MII_CLK);
429 DELAY(1);
430 SIO_SET(NGE_MEAR_MII_CLK);
431 }
432}
433
434/*
435 * Read an PHY register through the MII.
436 */
437static int
438nge_mii_readreg(sc, frame)
439 struct nge_softc *sc;
440 struct nge_mii_frame *frame;
441
442{
443 int i, ack;
444
445 /*
446 * Set up frame for RX.
447 */
448 frame->mii_stdelim = NGE_MII_STARTDELIM;
449 frame->mii_opcode = NGE_MII_READOP;
450 frame->mii_turnaround = 0;
451 frame->mii_data = 0;
452
453 CSR_WRITE_4(sc, NGE_MEAR, 0);
454
455 /*
456 * Turn on data xmit.
457 */
458 SIO_SET(NGE_MEAR_MII_DIR);
459
460 nge_mii_sync(sc);
461
462 /*
463 * Send command/address info.
464 */
465 nge_mii_send(sc, frame->mii_stdelim, 2);
466 nge_mii_send(sc, frame->mii_opcode, 2);
467 nge_mii_send(sc, frame->mii_phyaddr, 5);
468 nge_mii_send(sc, frame->mii_regaddr, 5);
469
470 /* Idle bit */
471 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA));
472 DELAY(1);
473 SIO_SET(NGE_MEAR_MII_CLK);
474 DELAY(1);
475
476 /* Turn off xmit. */
477 SIO_CLR(NGE_MEAR_MII_DIR);
478 /* Check for ack */
479 SIO_CLR(NGE_MEAR_MII_CLK);
480 DELAY(1);
481 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
482 SIO_SET(NGE_MEAR_MII_CLK);
483 DELAY(1);
484
485 /*
486 * Now try reading data bits. If the ack failed, we still
487 * need to clock through 16 cycles to keep the PHY(s) in sync.
488 */
489 if (ack) {
490 for(i = 0; i < 16; i++) {
491 SIO_CLR(NGE_MEAR_MII_CLK);
492 DELAY(1);
493 SIO_SET(NGE_MEAR_MII_CLK);
494 DELAY(1);
495 }
496 goto fail;
497 }
498
499 for (i = 0x8000; i; i >>= 1) {
500 SIO_CLR(NGE_MEAR_MII_CLK);
501 DELAY(1);
502 if (!ack) {
503 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
504 frame->mii_data |= i;
505 DELAY(1);
506 }
507 SIO_SET(NGE_MEAR_MII_CLK);
508 DELAY(1);
509 }
510
511fail:
512
513 SIO_CLR(NGE_MEAR_MII_CLK);
514 DELAY(1);
515 SIO_SET(NGE_MEAR_MII_CLK);
516 DELAY(1);
517
518 if (ack)
519 return(1);
520 return(0);
521}
522
523/*
524 * Write to a PHY register through the MII.
525 */
526static int
527nge_mii_writereg(sc, frame)
528 struct nge_softc *sc;
529 struct nge_mii_frame *frame;
530
531{
532
533 /*
534 * Set up frame for TX.
535 */
536
537 frame->mii_stdelim = NGE_MII_STARTDELIM;
538 frame->mii_opcode = NGE_MII_WRITEOP;
539 frame->mii_turnaround = NGE_MII_TURNAROUND;
540
541 /*
542 * Turn on data output.
543 */
544 SIO_SET(NGE_MEAR_MII_DIR);
545
546 nge_mii_sync(sc);
547
548 nge_mii_send(sc, frame->mii_stdelim, 2);
549 nge_mii_send(sc, frame->mii_opcode, 2);
550 nge_mii_send(sc, frame->mii_phyaddr, 5);
551 nge_mii_send(sc, frame->mii_regaddr, 5);
552 nge_mii_send(sc, frame->mii_turnaround, 2);
553 nge_mii_send(sc, frame->mii_data, 16);
554
555 /* Idle bit. */
556 SIO_SET(NGE_MEAR_MII_CLK);
557 DELAY(1);
558 SIO_CLR(NGE_MEAR_MII_CLK);
559 DELAY(1);
560
561 /*
562 * Turn off xmit.
563 */
564 SIO_CLR(NGE_MEAR_MII_DIR);
565
566 return(0);
567}
568
569static int
570nge_miibus_readreg(dev, phy, reg)
571 device_t dev;
572 int phy, reg;
573{
574 struct nge_softc *sc;
575 struct nge_mii_frame frame;
576
577 sc = device_get_softc(dev);
578
579 bzero((char *)&frame, sizeof(frame));
580
581 frame.mii_phyaddr = phy;
582 frame.mii_regaddr = reg;
583 nge_mii_readreg(sc, &frame);
584
585 return(frame.mii_data);
586}
587
588static int
589nge_miibus_writereg(dev, phy, reg, data)
590 device_t dev;
591 int phy, reg, data;
592{
593 struct nge_softc *sc;
594 struct nge_mii_frame frame;
595
596 sc = device_get_softc(dev);
597
598 bzero((char *)&frame, sizeof(frame));
599
600 frame.mii_phyaddr = phy;
601 frame.mii_regaddr = reg;
602 frame.mii_data = data;
603 nge_mii_writereg(sc, &frame);
604
605 return(0);
606}
607
608static void
609nge_miibus_statchg(dev)
610 device_t dev;
611{
612 int status;
613 struct nge_softc *sc;
614 struct mii_data *mii;
615
616 sc = device_get_softc(dev);
617 if (sc->nge_tbi) {
618 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
619 == IFM_AUTO) {
620 status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
621 if (status == 0 || status & NGE_TBIANAR_FDX) {
622 NGE_SETBIT(sc, NGE_TX_CFG,
623 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
624 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
625 } else {
626 NGE_CLRBIT(sc, NGE_TX_CFG,
627 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
628 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
629 }
630
631 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
632 != IFM_FDX) {
633 NGE_CLRBIT(sc, NGE_TX_CFG,
634 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
635 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
636 } else {
637 NGE_SETBIT(sc, NGE_TX_CFG,
638 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
639 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
640 }
641 } else {
642 mii = device_get_softc(sc->nge_miibus);
643
644 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
645 NGE_SETBIT(sc, NGE_TX_CFG,
646 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
647 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
648 } else {
649 NGE_CLRBIT(sc, NGE_TX_CFG,
650 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
651 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
652 }
653
654 /* If we have a 1000Mbps link, set the mode_1000 bit. */
655 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
656 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
657 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
658 } else {
659 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
660 }
661 }
662 return;
663}
664
665static void
666nge_setmulti(sc)
667 struct nge_softc *sc;
668{
669 struct ifnet *ifp;
670 struct ifmultiaddr *ifma;
671 u_int32_t h = 0, i, filtsave;
672 int bit, index;
673
674 NGE_LOCK_ASSERT(sc);
675 ifp = sc->nge_ifp;
676
677 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
678 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
679 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH);
680 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
681 return;
682 }
683
684 /*
685 * We have to explicitly enable the multicast hash table
686 * on the NatSemi chip if we want to use it, which we do.
687 * We also have to tell it that we don't want to use the
688 * hash table for matching unicast addresses.
689 */
690 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
691 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
692 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH);
693
694 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
695
696 /* first, zot all the existing hash bits */
697 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
698 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
699 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
700 }
701
702 /*
703 * From the 11 bits returned by the crc routine, the top 7
704 * bits represent the 16-bit word in the mcast hash table
705 * that needs to be updated, and the lower 4 bits represent
706 * which bit within that byte needs to be set.
707 */
708 IF_ADDR_LOCK(ifp);
709 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
710 if (ifma->ifma_addr->sa_family != AF_LINK)
711 continue;
712 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
713 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
714 index = (h >> 4) & 0x7F;
715 bit = h & 0xF;
716 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
717 NGE_FILTADDR_MCAST_LO + (index * 2));
718 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
719 }
720 IF_ADDR_UNLOCK(ifp);
721
722 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
723
724 return;
725}
726
727static void
728nge_reset(sc)
729 struct nge_softc *sc;
730{
731 register int i;
732
733 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
734
735 for (i = 0; i < NGE_TIMEOUT; i++) {
736 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))
737 break;
738 }
739
740 if (i == NGE_TIMEOUT)
741 printf("nge%d: reset never completed\n", sc->nge_unit);
742
743 /* Wait a little while for the chip to get its brains in order. */
744 DELAY(1000);
745
746 /*
747 * If this is a NetSemi chip, make sure to clear
748 * PME mode.
749 */
750 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
751 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
752
753 return;
754}
755
756/*
757 * Probe for a NatSemi chip. Check the PCI vendor and device
758 * IDs against our list and return a device name if we find a match.
759 */
760static int
761nge_probe(dev)
762 device_t dev;
763{
764 struct nge_type *t;
765
766 t = nge_devs;
767
768 while(t->nge_name != NULL) {
769 if ((pci_get_vendor(dev) == t->nge_vid) &&
770 (pci_get_device(dev) == t->nge_did)) {
771 device_set_desc(dev, t->nge_name);
772 return(BUS_PROBE_DEFAULT);
773 }
774 t++;
775 }
776
777 return(ENXIO);
778}
779
780/*
781 * Attach the interface. Allocate softc structures, do ifmedia
782 * setup and ethernet/BPF attach.
783 */
784static int
785nge_attach(dev)
786 device_t dev;
787{
788 u_char eaddr[ETHER_ADDR_LEN];
789 struct nge_softc *sc;
790 struct ifnet *ifp;
791 int unit, error = 0, rid;
792 const char *sep = "";
793
794 sc = device_get_softc(dev);
795 unit = device_get_unit(dev);
796 bzero(sc, sizeof(struct nge_softc));
797
798 NGE_LOCK_INIT(sc, device_get_nameunit(dev));
799 /*
800 * Map control/status registers.
801 */
802 pci_enable_busmaster(dev);
803
804 rid = NGE_RID;
805 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
806
807 if (sc->nge_res == NULL) {
808 printf("nge%d: couldn't map ports/memory\n", unit);
809 error = ENXIO;
810 goto fail;
811 }
812
813 sc->nge_btag = rman_get_bustag(sc->nge_res);
814 sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
815
816 /* Allocate interrupt */
817 rid = 0;
818 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
819 RF_SHAREABLE | RF_ACTIVE);
820
821 if (sc->nge_irq == NULL) {
822 printf("nge%d: couldn't map interrupt\n", unit);
823 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
824 error = ENXIO;
825 goto fail;
826 }
827
828 /* Reset the adapter. */
829 nge_reset(sc);
830
831 /*
832 * Get station address from the EEPROM.
833 */
834 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0);
835 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0);
836 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0);
837
838 sc->nge_unit = unit;
839
840 /* XXX: leaked on error */
841 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
842 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
843
844 if (sc->nge_ldata == NULL) {
845 printf("nge%d: no memory for list buffers!\n", unit);
846 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
847 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
848 error = ENXIO;
849 goto fail;
850 }
851
852 ifp = sc->nge_ifp = if_alloc(IFT_ETHER);
853 if (ifp == NULL) {
854 printf("nge%d: can not if_alloc()\n", unit);
855 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
856 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
857 error = ENOSPC;
858 goto fail;
859 }
860 ifp->if_softc = sc;
861 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
862 ifp->if_mtu = ETHERMTU;
863 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
864 ifp->if_ioctl = nge_ioctl;
865 ifp->if_start = nge_start;
866 ifp->if_watchdog = nge_watchdog;
867 ifp->if_init = nge_init;
868 ifp->if_baudrate = 1000000000;
869 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1;
870 ifp->if_hwassist = NGE_CSUM_FEATURES;
871 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING;
872#ifdef DEVICE_POLLING
873 ifp->if_capabilities |= IFCAP_POLLING;
874#endif
875 ifp->if_capenable = ifp->if_capabilities;
876
877 /*
878 * Do MII setup.
879 */
880 if (mii_phy_probe(dev, &sc->nge_miibus,
881 nge_ifmedia_upd, nge_ifmedia_sts)) {
882 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
883 sc->nge_tbi = 1;
884 device_printf(dev, "Using TBI\n");
885
886 sc->nge_miibus = dev;
887
888 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
889 nge_ifmedia_sts);
890#define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
891#define PRINT(s) printf("%s%s", sep, s); sep = ", "
892 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
893 device_printf(dev, " ");
894 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
895 PRINT("1000baseSX");
896 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
897 PRINT("1000baseSX-FDX");
898 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
899 PRINT("auto");
900
901 printf("\n");
902#undef ADD
903#undef PRINT
904 ifmedia_set(&sc->nge_ifmedia,
905 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
906
907 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
908 | NGE_GPIO_GP4_OUT
909 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
910 | NGE_GPIO_GP3_OUTENB
911 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
912
913 } else {
914 printf("nge%d: MII without any PHY!\n", sc->nge_unit);
915 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
916 bus_release_resource(dev, NGE_RES, NGE_RID,
917 sc->nge_res);
918 error = ENXIO;
919 goto fail;
920 }
921 }
922
923 /*
924 * Call MI attach routine.
925 */
926 ether_ifattach(ifp, eaddr);
927 callout_init(&sc->nge_stat_ch, CALLOUT_MPSAFE);
928
929 /*
930 * Hookup IRQ last.
931 */
932 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET | INTR_MPSAFE,
933 nge_intr, sc, &sc->nge_intrhand);
934 if (error) {
935 /* XXX: resource leaks */
936 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
937 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
938 printf("nge%d: couldn't set up irq\n", unit);
939 }
940
941fail:
942
943 if (error)
944 NGE_LOCK_DESTROY(sc);
945 return(error);
946}
947
948static int
949nge_detach(dev)
950 device_t dev;
951{
952 struct nge_softc *sc;
953 struct ifnet *ifp;
954
955 sc = device_get_softc(dev);
956 ifp = sc->nge_ifp;
957
958 NGE_LOCK(sc);
959 nge_reset(sc);
960 nge_stop(sc);
961 NGE_UNLOCK(sc);
962 ether_ifdetach(ifp);
963 if_free(ifp);
964
965 bus_generic_detach(dev);
966 if (!sc->nge_tbi) {
967 device_delete_child(dev, sc->nge_miibus);
968 }
969 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
970 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
971 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
972
973 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF);
974
975 NGE_LOCK_DESTROY(sc);
976
977 return(0);
978}
979
980/*
981 * Initialize the transmit descriptors.
982 */
983static int
984nge_list_tx_init(sc)
985 struct nge_softc *sc;
986{
987 struct nge_list_data *ld;
988 struct nge_ring_data *cd;
989 int i;
990
991 cd = &sc->nge_cdata;
992 ld = sc->nge_ldata;
993
994 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
995 if (i == (NGE_TX_LIST_CNT - 1)) {
996 ld->nge_tx_list[i].nge_nextdesc =
997 &ld->nge_tx_list[0];
998 ld->nge_tx_list[i].nge_next =
999 vtophys(&ld->nge_tx_list[0]);
1000 } else {
1001 ld->nge_tx_list[i].nge_nextdesc =
1002 &ld->nge_tx_list[i + 1];
1003 ld->nge_tx_list[i].nge_next =
1004 vtophys(&ld->nge_tx_list[i + 1]);
1005 }
1006 ld->nge_tx_list[i].nge_mbuf = NULL;
1007 ld->nge_tx_list[i].nge_ptr = 0;
1008 ld->nge_tx_list[i].nge_ctl = 0;
1009 }
1010
1011 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
1012
1013 return(0);
1014}
1015
1016
1017/*
1018 * Initialize the RX descriptors and allocate mbufs for them. Note that
1019 * we arrange the descriptors in a closed ring, so that the last descriptor
1020 * points back to the first.
1021 */
1022static int
1023nge_list_rx_init(sc)
1024 struct nge_softc *sc;
1025{
1026 struct nge_list_data *ld;
1027 struct nge_ring_data *cd;
1028 int i;
1029
1030 ld = sc->nge_ldata;
1031 cd = &sc->nge_cdata;
1032
1033 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1034 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1035 return(ENOBUFS);
1036 if (i == (NGE_RX_LIST_CNT - 1)) {
1037 ld->nge_rx_list[i].nge_nextdesc =
1038 &ld->nge_rx_list[0];
1039 ld->nge_rx_list[i].nge_next =
1040 vtophys(&ld->nge_rx_list[0]);
1041 } else {
1042 ld->nge_rx_list[i].nge_nextdesc =
1043 &ld->nge_rx_list[i + 1];
1044 ld->nge_rx_list[i].nge_next =
1045 vtophys(&ld->nge_rx_list[i + 1]);
1046 }
1047 }
1048
1049 cd->nge_rx_prod = 0;
1050 sc->nge_head = sc->nge_tail = NULL;
1051
1052 return(0);
1053}
1054
1055/*
1056 * Initialize an RX descriptor and attach an MBUF cluster.
1057 */
1058static int
1059nge_newbuf(sc, c, m)
1060 struct nge_softc *sc;
1061 struct nge_desc *c;
1062 struct mbuf *m;
1063{
1064
1065 if (m == NULL) {
1066 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1067 if (m == NULL)
1068 return (ENOBUFS);
1069 } else
1070 m->m_data = m->m_ext.ext_buf;
1071
1072 m->m_len = m->m_pkthdr.len = MCLBYTES;
1073
1074 m_adj(m, sizeof(u_int64_t));
1075
1076 c->nge_mbuf = m;
1077 c->nge_ptr = vtophys(mtod(m, caddr_t));
1078 c->nge_ctl = m->m_len;
1079 c->nge_extsts = 0;
1080
1081 return(0);
1082}
1083
1084#ifdef NGE_FIXUP_RX
1085static __inline void
1086nge_fixup_rx(m)
1087 struct mbuf *m;
1088{
1089 int i;
1090 uint16_t *src, *dst;
1091
1092 src = mtod(m, uint16_t *);
1093 dst = src - 1;
1094
1095 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1096 *dst++ = *src++;
1097
1098 m->m_data -= ETHER_ALIGN;
1099
1100 return;
1101}
1102#endif
1103
1104/*
1105 * A frame has been uploaded: pass the resulting mbuf chain up to
1106 * the higher level protocols.
1107 */
1108static void
1109nge_rxeof(sc)
1110 struct nge_softc *sc;
1111{
1112 struct mbuf *m;
1113 struct ifnet *ifp;
1114 struct nge_desc *cur_rx;
1115 int i, total_len = 0;
1116 u_int32_t rxstat;
1117
1118 NGE_LOCK_ASSERT(sc);
1119 ifp = sc->nge_ifp;
1120 i = sc->nge_cdata.nge_rx_prod;
1121
1122 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
1123 u_int32_t extsts;
1124
1125#ifdef DEVICE_POLLING
1126 if (ifp->if_flags & IFF_POLLING) {
1127 if (sc->rxcycles <= 0)
1128 break;
1129 sc->rxcycles--;
1130 }
1131#endif /* DEVICE_POLLING */
1132
1133 cur_rx = &sc->nge_ldata->nge_rx_list[i];
1134 rxstat = cur_rx->nge_rxstat;
1135 extsts = cur_rx->nge_extsts;
1136 m = cur_rx->nge_mbuf;
1137 cur_rx->nge_mbuf = NULL;
1138 total_len = NGE_RXBYTES(cur_rx);
1139 NGE_INC(i, NGE_RX_LIST_CNT);
1140
1141 if (rxstat & NGE_CMDSTS_MORE) {
1142 m->m_len = total_len;
1143 if (sc->nge_head == NULL) {
1144 m->m_pkthdr.len = total_len;
1145 sc->nge_head = sc->nge_tail = m;
1146 } else {
1147 m->m_flags &= ~M_PKTHDR;
1148 sc->nge_head->m_pkthdr.len += total_len;
1149 sc->nge_tail->m_next = m;
1150 sc->nge_tail = m;
1151 }
1152 nge_newbuf(sc, cur_rx, NULL);
1153 continue;
1154 }
1155
1156 /*
1157 * If an error occurs, update stats, clear the
1158 * status word and leave the mbuf cluster in place:
1159 * it should simply get re-used next time this descriptor
1160 * comes up in the ring.
1161 */
1162 if (!(rxstat & NGE_CMDSTS_PKT_OK)) {
1163 ifp->if_ierrors++;
1164 if (sc->nge_head != NULL) {
1165 m_freem(sc->nge_head);
1166 sc->nge_head = sc->nge_tail = NULL;
1167 }
1168 nge_newbuf(sc, cur_rx, m);
1169 continue;
1170 }
1171
1172 /* Try conjure up a replacement mbuf. */
1173
1174 if (nge_newbuf(sc, cur_rx, NULL)) {
1175 ifp->if_ierrors++;
1176 if (sc->nge_head != NULL) {
1177 m_freem(sc->nge_head);
1178 sc->nge_head = sc->nge_tail = NULL;
1179 }
1180 nge_newbuf(sc, cur_rx, m);
1181 continue;
1182 }
1183
1184 if (sc->nge_head != NULL) {
1185 m->m_len = total_len;
1186 m->m_flags &= ~M_PKTHDR;
1187 sc->nge_tail->m_next = m;
1188 m = sc->nge_head;
1189 m->m_pkthdr.len += total_len;
1190 sc->nge_head = sc->nge_tail = NULL;
1191 } else
1192 m->m_pkthdr.len = m->m_len = total_len;
1193
1194 /*
1195 * Ok. NatSemi really screwed up here. This is the
1196 * only gigE chip I know of with alignment constraints
1197 * on receive buffers. RX buffers must be 64-bit aligned.
1198 */
1199 /*
1200 * By popular demand, ignore the alignment problems
1201 * on the Intel x86 platform. The performance hit
1202 * incurred due to unaligned accesses is much smaller
1203 * than the hit produced by forcing buffer copies all
1204 * the time, especially with jumbo frames. We still
1205 * need to fix up the alignment everywhere else though.
1206 */
1207#ifdef NGE_FIXUP_RX
1208 nge_fixup_rx(m);
1209#endif
1210
1211 ifp->if_ipackets++;
1212 m->m_pkthdr.rcvif = ifp;
1213
1214 /* Do IP checksum checking. */
1215 if (extsts & NGE_RXEXTSTS_IPPKT)
1216 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1217 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1218 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1219 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1220 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) ||
1221 (extsts & NGE_RXEXTSTS_UDPPKT &&
1222 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) {
1223 m->m_pkthdr.csum_flags |=
1224 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1225 m->m_pkthdr.csum_data = 0xffff;
1226 }
1227
1228 /*
1229 * If we received a packet with a vlan tag, pass it
1230 * to vlan_input() instead of ether_input().
1231 */
1232 if (extsts & NGE_RXEXTSTS_VLANPKT) {
1233 VLAN_INPUT_TAG(ifp, m,
1234 ntohs(extsts & NGE_RXEXTSTS_VTCI), continue);
1235 }
1236 NGE_UNLOCK(sc);
1237 (*ifp->if_input)(ifp, m);
1238 NGE_LOCK(sc);
1239 }
1240
1241 sc->nge_cdata.nge_rx_prod = i;
1242
1243 return;
1244}
1245
1246/*
1247 * A frame was downloaded to the chip. It's safe for us to clean up
1248 * the list buffers.
1249 */
1250
1251static void
1252nge_txeof(sc)
1253 struct nge_softc *sc;
1254{
1255 struct nge_desc *cur_tx;
1256 struct ifnet *ifp;
1257 u_int32_t idx;
1258
1259 NGE_LOCK_ASSERT(sc);
1260 ifp = sc->nge_ifp;
1261
1262 /*
1263 * Go through our tx list and free mbufs for those
1264 * frames that have been transmitted.
1265 */
1266 idx = sc->nge_cdata.nge_tx_cons;
1267 while (idx != sc->nge_cdata.nge_tx_prod) {
1268 cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1269
1270 if (NGE_OWNDESC(cur_tx))
1271 break;
1272
1273 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1274 sc->nge_cdata.nge_tx_cnt--;
1275 NGE_INC(idx, NGE_TX_LIST_CNT);
1276 continue;
1277 }
1278
1279 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1280 ifp->if_oerrors++;
1281 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1282 ifp->if_collisions++;
1283 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1284 ifp->if_collisions++;
1285 }
1286
1287 ifp->if_collisions +=
1288 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1289
1290 ifp->if_opackets++;
1291 if (cur_tx->nge_mbuf != NULL) {
1292 m_freem(cur_tx->nge_mbuf);
1293 cur_tx->nge_mbuf = NULL;
| 36
37/*
38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
39 * for FreeBSD. Datasheets are available from:
40 *
41 * http://www.national.com/ds/DP/DP83820.pdf
42 * http://www.national.com/ds/DP/DP83821.pdf
43 *
44 * These chips are used on several low cost gigabit ethernet NICs
45 * sold by D-Link, Addtron, SMC and Asante. Both parts are
46 * virtually the same, except the 83820 is a 64-bit/32-bit part,
47 * while the 83821 is 32-bit only.
48 *
49 * Many cards also use National gigE transceivers, such as the
50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
51 * contains a full register description that applies to all of these
52 * components:
53 *
54 * http://www.national.com/ds/DP/DP83861.pdf
55 *
56 * Written by Bill Paul <wpaul@bsdi.com>
57 * BSDi Open Source Solutions
58 */
59
60/*
61 * The NatSemi DP83820 and 83821 controllers are enhanced versions
62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
67 * matching buffers, one perfect address filter buffer and interrupt
68 * moderation. The 83820 supports both 64-bit and 32-bit addressing
69 * and data transfers: the 64-bit support can be toggled on or off
70 * via software. This affects the size of certain fields in the DMA
71 * descriptors.
72 *
73 * There are two bugs/misfeatures in the 83820/83821 that I have
74 * discovered so far:
75 *
76 * - Receive buffers must be aligned on 64-bit boundaries, which means
77 * you must resort to copying data in order to fix up the payload
78 * alignment.
79 *
80 * - In order to transmit jumbo frames larger than 8170 bytes, you have
81 * to turn off transmit checksum offloading, because the chip can't
82 * compute the checksum on an outgoing frame unless it fits entirely
83 * within the TX FIFO, which is only 8192 bytes in size. If you have
84 * TX checksum offload enabled and you transmit attempt to transmit a
85 * frame larger than 8170 bytes, the transmitter will wedge.
86 *
87 * To work around the latter problem, TX checksum offload is disabled
88 * if the user selects an MTU larger than 8152 (8170 - 18).
89 */
90
91#include <sys/param.h>
92#include <sys/systm.h>
93#include <sys/sockio.h>
94#include <sys/mbuf.h>
95#include <sys/malloc.h>
96#include <sys/module.h>
97#include <sys/kernel.h>
98#include <sys/socket.h>
99
100#include <net/if.h>
101#include <net/if_arp.h>
102#include <net/ethernet.h>
103#include <net/if_dl.h>
104#include <net/if_media.h>
105#include <net/if_types.h>
106#include <net/if_vlan_var.h>
107
108#include <net/bpf.h>
109
110#include <vm/vm.h> /* for vtophys */
111#include <vm/pmap.h> /* for vtophys */
112#include <machine/clock.h> /* for DELAY */
113#include <machine/bus.h>
114#include <machine/resource.h>
115#include <sys/bus.h>
116#include <sys/rman.h>
117
118#include <dev/mii/mii.h>
119#include <dev/mii/miivar.h>
120
121#include <dev/pci/pcireg.h>
122#include <dev/pci/pcivar.h>
123
124#define NGE_USEIOSPACE
125
126#include <dev/nge/if_ngereg.h>
127
128MODULE_DEPEND(nge, pci, 1, 1, 1);
129MODULE_DEPEND(nge, ether, 1, 1, 1);
130MODULE_DEPEND(nge, miibus, 1, 1, 1);
131
132/* "controller miibus0" required. See GENERIC if you get errors here. */
133#include "miibus_if.h"
134
135#define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
136
137/*
138 * Various supported device vendors/types and their names.
139 */
140static struct nge_type nge_devs[] = {
141 { NGE_VENDORID, NGE_DEVICEID,
142 "National Semiconductor Gigabit Ethernet" },
143 { 0, 0, NULL }
144};
145
146static int nge_probe(device_t);
147static int nge_attach(device_t);
148static int nge_detach(device_t);
149
150static int nge_newbuf(struct nge_softc *, struct nge_desc *, struct mbuf *);
151static int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *);
152#ifdef NGE_FIXUP_RX
153static __inline void nge_fixup_rx (struct mbuf *);
154#endif
155static void nge_rxeof(struct nge_softc *);
156static void nge_txeof(struct nge_softc *);
157static void nge_intr(void *);
158static void nge_tick(void *);
159static void nge_tick_locked(struct nge_softc *);
160static void nge_start(struct ifnet *);
161static void nge_start_locked(struct ifnet *);
162static int nge_ioctl(struct ifnet *, u_long, caddr_t);
163static void nge_init(void *);
164static void nge_init_locked(struct nge_softc *);
165static void nge_stop(struct nge_softc *);
166static void nge_watchdog(struct ifnet *);
167static void nge_shutdown(device_t);
168static int nge_ifmedia_upd(struct ifnet *);
169static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
170
171static void nge_delay(struct nge_softc *);
172static void nge_eeprom_idle(struct nge_softc *);
173static void nge_eeprom_putbyte(struct nge_softc *, int);
174static void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *);
175static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int);
176
177static void nge_mii_sync(struct nge_softc *);
178static void nge_mii_send(struct nge_softc *, u_int32_t, int);
179static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
180static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
181
182static int nge_miibus_readreg(device_t, int, int);
183static int nge_miibus_writereg(device_t, int, int, int);
184static void nge_miibus_statchg(device_t);
185
186static void nge_setmulti(struct nge_softc *);
187static void nge_reset(struct nge_softc *);
188static int nge_list_rx_init(struct nge_softc *);
189static int nge_list_tx_init(struct nge_softc *);
190
191#ifdef NGE_USEIOSPACE
192#define NGE_RES SYS_RES_IOPORT
193#define NGE_RID NGE_PCI_LOIO
194#else
195#define NGE_RES SYS_RES_MEMORY
196#define NGE_RID NGE_PCI_LOMEM
197#endif
198
199static device_method_t nge_methods[] = {
200 /* Device interface */
201 DEVMETHOD(device_probe, nge_probe),
202 DEVMETHOD(device_attach, nge_attach),
203 DEVMETHOD(device_detach, nge_detach),
204 DEVMETHOD(device_shutdown, nge_shutdown),
205
206 /* bus interface */
207 DEVMETHOD(bus_print_child, bus_generic_print_child),
208 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
209
210 /* MII interface */
211 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
212 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
213 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
214
215 { 0, 0 }
216};
217
218static driver_t nge_driver = {
219 "nge",
220 nge_methods,
221 sizeof(struct nge_softc)
222};
223
224static devclass_t nge_devclass;
225
226DRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0);
227DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
228
229#define NGE_SETBIT(sc, reg, x) \
230 CSR_WRITE_4(sc, reg, \
231 CSR_READ_4(sc, reg) | (x))
232
233#define NGE_CLRBIT(sc, reg, x) \
234 CSR_WRITE_4(sc, reg, \
235 CSR_READ_4(sc, reg) & ~(x))
236
237#define SIO_SET(x) \
238 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
239
240#define SIO_CLR(x) \
241 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
242
243static void
244nge_delay(sc)
245 struct nge_softc *sc;
246{
247 int idx;
248
249 for (idx = (300 / 33) + 1; idx > 0; idx--)
250 CSR_READ_4(sc, NGE_CSR);
251
252 return;
253}
254
255static void
256nge_eeprom_idle(sc)
257 struct nge_softc *sc;
258{
259 register int i;
260
261 SIO_SET(NGE_MEAR_EE_CSEL);
262 nge_delay(sc);
263 SIO_SET(NGE_MEAR_EE_CLK);
264 nge_delay(sc);
265
266 for (i = 0; i < 25; i++) {
267 SIO_CLR(NGE_MEAR_EE_CLK);
268 nge_delay(sc);
269 SIO_SET(NGE_MEAR_EE_CLK);
270 nge_delay(sc);
271 }
272
273 SIO_CLR(NGE_MEAR_EE_CLK);
274 nge_delay(sc);
275 SIO_CLR(NGE_MEAR_EE_CSEL);
276 nge_delay(sc);
277 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
278
279 return;
280}
281
282/*
283 * Send a read command and address to the EEPROM, check for ACK.
284 */
285static void
286nge_eeprom_putbyte(sc, addr)
287 struct nge_softc *sc;
288 int addr;
289{
290 register int d, i;
291
292 d = addr | NGE_EECMD_READ;
293
294 /*
295 * Feed in each bit and stobe the clock.
296 */
297 for (i = 0x400; i; i >>= 1) {
298 if (d & i) {
299 SIO_SET(NGE_MEAR_EE_DIN);
300 } else {
301 SIO_CLR(NGE_MEAR_EE_DIN);
302 }
303 nge_delay(sc);
304 SIO_SET(NGE_MEAR_EE_CLK);
305 nge_delay(sc);
306 SIO_CLR(NGE_MEAR_EE_CLK);
307 nge_delay(sc);
308 }
309
310 return;
311}
312
313/*
314 * Read a word of data stored in the EEPROM at address 'addr.'
315 */
316static void
317nge_eeprom_getword(sc, addr, dest)
318 struct nge_softc *sc;
319 int addr;
320 u_int16_t *dest;
321{
322 register int i;
323 u_int16_t word = 0;
324
325 /* Force EEPROM to idle state. */
326 nge_eeprom_idle(sc);
327
328 /* Enter EEPROM access mode. */
329 nge_delay(sc);
330 SIO_CLR(NGE_MEAR_EE_CLK);
331 nge_delay(sc);
332 SIO_SET(NGE_MEAR_EE_CSEL);
333 nge_delay(sc);
334
335 /*
336 * Send address of word we want to read.
337 */
338 nge_eeprom_putbyte(sc, addr);
339
340 /*
341 * Start reading bits from EEPROM.
342 */
343 for (i = 0x8000; i; i >>= 1) {
344 SIO_SET(NGE_MEAR_EE_CLK);
345 nge_delay(sc);
346 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
347 word |= i;
348 nge_delay(sc);
349 SIO_CLR(NGE_MEAR_EE_CLK);
350 nge_delay(sc);
351 }
352
353 /* Turn off EEPROM access mode. */
354 nge_eeprom_idle(sc);
355
356 *dest = word;
357
358 return;
359}
360
361/*
362 * Read a sequence of words from the EEPROM.
363 */
364static void
365nge_read_eeprom(sc, dest, off, cnt, swap)
366 struct nge_softc *sc;
367 caddr_t dest;
368 int off;
369 int cnt;
370 int swap;
371{
372 int i;
373 u_int16_t word = 0, *ptr;
374
375 for (i = 0; i < cnt; i++) {
376 nge_eeprom_getword(sc, off + i, &word);
377 ptr = (u_int16_t *)(dest + (i * 2));
378 if (swap)
379 *ptr = ntohs(word);
380 else
381 *ptr = word;
382 }
383
384 return;
385}
386
387/*
388 * Sync the PHYs by setting data bit and strobing the clock 32 times.
389 */
390static void
391nge_mii_sync(sc)
392 struct nge_softc *sc;
393{
394 register int i;
395
396 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA);
397
398 for (i = 0; i < 32; i++) {
399 SIO_SET(NGE_MEAR_MII_CLK);
400 DELAY(1);
401 SIO_CLR(NGE_MEAR_MII_CLK);
402 DELAY(1);
403 }
404
405 return;
406}
407
408/*
409 * Clock a series of bits through the MII.
410 */
411static void
412nge_mii_send(sc, bits, cnt)
413 struct nge_softc *sc;
414 u_int32_t bits;
415 int cnt;
416{
417 int i;
418
419 SIO_CLR(NGE_MEAR_MII_CLK);
420
421 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
422 if (bits & i) {
423 SIO_SET(NGE_MEAR_MII_DATA);
424 } else {
425 SIO_CLR(NGE_MEAR_MII_DATA);
426 }
427 DELAY(1);
428 SIO_CLR(NGE_MEAR_MII_CLK);
429 DELAY(1);
430 SIO_SET(NGE_MEAR_MII_CLK);
431 }
432}
433
434/*
435 * Read an PHY register through the MII.
436 */
437static int
438nge_mii_readreg(sc, frame)
439 struct nge_softc *sc;
440 struct nge_mii_frame *frame;
441
442{
443 int i, ack;
444
445 /*
446 * Set up frame for RX.
447 */
448 frame->mii_stdelim = NGE_MII_STARTDELIM;
449 frame->mii_opcode = NGE_MII_READOP;
450 frame->mii_turnaround = 0;
451 frame->mii_data = 0;
452
453 CSR_WRITE_4(sc, NGE_MEAR, 0);
454
455 /*
456 * Turn on data xmit.
457 */
458 SIO_SET(NGE_MEAR_MII_DIR);
459
460 nge_mii_sync(sc);
461
462 /*
463 * Send command/address info.
464 */
465 nge_mii_send(sc, frame->mii_stdelim, 2);
466 nge_mii_send(sc, frame->mii_opcode, 2);
467 nge_mii_send(sc, frame->mii_phyaddr, 5);
468 nge_mii_send(sc, frame->mii_regaddr, 5);
469
470 /* Idle bit */
471 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA));
472 DELAY(1);
473 SIO_SET(NGE_MEAR_MII_CLK);
474 DELAY(1);
475
476 /* Turn off xmit. */
477 SIO_CLR(NGE_MEAR_MII_DIR);
478 /* Check for ack */
479 SIO_CLR(NGE_MEAR_MII_CLK);
480 DELAY(1);
481 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
482 SIO_SET(NGE_MEAR_MII_CLK);
483 DELAY(1);
484
485 /*
486 * Now try reading data bits. If the ack failed, we still
487 * need to clock through 16 cycles to keep the PHY(s) in sync.
488 */
489 if (ack) {
490 for(i = 0; i < 16; i++) {
491 SIO_CLR(NGE_MEAR_MII_CLK);
492 DELAY(1);
493 SIO_SET(NGE_MEAR_MII_CLK);
494 DELAY(1);
495 }
496 goto fail;
497 }
498
499 for (i = 0x8000; i; i >>= 1) {
500 SIO_CLR(NGE_MEAR_MII_CLK);
501 DELAY(1);
502 if (!ack) {
503 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
504 frame->mii_data |= i;
505 DELAY(1);
506 }
507 SIO_SET(NGE_MEAR_MII_CLK);
508 DELAY(1);
509 }
510
511fail:
512
513 SIO_CLR(NGE_MEAR_MII_CLK);
514 DELAY(1);
515 SIO_SET(NGE_MEAR_MII_CLK);
516 DELAY(1);
517
518 if (ack)
519 return(1);
520 return(0);
521}
522
523/*
524 * Write to a PHY register through the MII.
525 */
526static int
527nge_mii_writereg(sc, frame)
528 struct nge_softc *sc;
529 struct nge_mii_frame *frame;
530
531{
532
533 /*
534 * Set up frame for TX.
535 */
536
537 frame->mii_stdelim = NGE_MII_STARTDELIM;
538 frame->mii_opcode = NGE_MII_WRITEOP;
539 frame->mii_turnaround = NGE_MII_TURNAROUND;
540
541 /*
542 * Turn on data output.
543 */
544 SIO_SET(NGE_MEAR_MII_DIR);
545
546 nge_mii_sync(sc);
547
548 nge_mii_send(sc, frame->mii_stdelim, 2);
549 nge_mii_send(sc, frame->mii_opcode, 2);
550 nge_mii_send(sc, frame->mii_phyaddr, 5);
551 nge_mii_send(sc, frame->mii_regaddr, 5);
552 nge_mii_send(sc, frame->mii_turnaround, 2);
553 nge_mii_send(sc, frame->mii_data, 16);
554
555 /* Idle bit. */
556 SIO_SET(NGE_MEAR_MII_CLK);
557 DELAY(1);
558 SIO_CLR(NGE_MEAR_MII_CLK);
559 DELAY(1);
560
561 /*
562 * Turn off xmit.
563 */
564 SIO_CLR(NGE_MEAR_MII_DIR);
565
566 return(0);
567}
568
569static int
570nge_miibus_readreg(dev, phy, reg)
571 device_t dev;
572 int phy, reg;
573{
574 struct nge_softc *sc;
575 struct nge_mii_frame frame;
576
577 sc = device_get_softc(dev);
578
579 bzero((char *)&frame, sizeof(frame));
580
581 frame.mii_phyaddr = phy;
582 frame.mii_regaddr = reg;
583 nge_mii_readreg(sc, &frame);
584
585 return(frame.mii_data);
586}
587
588static int
589nge_miibus_writereg(dev, phy, reg, data)
590 device_t dev;
591 int phy, reg, data;
592{
593 struct nge_softc *sc;
594 struct nge_mii_frame frame;
595
596 sc = device_get_softc(dev);
597
598 bzero((char *)&frame, sizeof(frame));
599
600 frame.mii_phyaddr = phy;
601 frame.mii_regaddr = reg;
602 frame.mii_data = data;
603 nge_mii_writereg(sc, &frame);
604
605 return(0);
606}
607
608static void
609nge_miibus_statchg(dev)
610 device_t dev;
611{
612 int status;
613 struct nge_softc *sc;
614 struct mii_data *mii;
615
616 sc = device_get_softc(dev);
617 if (sc->nge_tbi) {
618 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
619 == IFM_AUTO) {
620 status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
621 if (status == 0 || status & NGE_TBIANAR_FDX) {
622 NGE_SETBIT(sc, NGE_TX_CFG,
623 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
624 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
625 } else {
626 NGE_CLRBIT(sc, NGE_TX_CFG,
627 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
628 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
629 }
630
631 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
632 != IFM_FDX) {
633 NGE_CLRBIT(sc, NGE_TX_CFG,
634 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
635 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
636 } else {
637 NGE_SETBIT(sc, NGE_TX_CFG,
638 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
639 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
640 }
641 } else {
642 mii = device_get_softc(sc->nge_miibus);
643
644 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
645 NGE_SETBIT(sc, NGE_TX_CFG,
646 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
647 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
648 } else {
649 NGE_CLRBIT(sc, NGE_TX_CFG,
650 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
651 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
652 }
653
654 /* If we have a 1000Mbps link, set the mode_1000 bit. */
655 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
656 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
657 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
658 } else {
659 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
660 }
661 }
662 return;
663}
664
665static void
666nge_setmulti(sc)
667 struct nge_softc *sc;
668{
669 struct ifnet *ifp;
670 struct ifmultiaddr *ifma;
671 u_int32_t h = 0, i, filtsave;
672 int bit, index;
673
674 NGE_LOCK_ASSERT(sc);
675 ifp = sc->nge_ifp;
676
677 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
678 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
679 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH);
680 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
681 return;
682 }
683
684 /*
685 * We have to explicitly enable the multicast hash table
686 * on the NatSemi chip if we want to use it, which we do.
687 * We also have to tell it that we don't want to use the
688 * hash table for matching unicast addresses.
689 */
690 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
691 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
692 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH);
693
694 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
695
696 /* first, zot all the existing hash bits */
697 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
698 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
699 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
700 }
701
702 /*
703 * From the 11 bits returned by the crc routine, the top 7
704 * bits represent the 16-bit word in the mcast hash table
705 * that needs to be updated, and the lower 4 bits represent
706 * which bit within that byte needs to be set.
707 */
708 IF_ADDR_LOCK(ifp);
709 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
710 if (ifma->ifma_addr->sa_family != AF_LINK)
711 continue;
712 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
713 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
714 index = (h >> 4) & 0x7F;
715 bit = h & 0xF;
716 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
717 NGE_FILTADDR_MCAST_LO + (index * 2));
718 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
719 }
720 IF_ADDR_UNLOCK(ifp);
721
722 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
723
724 return;
725}
726
727static void
728nge_reset(sc)
729 struct nge_softc *sc;
730{
731 register int i;
732
733 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
734
735 for (i = 0; i < NGE_TIMEOUT; i++) {
736 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))
737 break;
738 }
739
740 if (i == NGE_TIMEOUT)
741 printf("nge%d: reset never completed\n", sc->nge_unit);
742
743 /* Wait a little while for the chip to get its brains in order. */
744 DELAY(1000);
745
746 /*
747 * If this is a NetSemi chip, make sure to clear
748 * PME mode.
749 */
750 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
751 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
752
753 return;
754}
755
756/*
757 * Probe for a NatSemi chip. Check the PCI vendor and device
758 * IDs against our list and return a device name if we find a match.
759 */
760static int
761nge_probe(dev)
762 device_t dev;
763{
764 struct nge_type *t;
765
766 t = nge_devs;
767
768 while(t->nge_name != NULL) {
769 if ((pci_get_vendor(dev) == t->nge_vid) &&
770 (pci_get_device(dev) == t->nge_did)) {
771 device_set_desc(dev, t->nge_name);
772 return(BUS_PROBE_DEFAULT);
773 }
774 t++;
775 }
776
777 return(ENXIO);
778}
779
780/*
781 * Attach the interface. Allocate softc structures, do ifmedia
782 * setup and ethernet/BPF attach.
783 */
784static int
785nge_attach(dev)
786 device_t dev;
787{
788 u_char eaddr[ETHER_ADDR_LEN];
789 struct nge_softc *sc;
790 struct ifnet *ifp;
791 int unit, error = 0, rid;
792 const char *sep = "";
793
794 sc = device_get_softc(dev);
795 unit = device_get_unit(dev);
796 bzero(sc, sizeof(struct nge_softc));
797
798 NGE_LOCK_INIT(sc, device_get_nameunit(dev));
799 /*
800 * Map control/status registers.
801 */
802 pci_enable_busmaster(dev);
803
804 rid = NGE_RID;
805 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
806
807 if (sc->nge_res == NULL) {
808 printf("nge%d: couldn't map ports/memory\n", unit);
809 error = ENXIO;
810 goto fail;
811 }
812
813 sc->nge_btag = rman_get_bustag(sc->nge_res);
814 sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
815
816 /* Allocate interrupt */
817 rid = 0;
818 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
819 RF_SHAREABLE | RF_ACTIVE);
820
821 if (sc->nge_irq == NULL) {
822 printf("nge%d: couldn't map interrupt\n", unit);
823 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
824 error = ENXIO;
825 goto fail;
826 }
827
828 /* Reset the adapter. */
829 nge_reset(sc);
830
831 /*
832 * Get station address from the EEPROM.
833 */
834 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0);
835 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0);
836 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0);
837
838 sc->nge_unit = unit;
839
840 /* XXX: leaked on error */
841 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
842 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
843
844 if (sc->nge_ldata == NULL) {
845 printf("nge%d: no memory for list buffers!\n", unit);
846 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
847 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
848 error = ENXIO;
849 goto fail;
850 }
851
852 ifp = sc->nge_ifp = if_alloc(IFT_ETHER);
853 if (ifp == NULL) {
854 printf("nge%d: can not if_alloc()\n", unit);
855 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
856 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
857 error = ENOSPC;
858 goto fail;
859 }
860 ifp->if_softc = sc;
861 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
862 ifp->if_mtu = ETHERMTU;
863 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
864 ifp->if_ioctl = nge_ioctl;
865 ifp->if_start = nge_start;
866 ifp->if_watchdog = nge_watchdog;
867 ifp->if_init = nge_init;
868 ifp->if_baudrate = 1000000000;
869 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1;
870 ifp->if_hwassist = NGE_CSUM_FEATURES;
871 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING;
872#ifdef DEVICE_POLLING
873 ifp->if_capabilities |= IFCAP_POLLING;
874#endif
875 ifp->if_capenable = ifp->if_capabilities;
876
877 /*
878 * Do MII setup.
879 */
880 if (mii_phy_probe(dev, &sc->nge_miibus,
881 nge_ifmedia_upd, nge_ifmedia_sts)) {
882 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
883 sc->nge_tbi = 1;
884 device_printf(dev, "Using TBI\n");
885
886 sc->nge_miibus = dev;
887
888 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
889 nge_ifmedia_sts);
890#define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
891#define PRINT(s) printf("%s%s", sep, s); sep = ", "
892 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
893 device_printf(dev, " ");
894 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
895 PRINT("1000baseSX");
896 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
897 PRINT("1000baseSX-FDX");
898 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
899 PRINT("auto");
900
901 printf("\n");
902#undef ADD
903#undef PRINT
904 ifmedia_set(&sc->nge_ifmedia,
905 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
906
907 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
908 | NGE_GPIO_GP4_OUT
909 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
910 | NGE_GPIO_GP3_OUTENB
911 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
912
913 } else {
914 printf("nge%d: MII without any PHY!\n", sc->nge_unit);
915 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
916 bus_release_resource(dev, NGE_RES, NGE_RID,
917 sc->nge_res);
918 error = ENXIO;
919 goto fail;
920 }
921 }
922
923 /*
924 * Call MI attach routine.
925 */
926 ether_ifattach(ifp, eaddr);
927 callout_init(&sc->nge_stat_ch, CALLOUT_MPSAFE);
928
929 /*
930 * Hookup IRQ last.
931 */
932 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET | INTR_MPSAFE,
933 nge_intr, sc, &sc->nge_intrhand);
934 if (error) {
935 /* XXX: resource leaks */
936 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
937 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
938 printf("nge%d: couldn't set up irq\n", unit);
939 }
940
941fail:
942
943 if (error)
944 NGE_LOCK_DESTROY(sc);
945 return(error);
946}
947
948static int
949nge_detach(dev)
950 device_t dev;
951{
952 struct nge_softc *sc;
953 struct ifnet *ifp;
954
955 sc = device_get_softc(dev);
956 ifp = sc->nge_ifp;
957
958 NGE_LOCK(sc);
959 nge_reset(sc);
960 nge_stop(sc);
961 NGE_UNLOCK(sc);
962 ether_ifdetach(ifp);
963 if_free(ifp);
964
965 bus_generic_detach(dev);
966 if (!sc->nge_tbi) {
967 device_delete_child(dev, sc->nge_miibus);
968 }
969 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
970 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
971 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
972
973 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF);
974
975 NGE_LOCK_DESTROY(sc);
976
977 return(0);
978}
979
980/*
981 * Initialize the transmit descriptors.
982 */
983static int
984nge_list_tx_init(sc)
985 struct nge_softc *sc;
986{
987 struct nge_list_data *ld;
988 struct nge_ring_data *cd;
989 int i;
990
991 cd = &sc->nge_cdata;
992 ld = sc->nge_ldata;
993
994 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
995 if (i == (NGE_TX_LIST_CNT - 1)) {
996 ld->nge_tx_list[i].nge_nextdesc =
997 &ld->nge_tx_list[0];
998 ld->nge_tx_list[i].nge_next =
999 vtophys(&ld->nge_tx_list[0]);
1000 } else {
1001 ld->nge_tx_list[i].nge_nextdesc =
1002 &ld->nge_tx_list[i + 1];
1003 ld->nge_tx_list[i].nge_next =
1004 vtophys(&ld->nge_tx_list[i + 1]);
1005 }
1006 ld->nge_tx_list[i].nge_mbuf = NULL;
1007 ld->nge_tx_list[i].nge_ptr = 0;
1008 ld->nge_tx_list[i].nge_ctl = 0;
1009 }
1010
1011 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
1012
1013 return(0);
1014}
1015
1016
1017/*
1018 * Initialize the RX descriptors and allocate mbufs for them. Note that
1019 * we arrange the descriptors in a closed ring, so that the last descriptor
1020 * points back to the first.
1021 */
1022static int
1023nge_list_rx_init(sc)
1024 struct nge_softc *sc;
1025{
1026 struct nge_list_data *ld;
1027 struct nge_ring_data *cd;
1028 int i;
1029
1030 ld = sc->nge_ldata;
1031 cd = &sc->nge_cdata;
1032
1033 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1034 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1035 return(ENOBUFS);
1036 if (i == (NGE_RX_LIST_CNT - 1)) {
1037 ld->nge_rx_list[i].nge_nextdesc =
1038 &ld->nge_rx_list[0];
1039 ld->nge_rx_list[i].nge_next =
1040 vtophys(&ld->nge_rx_list[0]);
1041 } else {
1042 ld->nge_rx_list[i].nge_nextdesc =
1043 &ld->nge_rx_list[i + 1];
1044 ld->nge_rx_list[i].nge_next =
1045 vtophys(&ld->nge_rx_list[i + 1]);
1046 }
1047 }
1048
1049 cd->nge_rx_prod = 0;
1050 sc->nge_head = sc->nge_tail = NULL;
1051
1052 return(0);
1053}
1054
1055/*
1056 * Initialize an RX descriptor and attach an MBUF cluster.
1057 */
1058static int
1059nge_newbuf(sc, c, m)
1060 struct nge_softc *sc;
1061 struct nge_desc *c;
1062 struct mbuf *m;
1063{
1064
1065 if (m == NULL) {
1066 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1067 if (m == NULL)
1068 return (ENOBUFS);
1069 } else
1070 m->m_data = m->m_ext.ext_buf;
1071
1072 m->m_len = m->m_pkthdr.len = MCLBYTES;
1073
1074 m_adj(m, sizeof(u_int64_t));
1075
1076 c->nge_mbuf = m;
1077 c->nge_ptr = vtophys(mtod(m, caddr_t));
1078 c->nge_ctl = m->m_len;
1079 c->nge_extsts = 0;
1080
1081 return(0);
1082}
1083
1084#ifdef NGE_FIXUP_RX
1085static __inline void
1086nge_fixup_rx(m)
1087 struct mbuf *m;
1088{
1089 int i;
1090 uint16_t *src, *dst;
1091
1092 src = mtod(m, uint16_t *);
1093 dst = src - 1;
1094
1095 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1096 *dst++ = *src++;
1097
1098 m->m_data -= ETHER_ALIGN;
1099
1100 return;
1101}
1102#endif
1103
1104/*
1105 * A frame has been uploaded: pass the resulting mbuf chain up to
1106 * the higher level protocols.
1107 */
1108static void
1109nge_rxeof(sc)
1110 struct nge_softc *sc;
1111{
1112 struct mbuf *m;
1113 struct ifnet *ifp;
1114 struct nge_desc *cur_rx;
1115 int i, total_len = 0;
1116 u_int32_t rxstat;
1117
1118 NGE_LOCK_ASSERT(sc);
1119 ifp = sc->nge_ifp;
1120 i = sc->nge_cdata.nge_rx_prod;
1121
1122 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
1123 u_int32_t extsts;
1124
1125#ifdef DEVICE_POLLING
1126 if (ifp->if_flags & IFF_POLLING) {
1127 if (sc->rxcycles <= 0)
1128 break;
1129 sc->rxcycles--;
1130 }
1131#endif /* DEVICE_POLLING */
1132
1133 cur_rx = &sc->nge_ldata->nge_rx_list[i];
1134 rxstat = cur_rx->nge_rxstat;
1135 extsts = cur_rx->nge_extsts;
1136 m = cur_rx->nge_mbuf;
1137 cur_rx->nge_mbuf = NULL;
1138 total_len = NGE_RXBYTES(cur_rx);
1139 NGE_INC(i, NGE_RX_LIST_CNT);
1140
1141 if (rxstat & NGE_CMDSTS_MORE) {
1142 m->m_len = total_len;
1143 if (sc->nge_head == NULL) {
1144 m->m_pkthdr.len = total_len;
1145 sc->nge_head = sc->nge_tail = m;
1146 } else {
1147 m->m_flags &= ~M_PKTHDR;
1148 sc->nge_head->m_pkthdr.len += total_len;
1149 sc->nge_tail->m_next = m;
1150 sc->nge_tail = m;
1151 }
1152 nge_newbuf(sc, cur_rx, NULL);
1153 continue;
1154 }
1155
1156 /*
1157 * If an error occurs, update stats, clear the
1158 * status word and leave the mbuf cluster in place:
1159 * it should simply get re-used next time this descriptor
1160 * comes up in the ring.
1161 */
1162 if (!(rxstat & NGE_CMDSTS_PKT_OK)) {
1163 ifp->if_ierrors++;
1164 if (sc->nge_head != NULL) {
1165 m_freem(sc->nge_head);
1166 sc->nge_head = sc->nge_tail = NULL;
1167 }
1168 nge_newbuf(sc, cur_rx, m);
1169 continue;
1170 }
1171
1172 /* Try conjure up a replacement mbuf. */
1173
1174 if (nge_newbuf(sc, cur_rx, NULL)) {
1175 ifp->if_ierrors++;
1176 if (sc->nge_head != NULL) {
1177 m_freem(sc->nge_head);
1178 sc->nge_head = sc->nge_tail = NULL;
1179 }
1180 nge_newbuf(sc, cur_rx, m);
1181 continue;
1182 }
1183
1184 if (sc->nge_head != NULL) {
1185 m->m_len = total_len;
1186 m->m_flags &= ~M_PKTHDR;
1187 sc->nge_tail->m_next = m;
1188 m = sc->nge_head;
1189 m->m_pkthdr.len += total_len;
1190 sc->nge_head = sc->nge_tail = NULL;
1191 } else
1192 m->m_pkthdr.len = m->m_len = total_len;
1193
1194 /*
1195 * Ok. NatSemi really screwed up here. This is the
1196 * only gigE chip I know of with alignment constraints
1197 * on receive buffers. RX buffers must be 64-bit aligned.
1198 */
1199 /*
1200 * By popular demand, ignore the alignment problems
1201 * on the Intel x86 platform. The performance hit
1202 * incurred due to unaligned accesses is much smaller
1203 * than the hit produced by forcing buffer copies all
1204 * the time, especially with jumbo frames. We still
1205 * need to fix up the alignment everywhere else though.
1206 */
1207#ifdef NGE_FIXUP_RX
1208 nge_fixup_rx(m);
1209#endif
1210
1211 ifp->if_ipackets++;
1212 m->m_pkthdr.rcvif = ifp;
1213
1214 /* Do IP checksum checking. */
1215 if (extsts & NGE_RXEXTSTS_IPPKT)
1216 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1217 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1218 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1219 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1220 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) ||
1221 (extsts & NGE_RXEXTSTS_UDPPKT &&
1222 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) {
1223 m->m_pkthdr.csum_flags |=
1224 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1225 m->m_pkthdr.csum_data = 0xffff;
1226 }
1227
1228 /*
1229 * If we received a packet with a vlan tag, pass it
1230 * to vlan_input() instead of ether_input().
1231 */
1232 if (extsts & NGE_RXEXTSTS_VLANPKT) {
1233 VLAN_INPUT_TAG(ifp, m,
1234 ntohs(extsts & NGE_RXEXTSTS_VTCI), continue);
1235 }
1236 NGE_UNLOCK(sc);
1237 (*ifp->if_input)(ifp, m);
1238 NGE_LOCK(sc);
1239 }
1240
1241 sc->nge_cdata.nge_rx_prod = i;
1242
1243 return;
1244}
1245
1246/*
1247 * A frame was downloaded to the chip. It's safe for us to clean up
1248 * the list buffers.
1249 */
1250
1251static void
1252nge_txeof(sc)
1253 struct nge_softc *sc;
1254{
1255 struct nge_desc *cur_tx;
1256 struct ifnet *ifp;
1257 u_int32_t idx;
1258
1259 NGE_LOCK_ASSERT(sc);
1260 ifp = sc->nge_ifp;
1261
1262 /*
1263 * Go through our tx list and free mbufs for those
1264 * frames that have been transmitted.
1265 */
1266 idx = sc->nge_cdata.nge_tx_cons;
1267 while (idx != sc->nge_cdata.nge_tx_prod) {
1268 cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1269
1270 if (NGE_OWNDESC(cur_tx))
1271 break;
1272
1273 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1274 sc->nge_cdata.nge_tx_cnt--;
1275 NGE_INC(idx, NGE_TX_LIST_CNT);
1276 continue;
1277 }
1278
1279 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1280 ifp->if_oerrors++;
1281 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1282 ifp->if_collisions++;
1283 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1284 ifp->if_collisions++;
1285 }
1286
1287 ifp->if_collisions +=
1288 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1289
1290 ifp->if_opackets++;
1291 if (cur_tx->nge_mbuf != NULL) {
1292 m_freem(cur_tx->nge_mbuf);
1293 cur_tx->nge_mbuf = NULL;
|
1680 return;
1681
1682 /*
1683 * Cancel pending I/O and free all RX/TX buffers.
1684 */
1685 nge_stop(sc);
1686
1687 if (sc->nge_tbi) {
1688 mii = NULL;
1689 } else {
1690 mii = device_get_softc(sc->nge_miibus);
1691 }
1692
1693 /* Set MAC address */
1694 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1695 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1696 ((u_int16_t *)IFP2ENADDR(sc->nge_ifp))[0]);
1697 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1698 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1699 ((u_int16_t *)IFP2ENADDR(sc->nge_ifp))[1]);
1700 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1701 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1702 ((u_int16_t *)IFP2ENADDR(sc->nge_ifp))[2]);
1703
1704 /* Init circular RX list. */
1705 if (nge_list_rx_init(sc) == ENOBUFS) {
1706 printf("nge%d: initialization failed: no "
1707 "memory for rx buffers\n", sc->nge_unit);
1708 nge_stop(sc);
1709 return;
1710 }
1711
1712 /*
1713 * Init tx descriptors.
1714 */
1715 nge_list_tx_init(sc);
1716
1717 /*
1718 * For the NatSemi chip, we have to explicitly enable the
1719 * reception of ARP frames, as well as turn on the 'perfect
1720 * match' filter where we store the station address, otherwise
1721 * we won't receive unicasts meant for this host.
1722 */
1723 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1724 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1725
1726 /* If we want promiscuous mode, set the allframes bit. */
1727 if (ifp->if_flags & IFF_PROMISC) {
1728 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1729 } else {
1730 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1731 }
1732
1733 /*
1734 * Set the capture broadcast bit to capture broadcast frames.
1735 */
1736 if (ifp->if_flags & IFF_BROADCAST) {
1737 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1738 } else {
1739 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1740 }
1741
1742 /*
1743 * Load the multicast filter.
1744 */
1745 nge_setmulti(sc);
1746
1747 /* Turn the receive filter on */
1748 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1749
1750 /*
1751 * Load the address of the RX and TX lists.
1752 */
1753 CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1754 vtophys(&sc->nge_ldata->nge_rx_list[0]));
1755 CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1756 vtophys(&sc->nge_ldata->nge_tx_list[0]));
1757
1758 /* Set RX configuration */
1759 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1760 /*
1761 * Enable hardware checksum validation for all IPv4
1762 * packets, do not reject packets with bad checksums.
1763 */
1764 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1765
1766 /*
1767 * Tell the chip to detect and strip VLAN tag info from
1768 * received frames. The tag will be provided in the extsts
1769 * field in the RX descriptors.
1770 */
1771 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1772 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1773
1774 /* Set TX configuration */
1775 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1776
1777 /*
1778 * Enable TX IPv4 checksumming on a per-packet basis.
1779 */
1780 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1781
1782 /*
1783 * Tell the chip to insert VLAN tags on a per-packet basis as
1784 * dictated by the code in the frame encapsulation routine.
1785 */
1786 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1787
1788 /* Set full/half duplex mode. */
1789 if (sc->nge_tbi) {
1790 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1791 == IFM_FDX) {
1792 NGE_SETBIT(sc, NGE_TX_CFG,
1793 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1794 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1795 } else {
1796 NGE_CLRBIT(sc, NGE_TX_CFG,
1797 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1798 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1799 }
1800 } else {
1801 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1802 NGE_SETBIT(sc, NGE_TX_CFG,
1803 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1804 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1805 } else {
1806 NGE_CLRBIT(sc, NGE_TX_CFG,
1807 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1808 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1809 }
1810 }
1811
1812 nge_tick_locked(sc);
1813
1814 /*
1815 * Enable the delivery of PHY interrupts based on
1816 * link/speed/duplex status changes. Also enable the
1817 * extsts field in the DMA descriptors (needed for
1818 * TCP/IP checksum offload on transmit).
1819 */
1820 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD|
1821 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB);
1822
1823 /*
1824 * Configure interrupt holdoff (moderation). We can
1825 * have the chip delay interrupt delivery for a certain
1826 * period. Units are in 100us, and the max setting
1827 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1828 */
1829 CSR_WRITE_4(sc, NGE_IHR, 0x01);
1830
1831 /*
1832 * Enable interrupts.
1833 */
1834 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1835#ifdef DEVICE_POLLING
1836 /*
1837 * ... only enable interrupts if we are not polling, make sure
1838 * they are off otherwise.
1839 */
1840 if (ifp->if_flags & IFF_POLLING)
1841 CSR_WRITE_4(sc, NGE_IER, 0);
1842 else
1843#endif /* DEVICE_POLLING */
1844 CSR_WRITE_4(sc, NGE_IER, 1);
1845
1846 /* Enable receiver and transmitter. */
1847 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
1848 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1849
1850 nge_ifmedia_upd(ifp);
1851
| 1680 return;
1681
1682 /*
1683 * Cancel pending I/O and free all RX/TX buffers.
1684 */
1685 nge_stop(sc);
1686
1687 if (sc->nge_tbi) {
1688 mii = NULL;
1689 } else {
1690 mii = device_get_softc(sc->nge_miibus);
1691 }
1692
1693 /* Set MAC address */
1694 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1695 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1696 ((u_int16_t *)IFP2ENADDR(sc->nge_ifp))[0]);
1697 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1698 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1699 ((u_int16_t *)IFP2ENADDR(sc->nge_ifp))[1]);
1700 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1701 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1702 ((u_int16_t *)IFP2ENADDR(sc->nge_ifp))[2]);
1703
1704 /* Init circular RX list. */
1705 if (nge_list_rx_init(sc) == ENOBUFS) {
1706 printf("nge%d: initialization failed: no "
1707 "memory for rx buffers\n", sc->nge_unit);
1708 nge_stop(sc);
1709 return;
1710 }
1711
1712 /*
1713 * Init tx descriptors.
1714 */
1715 nge_list_tx_init(sc);
1716
1717 /*
1718 * For the NatSemi chip, we have to explicitly enable the
1719 * reception of ARP frames, as well as turn on the 'perfect
1720 * match' filter where we store the station address, otherwise
1721 * we won't receive unicasts meant for this host.
1722 */
1723 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1724 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1725
1726 /* If we want promiscuous mode, set the allframes bit. */
1727 if (ifp->if_flags & IFF_PROMISC) {
1728 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1729 } else {
1730 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1731 }
1732
1733 /*
1734 * Set the capture broadcast bit to capture broadcast frames.
1735 */
1736 if (ifp->if_flags & IFF_BROADCAST) {
1737 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1738 } else {
1739 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1740 }
1741
1742 /*
1743 * Load the multicast filter.
1744 */
1745 nge_setmulti(sc);
1746
1747 /* Turn the receive filter on */
1748 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1749
1750 /*
1751 * Load the address of the RX and TX lists.
1752 */
1753 CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1754 vtophys(&sc->nge_ldata->nge_rx_list[0]));
1755 CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1756 vtophys(&sc->nge_ldata->nge_tx_list[0]));
1757
1758 /* Set RX configuration */
1759 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1760 /*
1761 * Enable hardware checksum validation for all IPv4
1762 * packets, do not reject packets with bad checksums.
1763 */
1764 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1765
1766 /*
1767 * Tell the chip to detect and strip VLAN tag info from
1768 * received frames. The tag will be provided in the extsts
1769 * field in the RX descriptors.
1770 */
1771 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1772 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1773
1774 /* Set TX configuration */
1775 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1776
1777 /*
1778 * Enable TX IPv4 checksumming on a per-packet basis.
1779 */
1780 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1781
1782 /*
1783 * Tell the chip to insert VLAN tags on a per-packet basis as
1784 * dictated by the code in the frame encapsulation routine.
1785 */
1786 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1787
1788 /* Set full/half duplex mode. */
1789 if (sc->nge_tbi) {
1790 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1791 == IFM_FDX) {
1792 NGE_SETBIT(sc, NGE_TX_CFG,
1793 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1794 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1795 } else {
1796 NGE_CLRBIT(sc, NGE_TX_CFG,
1797 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1798 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1799 }
1800 } else {
1801 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1802 NGE_SETBIT(sc, NGE_TX_CFG,
1803 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1804 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1805 } else {
1806 NGE_CLRBIT(sc, NGE_TX_CFG,
1807 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1808 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1809 }
1810 }
1811
1812 nge_tick_locked(sc);
1813
1814 /*
1815 * Enable the delivery of PHY interrupts based on
1816 * link/speed/duplex status changes. Also enable the
1817 * extsts field in the DMA descriptors (needed for
1818 * TCP/IP checksum offload on transmit).
1819 */
1820 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD|
1821 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB);
1822
1823 /*
1824 * Configure interrupt holdoff (moderation). We can
1825 * have the chip delay interrupt delivery for a certain
1826 * period. Units are in 100us, and the max setting
1827 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1828 */
1829 CSR_WRITE_4(sc, NGE_IHR, 0x01);
1830
1831 /*
1832 * Enable interrupts.
1833 */
1834 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1835#ifdef DEVICE_POLLING
1836 /*
1837 * ... only enable interrupts if we are not polling, make sure
1838 * they are off otherwise.
1839 */
1840 if (ifp->if_flags & IFF_POLLING)
1841 CSR_WRITE_4(sc, NGE_IER, 0);
1842 else
1843#endif /* DEVICE_POLLING */
1844 CSR_WRITE_4(sc, NGE_IER, 1);
1845
1846 /* Enable receiver and transmitter. */
1847 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
1848 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1849
1850 nge_ifmedia_upd(ifp);
1851
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