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if_mxge.c (171405) if_mxge.c (171500)
1/******************************************************************************
2
3Copyright (c) 2006-2007, Myricom Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8

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23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28***************************************************************************/
29
30#include <sys/cdefs.h>
1/******************************************************************************
2
3Copyright (c) 2006-2007, Myricom Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8

--- 14 unchanged lines hidden (view full) ---

23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28***************************************************************************/
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/mxge/if_mxge.c 171405 2007-07-12 16:04:55Z gallatin $");
31__FBSDID("$FreeBSD: head/sys/dev/mxge/if_mxge.c 171500 2007-07-19 16:16:00Z gallatin $");
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/linker.h>
36#include <sys/firmware.h>
37#include <sys/endian.h>
38#include <sys/sockio.h>
39#include <sys/mbuf.h>

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119 sizeof(mxge_softc_t),
120};
121
122static devclass_t mxge_devclass;
123
124/* Declare ourselves to be a child of the PCI bus.*/
125DRIVER_MODULE(mxge, pci, mxge_driver, mxge_devclass, 0, 0);
126MODULE_DEPEND(mxge, firmware, 1, 1, 1);
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/linker.h>
36#include <sys/firmware.h>
37#include <sys/endian.h>
38#include <sys/sockio.h>
39#include <sys/mbuf.h>

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119 sizeof(mxge_softc_t),
120};
121
122static devclass_t mxge_devclass;
123
124/* Declare ourselves to be a child of the PCI bus.*/
125DRIVER_MODULE(mxge, pci, mxge_driver, mxge_devclass, 0, 0);
126MODULE_DEPEND(mxge, firmware, 1, 1, 1);
127MODULE_DEPEND(mxge, zlib, 1, 1, 1);
127
128static int mxge_load_firmware(mxge_softc_t *sc);
129static int mxge_send_cmd(mxge_softc_t *sc, uint32_t cmd, mxge_cmd_t *data);
130static int mxge_close(mxge_softc_t *sc);
131static int mxge_open(mxge_softc_t *sc);
132static void mxge_tick(void *arg);
133
134static int

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140 return 0;
141 }
142 return ENXIO;
143}
144
145static void
146mxge_enable_wc(mxge_softc_t *sc)
147{
128
129static int mxge_load_firmware(mxge_softc_t *sc);
130static int mxge_send_cmd(mxge_softc_t *sc, uint32_t cmd, mxge_cmd_t *data);
131static int mxge_close(mxge_softc_t *sc);
132static int mxge_open(mxge_softc_t *sc);
133static void mxge_tick(void *arg);
134
135static int

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141 return 0;
142 }
143 return ENXIO;
144}
145
146static void
147mxge_enable_wc(mxge_softc_t *sc)
148{
149#if defined(__i386) || defined(__amd64)
148 struct mem_range_desc mrdesc;
149 vm_paddr_t pa;
150 vm_offset_t len;
151 int err, action;
152
153 sc->wc = 1;
154 len = rman_get_size(sc->mem_res);
150 struct mem_range_desc mrdesc;
151 vm_paddr_t pa;
152 vm_offset_t len;
153 int err, action;
154
155 sc->wc = 1;
156 len = rman_get_size(sc->mem_res);
155#if defined(__i386) || defined(__amd64)
156 err = pmap_change_attr((vm_offset_t) sc->sram,
157 len, PAT_WRITE_COMBINING);
158 if (err == 0)
159 return;
160 else
161 device_printf(sc->dev, "pmap_change_attr failed, %d\n",
162 err);
157 err = pmap_change_attr((vm_offset_t) sc->sram,
158 len, PAT_WRITE_COMBINING);
159 if (err == 0)
160 return;
161 else
162 device_printf(sc->dev, "pmap_change_attr failed, %d\n",
163 err);
163#endif
164 pa = rman_get_start(sc->mem_res);
165 mrdesc.mr_base = pa;
166 mrdesc.mr_len = len;
167 mrdesc.mr_flags = MDF_WRITECOMBINE;
168 action = MEMRANGE_SET_UPDATE;
169 strcpy((char *)&mrdesc.mr_owner, "mxge");
170 err = mem_range_attr_set(&mrdesc, &action);
171 if (err != 0) {
172 sc->wc = 0;
173 device_printf(sc->dev,
174 "w/c failed for pa 0x%lx, len 0x%lx, err = %d\n",
175 (unsigned long)pa, (unsigned long)len, err);
176 }
164 pa = rman_get_start(sc->mem_res);
165 mrdesc.mr_base = pa;
166 mrdesc.mr_len = len;
167 mrdesc.mr_flags = MDF_WRITECOMBINE;
168 action = MEMRANGE_SET_UPDATE;
169 strcpy((char *)&mrdesc.mr_owner, "mxge");
170 err = mem_range_attr_set(&mrdesc, &action);
171 if (err != 0) {
172 sc->wc = 0;
173 device_printf(sc->dev,
174 "w/c failed for pa 0x%lx, len 0x%lx, err = %d\n",
175 (unsigned long)pa, (unsigned long)len, err);
176 }
177#endif
177}
178
179
180/* callback to get our DMA address */
181static void
182mxge_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs,
183 int error)
184{

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418 device_printf(sc->dev,
419 "Enabled ECRC on upstream Nvidia bridge "
420 "at %d:%d:%d\n",
421 (int)bus, (int)slot, (int)func);
422 return;
423}
424#else
425static void
178}
179
180
181/* callback to get our DMA address */
182static void
183mxge_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs,
184 int error)
185{

--- 233 unchanged lines hidden (view full) ---

419 device_printf(sc->dev,
420 "Enabled ECRC on upstream Nvidia bridge "
421 "at %d:%d:%d\n",
422 (int)bus, (int)slot, (int)func);
423 return;
424}
425#else
426static void
426mxge_enable_nvidia_ecrc(mxge_softc_t *sc, device_t pdev)
427mxge_enable_nvidia_ecrc(mxge_softc_t *sc)
427{
428 device_printf(sc->dev,
429 "Nforce 4 chipset on non-x86/amd64!?!?!\n");
430 return;
431}
432#endif
433
434

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639 device_printf(sc->dev, "Driver needs %d.%d\n",
640 MXGEFW_VERSION_MAJOR, MXGEFW_VERSION_MINOR);
641 return EINVAL;
642 }
643 return 0;
644
645}
646
428{
429 device_printf(sc->dev,
430 "Nforce 4 chipset on non-x86/amd64!?!?!\n");
431 return;
432}
433#endif
434
435

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640 device_printf(sc->dev, "Driver needs %d.%d\n",
641 MXGEFW_VERSION_MAJOR, MXGEFW_VERSION_MINOR);
642 return EINVAL;
643 }
644 return 0;
645
646}
647
648static void *
649z_alloc(void *nil, u_int items, u_int size)
650{
651 void *ptr;
652
653 ptr = malloc(items * size, M_TEMP, M_NOWAIT);
654 return ptr;
655}
656
657static void
658z_free(void *nil, void *ptr)
659{
660 free(ptr, M_TEMP);
661}
662
663
647static int
648mxge_load_firmware_helper(mxge_softc_t *sc, uint32_t *limit)
649{
664static int
665mxge_load_firmware_helper(mxge_softc_t *sc, uint32_t *limit)
666{
667 z_stream zs;
668 char *inflate_buffer;
650 const struct firmware *fw;
651 const mcp_gen_header_t *hdr;
652 unsigned hdr_offset;
669 const struct firmware *fw;
670 const mcp_gen_header_t *hdr;
671 unsigned hdr_offset;
653 const char *fw_data;
654 union qualhack hack;
655 int status;
656 unsigned int i;
657 char dummy;
672 int status;
673 unsigned int i;
674 char dummy;
658
675 size_t fw_len;
659
660 fw = firmware_get(sc->fw_name);
676
677 fw = firmware_get(sc->fw_name);
661
662 if (fw == NULL) {
663 device_printf(sc->dev, "Could not find firmware image %s\n",
664 sc->fw_name);
665 return ENOENT;
666 }
678 if (fw == NULL) {
679 device_printf(sc->dev, "Could not find firmware image %s\n",
680 sc->fw_name);
681 return ENOENT;
682 }
667 if (fw->datasize > *limit ||
668 fw->datasize < MCP_HEADER_PTR_OFFSET + 4) {
669 device_printf(sc->dev, "Firmware image %s too large (%d/%d)\n",
670 sc->fw_name, (int)fw->datasize, (int) *limit);
671 status = ENOSPC;
683
684
685
686 /* setup zlib and decompress f/w */
687 bzero(&zs, sizeof (zs));
688 zs.zalloc = z_alloc;
689 zs.zfree = z_free;
690 status = inflateInit(&zs);
691 if (status != Z_OK) {
692 status = EIO;
672 goto abort_with_fw;
673 }
693 goto abort_with_fw;
694 }
674 *limit = fw->datasize;
675
695
696 /* the uncompressed size is stored as the firmware version,
697 which would otherwise go unused */
698 fw_len = (size_t) fw->version;
699 inflate_buffer = malloc(fw_len, M_TEMP, M_NOWAIT);
700 if (inflate_buffer == NULL)
701 goto abort_with_zs;
702 zs.avail_in = fw->datasize;
703 zs.next_in = __DECONST(char *, fw->data);
704 zs.avail_out = fw_len;
705 zs.next_out = inflate_buffer;
706 status = inflate(&zs, Z_FINISH);
707 if (status != Z_STREAM_END) {
708 device_printf(sc->dev, "zlib %d\n", status);
709 status = EIO;
710 goto abort_with_buffer;
711 }
712
676 /* check id */
713 /* check id */
677 fw_data = (const char *)fw->data;
678 hdr_offset = htobe32(*(const uint32_t *)
714 hdr_offset = htobe32(*(const uint32_t *)
679 (fw_data + MCP_HEADER_PTR_OFFSET));
680 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->datasize) {
715 (inflate_buffer + MCP_HEADER_PTR_OFFSET));
716 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw_len) {
681 device_printf(sc->dev, "Bad firmware file");
682 status = EIO;
717 device_printf(sc->dev, "Bad firmware file");
718 status = EIO;
683 goto abort_with_fw;
719 goto abort_with_buffer;
684 }
720 }
685 hdr = (const void*)(fw_data + hdr_offset);
721 hdr = (const void*)(inflate_buffer + hdr_offset);
686
687 status = mxge_validate_firmware(sc, hdr);
688 if (status != 0)
722
723 status = mxge_validate_firmware(sc, hdr);
724 if (status != 0)
689 goto abort_with_fw;
725 goto abort_with_buffer;
690
726
691 hack.ro_char = fw_data;
692 /* Copy the inflated firmware to NIC SRAM. */
727 /* Copy the inflated firmware to NIC SRAM. */
693 for (i = 0; i < *limit; i += 256) {
728 for (i = 0; i < fw_len; i += 256) {
694 mxge_pio_copy(sc->sram + MXGE_FW_OFFSET + i,
729 mxge_pio_copy(sc->sram + MXGE_FW_OFFSET + i,
695 hack.rw_char + i,
696 min(256U, (unsigned)(*limit - i)));
730 inflate_buffer + i,
731 min(256U, (unsigned)(fw_len - i)));
697 mb();
698 dummy = *sc->sram;
699 mb();
700 }
701
732 mb();
733 dummy = *sc->sram;
734 mb();
735 }
736
737 *limit = fw_len;
702 status = 0;
738 status = 0;
739abort_with_buffer:
740 free(inflate_buffer, M_TEMP);
741abort_with_zs:
742 inflateEnd(&zs);
703abort_with_fw:
704 firmware_put(fw, FIRMWARE_UNLOAD);
705 return status;
706}
707
708/*
709 * Enable or disable periodic RDMAs from the host to make certain
710 * chipsets resend dropped PCIe messages

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3200 TUNABLE_INT_FETCH("hw.mxge.force_firmware",
3201 &mxge_force_firmware);
3202 TUNABLE_INT_FETCH("hw.mxge.deassert_wait",
3203 &mxge_deassert_wait);
3204 TUNABLE_INT_FETCH("hw.mxge.verbose",
3205 &mxge_verbose);
3206 TUNABLE_INT_FETCH("hw.mxge.ticks", &mxge_ticks);
3207 TUNABLE_INT_FETCH("hw.mxge.lro_cnt", &sc->lro_cnt);
743abort_with_fw:
744 firmware_put(fw, FIRMWARE_UNLOAD);
745 return status;
746}
747
748/*
749 * Enable or disable periodic RDMAs from the host to make certain
750 * chipsets resend dropped PCIe messages

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3240 TUNABLE_INT_FETCH("hw.mxge.force_firmware",
3241 &mxge_force_firmware);
3242 TUNABLE_INT_FETCH("hw.mxge.deassert_wait",
3243 &mxge_deassert_wait);
3244 TUNABLE_INT_FETCH("hw.mxge.verbose",
3245 &mxge_verbose);
3246 TUNABLE_INT_FETCH("hw.mxge.ticks", &mxge_ticks);
3247 TUNABLE_INT_FETCH("hw.mxge.lro_cnt", &sc->lro_cnt);
3208 printf("%d %d\n", sc->lro_cnt, mxge_lro_cnt);
3209 if (sc->lro_cnt != 0)
3210 mxge_lro_cnt = sc->lro_cnt;
3211
3212 if (bootverbose)
3213 mxge_verbose = 1;
3214 if (mxge_intr_coal_delay < 0 || mxge_intr_coal_delay > 10*1000)
3215 mxge_intr_coal_delay = 30;
3216 if (mxge_ticks == 0)

--- 267 unchanged lines hidden --- 		3248 if (sc->lro_cnt != 0)
3249 mxge_lro_cnt = sc->lro_cnt;
3250
3251 if (bootverbose)
3252 mxge_verbose = 1;
3253 if (mxge_intr_coal_delay < 0 || mxge_intr_coal_delay > 10*1000)
3254 mxge_intr_coal_delay = 30;
3255 if (mxge_ticks == 0)

--- 267 unchanged lines hidden ---