46 47#ifndef MRSAS_H 48#define MRSAS_H 49 50#include <sys/param.h> /* defines used in kernel.h */ 51#include <sys/module.h> 52#include <sys/systm.h> 53#include <sys/proc.h> 54#include <sys/errno.h> 55#include <sys/kernel.h> /* types used in module initialization */ 56#include <sys/conf.h> /* cdevsw struct */ 57#include <sys/uio.h> /* uio struct */ 58#include <sys/malloc.h> 59#include <sys/bus.h> /* structs, prototypes for pci bus stuff */ 60 61#include <machine/bus.h> 62#include <sys/rman.h> 63#include <machine/resource.h> 64#include <machine/atomic.h> 65 66#include <dev/pci/pcivar.h> /* For pci_get macros! */ 67#include <dev/pci/pcireg.h> 68 69#include <sys/types.h> 70#include <sys/sysctl.h> 71#include <sys/stat.h> 72#include <sys/taskqueue.h> 73#include <sys/poll.h> 74#include <sys/selinfo.h> 75 76/* 77 * Device IDs and PCI 78 */ 79#define MRSAS_TBOLT 0x005b 80#define MRSAS_INVADER 0x005d 81#define MRSAS_FURY 0x005f 82#define MRSAS_PCI_BAR0 0x10 83#define MRSAS_PCI_BAR1 0x14 84#define MRSAS_PCI_BAR2 0x1C 85 86/* 87 * Firmware State Defines 88 */ 89#define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF 90#define MRSAS_FWSTATE_SGE_MASK 0x00FF0000 91#define MRSAS_FW_STATE_CHNG_INTERRUPT 1 92 93/* 94 * Message Frame Defines 95 */ 96#define MRSAS_SENSE_LEN 96 97#define MRSAS_FUSION_MAX_RESET_TRIES 3 98 99/* 100 * Miscellaneous Defines 101 */ 102#define BYTE_ALIGNMENT 1 103#define MRSAS_MAX_NAME_LENGTH 32 104#define MRSAS_VERSION "06.704.01.01-fbsd" 105#define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF 106#define MRSAS_DEFAULT_TIMEOUT 0x14 //temp 107#define DONE 0 108#define MRSAS_PAGE_SIZE 4096 109#define MRSAS_RESET_NOTICE_INTERVAL 5 110#define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */ 111#define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */ 112#define THRESHOLD_REPLY_COUNT 50 113 114/* 115 Boolean types 116*/ 117#if (__FreeBSD_version < 901000) 118 typedef enum _boolean { false, true } boolean; 119#endif 120enum err { SUCCESS, FAIL }; 121 122MALLOC_DECLARE(M_MRSAS); 123SYSCTL_DECL(_hw_mrsas); 124 125#define MRSAS_INFO (1 << 0) 126#define MRSAS_TRACE (1 << 1) 127#define MRSAS_FAULT (1 << 2) 128#define MRSAS_OCR (1 << 3) 129#define MRSAS_TOUT MRSAS_OCR 130#define MRSAS_AEN (1 << 4) 131#define MRSAS_PRL11 (1 << 5) 132 133#define mrsas_dprint(sc, level, msg, args...) \ 134do { \ 135 if (sc->mrsas_debug & level) \ 136 device_printf(sc->mrsas_dev, msg, ##args); \ 137} while (0) 138 139 140/**************************************************************************** 141 * Raid Context structure which describes MegaRAID specific IO Paramenters 142 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 143 ****************************************************************************/ 144 145typedef struct _RAID_CONTEXT { 146 u_int8_t Type:4; // 0x00 147 u_int8_t nseg:4; // 0x00 148 u_int8_t resvd0; // 0x01 149 u_int16_t timeoutValue; // 0x02 -0x03 150 u_int8_t regLockFlags; // 0x04 151 u_int8_t resvd1; // 0x05 152 u_int16_t VirtualDiskTgtId; // 0x06 -0x07 153 u_int64_t regLockRowLBA; // 0x08 - 0x0F 154 u_int32_t regLockLength; // 0x10 - 0x13 155 u_int16_t nextLMId; // 0x14 - 0x15 156 u_int8_t exStatus; // 0x16 157 u_int8_t status; // 0x17 status 158 u_int8_t RAIDFlags; // 0x18 resvd[7:6],ioSubType[5:4],resvd[3:1],preferredCpu[0] 159 u_int8_t numSGE; // 0x19 numSge; not including chain entries 160 u_int16_t configSeqNum; // 0x1A -0x1B 161 u_int8_t spanArm; // 0x1C span[7:5], arm[4:0] 162 u_int8_t resvd2[3]; // 0x1D-0x1f 163} RAID_CONTEXT; 164 165 166/************************************************************************* 167 * MPI2 Defines 168 ************************************************************************/ 169 170#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 171#define MPI2_WHOINIT_HOST_DRIVER (0x04) 172#define MPI2_VERSION_MAJOR (0x02) 173#define MPI2_VERSION_MINOR (0x00) 174#define MPI2_VERSION_MAJOR_MASK (0xFF00) 175#define MPI2_VERSION_MAJOR_SHIFT (8) 176#define MPI2_VERSION_MINOR_MASK (0x00FF) 177#define MPI2_VERSION_MINOR_SHIFT (0) 178#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 179 MPI2_VERSION_MINOR) 180#define MPI2_HEADER_VERSION_UNIT (0x10) 181#define MPI2_HEADER_VERSION_DEV (0x00) 182#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 183#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 184#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 185#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 186#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 187#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 188#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 189#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 190#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 191#define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 192#define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 193#define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 194#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 195#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 196#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 197#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 198#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 199#define MPI2_SCSIIO_CONTROL_READ (0x02000000) 200#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 201#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 202#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 203#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 204#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 205#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 206#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 207#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 208#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 209#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 210#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 211#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 212 213#ifndef MPI2_POINTER 214#define MPI2_POINTER * 215#endif 216 217 218/*************************************** 219 * MPI2 Structures 220 ***************************************/ 221 222typedef struct _MPI25_IEEE_SGE_CHAIN64 223{ 224 u_int64_t Address; 225 u_int32_t Length; 226 u_int16_t Reserved1; 227 u_int8_t NextChainOffset; 228 u_int8_t Flags; 229} MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 230 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 231 232typedef struct _MPI2_SGE_SIMPLE_UNION 233{ 234 u_int32_t FlagsLength; 235 union 236 { 237 u_int32_t Address32; 238 u_int64_t Address64; 239 } u; 240} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 241 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 242 243typedef struct 244{ 245 u_int8_t CDB[20]; /* 0x00 */ 246 u_int32_t PrimaryReferenceTag; /* 0x14 */ 247 u_int16_t PrimaryApplicationTag; /* 0x18 */ 248 u_int16_t PrimaryApplicationTagMask; /* 0x1A */ 249 u_int32_t TransferLength; /* 0x1C */ 250} MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32, 251 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t; 252 253typedef struct _MPI2_SGE_CHAIN_UNION 254{ 255 u_int16_t Length; 256 u_int8_t NextChainOffset; 257 u_int8_t Flags; 258 union 259 { 260 u_int32_t Address32; 261 u_int64_t Address64; 262 } u; 263} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 264 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 265 266typedef struct _MPI2_IEEE_SGE_SIMPLE32 267{ 268 u_int32_t Address; 269 u_int32_t FlagsLength; 270} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 271 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 272typedef struct _MPI2_IEEE_SGE_SIMPLE64 273{ 274 u_int64_t Address; 275 u_int32_t Length; 276 u_int16_t Reserved1; 277 u_int8_t Reserved2; 278 u_int8_t Flags; 279} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 280 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 281 282typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 283{ 284 MPI2_IEEE_SGE_SIMPLE32 Simple32; 285 MPI2_IEEE_SGE_SIMPLE64 Simple64; 286} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 287 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 288 289typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 290typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 291 292typedef union _MPI2_IEEE_SGE_CHAIN_UNION 293{ 294 MPI2_IEEE_SGE_CHAIN32 Chain32; 295 MPI2_IEEE_SGE_CHAIN64 Chain64; 296} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 297 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 298 299typedef union _MPI2_SGE_IO_UNION 300{ 301 MPI2_SGE_SIMPLE_UNION MpiSimple; 302 MPI2_SGE_CHAIN_UNION MpiChain; 303 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 304 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 305} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 306 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 307 308typedef union 309{ 310 u_int8_t CDB32[32]; 311 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 312 MPI2_SGE_SIMPLE_UNION SGE; 313} MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION, 314 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t; 315 316/* 317 * RAID SCSI IO Request Message 318 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 319 */ 320typedef struct _MPI2_RAID_SCSI_IO_REQUEST 321{ 322 u_int16_t DevHandle; /* 0x00 */ 323 u_int8_t ChainOffset; /* 0x02 */ 324 u_int8_t Function; /* 0x03 */ 325 u_int16_t Reserved1; /* 0x04 */ 326 u_int8_t Reserved2; /* 0x06 */ 327 u_int8_t MsgFlags; /* 0x07 */ 328 u_int8_t VP_ID; /* 0x08 */ 329 u_int8_t VF_ID; /* 0x09 */ 330 u_int16_t Reserved3; /* 0x0A */ 331 u_int32_t SenseBufferLowAddress; /* 0x0C */ 332 u_int16_t SGLFlags; /* 0x10 */ 333 u_int8_t SenseBufferLength; /* 0x12 */ 334 u_int8_t Reserved4; /* 0x13 */ 335 u_int8_t SGLOffset0; /* 0x14 */ 336 u_int8_t SGLOffset1; /* 0x15 */ 337 u_int8_t SGLOffset2; /* 0x16 */ 338 u_int8_t SGLOffset3; /* 0x17 */ 339 u_int32_t SkipCount; /* 0x18 */ 340 u_int32_t DataLength; /* 0x1C */ 341 u_int32_t BidirectionalDataLength; /* 0x20 */ 342 u_int16_t IoFlags; /* 0x24 */ 343 u_int16_t EEDPFlags; /* 0x26 */ 344 u_int32_t EEDPBlockSize; /* 0x28 */ 345 u_int32_t SecondaryReferenceTag; /* 0x2C */ 346 u_int16_t SecondaryApplicationTag; /* 0x30 */ 347 u_int16_t ApplicationTagTranslationMask; /* 0x32 */ 348 u_int8_t LUN[8]; /* 0x34 */ 349 u_int32_t Control; /* 0x3C */ 350 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 351 RAID_CONTEXT RaidContext; /* 0x60 */ 352 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 353} MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST, 354 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t; 355 356/* 357 * MPT RAID MFA IO Descriptor. 358 */ 359typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR { 360 u_int32_t RequestFlags : 8; 361 u_int32_t MessageAddress1 : 24; /* bits 31:8*/ 362 u_int32_t MessageAddress2; /* bits 61:32 */ 363} MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR; 364 365/* Default Request Descriptor */ 366typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 367{ 368 u_int8_t RequestFlags; /* 0x00 */ 369 u_int8_t MSIxIndex; /* 0x01 */ 370 u_int16_t SMID; /* 0x02 */ 371 u_int16_t LMID; /* 0x04 */ 372 u_int16_t DescriptorTypeDependent; /* 0x06 */ 373} MPI2_DEFAULT_REQUEST_DESCRIPTOR, 374 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 375 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 376 377/* High Priority Request Descriptor */ 378typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 379{ 380 u_int8_t RequestFlags; /* 0x00 */ 381 u_int8_t MSIxIndex; /* 0x01 */ 382 u_int16_t SMID; /* 0x02 */ 383 u_int16_t LMID; /* 0x04 */ 384 u_int16_t Reserved1; /* 0x06 */ 385} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 386 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 387 Mpi2HighPriorityRequestDescriptor_t, 388 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 389 390/* SCSI IO Request Descriptor */ 391typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 392{ 393 u_int8_t RequestFlags; /* 0x00 */ 394 u_int8_t MSIxIndex; /* 0x01 */ 395 u_int16_t SMID; /* 0x02 */ 396 u_int16_t LMID; /* 0x04 */ 397 u_int16_t DevHandle; /* 0x06 */ 398} MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 399 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 400 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 401 402/* SCSI Target Request Descriptor */ 403typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 404{ 405 u_int8_t RequestFlags; /* 0x00 */ 406 u_int8_t MSIxIndex; /* 0x01 */ 407 u_int16_t SMID; /* 0x02 */ 408 u_int16_t LMID; /* 0x04 */ 409 u_int16_t IoIndex; /* 0x06 */ 410} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 411 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 412 Mpi2SCSITargetRequestDescriptor_t, 413 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 414 415/* RAID Accelerator Request Descriptor */ 416typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 417{ 418 u_int8_t RequestFlags; /* 0x00 */ 419 u_int8_t MSIxIndex; /* 0x01 */ 420 u_int16_t SMID; /* 0x02 */ 421 u_int16_t LMID; /* 0x04 */ 422 u_int16_t Reserved; /* 0x06 */ 423} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 424 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 425 Mpi2RAIDAcceleratorRequestDescriptor_t, 426 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 427 428/* union of Request Descriptors */ 429typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION 430{ 431 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 432 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 433 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 434 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 435 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 436 MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 437 union { 438 struct { 439 u_int32_t low; 440 u_int32_t high; 441 } u; 442 u_int64_t Words; 443 } addr; 444} MRSAS_REQUEST_DESCRIPTOR_UNION; 445 446/* Default Reply Descriptor */ 447typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 448{ 449 u_int8_t ReplyFlags; /* 0x00 */ 450 u_int8_t MSIxIndex; /* 0x01 */ 451 u_int16_t DescriptorTypeDependent1; /* 0x02 */ 452 u_int32_t DescriptorTypeDependent2; /* 0x04 */ 453} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 454 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 455 456/* Address Reply Descriptor */ 457typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 458{ 459 u_int8_t ReplyFlags; /* 0x00 */ 460 u_int8_t MSIxIndex; /* 0x01 */ 461 u_int16_t SMID; /* 0x02 */ 462 u_int32_t ReplyFrameAddress; /* 0x04 */ 463} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 464 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 465 466/* SCSI IO Success Reply Descriptor */ 467typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 468{ 469 u_int8_t ReplyFlags; /* 0x00 */ 470 u_int8_t MSIxIndex; /* 0x01 */ 471 u_int16_t SMID; /* 0x02 */ 472 u_int16_t TaskTag; /* 0x04 */ 473 u_int16_t Reserved1; /* 0x06 */ 474} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 475 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 476 Mpi2SCSIIOSuccessReplyDescriptor_t, 477 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 478 479/* TargetAssist Success Reply Descriptor */ 480typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 481{ 482 u_int8_t ReplyFlags; /* 0x00 */ 483 u_int8_t MSIxIndex; /* 0x01 */ 484 u_int16_t SMID; /* 0x02 */ 485 u_int8_t SequenceNumber; /* 0x04 */ 486 u_int8_t Reserved1; /* 0x05 */ 487 u_int16_t IoIndex; /* 0x06 */ 488} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 489 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 490 Mpi2TargetAssistSuccessReplyDescriptor_t, 491 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 492 493/* Target Command Buffer Reply Descriptor */ 494typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 495{ 496 u_int8_t ReplyFlags; /* 0x00 */ 497 u_int8_t MSIxIndex; /* 0x01 */ 498 u_int8_t VP_ID; /* 0x02 */ 499 u_int8_t Flags; /* 0x03 */ 500 u_int16_t InitiatorDevHandle; /* 0x04 */ 501 u_int16_t IoIndex; /* 0x06 */ 502} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 503 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 504 Mpi2TargetCommandBufferReplyDescriptor_t, 505 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 506 507/* RAID Accelerator Success Reply Descriptor */ 508typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 509{ 510 u_int8_t ReplyFlags; /* 0x00 */ 511 u_int8_t MSIxIndex; /* 0x01 */ 512 u_int16_t SMID; /* 0x02 */ 513 u_int32_t Reserved; /* 0x04 */ 514} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 515 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 516 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 517 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 518 519/* union of Reply Descriptors */ 520typedef union _MPI2_REPLY_DESCRIPTORS_UNION 521{ 522 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 523 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 524 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 525 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 526 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 527 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 528 u_int64_t Words; 529} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 530 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 531 532typedef struct { 533 volatile unsigned int val; 534} atomic_t; 535 536#define atomic_read(v) atomic_load_acq_int(&(v)->val) 537#define atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 538#define atomic_dec(v) atomic_fetchadd_int(&(v)->val, -1) 539#define atomic_inc(v) atomic_fetchadd_int(&(v)->val, 1) 540 541/* IOCInit Request message */ 542typedef struct _MPI2_IOC_INIT_REQUEST 543{ 544 u_int8_t WhoInit; /* 0x00 */ 545 u_int8_t Reserved1; /* 0x01 */ 546 u_int8_t ChainOffset; /* 0x02 */ 547 u_int8_t Function; /* 0x03 */ 548 u_int16_t Reserved2; /* 0x04 */ 549 u_int8_t Reserved3; /* 0x06 */ 550 u_int8_t MsgFlags; /* 0x07 */ 551 u_int8_t VP_ID; /* 0x08 */ 552 u_int8_t VF_ID; /* 0x09 */ 553 u_int16_t Reserved4; /* 0x0A */ 554 u_int16_t MsgVersion; /* 0x0C */ 555 u_int16_t HeaderVersion; /* 0x0E */ 556 u_int32_t Reserved5; /* 0x10 */ 557 u_int16_t Reserved6; /* 0x14 */ 558 u_int8_t Reserved7; /* 0x16 */ 559 u_int8_t HostMSIxVectors; /* 0x17 */ 560 u_int16_t Reserved8; /* 0x18 */ 561 u_int16_t SystemRequestFrameSize; /* 0x1A */ 562 u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 563 u_int16_t ReplyFreeQueueDepth; /* 0x1E */ 564 u_int32_t SenseBufferAddressHigh; /* 0x20 */ 565 u_int32_t SystemReplyAddressHigh; /* 0x24 */ 566 u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */ 567 u_int64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 568 u_int64_t ReplyFreeQueueAddress; /* 0x38 */ 569 u_int64_t TimeStamp; /* 0x40 */ 570} MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 571 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 572 573/* 574 * MR private defines 575 */ 576#define MR_PD_INVALID 0xFFFF 577#define MAX_SPAN_DEPTH 8 578#define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 579#define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 580#define MAX_ROW_SIZE 32 581#define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 582#define MAX_LOGICAL_DRIVES 64 583#define MAX_LOGICAL_DRIVES_EXT 256 584 585#define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 586#define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 587 588#define MAX_ARRAYS 128 589#define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 590 591#define MAX_ARRAYS_EXT 256 592#define MAX_API_ARRAYS_EXT MAX_ARRAYS_EXT 593 594#define MAX_PHYSICAL_DEVICES 256 595#define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 596#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 // get the mapping information of this LD 597 598 599#define MRSAS_MAX_PD_CHANNELS 1 600#define MRSAS_MAX_LD_CHANNELS 1 601#define MRSAS_MAX_DEV_PER_CHANNEL 256 602#define MRSAS_DEFAULT_INIT_ID -1 603#define MRSAS_MAX_LUN 8 604#define MRSAS_DEFAULT_CMD_PER_LUN 256 605#define MRSAS_MAX_PD (MRSAS_MAX_PD_CHANNELS * \ 606 MRSAS_MAX_DEV_PER_CHANNEL) 607#define MRSAS_MAX_LD_IDS (MRSAS_MAX_LD_CHANNELS * \ 608 MRSAS_MAX_DEV_PER_CHANNEL) 609 610 611#define VD_EXT_DEBUG 0 612 613 614/******************************************************************* 615 * RAID map related structures 616 ********************************************************************/ 617#pragma pack(1) 618typedef struct _MR_DEV_HANDLE_INFO { 619 u_int16_t curDevHdl; // the device handle currently used by fw to issue the command. 620 u_int8_t validHandles; // bitmap of valid device handles. 621 u_int8_t reserved; 622 u_int16_t devHandle[2]; // 0x04 dev handles for all the paths. 623} MR_DEV_HANDLE_INFO; 624#pragma pack() 625 626typedef struct _MR_ARRAY_INFO { 627 u_int16_t pd[MAX_RAIDMAP_ROW_SIZE]; 628} MR_ARRAY_INFO; // 0x40, Total Size 629 630typedef struct _MR_QUAD_ELEMENT { 631 u_int64_t logStart; // 0x00 632 u_int64_t logEnd; // 0x08 633 u_int64_t offsetInSpan; // 0x10 634 u_int32_t diff; // 0x18 635 u_int32_t reserved1; // 0x1C 636} MR_QUAD_ELEMENT; // 0x20, Total size 637 638typedef struct _MR_SPAN_INFO { 639 u_int32_t noElements; // 0x00 640 u_int32_t reserved1; // 0x04 641 MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; // 0x08 642} MR_SPAN_INFO; // 0x108, Total size 643 644typedef struct _MR_LD_SPAN_ { // SPAN structure 645 u_int64_t startBlk; // 0x00, starting block number in array 646 u_int64_t numBlks; // 0x08, number of blocks 647 u_int16_t arrayRef; // 0x10, array reference 648 u_int8_t spanRowSize; // 0x11, span row size 649 u_int8_t spanRowDataSize; // 0x12, span row data size 650 u_int8_t reserved[4]; // 0x13, reserved 651} MR_LD_SPAN; // 0x18, Total Size 652 653typedef struct _MR_SPAN_BLOCK_INFO { 654 u_int64_t num_rows; // number of rows/span 655 MR_LD_SPAN span; // 0x08 656 MR_SPAN_INFO block_span_info; // 0x20 657} MR_SPAN_BLOCK_INFO; 658 659typedef struct _MR_LD_RAID { 660 struct { 661 u_int32_t fpCapable :1; 662 u_int32_t reserved5 :3; 663 u_int32_t ldPiMode :4; 664 u_int32_t pdPiMode :4; // Every Pd has to be same. 665 u_int32_t encryptionType :8; // FDE or ctlr encryption (MR_LD_ENCRYPTION_TYPE) 666 u_int32_t fpWriteCapable :1; 667 u_int32_t fpReadCapable :1; 668 u_int32_t fpWriteAcrossStripe :1; 669 u_int32_t fpReadAcrossStripe :1; 670 u_int32_t fpNonRWCapable :1; // TRUE if supporting Non RW IO 671 u_int32_t reserved4 :7; 672 } capability; // 0x00 673 u_int32_t reserved6; 674 u_int64_t size; // 0x08, LD size in blocks 675 676 u_int8_t spanDepth; // 0x10, Total Number of Spans 677 u_int8_t level; // 0x11, RAID level 678 u_int8_t stripeShift; // 0x12, shift-count to get stripe size (0=512, 1=1K, 7=64K, etc.) 679 u_int8_t rowSize; // 0x13, number of disks in a row 680 681 u_int8_t rowDataSize; // 0x14, number of data disks in a row 682 u_int8_t writeMode; // 0x15, WRITE_THROUGH or WRITE_BACK 683 u_int8_t PRL; // 0x16, To differentiate between RAID1 and RAID1E 684 u_int8_t SRL; // 0x17 685 686 u_int16_t targetId; // 0x18, ld Target Id. 687 u_int8_t ldState; // 0x1a, state of ld, state corresponds to MR_LD_STATE 688 u_int8_t regTypeReqOnWrite;// 0x1b, Pre calculate region type requests based on MFC etc.. 689 u_int8_t modFactor; // 0x1c, same as rowSize, 690 u_int8_t regTypeReqOnRead; // 0x1d, region lock type used for read, valid only if regTypeOnReadIsValid=1 691 u_int16_t seqNum; // 0x1e, LD sequence number 692 693 struct { 694 u_int32_t ldSyncRequired:1; // This LD requires sync command before completing 695 u_int32_t regTypeReqOnReadLsValid:1; // Qualifier for regTypeOnRead 696 u_int32_t reserved:30; 697 } flags; // 0x20 698 699 u_int8_t LUN[8]; // 0x24, 8 byte LUN field used for SCSI 700 u_int8_t fpIoTimeoutForLd; // 0x2C, timeout value for FP IOs 701 u_int8_t reserved2[3]; // 0x2D 702 u_int32_t logicalBlockLength; // 0x30 Logical block size for the LD 703 struct { 704 u_int32_t LdPiExp:4; // 0x34, P_I_EXPONENT for ReadCap 16 705 u_int32_t LdLogicalBlockExp:4; // 0x34, LOGICAL BLOCKS PER PHYS BLOCK 706 u_int32_t reserved1:24; // 0x34 707 } exponent; 708 u_int8_t reserved3[0x80-0x38]; // 0x38 709} MR_LD_RAID; // 0x80, Total Size 710 711typedef struct _MR_LD_SPAN_MAP { 712 MR_LD_RAID ldRaid; // 0x00 713 u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; // 0x80, needed for GET_ARM() - R0/1/5 only. 714 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; // 0xA0 715} MR_LD_SPAN_MAP; // 0x9E0 716 717typedef struct _MR_FW_RAID_MAP { 718 u_int32_t totalSize; // total size of this structure, including this field. 719 union { 720 struct { // Simple method of version checking variables 721 u_int32_t maxLd; 722 u_int32_t maxSpanDepth; 723 u_int32_t maxRowSize; 724 u_int32_t maxPdCount; 725 u_int32_t maxArrays; 726 } validationInfo; 727 u_int32_t version[5]; 728 u_int32_t reserved1[5]; 729 } raid_desc; 730 u_int32_t ldCount; // count of lds. 731 u_int32_t Reserved1; 732 u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS]; // 0x20 733 // This doesn't correspond to 734 // FW Ld Tgt Id to LD, but will purge. For example: if tgt Id is 4 735 // and FW LD is 2, and there is only one LD, FW will populate the 736 // array like this. [0xFF, 0xFF, 0xFF, 0xFF, 0x0,.....]. This is to 737 // help reduce the entire strcture size if there are few LDs or 738 // driver is looking info for 1 LD only. 739 u_int8_t fpPdIoTimeoutSec; // timeout value used by driver in FP IOs 740 u_int8_t reserved2[7]; 741 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; // 0x00a8 742 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; // 0x20a8 743 MR_LD_SPAN_MAP ldSpanMap[1]; // 0x28a8-[0-MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS+1]; 744} MR_FW_RAID_MAP; // 0x3288, Total Size 745 746 747typedef struct _MR_FW_RAID_MAP_EXT { 748 /* Not used in new map */ 749 u_int32_t reserved; 750 751 union { 752 struct { 753 u_int32_t maxLd; 754 u_int32_t maxSpanDepth; 755 u_int32_t maxRowSize; 756 u_int32_t maxPdCount; 757 u_int32_t maxArrays; 758 } validationInfo; 759 u_int32_t version[5]; 760 u_int32_t reserved1[5]; 761 }fw_raid_desc; 762 763 u_int8_t fpPdIoTimeoutSec; 764 u_int8_t reserved2[7]; 765 766 u_int16_t ldCount; 767 u_int16_t arCount; 768 u_int16_t spanCount; 769 u_int16_t reserve3; 770 771 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 772 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 773 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 774 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT]; 775} MR_FW_RAID_MAP_EXT; 776 777 778typedef struct _MR_DRV_RAID_MAP { 779 /* total size of this structure, including this field. 780 * This feild will be manupulated by driver for ext raid map, 781 * else pick the value from firmware raid map. 782 */ 783 u_int32_t totalSize; 784 785 union { 786 struct { 787 u_int32_t maxLd; 788 u_int32_t maxSpanDepth; 789 u_int32_t maxRowSize; 790 u_int32_t maxPdCount; 791 u_int32_t maxArrays; 792 } validationInfo; 793 u_int32_t version[5]; 794 u_int32_t reserved1[5]; 795 }drv_raid_desc; 796 797 /* timeout value used by driver in FP IOs*/ 798 u_int8_t fpPdIoTimeoutSec; 799 u_int8_t reserved2[7]; 800 801 u_int16_t ldCount; 802 u_int16_t arCount; 803 u_int16_t spanCount; 804 u_int16_t reserve3; 805 806 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 807 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 808 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 809 MR_LD_SPAN_MAP ldSpanMap[1]; 810 811}MR_DRV_RAID_MAP; 812 813/* Driver raid map size is same as raid map ext 814 * MR_DRV_RAID_MAP_ALL is created to sync with old raid. 815 * And it is mainly for code re-use purpose. 816 */ 817 818#pragma pack(1) 819typedef struct _MR_DRV_RAID_MAP_ALL { 820 821 MR_DRV_RAID_MAP raidMap; 822 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT - 1]; 823}MR_DRV_RAID_MAP_ALL; 824#pragma pack() 825 826typedef struct _LD_LOAD_BALANCE_INFO 827{ 828 u_int8_t loadBalanceFlag; 829 u_int8_t reserved1; 830 u_int16_t raid1DevHandle[2]; 831 atomic_t scsi_pending_cmds[2]; 832 u_int64_t last_accessed_block[2]; 833} LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO; 834 835/* SPAN_SET is info caclulated from span info from Raid map per ld */ 836typedef struct _LD_SPAN_SET { 837 u_int64_t log_start_lba; 838 u_int64_t log_end_lba; 839 u_int64_t span_row_start; 840 u_int64_t span_row_end; 841 u_int64_t data_strip_start; 842 u_int64_t data_strip_end; 843 u_int64_t data_row_start; 844 u_int64_t data_row_end; 845 u_int8_t strip_offset[MAX_SPAN_DEPTH]; 846 u_int32_t span_row_data_width; 847 u_int32_t diff; 848 u_int32_t reserved[2]; 849}LD_SPAN_SET, *PLD_SPAN_SET; 850 851typedef struct LOG_BLOCK_SPAN_INFO { 852 LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 853}LD_SPAN_INFO, *PLD_SPAN_INFO; 854 855#pragma pack(1) 856typedef struct _MR_FW_RAID_MAP_ALL { 857 MR_FW_RAID_MAP raidMap; 858 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 859} MR_FW_RAID_MAP_ALL; 860#pragma pack() 861 862struct IO_REQUEST_INFO { 863 u_int64_t ldStartBlock; 864 u_int32_t numBlocks; 865 u_int16_t ldTgtId; 866 u_int8_t isRead; 867 u_int16_t devHandle; 868 u_int64_t pdBlock; 869 u_int8_t fpOkForIo; 870 u_int8_t IoforUnevenSpan; 871 u_int8_t start_span; 872 u_int8_t reserved; 873 u_int64_t start_row; 874}; 875 876typedef struct _MR_LD_TARGET_SYNC { 877 u_int8_t targetId; 878 u_int8_t reserved; 879 u_int16_t seqNum; 880} MR_LD_TARGET_SYNC; 881 882#define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 883#define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 884#define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 885#define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 886#define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 887#define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 888#define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 889 890union desc_value { 891 u_int64_t word; 892 struct { 893 u_int32_t low; 894 u_int32_t high; 895 } u; 896}; 897 898/******************************************************************* 899 * Temporary command 900 ********************************************************************/ 901struct mrsas_tmp_dcmd { 902 bus_dma_tag_t tmp_dcmd_tag; // tag for tmp DMCD cmd 903 bus_dmamap_t tmp_dcmd_dmamap; // dmamap for tmp DCMD cmd 904 void *tmp_dcmd_mem; // virtual addr of tmp DCMD cmd 905 bus_addr_t tmp_dcmd_phys_addr; //physical addr of tmp DCMD 906}; 907 908/******************************************************************* 909 * Register set, included legacy controllers 1068 and 1078, 910 * structure extended for 1078 registers 911 ********************************************************************/ 912#pragma pack(1) 913typedef struct _mrsas_register_set { 914 u_int32_t doorbell; /*0000h*/ 915 u_int32_t fusion_seq_offset; /*0004h*/ 916 u_int32_t fusion_host_diag; /*0008h*/ 917 u_int32_t reserved_01; /*000Ch*/ 918 919 u_int32_t inbound_msg_0; /*0010h*/ 920 u_int32_t inbound_msg_1; /*0014h*/ 921 u_int32_t outbound_msg_0; /*0018h*/ 922 u_int32_t outbound_msg_1; /*001Ch*/ 923 924 u_int32_t inbound_doorbell; /*0020h*/ 925 u_int32_t inbound_intr_status; /*0024h*/ 926 u_int32_t inbound_intr_mask; /*0028h*/ 927 928 u_int32_t outbound_doorbell; /*002Ch*/ 929 u_int32_t outbound_intr_status; /*0030h*/ 930 u_int32_t outbound_intr_mask; /*0034h*/ 931 932 u_int32_t reserved_1[2]; /*0038h*/ 933 934 u_int32_t inbound_queue_port; /*0040h*/ 935 u_int32_t outbound_queue_port; /*0044h*/ 936 937 u_int32_t reserved_2[9]; /*0048h*/ 938 u_int32_t reply_post_host_index; /*006Ch*/ 939 u_int32_t reserved_2_2[12]; /*0070h*/ 940 941 u_int32_t outbound_doorbell_clear; /*00A0h*/ 942 943 u_int32_t reserved_3[3]; /*00A4h*/ 944 945 u_int32_t outbound_scratch_pad ; /*00B0h*/ 946 u_int32_t outbound_scratch_pad_2; /*00B4h*/ 947 948 u_int32_t reserved_4[2]; /*00B8h*/ 949 950 u_int32_t inbound_low_queue_port ; /*00C0h*/ 951 952 u_int32_t inbound_high_queue_port ; /*00C4h*/ 953 954 u_int32_t reserved_5; /*00C8h*/ 955 u_int32_t res_6[11]; /*CCh*/ 956 u_int32_t host_diag; 957 u_int32_t seq_offset; 958 u_int32_t index_registers[807]; /*00CCh*/ 959 960} mrsas_reg_set; 961#pragma pack() 962 963/******************************************************************* 964 * Firmware Interface Defines 965 ******************************************************************* 966 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker 967 * for protocol between the software and firmware. Commands are 968 * issued using "message frames". 969 ******************************************************************/ 970/* 971 * FW posts its state in upper 4 bits of outbound_msg_0 register 972 */ 973#define MFI_STATE_MASK 0xF0000000 974#define MFI_STATE_UNDEFINED 0x00000000 975#define MFI_STATE_BB_INIT 0x10000000 976#define MFI_STATE_FW_INIT 0x40000000 977#define MFI_STATE_WAIT_HANDSHAKE 0x60000000 978#define MFI_STATE_FW_INIT_2 0x70000000 979#define MFI_STATE_DEVICE_SCAN 0x80000000 980#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 981#define MFI_STATE_FLUSH_CACHE 0xA0000000 982#define MFI_STATE_READY 0xB0000000 983#define MFI_STATE_OPERATIONAL 0xC0000000 984#define MFI_STATE_FAULT 0xF0000000 985#define MFI_RESET_REQUIRED 0x00000001 986#define MFI_RESET_ADAPTER 0x00000002 987#define MEGAMFI_FRAME_SIZE 64 988#define MRSAS_MFI_FRAME_SIZE 1024 989#define MRSAS_MFI_SENSE_SIZE 128 990 991/* 992 * During FW init, clear pending cmds & reset state using inbound_msg_0 993 * 994 * ABORT : Abort all pending cmds 995 * READY : Move from OPERATIONAL to READY state; discard queue info 996 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 997 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 998 * HOTPLUG : Resume from Hotplug 999 * MFI_STOP_ADP : Send signal to FW to stop processing 1000 */ 1001 1002#define WRITE_SEQUENCE_OFFSET (0x0000000FC) // I20 1003#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) // I20 1004#define DIAG_WRITE_ENABLE (0x00000080) 1005#define DIAG_RESET_ADAPTER (0x00000004) 1006 1007#define MFI_ADP_RESET 0x00000040 1008#define MFI_INIT_ABORT 0x00000001 1009#define MFI_INIT_READY 0x00000002 1010#define MFI_INIT_MFIMODE 0x00000004 1011#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 1012#define MFI_INIT_HOTPLUG 0x00000010 1013#define MFI_STOP_ADP 0x00000020 1014#define MFI_RESET_FLAGS MFI_INIT_READY| \ 1015 MFI_INIT_MFIMODE| \ 1016 MFI_INIT_ABORT 1017 1018/* 1019 * MFI frame flags 1020 */ 1021#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 1022#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 1023#define MFI_FRAME_SGL32 0x0000 1024#define MFI_FRAME_SGL64 0x0002 1025#define MFI_FRAME_SENSE32 0x0000 1026#define MFI_FRAME_SENSE64 0x0004 1027#define MFI_FRAME_DIR_NONE 0x0000 1028#define MFI_FRAME_DIR_WRITE 0x0008 1029#define MFI_FRAME_DIR_READ 0x0010 1030#define MFI_FRAME_DIR_BOTH 0x0018 1031#define MFI_FRAME_IEEE 0x0020 1032 1033/* 1034 * Definition for cmd_status 1035 */ 1036#define MFI_CMD_STATUS_POLL_MODE 0xFF 1037 1038/* 1039 * MFI command opcodes 1040 */ 1041#define MFI_CMD_INIT 0x00 1042#define MFI_CMD_LD_READ 0x01 1043#define MFI_CMD_LD_WRITE 0x02 1044#define MFI_CMD_LD_SCSI_IO 0x03 1045#define MFI_CMD_PD_SCSI_IO 0x04 1046#define MFI_CMD_DCMD 0x05 1047#define MFI_CMD_ABORT 0x06 1048#define MFI_CMD_SMP 0x07 1049#define MFI_CMD_STP 0x08 1050#define MFI_CMD_INVALID 0xff 1051 1052#define MR_DCMD_CTRL_GET_INFO 0x01010000 1053#define MR_DCMD_LD_GET_LIST 0x03010000 1054#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 1055#define MR_FLUSH_CTRL_CACHE 0x01 1056#define MR_FLUSH_DISK_CACHE 0x02 1057 1058#define MR_DCMD_CTRL_SHUTDOWN 0x01050000 1059#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 1060#define MR_ENABLE_DRIVE_SPINDOWN 0x01 1061 1062#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 1063#define MR_DCMD_CTRL_EVENT_GET 0x01040300 1064#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 1065#define MR_DCMD_LD_GET_PROPERTIES 0x03030000 1066 1067#define MR_DCMD_CLUSTER 0x08000000 1068#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 1069#define MR_DCMD_CLUSTER_RESET_LD 0x08010200 1070#define MR_DCMD_PD_LIST_QUERY 0x02010100 1071 1072#define MR_DCMD_CTRL_MISC_CPX 0x0100e200 1073#define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201 1074#define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202 1075#define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203 1076#define MAX_MR_ROW_SIZE 32 1077#define MR_CPX_DIR_WRITE 1 1078#define MR_CPX_DIR_READ 0 1079#define MR_CPX_VERSION 1 1080 1081#define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200 // get IO metrics 1082 1083#define MR_EVT_CFG_CLEARED 0x0004 1084 1085#define MR_EVT_LD_STATE_CHANGE 0x0051 1086#define MR_EVT_PD_INSERTED 0x005b 1087#define MR_EVT_PD_REMOVED 0x0070 1088#define MR_EVT_LD_CREATED 0x008a 1089#define MR_EVT_LD_DELETED 0x008b 1090#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1091#define MR_EVT_LD_OFFLINE 0x00fc 1092#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1093#define MR_EVT_CTRL_PERF_COLLECTION 0x017e 1094 1095/* 1096 * MFI command completion codes 1097 */ 1098enum MFI_STAT { 1099 MFI_STAT_OK = 0x00, 1100 MFI_STAT_INVALID_CMD = 0x01, 1101 MFI_STAT_INVALID_DCMD = 0x02, 1102 MFI_STAT_INVALID_PARAMETER = 0x03, 1103 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 1104 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 1105 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 1106 MFI_STAT_APP_IN_USE = 0x07, 1107 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 1108 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 1109 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 1110 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 1111 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 1112 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 1113 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 1114 MFI_STAT_FLASH_BUSY = 0x0f, 1115 MFI_STAT_FLASH_ERROR = 0x10, 1116 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 1117 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 1118 MFI_STAT_FLASH_NOT_OPEN = 0x13, 1119 MFI_STAT_FLASH_NOT_STARTED = 0x14, 1120 MFI_STAT_FLUSH_FAILED = 0x15, 1121 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 1122 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 1123 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 1124 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 1125 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 1126 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 1127 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 1128 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 1129 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 1130 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 1131 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 1132 MFI_STAT_MFC_HW_ERROR = 0x21, 1133 MFI_STAT_NO_HW_PRESENT = 0x22, 1134 MFI_STAT_NOT_FOUND = 0x23, 1135 MFI_STAT_NOT_IN_ENCL = 0x24, 1136 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 1137 MFI_STAT_PD_TYPE_WRONG = 0x26, 1138 MFI_STAT_PR_DISABLED = 0x27, 1139 MFI_STAT_ROW_INDEX_INVALID = 0x28, 1140 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 1141 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 1142 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 1143 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 1144 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 1145 MFI_STAT_SCSI_IO_FAILED = 0x2e, 1146 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 1147 MFI_STAT_SHUTDOWN_FAILED = 0x30, 1148 MFI_STAT_TIME_NOT_SET = 0x31, 1149 MFI_STAT_WRONG_STATE = 0x32, 1150 MFI_STAT_LD_OFFLINE = 0x33, 1151 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 1152 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 1153 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 1154 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 1155 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 1156 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 1157 1158 MFI_STAT_INVALID_STATUS = 0xFF 1159}; 1160 1161/* 1162 * Number of mailbox bytes in DCMD message frame 1163 */ 1164#define MFI_MBOX_SIZE 12 1165 1166enum MR_EVT_CLASS { 1167 1168 MR_EVT_CLASS_DEBUG = -2, 1169 MR_EVT_CLASS_PROGRESS = -1, 1170 MR_EVT_CLASS_INFO = 0, 1171 MR_EVT_CLASS_WARNING = 1, 1172 MR_EVT_CLASS_CRITICAL = 2, 1173 MR_EVT_CLASS_FATAL = 3, 1174 MR_EVT_CLASS_DEAD = 4, 1175 1176}; 1177 1178enum MR_EVT_LOCALE { 1179 1180 MR_EVT_LOCALE_LD = 0x0001, 1181 MR_EVT_LOCALE_PD = 0x0002, 1182 MR_EVT_LOCALE_ENCL = 0x0004, 1183 MR_EVT_LOCALE_BBU = 0x0008, 1184 MR_EVT_LOCALE_SAS = 0x0010, 1185 MR_EVT_LOCALE_CTRL = 0x0020, 1186 MR_EVT_LOCALE_CONFIG = 0x0040, 1187 MR_EVT_LOCALE_CLUSTER = 0x0080, 1188 MR_EVT_LOCALE_ALL = 0xffff, 1189 1190}; 1191 1192enum MR_EVT_ARGS { 1193 1194 MR_EVT_ARGS_NONE, 1195 MR_EVT_ARGS_CDB_SENSE, 1196 MR_EVT_ARGS_LD, 1197 MR_EVT_ARGS_LD_COUNT, 1198 MR_EVT_ARGS_LD_LBA, 1199 MR_EVT_ARGS_LD_OWNER, 1200 MR_EVT_ARGS_LD_LBA_PD_LBA, 1201 MR_EVT_ARGS_LD_PROG, 1202 MR_EVT_ARGS_LD_STATE, 1203 MR_EVT_ARGS_LD_STRIP, 1204 MR_EVT_ARGS_PD, 1205 MR_EVT_ARGS_PD_ERR, 1206 MR_EVT_ARGS_PD_LBA, 1207 MR_EVT_ARGS_PD_LBA_LD, 1208 MR_EVT_ARGS_PD_PROG, 1209 MR_EVT_ARGS_PD_STATE, 1210 MR_EVT_ARGS_PCI, 1211 MR_EVT_ARGS_RATE, 1212 MR_EVT_ARGS_STR, 1213 MR_EVT_ARGS_TIME, 1214 MR_EVT_ARGS_ECC, 1215 MR_EVT_ARGS_LD_PROP, 1216 MR_EVT_ARGS_PD_SPARE, 1217 MR_EVT_ARGS_PD_INDEX, 1218 MR_EVT_ARGS_DIAG_PASS, 1219 MR_EVT_ARGS_DIAG_FAIL, 1220 MR_EVT_ARGS_PD_LBA_LBA, 1221 MR_EVT_ARGS_PORT_PHY, 1222 MR_EVT_ARGS_PD_MISSING, 1223 MR_EVT_ARGS_PD_ADDRESS, 1224 MR_EVT_ARGS_BITMAP, 1225 MR_EVT_ARGS_CONNECTOR, 1226 MR_EVT_ARGS_PD_PD, 1227 MR_EVT_ARGS_PD_FRU, 1228 MR_EVT_ARGS_PD_PATHINFO, 1229 MR_EVT_ARGS_PD_POWER_STATE, 1230 MR_EVT_ARGS_GENERIC, 1231}; 1232 1233 1234/* 1235 * Thunderbolt (and later) Defines 1236 */ 1237#define MRSAS_MAX_SZ_CHAIN_FRAME 1024 1238#define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 1239#define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 1240#define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 1241#define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 1242#define MRSAS_LOAD_BALANCE_FLAG 0x1 1243#define MRSAS_DCMD_MBOX_PEND_FLAG 0x1 1244#define HOST_DIAG_WRITE_ENABLE 0x80 1245#define HOST_DIAG_RESET_ADAPTER 0x4 1246#define MRSAS_TBOLT_MAX_RESET_TRIES 3 1247#define MRSAS_MAX_MFI_CMDS 32 1248 1249/* 1250 * Invader Defines 1251 */ 1252#define MPI2_TYPE_CUDA 0x2 1253#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 1254#define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 1255#define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 1256#define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 1257#define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 1258 1259/* 1260 * T10 PI defines 1261 */ 1262#define MR_PROT_INFO_TYPE_CONTROLLER 0x8 1263#define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 1264#define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9 1265#define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB 1266#define MRSAS_SCSI_ADDL_CDB_LEN 0x18 1267#define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20 1268#define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60 1269#define MRSAS_SCSIBLOCKSIZE 512 1270 1271/* 1272 * Raid context flags 1273 */ 1274#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 1275#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 1276typedef enum MR_RAID_FLAGS_IO_SUB_TYPE { 1277 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 1278 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 1279} MR_RAID_FLAGS_IO_SUB_TYPE; 1280 1281/* 1282 * Request descriptor types 1283 */ 1284#define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1285#define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1 1286#define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 1287#define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 1288#define MRSAS_FP_CMD_LEN 16 1289#define MRSAS_FUSION_IN_RESET 0 1290 1291#define RAID_CTX_SPANARM_ARM_SHIFT (0) 1292#define RAID_CTX_SPANARM_ARM_MASK (0x1f) 1293#define RAID_CTX_SPANARM_SPAN_SHIFT (5) 1294#define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 1295 1296/* 1297 * Define region lock types 1298 */ 1299typedef enum _REGION_TYPE { 1300 REGION_TYPE_UNUSED = 0, // lock is currently not active 1301 REGION_TYPE_SHARED_READ = 1, // shared lock (for reads) 1302 REGION_TYPE_SHARED_WRITE = 2, 1303 REGION_TYPE_EXCLUSIVE = 3, // exclusive lock (for writes) 1304} REGION_TYPE; 1305 1306 1307/* 1308 * SCSI-CAM Related Defines 1309 */ 1310#define MRSAS_SCSI_MAX_LUNS 0 //zero for now 1311#define MRSAS_SCSI_INITIATOR_ID 255 1312#define MRSAS_SCSI_MAX_CMDS 8 1313#define MRSAS_SCSI_MAX_CDB_LEN 16 1314#define MRSAS_SCSI_SENSE_BUFFERSIZE 96 1315#define MRSAS_MAX_SGL 70 1316#define MRSAS_MAX_IO_SIZE (256 * 1024) 1317#define MRSAS_INTERNAL_CMDS 32 1318 1319/* Request types */ 1320#define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0 1321#define MRSAS_REQ_TYPE_AEN_FETCH 0x1 1322#define MRSAS_REQ_TYPE_PASSTHRU 0x2 1323#define MRSAS_REQ_TYPE_GETSET_PARAM 0x3 1324#define MRSAS_REQ_TYPE_SCSI_IO 0x4 1325 1326/* Request states */ 1327#define MRSAS_REQ_STATE_FREE 0 1328#define MRSAS_REQ_STATE_BUSY 1 1329#define MRSAS_REQ_STATE_TRAN 2 1330#define MRSAS_REQ_STATE_COMPLETE 3 1331 1332enum mrsas_req_flags { 1333 MRSAS_DIR_UNKNOWN = 0x1, 1334 MRSAS_DIR_IN = 0x2, 1335 MRSAS_DIR_OUT = 0x4, 1336 MRSAS_DIR_NONE = 0x8, 1337}; 1338 1339/* 1340 * Adapter Reset States 1341 */ 1342enum { 1343 MRSAS_HBA_OPERATIONAL = 0, 1344 MRSAS_ADPRESET_SM_INFAULT = 1, 1345 MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 1346 MRSAS_ADPRESET_SM_OPERATIONAL = 3, 1347 MRSAS_HW_CRITICAL_ERROR = 4, 1348 MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1349}; 1350 1351/* 1352 * MPT Command Structure 1353 */ 1354struct mrsas_mpt_cmd { 1355 MRSAS_RAID_SCSI_IO_REQUEST *io_request; 1356 bus_addr_t io_request_phys_addr; 1357 MPI2_SGE_IO_UNION *chain_frame; 1358 bus_addr_t chain_frame_phys_addr; 1359 u_int32_t sge_count; 1360 u_int8_t *sense; 1361 bus_addr_t sense_phys_addr; 1362 u_int8_t retry_for_fw_reset; 1363 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc; 1364 u_int32_t sync_cmd_idx; //For getting MFI cmd from list when complete 1365 u_int32_t index; 1366 u_int8_t flags; 1367 u_int8_t load_balance; 1368 bus_size_t length; // request length 1369 u_int32_t error_code; // error during request dmamap load 1370 bus_dmamap_t data_dmamap; 1371 void *data; 1372 union ccb *ccb_ptr; // pointer to ccb 1373 struct callout cm_callout; 1374 struct mrsas_softc *sc; 1375 TAILQ_ENTRY(mrsas_mpt_cmd) next; 1376}; 1377 1378/* 1379 * MFI Command Structure 1380 */ 1381struct mrsas_mfi_cmd { 1382 union mrsas_frame *frame; 1383 bus_dmamap_t frame_dmamap; // mfi frame dmamap 1384 void *frame_mem; // mfi frame virtual addr 1385 bus_addr_t frame_phys_addr; // mfi frame physical addr 1386 u_int8_t *sense; 1387 bus_dmamap_t sense_dmamap; // mfi sense dmamap 1388 void *sense_mem; // mfi sense virtual addr 1389 bus_addr_t sense_phys_addr; 1390 u_int32_t index; 1391 u_int8_t sync_cmd; 1392 u_int8_t cmd_status; 1393 u_int8_t abort_aen; 1394 u_int8_t retry_for_fw_reset; 1395 struct mrsas_softc *sc; 1396 union ccb *ccb_ptr; 1397 union { 1398 struct { 1399 u_int16_t smid; 1400 u_int16_t resvd; 1401 } context; 1402 u_int32_t frame_count; 1403 } cmd_id; 1404 TAILQ_ENTRY(mrsas_mfi_cmd) next; 1405}; 1406 1407 1408/* 1409 * define constants for device list query options 1410 */ 1411enum MR_PD_QUERY_TYPE { 1412 MR_PD_QUERY_TYPE_ALL = 0, 1413 MR_PD_QUERY_TYPE_STATE = 1, 1414 MR_PD_QUERY_TYPE_POWER_STATE = 2, 1415 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 1416 MR_PD_QUERY_TYPE_SPEED = 4, 1417 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 1418}; 1419 1420#define MR_EVT_CFG_CLEARED 0x0004 1421#define MR_EVT_LD_STATE_CHANGE 0x0051 1422#define MR_EVT_PD_INSERTED 0x005b 1423#define MR_EVT_PD_REMOVED 0x0070 1424#define MR_EVT_LD_CREATED 0x008a 1425#define MR_EVT_LD_DELETED 0x008b 1426#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1427#define MR_EVT_LD_OFFLINE 0x00fc 1428#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1429 1430enum MR_PD_STATE { 1431 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1432 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 1433 MR_PD_STATE_HOT_SPARE = 0x02, 1434 MR_PD_STATE_OFFLINE = 0x10, 1435 MR_PD_STATE_FAILED = 0x11, 1436 MR_PD_STATE_REBUILD = 0x14, 1437 MR_PD_STATE_ONLINE = 0x18, 1438 MR_PD_STATE_COPYBACK = 0x20, 1439 MR_PD_STATE_SYSTEM = 0x40, 1440 }; 1441 1442 /* 1443 * defines the physical drive address structure 1444 */ 1445#pragma pack(1) 1446struct MR_PD_ADDRESS { 1447 u_int16_t deviceId; 1448 u_int16_t enclDeviceId; 1449 1450 union { 1451 struct { 1452 u_int8_t enclIndex; 1453 u_int8_t slotNumber; 1454 } mrPdAddress; 1455 struct { 1456 u_int8_t enclPosition; 1457 u_int8_t enclConnectorIndex; 1458 } mrEnclAddress; 1459 } u1; 1460 u_int8_t scsiDevType; 1461 union { 1462 u_int8_t connectedPortBitmap; 1463 u_int8_t connectedPortNumbers; 1464 } u2; 1465 u_int64_t sasAddr[2]; 1466}; 1467#pragma pack() 1468 1469/* 1470 * defines the physical drive list structure 1471 */ 1472#pragma pack(1) 1473struct MR_PD_LIST { 1474 u_int32_t size; 1475 u_int32_t count; 1476 struct MR_PD_ADDRESS addr[1]; 1477}; 1478#pragma pack() 1479 1480#pragma pack(1) 1481struct mrsas_pd_list { 1482 u_int16_t tid; 1483 u_int8_t driveType; 1484 u_int8_t driveState; 1485}; 1486#pragma pack() 1487 1488 /* 1489 * defines the logical drive reference structure 1490 */ 1491typedef union _MR_LD_REF { // LD reference structure 1492 struct { 1493 u_int8_t targetId; // LD target id (0 to MAX_TARGET_ID) 1494 u_int8_t reserved; // reserved to make in line with MR_PD_REF 1495 u_int16_t seqNum; // Sequence Number 1496 } ld_context; 1497 u_int32_t ref; // shorthand reference to full 32-bits 1498} MR_LD_REF; // 4 bytes 1499 1500 1501/* 1502 * defines the logical drive list structure 1503 */ 1504#pragma pack(1) 1505struct MR_LD_LIST { 1506 u_int32_t ldCount; // number of LDs 1507 u_int32_t reserved; // pad to 8-byte boundary 1508 struct { 1509 MR_LD_REF ref; // LD reference 1510 u_int8_t state; // current LD state (MR_LD_STATE) 1511 u_int8_t reserved[3]; // pad to 8-byte boundary 1512 u_int64_t size; // LD size 1513 } ldList[MAX_LOGICAL_DRIVES_EXT]; 1514}; 1515#pragma pack() 1516 1517/* 1518 * SAS controller properties 1519 */ 1520#pragma pack(1) 1521struct mrsas_ctrl_prop { 1522 u_int16_t seq_num; 1523 u_int16_t pred_fail_poll_interval; 1524 u_int16_t intr_throttle_count; 1525 u_int16_t intr_throttle_timeouts; 1526 u_int8_t rebuild_rate; 1527 u_int8_t patrol_read_rate; 1528 u_int8_t bgi_rate; 1529 u_int8_t cc_rate; 1530 u_int8_t recon_rate; 1531 u_int8_t cache_flush_interval; 1532 u_int8_t spinup_drv_count; 1533 u_int8_t spinup_delay; 1534 u_int8_t cluster_enable; 1535 u_int8_t coercion_mode; 1536 u_int8_t alarm_enable; 1537 u_int8_t disable_auto_rebuild; 1538 u_int8_t disable_battery_warn; 1539 u_int8_t ecc_bucket_size; 1540 u_int16_t ecc_bucket_leak_rate; 1541 u_int8_t restore_hotspare_on_insertion; 1542 u_int8_t expose_encl_devices; 1543 u_int8_t maintainPdFailHistory; 1544 u_int8_t disallowHostRequestReordering; 1545 u_int8_t abortCCOnError; // set TRUE to abort CC on detecting an inconsistency 1546 u_int8_t loadBalanceMode; // load balance mode (MR_LOAD_BALANCE_MODE) 1547 u_int8_t disableAutoDetectBackplane; // 0 - use auto detect logic of backplanes 1548 // like SGPIO, i2c SEP using h/w mechansim 1549 // like GPIO pins. 1550 // 1 - disable auto detect SGPIO, 1551 // 2 - disable i2c SEP auto detect 1552 // 3 - disable both auto detect 1553 u_int8_t snapVDSpace; // % of source LD to be reserved for a VDs snapshot in 1554 // snapshot repository, for metadata and user data. 1555 // 1=5%, 2=10%, 3=15% and so on. 1556 /* 1557 * Add properties that can be controlled by a bit in the following structure. 1558 */ 1559 struct { 1560 u_int32_t copyBackDisabled : 1; // set TRUE to disable copyBack 1561 // (0=copback enabled) 1562 u_int32_t SMARTerEnabled : 1; 1563 u_int32_t prCorrectUnconfiguredAreas : 1; 1564 u_int32_t useFdeOnly : 1; 1565 u_int32_t disableNCQ : 1; 1566 u_int32_t SSDSMARTerEnabled : 1; 1567 u_int32_t SSDPatrolReadEnabled : 1; 1568 u_int32_t enableSpinDownUnconfigured : 1; 1569 u_int32_t autoEnhancedImport : 1; 1570 u_int32_t enableSecretKeyControl : 1; 1571 u_int32_t disableOnlineCtrlReset : 1; 1572 u_int32_t allowBootWithPinnedCache : 1; 1573 u_int32_t disableSpinDownHS : 1; 1574 u_int32_t enableJBOD : 1; 1575 u_int32_t disableCacheBypass : 1; // 1 = disable cache-bypass-performance-improvement feature 1576 u_int32_t useDiskActivityForLocate : 1; // 1 = drive activity LED is toggled for LOCATE 1577 u_int32_t enablePI : 1; // 0 = Disable SCSI PI for controller. Remove any active protection information 1578 u_int32_t preventPIImport : 1; // 1 = Prevent import of SCSI DIF protected logical disks 1579 u_int32_t useGlobalSparesForEmergency : 1; // 1 = Use global spares for Emergency (if spare is incompatible without Emergency) 1580 u_int32_t useUnconfGoodForEmergency : 1; // 1 = Use uncofgured good drives for Emergency 1581 u_int32_t useEmergencySparesforSMARTer: 1; // 1 = Use Emergency spares for SMARTer 1582 u_int32_t forceSGPIOForQuadOnly : 1; // 1 = Force SGPIO status per port only for four drives, affects HPC controllers 1583 u_int32_t enableConfigAutoBalance : 1; // 0 = Configuration auto balance disabled, 1 = Configuration auto balance enabled 1584 u_int32_t enableVirtualCache : 1; // 1 = Virtual caching is enabled on DFF and SFM. 1585 u_int32_t enableAutoLockRecovery : 1; // 1 = Auto Lock Recovery on DFF and SFM 1586 u_int32_t disableImmediateIO : 1; // 1 = Disable Legacy Immediate IO, 0 = Enable 1587 u_int32_t disableT10RebuildAssist : 1; // 1 = Disable T10 Rebuild Assist, use legacy rebuild method 1588 u_int32_t ignore64ldRestriction : 1; // 0 - limit LD to 64 even if more LD support exists, 1 - support more than 64 ld with new DDF format 1589 u_int32_t enableSwZone : 1; // 1 = enable Software Zone 1590 u_int32_t limitMaxRateSATA3G : 1; // 1 = negotiated link rates to direct attached SATA devices shall be limited to 3Gbps 1591 u_int32_t reserved :2; 1592 } OnOffProperties; 1593 u_int8_t autoSnapVDSpace; // % of source LD to be reserved for auto 1594 // snapshot in snapshot repository, for 1595 // metadata and user data. 1596 // 1=5%, 2=10%, 3=15% and so on. 1597 u_int8_t viewSpace; // snapshot writeable VIEWs capacity as a % 1598 // of source LD capacity. 0=READ only. 1599 // 1=5%, 2=10%, 3=15% and so on 1600 u_int16_t spinDownTime; // # of idle minutes before device is spun 1601 // down (0=use FW defaults). 1602 u_int8_t reserved[24]; 1603 1604}; 1605#pragma pack() 1606 1607 1608/* 1609 * SAS controller information 1610 */ 1611//#pragma pack(1) 1612struct mrsas_ctrl_info { 1613 /* 1614 * PCI device information 1615 */ 1616 struct { 1617 u_int16_t vendor_id; 1618 u_int16_t device_id; 1619 u_int16_t sub_vendor_id; 1620 u_int16_t sub_device_id; 1621 u_int8_t reserved[24]; 1622 } __packed pci; 1623 /* 1624 * Host interface information 1625 */ 1626 struct { 1627 u_int8_t PCIX:1; 1628 u_int8_t PCIE:1; 1629 u_int8_t iSCSI:1; 1630 u_int8_t SAS_3G:1; 1631 u_int8_t reserved_0:4; 1632 u_int8_t reserved_1[6]; 1633 u_int8_t port_count; 1634 u_int64_t port_addr[8]; 1635 } __packed host_interface; 1636 /* 1637 * Device (backend) interface information 1638 */ 1639 struct { 1640 u_int8_t SPI:1; 1641 u_int8_t SAS_3G:1; 1642 u_int8_t SATA_1_5G:1; 1643 u_int8_t SATA_3G:1; 1644 u_int8_t reserved_0:4; 1645 u_int8_t reserved_1[6]; 1646 u_int8_t port_count; 1647 u_int64_t port_addr[8]; 1648 } __packed device_interface; 1649 1650 /* 1651 * List of components residing in flash. All str are null terminated 1652 */ 1653 u_int32_t image_check_word; 1654 u_int32_t image_component_count; 1655 1656 struct { 1657 char name[8]; 1658 char version[32]; 1659 char build_date[16]; 1660 char built_time[16]; 1661 } __packed image_component[8]; 1662 /* 1663 * List of flash components that have been flashed on the card, but 1664 * are not in use, pending reset of the adapter. This list will be 1665 * empty if a flash operation has not occurred. All stings are null 1666 * terminated 1667 */ 1668 u_int32_t pending_image_component_count; 1669 1670 struct { 1671 char name[8]; 1672 char version[32]; 1673 char build_date[16]; 1674 char build_time[16]; 1675 } __packed pending_image_component[8]; 1676 1677 u_int8_t max_arms; 1678 u_int8_t max_spans; 1679 u_int8_t max_arrays; 1680 u_int8_t max_lds; 1681 char product_name[80]; 1682 char serial_no[32]; 1683 1684 /* 1685 * Other physical/controller/operation information. Indicates the 1686 * presence of the hardware 1687 */ 1688 struct { 1689 u_int32_t bbu:1; 1690 u_int32_t alarm:1; 1691 u_int32_t nvram:1; 1692 u_int32_t uart:1; 1693 u_int32_t reserved:28; 1694 } __packed hw_present; 1695 1696 u_int32_t current_fw_time; 1697 1698 /* 1699 * Maximum data transfer sizes 1700 */ 1701 u_int16_t max_concurrent_cmds; 1702 u_int16_t max_sge_count; 1703 u_int32_t max_request_size; 1704 1705 /* 1706 * Logical and physical device counts 1707 */ 1708 u_int16_t ld_present_count; 1709 u_int16_t ld_degraded_count; 1710 u_int16_t ld_offline_count; 1711 1712 u_int16_t pd_present_count; 1713 u_int16_t pd_disk_present_count; 1714 u_int16_t pd_disk_pred_failure_count; 1715 u_int16_t pd_disk_failed_count; 1716 1717 /* 1718 * Memory size information 1719 */ 1720 u_int16_t nvram_size; 1721 u_int16_t memory_size; 1722 u_int16_t flash_size; 1723 1724 /* 1725 * Error counters 1726 */ 1727 u_int16_t mem_correctable_error_count; 1728 u_int16_t mem_uncorrectable_error_count; 1729 1730 /* 1731 * Cluster information 1732 */ 1733 u_int8_t cluster_permitted; 1734 u_int8_t cluster_active; 1735 1736 /* 1737 * Additional max data transfer sizes 1738 */ 1739 u_int16_t max_strips_per_io; 1740 1741 /* 1742 * Controller capabilities structures 1743 */ 1744 struct { 1745 u_int32_t raid_level_0:1; 1746 u_int32_t raid_level_1:1; 1747 u_int32_t raid_level_5:1; 1748 u_int32_t raid_level_1E:1; 1749 u_int32_t raid_level_6:1; 1750 u_int32_t reserved:27; 1751 } __packed raid_levels; 1752 1753 struct { 1754 u_int32_t rbld_rate:1; 1755 u_int32_t cc_rate:1; 1756 u_int32_t bgi_rate:1; 1757 u_int32_t recon_rate:1; 1758 u_int32_t patrol_rate:1; 1759 u_int32_t alarm_control:1; 1760 u_int32_t cluster_supported:1; 1761 u_int32_t bbu:1; 1762 u_int32_t spanning_allowed:1; 1763 u_int32_t dedicated_hotspares:1; 1764 u_int32_t revertible_hotspares:1; 1765 u_int32_t foreign_config_import:1; 1766 u_int32_t self_diagnostic:1; 1767 u_int32_t mixed_redundancy_arr:1; 1768 u_int32_t global_hot_spares:1; 1769 u_int32_t reserved:17; 1770 } __packed adapter_operations; 1771 1772 struct { 1773 u_int32_t read_policy:1; 1774 u_int32_t write_policy:1; 1775 u_int32_t io_policy:1; 1776 u_int32_t access_policy:1; 1777 u_int32_t disk_cache_policy:1; 1778 u_int32_t reserved:27; 1779 } __packed ld_operations; 1780 1781 struct { 1782 u_int8_t min; 1783 u_int8_t max; 1784 u_int8_t reserved[2]; 1785 } __packed stripe_sz_ops; 1786 1787 struct { 1788 u_int32_t force_online:1; 1789 u_int32_t force_offline:1; 1790 u_int32_t force_rebuild:1; 1791 u_int32_t reserved:29; 1792 } __packed pd_operations; 1793 1794 struct { 1795 u_int32_t ctrl_supports_sas:1; 1796 u_int32_t ctrl_supports_sata:1; 1797 u_int32_t allow_mix_in_encl:1; 1798 u_int32_t allow_mix_in_ld:1; 1799 u_int32_t allow_sata_in_cluster:1; 1800 u_int32_t reserved:27; 1801 } __packed pd_mix_support; 1802 1803 /* 1804 * Define ECC single-bit-error bucket information 1805 */ 1806 u_int8_t ecc_bucket_count; 1807 u_int8_t reserved_2[11]; 1808 1809 /* 1810 * Include the controller properties (changeable items) 1811 */ 1812 struct mrsas_ctrl_prop properties; 1813 1814 /* 1815 * Define FW pkg version (set in envt v'bles on OEM basis) 1816 */ 1817 char package_version[0x60]; 1818 1819 /* 1820 * If adapterOperations.supportMoreThan8Phys is set, and deviceInterface.portCount is greater than 8, 1821 * SAS Addrs for first 8 ports shall be populated in deviceInterface.portAddr, and the rest shall be 1822 * populated in deviceInterfacePortAddr2. 1823 */ 1824 u_int64_t deviceInterfacePortAddr2[8]; //0x6a0 1825 u_int8_t reserved3[128]; //0x6e0 1826 1827 struct { //0x760 1828 u_int16_t minPdRaidLevel_0 : 4; 1829 u_int16_t maxPdRaidLevel_0 : 12; 1830 1831 u_int16_t minPdRaidLevel_1 : 4; 1832 u_int16_t maxPdRaidLevel_1 : 12; 1833 1834 u_int16_t minPdRaidLevel_5 : 4; 1835 u_int16_t maxPdRaidLevel_5 : 12; 1836 1837 u_int16_t minPdRaidLevel_1E : 4; 1838 u_int16_t maxPdRaidLevel_1E : 12; 1839 1840 u_int16_t minPdRaidLevel_6 : 4; 1841 u_int16_t maxPdRaidLevel_6 : 12; 1842 1843 u_int16_t minPdRaidLevel_10 : 4; 1844 u_int16_t maxPdRaidLevel_10 : 12; 1845 1846 u_int16_t minPdRaidLevel_50 : 4; 1847 u_int16_t maxPdRaidLevel_50 : 12; 1848 1849 u_int16_t minPdRaidLevel_60 : 4; 1850 u_int16_t maxPdRaidLevel_60 : 12; 1851 1852 u_int16_t minPdRaidLevel_1E_RLQ0 : 4; 1853 u_int16_t maxPdRaidLevel_1E_RLQ0 : 12; 1854 1855 u_int16_t minPdRaidLevel_1E0_RLQ0 : 4; 1856 u_int16_t maxPdRaidLevel_1E0_RLQ0 : 12; 1857 1858 u_int16_t reserved[6]; 1859 } pdsForRaidLevels; 1860 1861 u_int16_t maxPds; //0x780 1862 u_int16_t maxDedHSPs; //0x782 1863 u_int16_t maxGlobalHSPs; //0x784 1864 u_int16_t ddfSize; //0x786 1865 u_int8_t maxLdsPerArray; //0x788 1866 u_int8_t partitionsInDDF; //0x789 1867 u_int8_t lockKeyBinding; //0x78a 1868 u_int8_t maxPITsPerLd; //0x78b 1869 u_int8_t maxViewsPerLd; //0x78c 1870 u_int8_t maxTargetId; //0x78d 1871 u_int16_t maxBvlVdSize; //0x78e 1872 1873 u_int16_t maxConfigurableSSCSize; //0x790 1874 u_int16_t currentSSCsize; //0x792 1875 1876 char expanderFwVersion[12]; //0x794 1877 1878 u_int16_t PFKTrialTimeRemaining; //0x7A0 1879 1880 u_int16_t cacheMemorySize; //0x7A2 1881 1882 struct { //0x7A4 1883 u_int32_t supportPIcontroller :1; 1884 u_int32_t supportLdPIType1 :1; 1885 u_int32_t supportLdPIType2 :1; 1886 u_int32_t supportLdPIType3 :1; 1887 u_int32_t supportLdBBMInfo :1; 1888 u_int32_t supportShieldState :1; 1889 u_int32_t blockSSDWriteCacheChange :1; 1890 u_int32_t supportSuspendResumeBGops :1; 1891 u_int32_t supportEmergencySpares :1; 1892 u_int32_t supportSetLinkSpeed :1; 1893 u_int32_t supportBootTimePFKChange :1; 1894 u_int32_t supportJBOD :1; 1895 u_int32_t disableOnlinePFKChange :1; 1896 u_int32_t supportPerfTuning :1; 1897 u_int32_t supportSSDPatrolRead :1; 1898 u_int32_t realTimeScheduler :1; 1899 1900 u_int32_t supportResetNow :1; 1901 u_int32_t supportEmulatedDrives :1; 1902 u_int32_t headlessMode :1; 1903 u_int32_t dedicatedHotSparesLimited :1; 1904 1905 1906 u_int32_t supportUnevenSpans :1; 1907 u_int32_t reserved :11; 1908 } adapterOperations2; 1909 1910 u_int8_t driverVersion[32]; //0x7A8 1911 u_int8_t maxDAPdCountSpinup60; //0x7C8 1912 u_int8_t temperatureROC; //0x7C9 1913 u_int8_t temperatureCtrl; //0x7CA 1914 u_int8_t reserved4; //0x7CB 1915 u_int16_t maxConfigurablePds; //0x7CC 1916 1917 1918 u_int8_t reserved5[2]; //0x7CD reserved for future use 1919 1920 /* 1921 * HA cluster information 1922 */ 1923 struct { 1924 u_int32_t peerIsPresent :1; 1925 u_int32_t peerIsIncompatible :1; 1926 1927 u_int32_t hwIncompatible :1; 1928 u_int32_t fwVersionMismatch :1; 1929 u_int32_t ctrlPropIncompatible :1; 1930 u_int32_t premiumFeatureMismatch :1; 1931 u_int32_t reserved :26; 1932 } cluster; 1933 1934 char clusterId[16]; //0x7D4 1935 1936 char reserved6[4]; //0x7E4 RESERVED FOR IOV 1937 1938 struct{ //0x7E8 1939 u_int32_t resrved :5; 1940 u_int32_t supportMaxExtLDs :1; 1941 u_int32_t reserved1 :26; 1942 }adapterOperations3; 1943 1944 u_int8_t pad[0x800-0x7EC]; //0x7EC 1945} __packed; 1946 1947/* 1948 * When SCSI mid-layer calls driver's reset routine, driver waits for 1949 * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 1950 * that the driver cannot _actually_ abort or reset pending commands. While 1951 * it is waiting for the commands to complete, it prints a diagnostic message 1952 * every MRSAS_RESET_NOTICE_INTERVAL seconds 1953 */ 1954#define MRSAS_RESET_WAIT_TIME 180 1955#define MRSAS_INTERNAL_CMD_WAIT_TIME 180 1956#define MRSAS_IOC_INIT_WAIT_TIME 60 1957#define MRSAS_RESET_NOTICE_INTERVAL 5 1958#define MRSAS_IOCTL_CMD 0 1959#define MRSAS_DEFAULT_CMD_TIMEOUT 90 1960#define MRSAS_THROTTLE_QUEUE_DEPTH 16 1961 1962/* 1963 * FW reports the maximum of number of commands that it can accept (maximum 1964 * commands that can be outstanding) at any time. The driver must report a 1965 * lower number to the mid layer because it can issue a few internal commands 1966 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 1967 * is shown below 1968 */ 1969#define MRSAS_INT_CMDS 32 1970#define MRSAS_SKINNY_INT_CMDS 5 1971#define MRSAS_MAX_MSIX_QUEUES 16 1972 1973/* 1974 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 1975 * SGLs based on the size of bus_addr_t 1976 */ 1977#define IS_DMA64 (sizeof(bus_addr_t) == 8) 1978 1979#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 // MFI state change interrupt 1980#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 1981#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 1982#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 //MFI state change interrupt 1983 1984#define MFI_OB_INTR_STATUS_MASK 0x00000002 1985#define MFI_POLL_TIMEOUT_SECS 60 1986 1987#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 1988#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 1989#define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001 1990#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 1991#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 1992#define MFI_1068_PCSR_OFFSET 0x84 1993#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 1994#define MFI_1068_FW_READY 0xDDDD0000 1995 1996#pragma pack(1) 1997struct mrsas_sge32 { 1998 u_int32_t phys_addr; 1999 u_int32_t length; 2000}; 2001#pragma pack() 2002 2003#pragma pack(1) 2004struct mrsas_sge64 { 2005 u_int64_t phys_addr; 2006 u_int32_t length; 2007}; 2008#pragma pack() 2009 2010#pragma pack() 2011union mrsas_sgl { 2012 struct mrsas_sge32 sge32[1]; 2013 struct mrsas_sge64 sge64[1]; 2014}; 2015#pragma pack() 2016 2017#pragma pack(1) 2018struct mrsas_header { 2019 u_int8_t cmd; /*00e */ 2020 u_int8_t sense_len; /*01h */ 2021 u_int8_t cmd_status; /*02h */ 2022 u_int8_t scsi_status; /*03h */ 2023 2024 u_int8_t target_id; /*04h */ 2025 u_int8_t lun; /*05h */ 2026 u_int8_t cdb_len; /*06h */ 2027 u_int8_t sge_count; /*07h */ 2028 2029 u_int32_t context; /*08h */ 2030 u_int32_t pad_0; /*0Ch */ 2031 2032 u_int16_t flags; /*10h */ 2033 u_int16_t timeout; /*12h */ 2034 u_int32_t data_xferlen; /*14h */ 2035}; 2036#pragma pack() 2037 2038 2039typedef union _MFI_CAPABILITIES { 2040 struct { 2041 u_int32_t support_fp_remote_lun:1; 2042 u_int32_t support_additional_msix:1; 2043 u_int32_t support_fastpath_wb:1; 2044 u_int32_t support_max_255lds:1; 2045 u_int32_t reserved:28; 2046 } mfi_capabilities; 2047 u_int32_t reg; 2048} MFI_CAPABILITIES; 2049 2050#pragma pack(1) 2051struct mrsas_init_frame { 2052 u_int8_t cmd; /*00h */ 2053 u_int8_t reserved_0; /*01h */ 2054 u_int8_t cmd_status; /*02h */ 2055 2056 u_int8_t reserved_1; /*03h */ 2057 MFI_CAPABILITIES driver_operations; /*04h*/ 2058 u_int32_t context; /*08h */ 2059 u_int32_t pad_0; /*0Ch */ 2060 2061 u_int16_t flags; /*10h */ 2062 u_int16_t reserved_3; /*12h */ 2063 u_int32_t data_xfer_len; /*14h */ 2064 2065 u_int32_t queue_info_new_phys_addr_lo; /*18h */ 2066 u_int32_t queue_info_new_phys_addr_hi; /*1Ch */ 2067 u_int32_t queue_info_old_phys_addr_lo; /*20h */ 2068 u_int32_t queue_info_old_phys_addr_hi; /*24h */ 2069 u_int32_t driver_ver_lo; /*28h */ 2070 u_int32_t driver_ver_hi; /*2Ch */ 2071 u_int32_t reserved_4[4]; /*30h */ 2072}; 2073#pragma pack() 2074 2075#pragma pack(1) 2076struct mrsas_io_frame { 2077 u_int8_t cmd; /*00h */ 2078 u_int8_t sense_len; /*01h */ 2079 u_int8_t cmd_status; /*02h */ 2080 u_int8_t scsi_status; /*03h */ 2081 2082 u_int8_t target_id; /*04h */ 2083 u_int8_t access_byte; /*05h */ 2084 u_int8_t reserved_0; /*06h */ 2085 u_int8_t sge_count; /*07h */ 2086 2087 u_int32_t context; /*08h */ 2088 u_int32_t pad_0; /*0Ch */ 2089 2090 u_int16_t flags; /*10h */ 2091 u_int16_t timeout; /*12h */ 2092 u_int32_t lba_count; /*14h */ 2093 2094 u_int32_t sense_buf_phys_addr_lo; /*18h */ 2095 u_int32_t sense_buf_phys_addr_hi; /*1Ch */ 2096 2097 u_int32_t start_lba_lo; /*20h */ 2098 u_int32_t start_lba_hi; /*24h */ 2099 2100 union mrsas_sgl sgl; /*28h */ 2101}; 2102#pragma pack() 2103 2104#pragma pack(1) 2105struct mrsas_pthru_frame { 2106 u_int8_t cmd; /*00h */ 2107 u_int8_t sense_len; /*01h */ 2108 u_int8_t cmd_status; /*02h */ 2109 u_int8_t scsi_status; /*03h */ 2110 2111 u_int8_t target_id; /*04h */ 2112 u_int8_t lun; /*05h */ 2113 u_int8_t cdb_len; /*06h */ 2114 u_int8_t sge_count; /*07h */ 2115 2116 u_int32_t context; /*08h */ 2117 u_int32_t pad_0; /*0Ch */ 2118 2119 u_int16_t flags; /*10h */ 2120 u_int16_t timeout; /*12h */ 2121 u_int32_t data_xfer_len; /*14h */ 2122 2123 u_int32_t sense_buf_phys_addr_lo; /*18h */ 2124 u_int32_t sense_buf_phys_addr_hi; /*1Ch */ 2125 2126 u_int8_t cdb[16]; /*20h */ 2127 union mrsas_sgl sgl; /*30h */ 2128}; 2129#pragma pack() 2130 2131#pragma pack(1) 2132struct mrsas_dcmd_frame { 2133 u_int8_t cmd; /*00h */ 2134 u_int8_t reserved_0; /*01h */ 2135 u_int8_t cmd_status; /*02h */ 2136 u_int8_t reserved_1[4]; /*03h */ 2137 u_int8_t sge_count; /*07h */ 2138 2139 u_int32_t context; /*08h */ 2140 u_int32_t pad_0; /*0Ch */ 2141 2142 u_int16_t flags; /*10h */ 2143 u_int16_t timeout; /*12h */ 2144 2145 u_int32_t data_xfer_len; /*14h */ 2146 u_int32_t opcode; /*18h */ 2147 2148 union { /*1Ch */ 2149 u_int8_t b[12]; 2150 u_int16_t s[6]; 2151 u_int32_t w[3]; 2152 } mbox; 2153 2154 union mrsas_sgl sgl; /*28h */ 2155}; 2156#pragma pack() 2157 2158#pragma pack(1) 2159struct mrsas_abort_frame { 2160 u_int8_t cmd; /*00h */ 2161 u_int8_t reserved_0; /*01h */ 2162 u_int8_t cmd_status; /*02h */ 2163 2164 u_int8_t reserved_1; /*03h */ 2165 u_int32_t reserved_2; /*04h */ 2166 2167 u_int32_t context; /*08h */ 2168 u_int32_t pad_0; /*0Ch */ 2169 2170 u_int16_t flags; /*10h */ 2171 u_int16_t reserved_3; /*12h */ 2172 u_int32_t reserved_4; /*14h */ 2173 2174 u_int32_t abort_context; /*18h */ 2175 u_int32_t pad_1; /*1Ch */ 2176 2177 u_int32_t abort_mfi_phys_addr_lo; /*20h */ 2178 u_int32_t abort_mfi_phys_addr_hi; /*24h */ 2179 2180 u_int32_t reserved_5[6]; /*28h */ 2181}; 2182#pragma pack() 2183 2184#pragma pack(1) 2185struct mrsas_smp_frame { 2186 u_int8_t cmd; /*00h */ 2187 u_int8_t reserved_1; /*01h */ 2188 u_int8_t cmd_status; /*02h */ 2189 u_int8_t connection_status; /*03h */ 2190 2191 u_int8_t reserved_2[3]; /*04h */ 2192 u_int8_t sge_count; /*07h */ 2193 2194 u_int32_t context; /*08h */ 2195 u_int32_t pad_0; /*0Ch */ 2196 2197 u_int16_t flags; /*10h */ 2198 u_int16_t timeout; /*12h */ 2199 2200 u_int32_t data_xfer_len; /*14h */ 2201 u_int64_t sas_addr; /*18h */ 2202 2203 union { 2204 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */ 2205 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */ 2206 } sgl; 2207}; 2208#pragma pack() 2209 2210 2211#pragma pack(1) 2212struct mrsas_stp_frame { 2213 u_int8_t cmd; /*00h */ 2214 u_int8_t reserved_1; /*01h */ 2215 u_int8_t cmd_status; /*02h */ 2216 u_int8_t reserved_2; /*03h */ 2217 2218 u_int8_t target_id; /*04h */ 2219 u_int8_t reserved_3[2]; /*05h */ 2220 u_int8_t sge_count; /*07h */ 2221 2222 u_int32_t context; /*08h */ 2223 u_int32_t pad_0; /*0Ch */ 2224 2225 u_int16_t flags; /*10h */ 2226 u_int16_t timeout; /*12h */ 2227 2228 u_int32_t data_xfer_len; /*14h */ 2229 2230 u_int16_t fis[10]; /*18h */ 2231 u_int32_t stp_flags; 2232 2233 union { 2234 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */ 2235 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */ 2236 } sgl; 2237}; 2238#pragma pack() 2239 2240union mrsas_frame { 2241 struct mrsas_header hdr; 2242 struct mrsas_init_frame init; 2243 struct mrsas_io_frame io; 2244 struct mrsas_pthru_frame pthru; 2245 struct mrsas_dcmd_frame dcmd; 2246 struct mrsas_abort_frame abort; 2247 struct mrsas_smp_frame smp; 2248 struct mrsas_stp_frame stp; 2249 u_int8_t raw_bytes[64]; 2250}; 2251 2252#pragma pack(1) 2253union mrsas_evt_class_locale { 2254 2255 struct { 2256 u_int16_t locale; 2257 u_int8_t reserved; 2258 int8_t class; 2259 } __packed members; 2260 2261 u_int32_t word; 2262 2263} __packed; 2264 2265#pragma pack() 2266 2267 2268#pragma pack(1) 2269struct mrsas_evt_log_info { 2270 u_int32_t newest_seq_num; 2271 u_int32_t oldest_seq_num; 2272 u_int32_t clear_seq_num; 2273 u_int32_t shutdown_seq_num; 2274 u_int32_t boot_seq_num; 2275 2276} __packed; 2277 2278#pragma pack() 2279 2280struct mrsas_progress { 2281 2282 u_int16_t progress; 2283 u_int16_t elapsed_seconds; 2284 2285} __packed; 2286 2287struct mrsas_evtarg_ld { 2288 2289 u_int16_t target_id; 2290 u_int8_t ld_index; 2291 u_int8_t reserved; 2292 2293} __packed; 2294 2295struct mrsas_evtarg_pd { 2296 u_int16_t device_id; 2297 u_int8_t encl_index; 2298 u_int8_t slot_number; 2299 2300} __packed; 2301 2302struct mrsas_evt_detail { 2303 2304 u_int32_t seq_num; 2305 u_int32_t time_stamp; 2306 u_int32_t code; 2307 union mrsas_evt_class_locale cl; 2308 u_int8_t arg_type; 2309 u_int8_t reserved1[15]; 2310 2311 union { 2312 struct { 2313 struct mrsas_evtarg_pd pd; 2314 u_int8_t cdb_length; 2315 u_int8_t sense_length; 2316 u_int8_t reserved[2]; 2317 u_int8_t cdb[16]; 2318 u_int8_t sense[64]; 2319 } __packed cdbSense; 2320 2321 struct mrsas_evtarg_ld ld; 2322 2323 struct { 2324 struct mrsas_evtarg_ld ld; 2325 u_int64_t count; 2326 } __packed ld_count; 2327 2328 struct { 2329 u_int64_t lba; 2330 struct mrsas_evtarg_ld ld; 2331 } __packed ld_lba; 2332 2333 struct { 2334 struct mrsas_evtarg_ld ld; 2335 u_int32_t prevOwner; 2336 u_int32_t newOwner; 2337 } __packed ld_owner; 2338 2339 struct { 2340 u_int64_t ld_lba; 2341 u_int64_t pd_lba; 2342 struct mrsas_evtarg_ld ld; 2343 struct mrsas_evtarg_pd pd; 2344 } __packed ld_lba_pd_lba; 2345 2346 struct { 2347 struct mrsas_evtarg_ld ld; 2348 struct mrsas_progress prog; 2349 } __packed ld_prog; 2350 2351 struct { 2352 struct mrsas_evtarg_ld ld; 2353 u_int32_t prev_state; 2354 u_int32_t new_state; 2355 } __packed ld_state; 2356 2357 struct { 2358 u_int64_t strip; 2359 struct mrsas_evtarg_ld ld; 2360 } __packed ld_strip; 2361 2362 struct mrsas_evtarg_pd pd; 2363 2364 struct { 2365 struct mrsas_evtarg_pd pd; 2366 u_int32_t err; 2367 } __packed pd_err; 2368 2369 struct { 2370 u_int64_t lba; 2371 struct mrsas_evtarg_pd pd; 2372 } __packed pd_lba; 2373 2374 struct { 2375 u_int64_t lba; 2376 struct mrsas_evtarg_pd pd; 2377 struct mrsas_evtarg_ld ld; 2378 } __packed pd_lba_ld; 2379 2380 struct { 2381 struct mrsas_evtarg_pd pd; 2382 struct mrsas_progress prog; 2383 } __packed pd_prog; 2384 2385 struct { 2386 struct mrsas_evtarg_pd pd; 2387 u_int32_t prevState; 2388 u_int32_t newState; 2389 } __packed pd_state; 2390 2391 struct { 2392 u_int16_t vendorId; 2393 u_int16_t deviceId; 2394 u_int16_t subVendorId; 2395 u_int16_t subDeviceId; 2396 } __packed pci; 2397 2398 u_int32_t rate; 2399 char str[96]; 2400 2401 struct { 2402 u_int32_t rtc; 2403 u_int32_t elapsedSeconds; 2404 } __packed time; 2405 2406 struct { 2407 u_int32_t ecar; 2408 u_int32_t elog; 2409 char str[64]; 2410 } __packed ecc; 2411 2412 u_int8_t b[96]; 2413 u_int16_t s[48]; 2414 u_int32_t w[24]; 2415 u_int64_t d[12]; 2416 } args; 2417 2418 char description[128]; 2419 2420} __packed; 2421
| 46 47#ifndef MRSAS_H 48#define MRSAS_H 49 50#include <sys/param.h> /* defines used in kernel.h */ 51#include <sys/module.h> 52#include <sys/systm.h> 53#include <sys/proc.h> 54#include <sys/errno.h> 55#include <sys/kernel.h> /* types used in module initialization */ 56#include <sys/conf.h> /* cdevsw struct */ 57#include <sys/uio.h> /* uio struct */ 58#include <sys/malloc.h> 59#include <sys/bus.h> /* structs, prototypes for pci bus stuff */ 60 61#include <machine/bus.h> 62#include <sys/rman.h> 63#include <machine/resource.h> 64#include <machine/atomic.h> 65 66#include <dev/pci/pcivar.h> /* For pci_get macros! */ 67#include <dev/pci/pcireg.h> 68 69#include <sys/types.h> 70#include <sys/sysctl.h> 71#include <sys/stat.h> 72#include <sys/taskqueue.h> 73#include <sys/poll.h> 74#include <sys/selinfo.h> 75 76/* 77 * Device IDs and PCI 78 */ 79#define MRSAS_TBOLT 0x005b 80#define MRSAS_INVADER 0x005d 81#define MRSAS_FURY 0x005f 82#define MRSAS_PCI_BAR0 0x10 83#define MRSAS_PCI_BAR1 0x14 84#define MRSAS_PCI_BAR2 0x1C 85 86/* 87 * Firmware State Defines 88 */ 89#define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF 90#define MRSAS_FWSTATE_SGE_MASK 0x00FF0000 91#define MRSAS_FW_STATE_CHNG_INTERRUPT 1 92 93/* 94 * Message Frame Defines 95 */ 96#define MRSAS_SENSE_LEN 96 97#define MRSAS_FUSION_MAX_RESET_TRIES 3 98 99/* 100 * Miscellaneous Defines 101 */ 102#define BYTE_ALIGNMENT 1 103#define MRSAS_MAX_NAME_LENGTH 32 104#define MRSAS_VERSION "06.704.01.01-fbsd" 105#define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF 106#define MRSAS_DEFAULT_TIMEOUT 0x14 //temp 107#define DONE 0 108#define MRSAS_PAGE_SIZE 4096 109#define MRSAS_RESET_NOTICE_INTERVAL 5 110#define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */ 111#define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */ 112#define THRESHOLD_REPLY_COUNT 50 113 114/* 115 Boolean types 116*/ 117#if (__FreeBSD_version < 901000) 118 typedef enum _boolean { false, true } boolean; 119#endif 120enum err { SUCCESS, FAIL }; 121 122MALLOC_DECLARE(M_MRSAS); 123SYSCTL_DECL(_hw_mrsas); 124 125#define MRSAS_INFO (1 << 0) 126#define MRSAS_TRACE (1 << 1) 127#define MRSAS_FAULT (1 << 2) 128#define MRSAS_OCR (1 << 3) 129#define MRSAS_TOUT MRSAS_OCR 130#define MRSAS_AEN (1 << 4) 131#define MRSAS_PRL11 (1 << 5) 132 133#define mrsas_dprint(sc, level, msg, args...) \ 134do { \ 135 if (sc->mrsas_debug & level) \ 136 device_printf(sc->mrsas_dev, msg, ##args); \ 137} while (0) 138 139 140/**************************************************************************** 141 * Raid Context structure which describes MegaRAID specific IO Paramenters 142 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 143 ****************************************************************************/ 144 145typedef struct _RAID_CONTEXT { 146 u_int8_t Type:4; // 0x00 147 u_int8_t nseg:4; // 0x00 148 u_int8_t resvd0; // 0x01 149 u_int16_t timeoutValue; // 0x02 -0x03 150 u_int8_t regLockFlags; // 0x04 151 u_int8_t resvd1; // 0x05 152 u_int16_t VirtualDiskTgtId; // 0x06 -0x07 153 u_int64_t regLockRowLBA; // 0x08 - 0x0F 154 u_int32_t regLockLength; // 0x10 - 0x13 155 u_int16_t nextLMId; // 0x14 - 0x15 156 u_int8_t exStatus; // 0x16 157 u_int8_t status; // 0x17 status 158 u_int8_t RAIDFlags; // 0x18 resvd[7:6],ioSubType[5:4],resvd[3:1],preferredCpu[0] 159 u_int8_t numSGE; // 0x19 numSge; not including chain entries 160 u_int16_t configSeqNum; // 0x1A -0x1B 161 u_int8_t spanArm; // 0x1C span[7:5], arm[4:0] 162 u_int8_t resvd2[3]; // 0x1D-0x1f 163} RAID_CONTEXT; 164 165 166/************************************************************************* 167 * MPI2 Defines 168 ************************************************************************/ 169 170#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 171#define MPI2_WHOINIT_HOST_DRIVER (0x04) 172#define MPI2_VERSION_MAJOR (0x02) 173#define MPI2_VERSION_MINOR (0x00) 174#define MPI2_VERSION_MAJOR_MASK (0xFF00) 175#define MPI2_VERSION_MAJOR_SHIFT (8) 176#define MPI2_VERSION_MINOR_MASK (0x00FF) 177#define MPI2_VERSION_MINOR_SHIFT (0) 178#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 179 MPI2_VERSION_MINOR) 180#define MPI2_HEADER_VERSION_UNIT (0x10) 181#define MPI2_HEADER_VERSION_DEV (0x00) 182#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 183#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 184#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 185#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 186#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 187#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 188#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 189#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 190#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 191#define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 192#define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 193#define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 194#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 195#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 196#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 197#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 198#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 199#define MPI2_SCSIIO_CONTROL_READ (0x02000000) 200#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 201#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 202#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 203#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 204#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 205#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 206#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 207#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 208#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 209#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 210#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 211#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 212 213#ifndef MPI2_POINTER 214#define MPI2_POINTER * 215#endif 216 217 218/*************************************** 219 * MPI2 Structures 220 ***************************************/ 221 222typedef struct _MPI25_IEEE_SGE_CHAIN64 223{ 224 u_int64_t Address; 225 u_int32_t Length; 226 u_int16_t Reserved1; 227 u_int8_t NextChainOffset; 228 u_int8_t Flags; 229} MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 230 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 231 232typedef struct _MPI2_SGE_SIMPLE_UNION 233{ 234 u_int32_t FlagsLength; 235 union 236 { 237 u_int32_t Address32; 238 u_int64_t Address64; 239 } u; 240} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 241 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 242 243typedef struct 244{ 245 u_int8_t CDB[20]; /* 0x00 */ 246 u_int32_t PrimaryReferenceTag; /* 0x14 */ 247 u_int16_t PrimaryApplicationTag; /* 0x18 */ 248 u_int16_t PrimaryApplicationTagMask; /* 0x1A */ 249 u_int32_t TransferLength; /* 0x1C */ 250} MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32, 251 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t; 252 253typedef struct _MPI2_SGE_CHAIN_UNION 254{ 255 u_int16_t Length; 256 u_int8_t NextChainOffset; 257 u_int8_t Flags; 258 union 259 { 260 u_int32_t Address32; 261 u_int64_t Address64; 262 } u; 263} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 264 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 265 266typedef struct _MPI2_IEEE_SGE_SIMPLE32 267{ 268 u_int32_t Address; 269 u_int32_t FlagsLength; 270} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 271 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 272typedef struct _MPI2_IEEE_SGE_SIMPLE64 273{ 274 u_int64_t Address; 275 u_int32_t Length; 276 u_int16_t Reserved1; 277 u_int8_t Reserved2; 278 u_int8_t Flags; 279} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 280 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 281 282typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 283{ 284 MPI2_IEEE_SGE_SIMPLE32 Simple32; 285 MPI2_IEEE_SGE_SIMPLE64 Simple64; 286} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 287 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 288 289typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 290typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 291 292typedef union _MPI2_IEEE_SGE_CHAIN_UNION 293{ 294 MPI2_IEEE_SGE_CHAIN32 Chain32; 295 MPI2_IEEE_SGE_CHAIN64 Chain64; 296} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 297 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 298 299typedef union _MPI2_SGE_IO_UNION 300{ 301 MPI2_SGE_SIMPLE_UNION MpiSimple; 302 MPI2_SGE_CHAIN_UNION MpiChain; 303 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 304 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 305} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 306 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 307 308typedef union 309{ 310 u_int8_t CDB32[32]; 311 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 312 MPI2_SGE_SIMPLE_UNION SGE; 313} MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION, 314 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t; 315 316/* 317 * RAID SCSI IO Request Message 318 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 319 */ 320typedef struct _MPI2_RAID_SCSI_IO_REQUEST 321{ 322 u_int16_t DevHandle; /* 0x00 */ 323 u_int8_t ChainOffset; /* 0x02 */ 324 u_int8_t Function; /* 0x03 */ 325 u_int16_t Reserved1; /* 0x04 */ 326 u_int8_t Reserved2; /* 0x06 */ 327 u_int8_t MsgFlags; /* 0x07 */ 328 u_int8_t VP_ID; /* 0x08 */ 329 u_int8_t VF_ID; /* 0x09 */ 330 u_int16_t Reserved3; /* 0x0A */ 331 u_int32_t SenseBufferLowAddress; /* 0x0C */ 332 u_int16_t SGLFlags; /* 0x10 */ 333 u_int8_t SenseBufferLength; /* 0x12 */ 334 u_int8_t Reserved4; /* 0x13 */ 335 u_int8_t SGLOffset0; /* 0x14 */ 336 u_int8_t SGLOffset1; /* 0x15 */ 337 u_int8_t SGLOffset2; /* 0x16 */ 338 u_int8_t SGLOffset3; /* 0x17 */ 339 u_int32_t SkipCount; /* 0x18 */ 340 u_int32_t DataLength; /* 0x1C */ 341 u_int32_t BidirectionalDataLength; /* 0x20 */ 342 u_int16_t IoFlags; /* 0x24 */ 343 u_int16_t EEDPFlags; /* 0x26 */ 344 u_int32_t EEDPBlockSize; /* 0x28 */ 345 u_int32_t SecondaryReferenceTag; /* 0x2C */ 346 u_int16_t SecondaryApplicationTag; /* 0x30 */ 347 u_int16_t ApplicationTagTranslationMask; /* 0x32 */ 348 u_int8_t LUN[8]; /* 0x34 */ 349 u_int32_t Control; /* 0x3C */ 350 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 351 RAID_CONTEXT RaidContext; /* 0x60 */ 352 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 353} MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST, 354 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t; 355 356/* 357 * MPT RAID MFA IO Descriptor. 358 */ 359typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR { 360 u_int32_t RequestFlags : 8; 361 u_int32_t MessageAddress1 : 24; /* bits 31:8*/ 362 u_int32_t MessageAddress2; /* bits 61:32 */ 363} MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR; 364 365/* Default Request Descriptor */ 366typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 367{ 368 u_int8_t RequestFlags; /* 0x00 */ 369 u_int8_t MSIxIndex; /* 0x01 */ 370 u_int16_t SMID; /* 0x02 */ 371 u_int16_t LMID; /* 0x04 */ 372 u_int16_t DescriptorTypeDependent; /* 0x06 */ 373} MPI2_DEFAULT_REQUEST_DESCRIPTOR, 374 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 375 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 376 377/* High Priority Request Descriptor */ 378typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 379{ 380 u_int8_t RequestFlags; /* 0x00 */ 381 u_int8_t MSIxIndex; /* 0x01 */ 382 u_int16_t SMID; /* 0x02 */ 383 u_int16_t LMID; /* 0x04 */ 384 u_int16_t Reserved1; /* 0x06 */ 385} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 386 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 387 Mpi2HighPriorityRequestDescriptor_t, 388 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 389 390/* SCSI IO Request Descriptor */ 391typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 392{ 393 u_int8_t RequestFlags; /* 0x00 */ 394 u_int8_t MSIxIndex; /* 0x01 */ 395 u_int16_t SMID; /* 0x02 */ 396 u_int16_t LMID; /* 0x04 */ 397 u_int16_t DevHandle; /* 0x06 */ 398} MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 399 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 400 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 401 402/* SCSI Target Request Descriptor */ 403typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 404{ 405 u_int8_t RequestFlags; /* 0x00 */ 406 u_int8_t MSIxIndex; /* 0x01 */ 407 u_int16_t SMID; /* 0x02 */ 408 u_int16_t LMID; /* 0x04 */ 409 u_int16_t IoIndex; /* 0x06 */ 410} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 411 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 412 Mpi2SCSITargetRequestDescriptor_t, 413 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 414 415/* RAID Accelerator Request Descriptor */ 416typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 417{ 418 u_int8_t RequestFlags; /* 0x00 */ 419 u_int8_t MSIxIndex; /* 0x01 */ 420 u_int16_t SMID; /* 0x02 */ 421 u_int16_t LMID; /* 0x04 */ 422 u_int16_t Reserved; /* 0x06 */ 423} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 424 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 425 Mpi2RAIDAcceleratorRequestDescriptor_t, 426 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 427 428/* union of Request Descriptors */ 429typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION 430{ 431 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 432 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 433 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 434 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 435 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 436 MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 437 union { 438 struct { 439 u_int32_t low; 440 u_int32_t high; 441 } u; 442 u_int64_t Words; 443 } addr; 444} MRSAS_REQUEST_DESCRIPTOR_UNION; 445 446/* Default Reply Descriptor */ 447typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 448{ 449 u_int8_t ReplyFlags; /* 0x00 */ 450 u_int8_t MSIxIndex; /* 0x01 */ 451 u_int16_t DescriptorTypeDependent1; /* 0x02 */ 452 u_int32_t DescriptorTypeDependent2; /* 0x04 */ 453} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 454 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 455 456/* Address Reply Descriptor */ 457typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 458{ 459 u_int8_t ReplyFlags; /* 0x00 */ 460 u_int8_t MSIxIndex; /* 0x01 */ 461 u_int16_t SMID; /* 0x02 */ 462 u_int32_t ReplyFrameAddress; /* 0x04 */ 463} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 464 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 465 466/* SCSI IO Success Reply Descriptor */ 467typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 468{ 469 u_int8_t ReplyFlags; /* 0x00 */ 470 u_int8_t MSIxIndex; /* 0x01 */ 471 u_int16_t SMID; /* 0x02 */ 472 u_int16_t TaskTag; /* 0x04 */ 473 u_int16_t Reserved1; /* 0x06 */ 474} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 475 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 476 Mpi2SCSIIOSuccessReplyDescriptor_t, 477 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 478 479/* TargetAssist Success Reply Descriptor */ 480typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 481{ 482 u_int8_t ReplyFlags; /* 0x00 */ 483 u_int8_t MSIxIndex; /* 0x01 */ 484 u_int16_t SMID; /* 0x02 */ 485 u_int8_t SequenceNumber; /* 0x04 */ 486 u_int8_t Reserved1; /* 0x05 */ 487 u_int16_t IoIndex; /* 0x06 */ 488} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 489 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 490 Mpi2TargetAssistSuccessReplyDescriptor_t, 491 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 492 493/* Target Command Buffer Reply Descriptor */ 494typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 495{ 496 u_int8_t ReplyFlags; /* 0x00 */ 497 u_int8_t MSIxIndex; /* 0x01 */ 498 u_int8_t VP_ID; /* 0x02 */ 499 u_int8_t Flags; /* 0x03 */ 500 u_int16_t InitiatorDevHandle; /* 0x04 */ 501 u_int16_t IoIndex; /* 0x06 */ 502} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 503 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 504 Mpi2TargetCommandBufferReplyDescriptor_t, 505 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 506 507/* RAID Accelerator Success Reply Descriptor */ 508typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 509{ 510 u_int8_t ReplyFlags; /* 0x00 */ 511 u_int8_t MSIxIndex; /* 0x01 */ 512 u_int16_t SMID; /* 0x02 */ 513 u_int32_t Reserved; /* 0x04 */ 514} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 515 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 516 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 517 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 518 519/* union of Reply Descriptors */ 520typedef union _MPI2_REPLY_DESCRIPTORS_UNION 521{ 522 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 523 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 524 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 525 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 526 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 527 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 528 u_int64_t Words; 529} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 530 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 531 532typedef struct { 533 volatile unsigned int val; 534} atomic_t; 535 536#define atomic_read(v) atomic_load_acq_int(&(v)->val) 537#define atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 538#define atomic_dec(v) atomic_fetchadd_int(&(v)->val, -1) 539#define atomic_inc(v) atomic_fetchadd_int(&(v)->val, 1) 540 541/* IOCInit Request message */ 542typedef struct _MPI2_IOC_INIT_REQUEST 543{ 544 u_int8_t WhoInit; /* 0x00 */ 545 u_int8_t Reserved1; /* 0x01 */ 546 u_int8_t ChainOffset; /* 0x02 */ 547 u_int8_t Function; /* 0x03 */ 548 u_int16_t Reserved2; /* 0x04 */ 549 u_int8_t Reserved3; /* 0x06 */ 550 u_int8_t MsgFlags; /* 0x07 */ 551 u_int8_t VP_ID; /* 0x08 */ 552 u_int8_t VF_ID; /* 0x09 */ 553 u_int16_t Reserved4; /* 0x0A */ 554 u_int16_t MsgVersion; /* 0x0C */ 555 u_int16_t HeaderVersion; /* 0x0E */ 556 u_int32_t Reserved5; /* 0x10 */ 557 u_int16_t Reserved6; /* 0x14 */ 558 u_int8_t Reserved7; /* 0x16 */ 559 u_int8_t HostMSIxVectors; /* 0x17 */ 560 u_int16_t Reserved8; /* 0x18 */ 561 u_int16_t SystemRequestFrameSize; /* 0x1A */ 562 u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 563 u_int16_t ReplyFreeQueueDepth; /* 0x1E */ 564 u_int32_t SenseBufferAddressHigh; /* 0x20 */ 565 u_int32_t SystemReplyAddressHigh; /* 0x24 */ 566 u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */ 567 u_int64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 568 u_int64_t ReplyFreeQueueAddress; /* 0x38 */ 569 u_int64_t TimeStamp; /* 0x40 */ 570} MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 571 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 572 573/* 574 * MR private defines 575 */ 576#define MR_PD_INVALID 0xFFFF 577#define MAX_SPAN_DEPTH 8 578#define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 579#define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 580#define MAX_ROW_SIZE 32 581#define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 582#define MAX_LOGICAL_DRIVES 64 583#define MAX_LOGICAL_DRIVES_EXT 256 584 585#define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 586#define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 587 588#define MAX_ARRAYS 128 589#define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 590 591#define MAX_ARRAYS_EXT 256 592#define MAX_API_ARRAYS_EXT MAX_ARRAYS_EXT 593 594#define MAX_PHYSICAL_DEVICES 256 595#define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 596#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 // get the mapping information of this LD 597 598 599#define MRSAS_MAX_PD_CHANNELS 1 600#define MRSAS_MAX_LD_CHANNELS 1 601#define MRSAS_MAX_DEV_PER_CHANNEL 256 602#define MRSAS_DEFAULT_INIT_ID -1 603#define MRSAS_MAX_LUN 8 604#define MRSAS_DEFAULT_CMD_PER_LUN 256 605#define MRSAS_MAX_PD (MRSAS_MAX_PD_CHANNELS * \ 606 MRSAS_MAX_DEV_PER_CHANNEL) 607#define MRSAS_MAX_LD_IDS (MRSAS_MAX_LD_CHANNELS * \ 608 MRSAS_MAX_DEV_PER_CHANNEL) 609 610 611#define VD_EXT_DEBUG 0 612 613 614/******************************************************************* 615 * RAID map related structures 616 ********************************************************************/ 617#pragma pack(1) 618typedef struct _MR_DEV_HANDLE_INFO { 619 u_int16_t curDevHdl; // the device handle currently used by fw to issue the command. 620 u_int8_t validHandles; // bitmap of valid device handles. 621 u_int8_t reserved; 622 u_int16_t devHandle[2]; // 0x04 dev handles for all the paths. 623} MR_DEV_HANDLE_INFO; 624#pragma pack() 625 626typedef struct _MR_ARRAY_INFO { 627 u_int16_t pd[MAX_RAIDMAP_ROW_SIZE]; 628} MR_ARRAY_INFO; // 0x40, Total Size 629 630typedef struct _MR_QUAD_ELEMENT { 631 u_int64_t logStart; // 0x00 632 u_int64_t logEnd; // 0x08 633 u_int64_t offsetInSpan; // 0x10 634 u_int32_t diff; // 0x18 635 u_int32_t reserved1; // 0x1C 636} MR_QUAD_ELEMENT; // 0x20, Total size 637 638typedef struct _MR_SPAN_INFO { 639 u_int32_t noElements; // 0x00 640 u_int32_t reserved1; // 0x04 641 MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; // 0x08 642} MR_SPAN_INFO; // 0x108, Total size 643 644typedef struct _MR_LD_SPAN_ { // SPAN structure 645 u_int64_t startBlk; // 0x00, starting block number in array 646 u_int64_t numBlks; // 0x08, number of blocks 647 u_int16_t arrayRef; // 0x10, array reference 648 u_int8_t spanRowSize; // 0x11, span row size 649 u_int8_t spanRowDataSize; // 0x12, span row data size 650 u_int8_t reserved[4]; // 0x13, reserved 651} MR_LD_SPAN; // 0x18, Total Size 652 653typedef struct _MR_SPAN_BLOCK_INFO { 654 u_int64_t num_rows; // number of rows/span 655 MR_LD_SPAN span; // 0x08 656 MR_SPAN_INFO block_span_info; // 0x20 657} MR_SPAN_BLOCK_INFO; 658 659typedef struct _MR_LD_RAID { 660 struct { 661 u_int32_t fpCapable :1; 662 u_int32_t reserved5 :3; 663 u_int32_t ldPiMode :4; 664 u_int32_t pdPiMode :4; // Every Pd has to be same. 665 u_int32_t encryptionType :8; // FDE or ctlr encryption (MR_LD_ENCRYPTION_TYPE) 666 u_int32_t fpWriteCapable :1; 667 u_int32_t fpReadCapable :1; 668 u_int32_t fpWriteAcrossStripe :1; 669 u_int32_t fpReadAcrossStripe :1; 670 u_int32_t fpNonRWCapable :1; // TRUE if supporting Non RW IO 671 u_int32_t reserved4 :7; 672 } capability; // 0x00 673 u_int32_t reserved6; 674 u_int64_t size; // 0x08, LD size in blocks 675 676 u_int8_t spanDepth; // 0x10, Total Number of Spans 677 u_int8_t level; // 0x11, RAID level 678 u_int8_t stripeShift; // 0x12, shift-count to get stripe size (0=512, 1=1K, 7=64K, etc.) 679 u_int8_t rowSize; // 0x13, number of disks in a row 680 681 u_int8_t rowDataSize; // 0x14, number of data disks in a row 682 u_int8_t writeMode; // 0x15, WRITE_THROUGH or WRITE_BACK 683 u_int8_t PRL; // 0x16, To differentiate between RAID1 and RAID1E 684 u_int8_t SRL; // 0x17 685 686 u_int16_t targetId; // 0x18, ld Target Id. 687 u_int8_t ldState; // 0x1a, state of ld, state corresponds to MR_LD_STATE 688 u_int8_t regTypeReqOnWrite;// 0x1b, Pre calculate region type requests based on MFC etc.. 689 u_int8_t modFactor; // 0x1c, same as rowSize, 690 u_int8_t regTypeReqOnRead; // 0x1d, region lock type used for read, valid only if regTypeOnReadIsValid=1 691 u_int16_t seqNum; // 0x1e, LD sequence number 692 693 struct { 694 u_int32_t ldSyncRequired:1; // This LD requires sync command before completing 695 u_int32_t regTypeReqOnReadLsValid:1; // Qualifier for regTypeOnRead 696 u_int32_t reserved:30; 697 } flags; // 0x20 698 699 u_int8_t LUN[8]; // 0x24, 8 byte LUN field used for SCSI 700 u_int8_t fpIoTimeoutForLd; // 0x2C, timeout value for FP IOs 701 u_int8_t reserved2[3]; // 0x2D 702 u_int32_t logicalBlockLength; // 0x30 Logical block size for the LD 703 struct { 704 u_int32_t LdPiExp:4; // 0x34, P_I_EXPONENT for ReadCap 16 705 u_int32_t LdLogicalBlockExp:4; // 0x34, LOGICAL BLOCKS PER PHYS BLOCK 706 u_int32_t reserved1:24; // 0x34 707 } exponent; 708 u_int8_t reserved3[0x80-0x38]; // 0x38 709} MR_LD_RAID; // 0x80, Total Size 710 711typedef struct _MR_LD_SPAN_MAP { 712 MR_LD_RAID ldRaid; // 0x00 713 u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; // 0x80, needed for GET_ARM() - R0/1/5 only. 714 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; // 0xA0 715} MR_LD_SPAN_MAP; // 0x9E0 716 717typedef struct _MR_FW_RAID_MAP { 718 u_int32_t totalSize; // total size of this structure, including this field. 719 union { 720 struct { // Simple method of version checking variables 721 u_int32_t maxLd; 722 u_int32_t maxSpanDepth; 723 u_int32_t maxRowSize; 724 u_int32_t maxPdCount; 725 u_int32_t maxArrays; 726 } validationInfo; 727 u_int32_t version[5]; 728 u_int32_t reserved1[5]; 729 } raid_desc; 730 u_int32_t ldCount; // count of lds. 731 u_int32_t Reserved1; 732 u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS]; // 0x20 733 // This doesn't correspond to 734 // FW Ld Tgt Id to LD, but will purge. For example: if tgt Id is 4 735 // and FW LD is 2, and there is only one LD, FW will populate the 736 // array like this. [0xFF, 0xFF, 0xFF, 0xFF, 0x0,.....]. This is to 737 // help reduce the entire strcture size if there are few LDs or 738 // driver is looking info for 1 LD only. 739 u_int8_t fpPdIoTimeoutSec; // timeout value used by driver in FP IOs 740 u_int8_t reserved2[7]; 741 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; // 0x00a8 742 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; // 0x20a8 743 MR_LD_SPAN_MAP ldSpanMap[1]; // 0x28a8-[0-MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS+1]; 744} MR_FW_RAID_MAP; // 0x3288, Total Size 745 746 747typedef struct _MR_FW_RAID_MAP_EXT { 748 /* Not used in new map */ 749 u_int32_t reserved; 750 751 union { 752 struct { 753 u_int32_t maxLd; 754 u_int32_t maxSpanDepth; 755 u_int32_t maxRowSize; 756 u_int32_t maxPdCount; 757 u_int32_t maxArrays; 758 } validationInfo; 759 u_int32_t version[5]; 760 u_int32_t reserved1[5]; 761 }fw_raid_desc; 762 763 u_int8_t fpPdIoTimeoutSec; 764 u_int8_t reserved2[7]; 765 766 u_int16_t ldCount; 767 u_int16_t arCount; 768 u_int16_t spanCount; 769 u_int16_t reserve3; 770 771 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 772 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 773 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 774 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT]; 775} MR_FW_RAID_MAP_EXT; 776 777 778typedef struct _MR_DRV_RAID_MAP { 779 /* total size of this structure, including this field. 780 * This feild will be manupulated by driver for ext raid map, 781 * else pick the value from firmware raid map. 782 */ 783 u_int32_t totalSize; 784 785 union { 786 struct { 787 u_int32_t maxLd; 788 u_int32_t maxSpanDepth; 789 u_int32_t maxRowSize; 790 u_int32_t maxPdCount; 791 u_int32_t maxArrays; 792 } validationInfo; 793 u_int32_t version[5]; 794 u_int32_t reserved1[5]; 795 }drv_raid_desc; 796 797 /* timeout value used by driver in FP IOs*/ 798 u_int8_t fpPdIoTimeoutSec; 799 u_int8_t reserved2[7]; 800 801 u_int16_t ldCount; 802 u_int16_t arCount; 803 u_int16_t spanCount; 804 u_int16_t reserve3; 805 806 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 807 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 808 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 809 MR_LD_SPAN_MAP ldSpanMap[1]; 810 811}MR_DRV_RAID_MAP; 812 813/* Driver raid map size is same as raid map ext 814 * MR_DRV_RAID_MAP_ALL is created to sync with old raid. 815 * And it is mainly for code re-use purpose. 816 */ 817 818#pragma pack(1) 819typedef struct _MR_DRV_RAID_MAP_ALL { 820 821 MR_DRV_RAID_MAP raidMap; 822 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT - 1]; 823}MR_DRV_RAID_MAP_ALL; 824#pragma pack() 825 826typedef struct _LD_LOAD_BALANCE_INFO 827{ 828 u_int8_t loadBalanceFlag; 829 u_int8_t reserved1; 830 u_int16_t raid1DevHandle[2]; 831 atomic_t scsi_pending_cmds[2]; 832 u_int64_t last_accessed_block[2]; 833} LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO; 834 835/* SPAN_SET is info caclulated from span info from Raid map per ld */ 836typedef struct _LD_SPAN_SET { 837 u_int64_t log_start_lba; 838 u_int64_t log_end_lba; 839 u_int64_t span_row_start; 840 u_int64_t span_row_end; 841 u_int64_t data_strip_start; 842 u_int64_t data_strip_end; 843 u_int64_t data_row_start; 844 u_int64_t data_row_end; 845 u_int8_t strip_offset[MAX_SPAN_DEPTH]; 846 u_int32_t span_row_data_width; 847 u_int32_t diff; 848 u_int32_t reserved[2]; 849}LD_SPAN_SET, *PLD_SPAN_SET; 850 851typedef struct LOG_BLOCK_SPAN_INFO { 852 LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 853}LD_SPAN_INFO, *PLD_SPAN_INFO; 854 855#pragma pack(1) 856typedef struct _MR_FW_RAID_MAP_ALL { 857 MR_FW_RAID_MAP raidMap; 858 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 859} MR_FW_RAID_MAP_ALL; 860#pragma pack() 861 862struct IO_REQUEST_INFO { 863 u_int64_t ldStartBlock; 864 u_int32_t numBlocks; 865 u_int16_t ldTgtId; 866 u_int8_t isRead; 867 u_int16_t devHandle; 868 u_int64_t pdBlock; 869 u_int8_t fpOkForIo; 870 u_int8_t IoforUnevenSpan; 871 u_int8_t start_span; 872 u_int8_t reserved; 873 u_int64_t start_row; 874}; 875 876typedef struct _MR_LD_TARGET_SYNC { 877 u_int8_t targetId; 878 u_int8_t reserved; 879 u_int16_t seqNum; 880} MR_LD_TARGET_SYNC; 881 882#define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 883#define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 884#define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 885#define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 886#define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 887#define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 888#define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 889 890union desc_value { 891 u_int64_t word; 892 struct { 893 u_int32_t low; 894 u_int32_t high; 895 } u; 896}; 897 898/******************************************************************* 899 * Temporary command 900 ********************************************************************/ 901struct mrsas_tmp_dcmd { 902 bus_dma_tag_t tmp_dcmd_tag; // tag for tmp DMCD cmd 903 bus_dmamap_t tmp_dcmd_dmamap; // dmamap for tmp DCMD cmd 904 void *tmp_dcmd_mem; // virtual addr of tmp DCMD cmd 905 bus_addr_t tmp_dcmd_phys_addr; //physical addr of tmp DCMD 906}; 907 908/******************************************************************* 909 * Register set, included legacy controllers 1068 and 1078, 910 * structure extended for 1078 registers 911 ********************************************************************/ 912#pragma pack(1) 913typedef struct _mrsas_register_set { 914 u_int32_t doorbell; /*0000h*/ 915 u_int32_t fusion_seq_offset; /*0004h*/ 916 u_int32_t fusion_host_diag; /*0008h*/ 917 u_int32_t reserved_01; /*000Ch*/ 918 919 u_int32_t inbound_msg_0; /*0010h*/ 920 u_int32_t inbound_msg_1; /*0014h*/ 921 u_int32_t outbound_msg_0; /*0018h*/ 922 u_int32_t outbound_msg_1; /*001Ch*/ 923 924 u_int32_t inbound_doorbell; /*0020h*/ 925 u_int32_t inbound_intr_status; /*0024h*/ 926 u_int32_t inbound_intr_mask; /*0028h*/ 927 928 u_int32_t outbound_doorbell; /*002Ch*/ 929 u_int32_t outbound_intr_status; /*0030h*/ 930 u_int32_t outbound_intr_mask; /*0034h*/ 931 932 u_int32_t reserved_1[2]; /*0038h*/ 933 934 u_int32_t inbound_queue_port; /*0040h*/ 935 u_int32_t outbound_queue_port; /*0044h*/ 936 937 u_int32_t reserved_2[9]; /*0048h*/ 938 u_int32_t reply_post_host_index; /*006Ch*/ 939 u_int32_t reserved_2_2[12]; /*0070h*/ 940 941 u_int32_t outbound_doorbell_clear; /*00A0h*/ 942 943 u_int32_t reserved_3[3]; /*00A4h*/ 944 945 u_int32_t outbound_scratch_pad ; /*00B0h*/ 946 u_int32_t outbound_scratch_pad_2; /*00B4h*/ 947 948 u_int32_t reserved_4[2]; /*00B8h*/ 949 950 u_int32_t inbound_low_queue_port ; /*00C0h*/ 951 952 u_int32_t inbound_high_queue_port ; /*00C4h*/ 953 954 u_int32_t reserved_5; /*00C8h*/ 955 u_int32_t res_6[11]; /*CCh*/ 956 u_int32_t host_diag; 957 u_int32_t seq_offset; 958 u_int32_t index_registers[807]; /*00CCh*/ 959 960} mrsas_reg_set; 961#pragma pack() 962 963/******************************************************************* 964 * Firmware Interface Defines 965 ******************************************************************* 966 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker 967 * for protocol between the software and firmware. Commands are 968 * issued using "message frames". 969 ******************************************************************/ 970/* 971 * FW posts its state in upper 4 bits of outbound_msg_0 register 972 */ 973#define MFI_STATE_MASK 0xF0000000 974#define MFI_STATE_UNDEFINED 0x00000000 975#define MFI_STATE_BB_INIT 0x10000000 976#define MFI_STATE_FW_INIT 0x40000000 977#define MFI_STATE_WAIT_HANDSHAKE 0x60000000 978#define MFI_STATE_FW_INIT_2 0x70000000 979#define MFI_STATE_DEVICE_SCAN 0x80000000 980#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 981#define MFI_STATE_FLUSH_CACHE 0xA0000000 982#define MFI_STATE_READY 0xB0000000 983#define MFI_STATE_OPERATIONAL 0xC0000000 984#define MFI_STATE_FAULT 0xF0000000 985#define MFI_RESET_REQUIRED 0x00000001 986#define MFI_RESET_ADAPTER 0x00000002 987#define MEGAMFI_FRAME_SIZE 64 988#define MRSAS_MFI_FRAME_SIZE 1024 989#define MRSAS_MFI_SENSE_SIZE 128 990 991/* 992 * During FW init, clear pending cmds & reset state using inbound_msg_0 993 * 994 * ABORT : Abort all pending cmds 995 * READY : Move from OPERATIONAL to READY state; discard queue info 996 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 997 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 998 * HOTPLUG : Resume from Hotplug 999 * MFI_STOP_ADP : Send signal to FW to stop processing 1000 */ 1001 1002#define WRITE_SEQUENCE_OFFSET (0x0000000FC) // I20 1003#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) // I20 1004#define DIAG_WRITE_ENABLE (0x00000080) 1005#define DIAG_RESET_ADAPTER (0x00000004) 1006 1007#define MFI_ADP_RESET 0x00000040 1008#define MFI_INIT_ABORT 0x00000001 1009#define MFI_INIT_READY 0x00000002 1010#define MFI_INIT_MFIMODE 0x00000004 1011#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 1012#define MFI_INIT_HOTPLUG 0x00000010 1013#define MFI_STOP_ADP 0x00000020 1014#define MFI_RESET_FLAGS MFI_INIT_READY| \ 1015 MFI_INIT_MFIMODE| \ 1016 MFI_INIT_ABORT 1017 1018/* 1019 * MFI frame flags 1020 */ 1021#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 1022#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 1023#define MFI_FRAME_SGL32 0x0000 1024#define MFI_FRAME_SGL64 0x0002 1025#define MFI_FRAME_SENSE32 0x0000 1026#define MFI_FRAME_SENSE64 0x0004 1027#define MFI_FRAME_DIR_NONE 0x0000 1028#define MFI_FRAME_DIR_WRITE 0x0008 1029#define MFI_FRAME_DIR_READ 0x0010 1030#define MFI_FRAME_DIR_BOTH 0x0018 1031#define MFI_FRAME_IEEE 0x0020 1032 1033/* 1034 * Definition for cmd_status 1035 */ 1036#define MFI_CMD_STATUS_POLL_MODE 0xFF 1037 1038/* 1039 * MFI command opcodes 1040 */ 1041#define MFI_CMD_INIT 0x00 1042#define MFI_CMD_LD_READ 0x01 1043#define MFI_CMD_LD_WRITE 0x02 1044#define MFI_CMD_LD_SCSI_IO 0x03 1045#define MFI_CMD_PD_SCSI_IO 0x04 1046#define MFI_CMD_DCMD 0x05 1047#define MFI_CMD_ABORT 0x06 1048#define MFI_CMD_SMP 0x07 1049#define MFI_CMD_STP 0x08 1050#define MFI_CMD_INVALID 0xff 1051 1052#define MR_DCMD_CTRL_GET_INFO 0x01010000 1053#define MR_DCMD_LD_GET_LIST 0x03010000 1054#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 1055#define MR_FLUSH_CTRL_CACHE 0x01 1056#define MR_FLUSH_DISK_CACHE 0x02 1057 1058#define MR_DCMD_CTRL_SHUTDOWN 0x01050000 1059#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 1060#define MR_ENABLE_DRIVE_SPINDOWN 0x01 1061 1062#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 1063#define MR_DCMD_CTRL_EVENT_GET 0x01040300 1064#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 1065#define MR_DCMD_LD_GET_PROPERTIES 0x03030000 1066 1067#define MR_DCMD_CLUSTER 0x08000000 1068#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 1069#define MR_DCMD_CLUSTER_RESET_LD 0x08010200 1070#define MR_DCMD_PD_LIST_QUERY 0x02010100 1071 1072#define MR_DCMD_CTRL_MISC_CPX 0x0100e200 1073#define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201 1074#define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202 1075#define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203 1076#define MAX_MR_ROW_SIZE 32 1077#define MR_CPX_DIR_WRITE 1 1078#define MR_CPX_DIR_READ 0 1079#define MR_CPX_VERSION 1 1080 1081#define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200 // get IO metrics 1082 1083#define MR_EVT_CFG_CLEARED 0x0004 1084 1085#define MR_EVT_LD_STATE_CHANGE 0x0051 1086#define MR_EVT_PD_INSERTED 0x005b 1087#define MR_EVT_PD_REMOVED 0x0070 1088#define MR_EVT_LD_CREATED 0x008a 1089#define MR_EVT_LD_DELETED 0x008b 1090#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1091#define MR_EVT_LD_OFFLINE 0x00fc 1092#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1093#define MR_EVT_CTRL_PERF_COLLECTION 0x017e 1094 1095/* 1096 * MFI command completion codes 1097 */ 1098enum MFI_STAT { 1099 MFI_STAT_OK = 0x00, 1100 MFI_STAT_INVALID_CMD = 0x01, 1101 MFI_STAT_INVALID_DCMD = 0x02, 1102 MFI_STAT_INVALID_PARAMETER = 0x03, 1103 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 1104 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 1105 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 1106 MFI_STAT_APP_IN_USE = 0x07, 1107 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 1108 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 1109 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 1110 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 1111 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 1112 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 1113 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 1114 MFI_STAT_FLASH_BUSY = 0x0f, 1115 MFI_STAT_FLASH_ERROR = 0x10, 1116 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 1117 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 1118 MFI_STAT_FLASH_NOT_OPEN = 0x13, 1119 MFI_STAT_FLASH_NOT_STARTED = 0x14, 1120 MFI_STAT_FLUSH_FAILED = 0x15, 1121 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 1122 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 1123 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 1124 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 1125 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 1126 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 1127 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 1128 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 1129 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 1130 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 1131 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 1132 MFI_STAT_MFC_HW_ERROR = 0x21, 1133 MFI_STAT_NO_HW_PRESENT = 0x22, 1134 MFI_STAT_NOT_FOUND = 0x23, 1135 MFI_STAT_NOT_IN_ENCL = 0x24, 1136 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 1137 MFI_STAT_PD_TYPE_WRONG = 0x26, 1138 MFI_STAT_PR_DISABLED = 0x27, 1139 MFI_STAT_ROW_INDEX_INVALID = 0x28, 1140 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 1141 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 1142 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 1143 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 1144 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 1145 MFI_STAT_SCSI_IO_FAILED = 0x2e, 1146 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 1147 MFI_STAT_SHUTDOWN_FAILED = 0x30, 1148 MFI_STAT_TIME_NOT_SET = 0x31, 1149 MFI_STAT_WRONG_STATE = 0x32, 1150 MFI_STAT_LD_OFFLINE = 0x33, 1151 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 1152 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 1153 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 1154 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 1155 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 1156 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 1157 1158 MFI_STAT_INVALID_STATUS = 0xFF 1159}; 1160 1161/* 1162 * Number of mailbox bytes in DCMD message frame 1163 */ 1164#define MFI_MBOX_SIZE 12 1165 1166enum MR_EVT_CLASS { 1167 1168 MR_EVT_CLASS_DEBUG = -2, 1169 MR_EVT_CLASS_PROGRESS = -1, 1170 MR_EVT_CLASS_INFO = 0, 1171 MR_EVT_CLASS_WARNING = 1, 1172 MR_EVT_CLASS_CRITICAL = 2, 1173 MR_EVT_CLASS_FATAL = 3, 1174 MR_EVT_CLASS_DEAD = 4, 1175 1176}; 1177 1178enum MR_EVT_LOCALE { 1179 1180 MR_EVT_LOCALE_LD = 0x0001, 1181 MR_EVT_LOCALE_PD = 0x0002, 1182 MR_EVT_LOCALE_ENCL = 0x0004, 1183 MR_EVT_LOCALE_BBU = 0x0008, 1184 MR_EVT_LOCALE_SAS = 0x0010, 1185 MR_EVT_LOCALE_CTRL = 0x0020, 1186 MR_EVT_LOCALE_CONFIG = 0x0040, 1187 MR_EVT_LOCALE_CLUSTER = 0x0080, 1188 MR_EVT_LOCALE_ALL = 0xffff, 1189 1190}; 1191 1192enum MR_EVT_ARGS { 1193 1194 MR_EVT_ARGS_NONE, 1195 MR_EVT_ARGS_CDB_SENSE, 1196 MR_EVT_ARGS_LD, 1197 MR_EVT_ARGS_LD_COUNT, 1198 MR_EVT_ARGS_LD_LBA, 1199 MR_EVT_ARGS_LD_OWNER, 1200 MR_EVT_ARGS_LD_LBA_PD_LBA, 1201 MR_EVT_ARGS_LD_PROG, 1202 MR_EVT_ARGS_LD_STATE, 1203 MR_EVT_ARGS_LD_STRIP, 1204 MR_EVT_ARGS_PD, 1205 MR_EVT_ARGS_PD_ERR, 1206 MR_EVT_ARGS_PD_LBA, 1207 MR_EVT_ARGS_PD_LBA_LD, 1208 MR_EVT_ARGS_PD_PROG, 1209 MR_EVT_ARGS_PD_STATE, 1210 MR_EVT_ARGS_PCI, 1211 MR_EVT_ARGS_RATE, 1212 MR_EVT_ARGS_STR, 1213 MR_EVT_ARGS_TIME, 1214 MR_EVT_ARGS_ECC, 1215 MR_EVT_ARGS_LD_PROP, 1216 MR_EVT_ARGS_PD_SPARE, 1217 MR_EVT_ARGS_PD_INDEX, 1218 MR_EVT_ARGS_DIAG_PASS, 1219 MR_EVT_ARGS_DIAG_FAIL, 1220 MR_EVT_ARGS_PD_LBA_LBA, 1221 MR_EVT_ARGS_PORT_PHY, 1222 MR_EVT_ARGS_PD_MISSING, 1223 MR_EVT_ARGS_PD_ADDRESS, 1224 MR_EVT_ARGS_BITMAP, 1225 MR_EVT_ARGS_CONNECTOR, 1226 MR_EVT_ARGS_PD_PD, 1227 MR_EVT_ARGS_PD_FRU, 1228 MR_EVT_ARGS_PD_PATHINFO, 1229 MR_EVT_ARGS_PD_POWER_STATE, 1230 MR_EVT_ARGS_GENERIC, 1231}; 1232 1233 1234/* 1235 * Thunderbolt (and later) Defines 1236 */ 1237#define MRSAS_MAX_SZ_CHAIN_FRAME 1024 1238#define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 1239#define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 1240#define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 1241#define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 1242#define MRSAS_LOAD_BALANCE_FLAG 0x1 1243#define MRSAS_DCMD_MBOX_PEND_FLAG 0x1 1244#define HOST_DIAG_WRITE_ENABLE 0x80 1245#define HOST_DIAG_RESET_ADAPTER 0x4 1246#define MRSAS_TBOLT_MAX_RESET_TRIES 3 1247#define MRSAS_MAX_MFI_CMDS 32 1248 1249/* 1250 * Invader Defines 1251 */ 1252#define MPI2_TYPE_CUDA 0x2 1253#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 1254#define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 1255#define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 1256#define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 1257#define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 1258 1259/* 1260 * T10 PI defines 1261 */ 1262#define MR_PROT_INFO_TYPE_CONTROLLER 0x8 1263#define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 1264#define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9 1265#define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB 1266#define MRSAS_SCSI_ADDL_CDB_LEN 0x18 1267#define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20 1268#define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60 1269#define MRSAS_SCSIBLOCKSIZE 512 1270 1271/* 1272 * Raid context flags 1273 */ 1274#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 1275#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 1276typedef enum MR_RAID_FLAGS_IO_SUB_TYPE { 1277 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 1278 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 1279} MR_RAID_FLAGS_IO_SUB_TYPE; 1280 1281/* 1282 * Request descriptor types 1283 */ 1284#define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1285#define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1 1286#define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 1287#define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 1288#define MRSAS_FP_CMD_LEN 16 1289#define MRSAS_FUSION_IN_RESET 0 1290 1291#define RAID_CTX_SPANARM_ARM_SHIFT (0) 1292#define RAID_CTX_SPANARM_ARM_MASK (0x1f) 1293#define RAID_CTX_SPANARM_SPAN_SHIFT (5) 1294#define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 1295 1296/* 1297 * Define region lock types 1298 */ 1299typedef enum _REGION_TYPE { 1300 REGION_TYPE_UNUSED = 0, // lock is currently not active 1301 REGION_TYPE_SHARED_READ = 1, // shared lock (for reads) 1302 REGION_TYPE_SHARED_WRITE = 2, 1303 REGION_TYPE_EXCLUSIVE = 3, // exclusive lock (for writes) 1304} REGION_TYPE; 1305 1306 1307/* 1308 * SCSI-CAM Related Defines 1309 */ 1310#define MRSAS_SCSI_MAX_LUNS 0 //zero for now 1311#define MRSAS_SCSI_INITIATOR_ID 255 1312#define MRSAS_SCSI_MAX_CMDS 8 1313#define MRSAS_SCSI_MAX_CDB_LEN 16 1314#define MRSAS_SCSI_SENSE_BUFFERSIZE 96 1315#define MRSAS_MAX_SGL 70 1316#define MRSAS_MAX_IO_SIZE (256 * 1024) 1317#define MRSAS_INTERNAL_CMDS 32 1318 1319/* Request types */ 1320#define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0 1321#define MRSAS_REQ_TYPE_AEN_FETCH 0x1 1322#define MRSAS_REQ_TYPE_PASSTHRU 0x2 1323#define MRSAS_REQ_TYPE_GETSET_PARAM 0x3 1324#define MRSAS_REQ_TYPE_SCSI_IO 0x4 1325 1326/* Request states */ 1327#define MRSAS_REQ_STATE_FREE 0 1328#define MRSAS_REQ_STATE_BUSY 1 1329#define MRSAS_REQ_STATE_TRAN 2 1330#define MRSAS_REQ_STATE_COMPLETE 3 1331 1332enum mrsas_req_flags { 1333 MRSAS_DIR_UNKNOWN = 0x1, 1334 MRSAS_DIR_IN = 0x2, 1335 MRSAS_DIR_OUT = 0x4, 1336 MRSAS_DIR_NONE = 0x8, 1337}; 1338 1339/* 1340 * Adapter Reset States 1341 */ 1342enum { 1343 MRSAS_HBA_OPERATIONAL = 0, 1344 MRSAS_ADPRESET_SM_INFAULT = 1, 1345 MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 1346 MRSAS_ADPRESET_SM_OPERATIONAL = 3, 1347 MRSAS_HW_CRITICAL_ERROR = 4, 1348 MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1349}; 1350 1351/* 1352 * MPT Command Structure 1353 */ 1354struct mrsas_mpt_cmd { 1355 MRSAS_RAID_SCSI_IO_REQUEST *io_request; 1356 bus_addr_t io_request_phys_addr; 1357 MPI2_SGE_IO_UNION *chain_frame; 1358 bus_addr_t chain_frame_phys_addr; 1359 u_int32_t sge_count; 1360 u_int8_t *sense; 1361 bus_addr_t sense_phys_addr; 1362 u_int8_t retry_for_fw_reset; 1363 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc; 1364 u_int32_t sync_cmd_idx; //For getting MFI cmd from list when complete 1365 u_int32_t index; 1366 u_int8_t flags; 1367 u_int8_t load_balance; 1368 bus_size_t length; // request length 1369 u_int32_t error_code; // error during request dmamap load 1370 bus_dmamap_t data_dmamap; 1371 void *data; 1372 union ccb *ccb_ptr; // pointer to ccb 1373 struct callout cm_callout; 1374 struct mrsas_softc *sc; 1375 TAILQ_ENTRY(mrsas_mpt_cmd) next; 1376}; 1377 1378/* 1379 * MFI Command Structure 1380 */ 1381struct mrsas_mfi_cmd { 1382 union mrsas_frame *frame; 1383 bus_dmamap_t frame_dmamap; // mfi frame dmamap 1384 void *frame_mem; // mfi frame virtual addr 1385 bus_addr_t frame_phys_addr; // mfi frame physical addr 1386 u_int8_t *sense; 1387 bus_dmamap_t sense_dmamap; // mfi sense dmamap 1388 void *sense_mem; // mfi sense virtual addr 1389 bus_addr_t sense_phys_addr; 1390 u_int32_t index; 1391 u_int8_t sync_cmd; 1392 u_int8_t cmd_status; 1393 u_int8_t abort_aen; 1394 u_int8_t retry_for_fw_reset; 1395 struct mrsas_softc *sc; 1396 union ccb *ccb_ptr; 1397 union { 1398 struct { 1399 u_int16_t smid; 1400 u_int16_t resvd; 1401 } context; 1402 u_int32_t frame_count; 1403 } cmd_id; 1404 TAILQ_ENTRY(mrsas_mfi_cmd) next; 1405}; 1406 1407 1408/* 1409 * define constants for device list query options 1410 */ 1411enum MR_PD_QUERY_TYPE { 1412 MR_PD_QUERY_TYPE_ALL = 0, 1413 MR_PD_QUERY_TYPE_STATE = 1, 1414 MR_PD_QUERY_TYPE_POWER_STATE = 2, 1415 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 1416 MR_PD_QUERY_TYPE_SPEED = 4, 1417 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 1418}; 1419 1420#define MR_EVT_CFG_CLEARED 0x0004 1421#define MR_EVT_LD_STATE_CHANGE 0x0051 1422#define MR_EVT_PD_INSERTED 0x005b 1423#define MR_EVT_PD_REMOVED 0x0070 1424#define MR_EVT_LD_CREATED 0x008a 1425#define MR_EVT_LD_DELETED 0x008b 1426#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1427#define MR_EVT_LD_OFFLINE 0x00fc 1428#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1429 1430enum MR_PD_STATE { 1431 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1432 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 1433 MR_PD_STATE_HOT_SPARE = 0x02, 1434 MR_PD_STATE_OFFLINE = 0x10, 1435 MR_PD_STATE_FAILED = 0x11, 1436 MR_PD_STATE_REBUILD = 0x14, 1437 MR_PD_STATE_ONLINE = 0x18, 1438 MR_PD_STATE_COPYBACK = 0x20, 1439 MR_PD_STATE_SYSTEM = 0x40, 1440 }; 1441 1442 /* 1443 * defines the physical drive address structure 1444 */ 1445#pragma pack(1) 1446struct MR_PD_ADDRESS { 1447 u_int16_t deviceId; 1448 u_int16_t enclDeviceId; 1449 1450 union { 1451 struct { 1452 u_int8_t enclIndex; 1453 u_int8_t slotNumber; 1454 } mrPdAddress; 1455 struct { 1456 u_int8_t enclPosition; 1457 u_int8_t enclConnectorIndex; 1458 } mrEnclAddress; 1459 } u1; 1460 u_int8_t scsiDevType; 1461 union { 1462 u_int8_t connectedPortBitmap; 1463 u_int8_t connectedPortNumbers; 1464 } u2; 1465 u_int64_t sasAddr[2]; 1466}; 1467#pragma pack() 1468 1469/* 1470 * defines the physical drive list structure 1471 */ 1472#pragma pack(1) 1473struct MR_PD_LIST { 1474 u_int32_t size; 1475 u_int32_t count; 1476 struct MR_PD_ADDRESS addr[1]; 1477}; 1478#pragma pack() 1479 1480#pragma pack(1) 1481struct mrsas_pd_list { 1482 u_int16_t tid; 1483 u_int8_t driveType; 1484 u_int8_t driveState; 1485}; 1486#pragma pack() 1487 1488 /* 1489 * defines the logical drive reference structure 1490 */ 1491typedef union _MR_LD_REF { // LD reference structure 1492 struct { 1493 u_int8_t targetId; // LD target id (0 to MAX_TARGET_ID) 1494 u_int8_t reserved; // reserved to make in line with MR_PD_REF 1495 u_int16_t seqNum; // Sequence Number 1496 } ld_context; 1497 u_int32_t ref; // shorthand reference to full 32-bits 1498} MR_LD_REF; // 4 bytes 1499 1500 1501/* 1502 * defines the logical drive list structure 1503 */ 1504#pragma pack(1) 1505struct MR_LD_LIST { 1506 u_int32_t ldCount; // number of LDs 1507 u_int32_t reserved; // pad to 8-byte boundary 1508 struct { 1509 MR_LD_REF ref; // LD reference 1510 u_int8_t state; // current LD state (MR_LD_STATE) 1511 u_int8_t reserved[3]; // pad to 8-byte boundary 1512 u_int64_t size; // LD size 1513 } ldList[MAX_LOGICAL_DRIVES_EXT]; 1514}; 1515#pragma pack() 1516 1517/* 1518 * SAS controller properties 1519 */ 1520#pragma pack(1) 1521struct mrsas_ctrl_prop { 1522 u_int16_t seq_num; 1523 u_int16_t pred_fail_poll_interval; 1524 u_int16_t intr_throttle_count; 1525 u_int16_t intr_throttle_timeouts; 1526 u_int8_t rebuild_rate; 1527 u_int8_t patrol_read_rate; 1528 u_int8_t bgi_rate; 1529 u_int8_t cc_rate; 1530 u_int8_t recon_rate; 1531 u_int8_t cache_flush_interval; 1532 u_int8_t spinup_drv_count; 1533 u_int8_t spinup_delay; 1534 u_int8_t cluster_enable; 1535 u_int8_t coercion_mode; 1536 u_int8_t alarm_enable; 1537 u_int8_t disable_auto_rebuild; 1538 u_int8_t disable_battery_warn; 1539 u_int8_t ecc_bucket_size; 1540 u_int16_t ecc_bucket_leak_rate; 1541 u_int8_t restore_hotspare_on_insertion; 1542 u_int8_t expose_encl_devices; 1543 u_int8_t maintainPdFailHistory; 1544 u_int8_t disallowHostRequestReordering; 1545 u_int8_t abortCCOnError; // set TRUE to abort CC on detecting an inconsistency 1546 u_int8_t loadBalanceMode; // load balance mode (MR_LOAD_BALANCE_MODE) 1547 u_int8_t disableAutoDetectBackplane; // 0 - use auto detect logic of backplanes 1548 // like SGPIO, i2c SEP using h/w mechansim 1549 // like GPIO pins. 1550 // 1 - disable auto detect SGPIO, 1551 // 2 - disable i2c SEP auto detect 1552 // 3 - disable both auto detect 1553 u_int8_t snapVDSpace; // % of source LD to be reserved for a VDs snapshot in 1554 // snapshot repository, for metadata and user data. 1555 // 1=5%, 2=10%, 3=15% and so on. 1556 /* 1557 * Add properties that can be controlled by a bit in the following structure. 1558 */ 1559 struct { 1560 u_int32_t copyBackDisabled : 1; // set TRUE to disable copyBack 1561 // (0=copback enabled) 1562 u_int32_t SMARTerEnabled : 1; 1563 u_int32_t prCorrectUnconfiguredAreas : 1; 1564 u_int32_t useFdeOnly : 1; 1565 u_int32_t disableNCQ : 1; 1566 u_int32_t SSDSMARTerEnabled : 1; 1567 u_int32_t SSDPatrolReadEnabled : 1; 1568 u_int32_t enableSpinDownUnconfigured : 1; 1569 u_int32_t autoEnhancedImport : 1; 1570 u_int32_t enableSecretKeyControl : 1; 1571 u_int32_t disableOnlineCtrlReset : 1; 1572 u_int32_t allowBootWithPinnedCache : 1; 1573 u_int32_t disableSpinDownHS : 1; 1574 u_int32_t enableJBOD : 1; 1575 u_int32_t disableCacheBypass : 1; // 1 = disable cache-bypass-performance-improvement feature 1576 u_int32_t useDiskActivityForLocate : 1; // 1 = drive activity LED is toggled for LOCATE 1577 u_int32_t enablePI : 1; // 0 = Disable SCSI PI for controller. Remove any active protection information 1578 u_int32_t preventPIImport : 1; // 1 = Prevent import of SCSI DIF protected logical disks 1579 u_int32_t useGlobalSparesForEmergency : 1; // 1 = Use global spares for Emergency (if spare is incompatible without Emergency) 1580 u_int32_t useUnconfGoodForEmergency : 1; // 1 = Use uncofgured good drives for Emergency 1581 u_int32_t useEmergencySparesforSMARTer: 1; // 1 = Use Emergency spares for SMARTer 1582 u_int32_t forceSGPIOForQuadOnly : 1; // 1 = Force SGPIO status per port only for four drives, affects HPC controllers 1583 u_int32_t enableConfigAutoBalance : 1; // 0 = Configuration auto balance disabled, 1 = Configuration auto balance enabled 1584 u_int32_t enableVirtualCache : 1; // 1 = Virtual caching is enabled on DFF and SFM. 1585 u_int32_t enableAutoLockRecovery : 1; // 1 = Auto Lock Recovery on DFF and SFM 1586 u_int32_t disableImmediateIO : 1; // 1 = Disable Legacy Immediate IO, 0 = Enable 1587 u_int32_t disableT10RebuildAssist : 1; // 1 = Disable T10 Rebuild Assist, use legacy rebuild method 1588 u_int32_t ignore64ldRestriction : 1; // 0 - limit LD to 64 even if more LD support exists, 1 - support more than 64 ld with new DDF format 1589 u_int32_t enableSwZone : 1; // 1 = enable Software Zone 1590 u_int32_t limitMaxRateSATA3G : 1; // 1 = negotiated link rates to direct attached SATA devices shall be limited to 3Gbps 1591 u_int32_t reserved :2; 1592 } OnOffProperties; 1593 u_int8_t autoSnapVDSpace; // % of source LD to be reserved for auto 1594 // snapshot in snapshot repository, for 1595 // metadata and user data. 1596 // 1=5%, 2=10%, 3=15% and so on. 1597 u_int8_t viewSpace; // snapshot writeable VIEWs capacity as a % 1598 // of source LD capacity. 0=READ only. 1599 // 1=5%, 2=10%, 3=15% and so on 1600 u_int16_t spinDownTime; // # of idle minutes before device is spun 1601 // down (0=use FW defaults). 1602 u_int8_t reserved[24]; 1603 1604}; 1605#pragma pack() 1606 1607 1608/* 1609 * SAS controller information 1610 */ 1611//#pragma pack(1) 1612struct mrsas_ctrl_info { 1613 /* 1614 * PCI device information 1615 */ 1616 struct { 1617 u_int16_t vendor_id; 1618 u_int16_t device_id; 1619 u_int16_t sub_vendor_id; 1620 u_int16_t sub_device_id; 1621 u_int8_t reserved[24]; 1622 } __packed pci; 1623 /* 1624 * Host interface information 1625 */ 1626 struct { 1627 u_int8_t PCIX:1; 1628 u_int8_t PCIE:1; 1629 u_int8_t iSCSI:1; 1630 u_int8_t SAS_3G:1; 1631 u_int8_t reserved_0:4; 1632 u_int8_t reserved_1[6]; 1633 u_int8_t port_count; 1634 u_int64_t port_addr[8]; 1635 } __packed host_interface; 1636 /* 1637 * Device (backend) interface information 1638 */ 1639 struct { 1640 u_int8_t SPI:1; 1641 u_int8_t SAS_3G:1; 1642 u_int8_t SATA_1_5G:1; 1643 u_int8_t SATA_3G:1; 1644 u_int8_t reserved_0:4; 1645 u_int8_t reserved_1[6]; 1646 u_int8_t port_count; 1647 u_int64_t port_addr[8]; 1648 } __packed device_interface; 1649 1650 /* 1651 * List of components residing in flash. All str are null terminated 1652 */ 1653 u_int32_t image_check_word; 1654 u_int32_t image_component_count; 1655 1656 struct { 1657 char name[8]; 1658 char version[32]; 1659 char build_date[16]; 1660 char built_time[16]; 1661 } __packed image_component[8]; 1662 /* 1663 * List of flash components that have been flashed on the card, but 1664 * are not in use, pending reset of the adapter. This list will be 1665 * empty if a flash operation has not occurred. All stings are null 1666 * terminated 1667 */ 1668 u_int32_t pending_image_component_count; 1669 1670 struct { 1671 char name[8]; 1672 char version[32]; 1673 char build_date[16]; 1674 char build_time[16]; 1675 } __packed pending_image_component[8]; 1676 1677 u_int8_t max_arms; 1678 u_int8_t max_spans; 1679 u_int8_t max_arrays; 1680 u_int8_t max_lds; 1681 char product_name[80]; 1682 char serial_no[32]; 1683 1684 /* 1685 * Other physical/controller/operation information. Indicates the 1686 * presence of the hardware 1687 */ 1688 struct { 1689 u_int32_t bbu:1; 1690 u_int32_t alarm:1; 1691 u_int32_t nvram:1; 1692 u_int32_t uart:1; 1693 u_int32_t reserved:28; 1694 } __packed hw_present; 1695 1696 u_int32_t current_fw_time; 1697 1698 /* 1699 * Maximum data transfer sizes 1700 */ 1701 u_int16_t max_concurrent_cmds; 1702 u_int16_t max_sge_count; 1703 u_int32_t max_request_size; 1704 1705 /* 1706 * Logical and physical device counts 1707 */ 1708 u_int16_t ld_present_count; 1709 u_int16_t ld_degraded_count; 1710 u_int16_t ld_offline_count; 1711 1712 u_int16_t pd_present_count; 1713 u_int16_t pd_disk_present_count; 1714 u_int16_t pd_disk_pred_failure_count; 1715 u_int16_t pd_disk_failed_count; 1716 1717 /* 1718 * Memory size information 1719 */ 1720 u_int16_t nvram_size; 1721 u_int16_t memory_size; 1722 u_int16_t flash_size; 1723 1724 /* 1725 * Error counters 1726 */ 1727 u_int16_t mem_correctable_error_count; 1728 u_int16_t mem_uncorrectable_error_count; 1729 1730 /* 1731 * Cluster information 1732 */ 1733 u_int8_t cluster_permitted; 1734 u_int8_t cluster_active; 1735 1736 /* 1737 * Additional max data transfer sizes 1738 */ 1739 u_int16_t max_strips_per_io; 1740 1741 /* 1742 * Controller capabilities structures 1743 */ 1744 struct { 1745 u_int32_t raid_level_0:1; 1746 u_int32_t raid_level_1:1; 1747 u_int32_t raid_level_5:1; 1748 u_int32_t raid_level_1E:1; 1749 u_int32_t raid_level_6:1; 1750 u_int32_t reserved:27; 1751 } __packed raid_levels; 1752 1753 struct { 1754 u_int32_t rbld_rate:1; 1755 u_int32_t cc_rate:1; 1756 u_int32_t bgi_rate:1; 1757 u_int32_t recon_rate:1; 1758 u_int32_t patrol_rate:1; 1759 u_int32_t alarm_control:1; 1760 u_int32_t cluster_supported:1; 1761 u_int32_t bbu:1; 1762 u_int32_t spanning_allowed:1; 1763 u_int32_t dedicated_hotspares:1; 1764 u_int32_t revertible_hotspares:1; 1765 u_int32_t foreign_config_import:1; 1766 u_int32_t self_diagnostic:1; 1767 u_int32_t mixed_redundancy_arr:1; 1768 u_int32_t global_hot_spares:1; 1769 u_int32_t reserved:17; 1770 } __packed adapter_operations; 1771 1772 struct { 1773 u_int32_t read_policy:1; 1774 u_int32_t write_policy:1; 1775 u_int32_t io_policy:1; 1776 u_int32_t access_policy:1; 1777 u_int32_t disk_cache_policy:1; 1778 u_int32_t reserved:27; 1779 } __packed ld_operations; 1780 1781 struct { 1782 u_int8_t min; 1783 u_int8_t max; 1784 u_int8_t reserved[2]; 1785 } __packed stripe_sz_ops; 1786 1787 struct { 1788 u_int32_t force_online:1; 1789 u_int32_t force_offline:1; 1790 u_int32_t force_rebuild:1; 1791 u_int32_t reserved:29; 1792 } __packed pd_operations; 1793 1794 struct { 1795 u_int32_t ctrl_supports_sas:1; 1796 u_int32_t ctrl_supports_sata:1; 1797 u_int32_t allow_mix_in_encl:1; 1798 u_int32_t allow_mix_in_ld:1; 1799 u_int32_t allow_sata_in_cluster:1; 1800 u_int32_t reserved:27; 1801 } __packed pd_mix_support; 1802 1803 /* 1804 * Define ECC single-bit-error bucket information 1805 */ 1806 u_int8_t ecc_bucket_count; 1807 u_int8_t reserved_2[11]; 1808 1809 /* 1810 * Include the controller properties (changeable items) 1811 */ 1812 struct mrsas_ctrl_prop properties; 1813 1814 /* 1815 * Define FW pkg version (set in envt v'bles on OEM basis) 1816 */ 1817 char package_version[0x60]; 1818 1819 /* 1820 * If adapterOperations.supportMoreThan8Phys is set, and deviceInterface.portCount is greater than 8, 1821 * SAS Addrs for first 8 ports shall be populated in deviceInterface.portAddr, and the rest shall be 1822 * populated in deviceInterfacePortAddr2. 1823 */ 1824 u_int64_t deviceInterfacePortAddr2[8]; //0x6a0 1825 u_int8_t reserved3[128]; //0x6e0 1826 1827 struct { //0x760 1828 u_int16_t minPdRaidLevel_0 : 4; 1829 u_int16_t maxPdRaidLevel_0 : 12; 1830 1831 u_int16_t minPdRaidLevel_1 : 4; 1832 u_int16_t maxPdRaidLevel_1 : 12; 1833 1834 u_int16_t minPdRaidLevel_5 : 4; 1835 u_int16_t maxPdRaidLevel_5 : 12; 1836 1837 u_int16_t minPdRaidLevel_1E : 4; 1838 u_int16_t maxPdRaidLevel_1E : 12; 1839 1840 u_int16_t minPdRaidLevel_6 : 4; 1841 u_int16_t maxPdRaidLevel_6 : 12; 1842 1843 u_int16_t minPdRaidLevel_10 : 4; 1844 u_int16_t maxPdRaidLevel_10 : 12; 1845 1846 u_int16_t minPdRaidLevel_50 : 4; 1847 u_int16_t maxPdRaidLevel_50 : 12; 1848 1849 u_int16_t minPdRaidLevel_60 : 4; 1850 u_int16_t maxPdRaidLevel_60 : 12; 1851 1852 u_int16_t minPdRaidLevel_1E_RLQ0 : 4; 1853 u_int16_t maxPdRaidLevel_1E_RLQ0 : 12; 1854 1855 u_int16_t minPdRaidLevel_1E0_RLQ0 : 4; 1856 u_int16_t maxPdRaidLevel_1E0_RLQ0 : 12; 1857 1858 u_int16_t reserved[6]; 1859 } pdsForRaidLevels; 1860 1861 u_int16_t maxPds; //0x780 1862 u_int16_t maxDedHSPs; //0x782 1863 u_int16_t maxGlobalHSPs; //0x784 1864 u_int16_t ddfSize; //0x786 1865 u_int8_t maxLdsPerArray; //0x788 1866 u_int8_t partitionsInDDF; //0x789 1867 u_int8_t lockKeyBinding; //0x78a 1868 u_int8_t maxPITsPerLd; //0x78b 1869 u_int8_t maxViewsPerLd; //0x78c 1870 u_int8_t maxTargetId; //0x78d 1871 u_int16_t maxBvlVdSize; //0x78e 1872 1873 u_int16_t maxConfigurableSSCSize; //0x790 1874 u_int16_t currentSSCsize; //0x792 1875 1876 char expanderFwVersion[12]; //0x794 1877 1878 u_int16_t PFKTrialTimeRemaining; //0x7A0 1879 1880 u_int16_t cacheMemorySize; //0x7A2 1881 1882 struct { //0x7A4 1883 u_int32_t supportPIcontroller :1; 1884 u_int32_t supportLdPIType1 :1; 1885 u_int32_t supportLdPIType2 :1; 1886 u_int32_t supportLdPIType3 :1; 1887 u_int32_t supportLdBBMInfo :1; 1888 u_int32_t supportShieldState :1; 1889 u_int32_t blockSSDWriteCacheChange :1; 1890 u_int32_t supportSuspendResumeBGops :1; 1891 u_int32_t supportEmergencySpares :1; 1892 u_int32_t supportSetLinkSpeed :1; 1893 u_int32_t supportBootTimePFKChange :1; 1894 u_int32_t supportJBOD :1; 1895 u_int32_t disableOnlinePFKChange :1; 1896 u_int32_t supportPerfTuning :1; 1897 u_int32_t supportSSDPatrolRead :1; 1898 u_int32_t realTimeScheduler :1; 1899 1900 u_int32_t supportResetNow :1; 1901 u_int32_t supportEmulatedDrives :1; 1902 u_int32_t headlessMode :1; 1903 u_int32_t dedicatedHotSparesLimited :1; 1904 1905 1906 u_int32_t supportUnevenSpans :1; 1907 u_int32_t reserved :11; 1908 } adapterOperations2; 1909 1910 u_int8_t driverVersion[32]; //0x7A8 1911 u_int8_t maxDAPdCountSpinup60; //0x7C8 1912 u_int8_t temperatureROC; //0x7C9 1913 u_int8_t temperatureCtrl; //0x7CA 1914 u_int8_t reserved4; //0x7CB 1915 u_int16_t maxConfigurablePds; //0x7CC 1916 1917 1918 u_int8_t reserved5[2]; //0x7CD reserved for future use 1919 1920 /* 1921 * HA cluster information 1922 */ 1923 struct { 1924 u_int32_t peerIsPresent :1; 1925 u_int32_t peerIsIncompatible :1; 1926 1927 u_int32_t hwIncompatible :1; 1928 u_int32_t fwVersionMismatch :1; 1929 u_int32_t ctrlPropIncompatible :1; 1930 u_int32_t premiumFeatureMismatch :1; 1931 u_int32_t reserved :26; 1932 } cluster; 1933 1934 char clusterId[16]; //0x7D4 1935 1936 char reserved6[4]; //0x7E4 RESERVED FOR IOV 1937 1938 struct{ //0x7E8 1939 u_int32_t resrved :5; 1940 u_int32_t supportMaxExtLDs :1; 1941 u_int32_t reserved1 :26; 1942 }adapterOperations3; 1943 1944 u_int8_t pad[0x800-0x7EC]; //0x7EC 1945} __packed; 1946 1947/* 1948 * When SCSI mid-layer calls driver's reset routine, driver waits for 1949 * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 1950 * that the driver cannot _actually_ abort or reset pending commands. While 1951 * it is waiting for the commands to complete, it prints a diagnostic message 1952 * every MRSAS_RESET_NOTICE_INTERVAL seconds 1953 */ 1954#define MRSAS_RESET_WAIT_TIME 180 1955#define MRSAS_INTERNAL_CMD_WAIT_TIME 180 1956#define MRSAS_IOC_INIT_WAIT_TIME 60 1957#define MRSAS_RESET_NOTICE_INTERVAL 5 1958#define MRSAS_IOCTL_CMD 0 1959#define MRSAS_DEFAULT_CMD_TIMEOUT 90 1960#define MRSAS_THROTTLE_QUEUE_DEPTH 16 1961 1962/* 1963 * FW reports the maximum of number of commands that it can accept (maximum 1964 * commands that can be outstanding) at any time. The driver must report a 1965 * lower number to the mid layer because it can issue a few internal commands 1966 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 1967 * is shown below 1968 */ 1969#define MRSAS_INT_CMDS 32 1970#define MRSAS_SKINNY_INT_CMDS 5 1971#define MRSAS_MAX_MSIX_QUEUES 16 1972 1973/* 1974 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 1975 * SGLs based on the size of bus_addr_t 1976 */ 1977#define IS_DMA64 (sizeof(bus_addr_t) == 8) 1978 1979#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 // MFI state change interrupt 1980#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 1981#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 1982#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 //MFI state change interrupt 1983 1984#define MFI_OB_INTR_STATUS_MASK 0x00000002 1985#define MFI_POLL_TIMEOUT_SECS 60 1986 1987#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 1988#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 1989#define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001 1990#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 1991#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 1992#define MFI_1068_PCSR_OFFSET 0x84 1993#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 1994#define MFI_1068_FW_READY 0xDDDD0000 1995 1996#pragma pack(1) 1997struct mrsas_sge32 { 1998 u_int32_t phys_addr; 1999 u_int32_t length; 2000}; 2001#pragma pack() 2002 2003#pragma pack(1) 2004struct mrsas_sge64 { 2005 u_int64_t phys_addr; 2006 u_int32_t length; 2007}; 2008#pragma pack() 2009 2010#pragma pack() 2011union mrsas_sgl { 2012 struct mrsas_sge32 sge32[1]; 2013 struct mrsas_sge64 sge64[1]; 2014}; 2015#pragma pack() 2016 2017#pragma pack(1) 2018struct mrsas_header { 2019 u_int8_t cmd; /*00e */ 2020 u_int8_t sense_len; /*01h */ 2021 u_int8_t cmd_status; /*02h */ 2022 u_int8_t scsi_status; /*03h */ 2023 2024 u_int8_t target_id; /*04h */ 2025 u_int8_t lun; /*05h */ 2026 u_int8_t cdb_len; /*06h */ 2027 u_int8_t sge_count; /*07h */ 2028 2029 u_int32_t context; /*08h */ 2030 u_int32_t pad_0; /*0Ch */ 2031 2032 u_int16_t flags; /*10h */ 2033 u_int16_t timeout; /*12h */ 2034 u_int32_t data_xferlen; /*14h */ 2035}; 2036#pragma pack() 2037 2038 2039typedef union _MFI_CAPABILITIES { 2040 struct { 2041 u_int32_t support_fp_remote_lun:1; 2042 u_int32_t support_additional_msix:1; 2043 u_int32_t support_fastpath_wb:1; 2044 u_int32_t support_max_255lds:1; 2045 u_int32_t reserved:28; 2046 } mfi_capabilities; 2047 u_int32_t reg; 2048} MFI_CAPABILITIES; 2049 2050#pragma pack(1) 2051struct mrsas_init_frame { 2052 u_int8_t cmd; /*00h */ 2053 u_int8_t reserved_0; /*01h */ 2054 u_int8_t cmd_status; /*02h */ 2055 2056 u_int8_t reserved_1; /*03h */ 2057 MFI_CAPABILITIES driver_operations; /*04h*/ 2058 u_int32_t context; /*08h */ 2059 u_int32_t pad_0; /*0Ch */ 2060 2061 u_int16_t flags; /*10h */ 2062 u_int16_t reserved_3; /*12h */ 2063 u_int32_t data_xfer_len; /*14h */ 2064 2065 u_int32_t queue_info_new_phys_addr_lo; /*18h */ 2066 u_int32_t queue_info_new_phys_addr_hi; /*1Ch */ 2067 u_int32_t queue_info_old_phys_addr_lo; /*20h */ 2068 u_int32_t queue_info_old_phys_addr_hi; /*24h */ 2069 u_int32_t driver_ver_lo; /*28h */ 2070 u_int32_t driver_ver_hi; /*2Ch */ 2071 u_int32_t reserved_4[4]; /*30h */ 2072}; 2073#pragma pack() 2074 2075#pragma pack(1) 2076struct mrsas_io_frame { 2077 u_int8_t cmd; /*00h */ 2078 u_int8_t sense_len; /*01h */ 2079 u_int8_t cmd_status; /*02h */ 2080 u_int8_t scsi_status; /*03h */ 2081 2082 u_int8_t target_id; /*04h */ 2083 u_int8_t access_byte; /*05h */ 2084 u_int8_t reserved_0; /*06h */ 2085 u_int8_t sge_count; /*07h */ 2086 2087 u_int32_t context; /*08h */ 2088 u_int32_t pad_0; /*0Ch */ 2089 2090 u_int16_t flags; /*10h */ 2091 u_int16_t timeout; /*12h */ 2092 u_int32_t lba_count; /*14h */ 2093 2094 u_int32_t sense_buf_phys_addr_lo; /*18h */ 2095 u_int32_t sense_buf_phys_addr_hi; /*1Ch */ 2096 2097 u_int32_t start_lba_lo; /*20h */ 2098 u_int32_t start_lba_hi; /*24h */ 2099 2100 union mrsas_sgl sgl; /*28h */ 2101}; 2102#pragma pack() 2103 2104#pragma pack(1) 2105struct mrsas_pthru_frame { 2106 u_int8_t cmd; /*00h */ 2107 u_int8_t sense_len; /*01h */ 2108 u_int8_t cmd_status; /*02h */ 2109 u_int8_t scsi_status; /*03h */ 2110 2111 u_int8_t target_id; /*04h */ 2112 u_int8_t lun; /*05h */ 2113 u_int8_t cdb_len; /*06h */ 2114 u_int8_t sge_count; /*07h */ 2115 2116 u_int32_t context; /*08h */ 2117 u_int32_t pad_0; /*0Ch */ 2118 2119 u_int16_t flags; /*10h */ 2120 u_int16_t timeout; /*12h */ 2121 u_int32_t data_xfer_len; /*14h */ 2122 2123 u_int32_t sense_buf_phys_addr_lo; /*18h */ 2124 u_int32_t sense_buf_phys_addr_hi; /*1Ch */ 2125 2126 u_int8_t cdb[16]; /*20h */ 2127 union mrsas_sgl sgl; /*30h */ 2128}; 2129#pragma pack() 2130 2131#pragma pack(1) 2132struct mrsas_dcmd_frame { 2133 u_int8_t cmd; /*00h */ 2134 u_int8_t reserved_0; /*01h */ 2135 u_int8_t cmd_status; /*02h */ 2136 u_int8_t reserved_1[4]; /*03h */ 2137 u_int8_t sge_count; /*07h */ 2138 2139 u_int32_t context; /*08h */ 2140 u_int32_t pad_0; /*0Ch */ 2141 2142 u_int16_t flags; /*10h */ 2143 u_int16_t timeout; /*12h */ 2144 2145 u_int32_t data_xfer_len; /*14h */ 2146 u_int32_t opcode; /*18h */ 2147 2148 union { /*1Ch */ 2149 u_int8_t b[12]; 2150 u_int16_t s[6]; 2151 u_int32_t w[3]; 2152 } mbox; 2153 2154 union mrsas_sgl sgl; /*28h */ 2155}; 2156#pragma pack() 2157 2158#pragma pack(1) 2159struct mrsas_abort_frame { 2160 u_int8_t cmd; /*00h */ 2161 u_int8_t reserved_0; /*01h */ 2162 u_int8_t cmd_status; /*02h */ 2163 2164 u_int8_t reserved_1; /*03h */ 2165 u_int32_t reserved_2; /*04h */ 2166 2167 u_int32_t context; /*08h */ 2168 u_int32_t pad_0; /*0Ch */ 2169 2170 u_int16_t flags; /*10h */ 2171 u_int16_t reserved_3; /*12h */ 2172 u_int32_t reserved_4; /*14h */ 2173 2174 u_int32_t abort_context; /*18h */ 2175 u_int32_t pad_1; /*1Ch */ 2176 2177 u_int32_t abort_mfi_phys_addr_lo; /*20h */ 2178 u_int32_t abort_mfi_phys_addr_hi; /*24h */ 2179 2180 u_int32_t reserved_5[6]; /*28h */ 2181}; 2182#pragma pack() 2183 2184#pragma pack(1) 2185struct mrsas_smp_frame { 2186 u_int8_t cmd; /*00h */ 2187 u_int8_t reserved_1; /*01h */ 2188 u_int8_t cmd_status; /*02h */ 2189 u_int8_t connection_status; /*03h */ 2190 2191 u_int8_t reserved_2[3]; /*04h */ 2192 u_int8_t sge_count; /*07h */ 2193 2194 u_int32_t context; /*08h */ 2195 u_int32_t pad_0; /*0Ch */ 2196 2197 u_int16_t flags; /*10h */ 2198 u_int16_t timeout; /*12h */ 2199 2200 u_int32_t data_xfer_len; /*14h */ 2201 u_int64_t sas_addr; /*18h */ 2202 2203 union { 2204 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */ 2205 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */ 2206 } sgl; 2207}; 2208#pragma pack() 2209 2210 2211#pragma pack(1) 2212struct mrsas_stp_frame { 2213 u_int8_t cmd; /*00h */ 2214 u_int8_t reserved_1; /*01h */ 2215 u_int8_t cmd_status; /*02h */ 2216 u_int8_t reserved_2; /*03h */ 2217 2218 u_int8_t target_id; /*04h */ 2219 u_int8_t reserved_3[2]; /*05h */ 2220 u_int8_t sge_count; /*07h */ 2221 2222 u_int32_t context; /*08h */ 2223 u_int32_t pad_0; /*0Ch */ 2224 2225 u_int16_t flags; /*10h */ 2226 u_int16_t timeout; /*12h */ 2227 2228 u_int32_t data_xfer_len; /*14h */ 2229 2230 u_int16_t fis[10]; /*18h */ 2231 u_int32_t stp_flags; 2232 2233 union { 2234 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */ 2235 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */ 2236 } sgl; 2237}; 2238#pragma pack() 2239 2240union mrsas_frame { 2241 struct mrsas_header hdr; 2242 struct mrsas_init_frame init; 2243 struct mrsas_io_frame io; 2244 struct mrsas_pthru_frame pthru; 2245 struct mrsas_dcmd_frame dcmd; 2246 struct mrsas_abort_frame abort; 2247 struct mrsas_smp_frame smp; 2248 struct mrsas_stp_frame stp; 2249 u_int8_t raw_bytes[64]; 2250}; 2251 2252#pragma pack(1) 2253union mrsas_evt_class_locale { 2254 2255 struct { 2256 u_int16_t locale; 2257 u_int8_t reserved; 2258 int8_t class; 2259 } __packed members; 2260 2261 u_int32_t word; 2262 2263} __packed; 2264 2265#pragma pack() 2266 2267 2268#pragma pack(1) 2269struct mrsas_evt_log_info { 2270 u_int32_t newest_seq_num; 2271 u_int32_t oldest_seq_num; 2272 u_int32_t clear_seq_num; 2273 u_int32_t shutdown_seq_num; 2274 u_int32_t boot_seq_num; 2275 2276} __packed; 2277 2278#pragma pack() 2279 2280struct mrsas_progress { 2281 2282 u_int16_t progress; 2283 u_int16_t elapsed_seconds; 2284 2285} __packed; 2286 2287struct mrsas_evtarg_ld { 2288 2289 u_int16_t target_id; 2290 u_int8_t ld_index; 2291 u_int8_t reserved; 2292 2293} __packed; 2294 2295struct mrsas_evtarg_pd { 2296 u_int16_t device_id; 2297 u_int8_t encl_index; 2298 u_int8_t slot_number; 2299 2300} __packed; 2301 2302struct mrsas_evt_detail { 2303 2304 u_int32_t seq_num; 2305 u_int32_t time_stamp; 2306 u_int32_t code; 2307 union mrsas_evt_class_locale cl; 2308 u_int8_t arg_type; 2309 u_int8_t reserved1[15]; 2310 2311 union { 2312 struct { 2313 struct mrsas_evtarg_pd pd; 2314 u_int8_t cdb_length; 2315 u_int8_t sense_length; 2316 u_int8_t reserved[2]; 2317 u_int8_t cdb[16]; 2318 u_int8_t sense[64]; 2319 } __packed cdbSense; 2320 2321 struct mrsas_evtarg_ld ld; 2322 2323 struct { 2324 struct mrsas_evtarg_ld ld; 2325 u_int64_t count; 2326 } __packed ld_count; 2327 2328 struct { 2329 u_int64_t lba; 2330 struct mrsas_evtarg_ld ld; 2331 } __packed ld_lba; 2332 2333 struct { 2334 struct mrsas_evtarg_ld ld; 2335 u_int32_t prevOwner; 2336 u_int32_t newOwner; 2337 } __packed ld_owner; 2338 2339 struct { 2340 u_int64_t ld_lba; 2341 u_int64_t pd_lba; 2342 struct mrsas_evtarg_ld ld; 2343 struct mrsas_evtarg_pd pd; 2344 } __packed ld_lba_pd_lba; 2345 2346 struct { 2347 struct mrsas_evtarg_ld ld; 2348 struct mrsas_progress prog; 2349 } __packed ld_prog; 2350 2351 struct { 2352 struct mrsas_evtarg_ld ld; 2353 u_int32_t prev_state; 2354 u_int32_t new_state; 2355 } __packed ld_state; 2356 2357 struct { 2358 u_int64_t strip; 2359 struct mrsas_evtarg_ld ld; 2360 } __packed ld_strip; 2361 2362 struct mrsas_evtarg_pd pd; 2363 2364 struct { 2365 struct mrsas_evtarg_pd pd; 2366 u_int32_t err; 2367 } __packed pd_err; 2368 2369 struct { 2370 u_int64_t lba; 2371 struct mrsas_evtarg_pd pd; 2372 } __packed pd_lba; 2373 2374 struct { 2375 u_int64_t lba; 2376 struct mrsas_evtarg_pd pd; 2377 struct mrsas_evtarg_ld ld; 2378 } __packed pd_lba_ld; 2379 2380 struct { 2381 struct mrsas_evtarg_pd pd; 2382 struct mrsas_progress prog; 2383 } __packed pd_prog; 2384 2385 struct { 2386 struct mrsas_evtarg_pd pd; 2387 u_int32_t prevState; 2388 u_int32_t newState; 2389 } __packed pd_state; 2390 2391 struct { 2392 u_int16_t vendorId; 2393 u_int16_t deviceId; 2394 u_int16_t subVendorId; 2395 u_int16_t subDeviceId; 2396 } __packed pci; 2397 2398 u_int32_t rate; 2399 char str[96]; 2400 2401 struct { 2402 u_int32_t rtc; 2403 u_int32_t elapsedSeconds; 2404 } __packed time; 2405 2406 struct { 2407 u_int32_t ecar; 2408 u_int32_t elog; 2409 char str[64]; 2410 } __packed ecc; 2411 2412 u_int8_t b[96]; 2413 u_int16_t s[48]; 2414 u_int32_t w[24]; 2415 u_int64_t d[12]; 2416 } args; 2417 2418 char description[128]; 2419 2420} __packed; 2421
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