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mpi2_ioc.h (283661) mpi2_ioc.h (299263)
1/*-
2 * Copyright (c) 2012-2015 LSI Corp.
1/*-
2 * Copyright (c) 2012-2015 LSI Corp.
3 * Copyright (c) 2013-2015 Avago Technologies
3 * Copyright (c) 2013-2016 Avago Technologies
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright

--- 12 unchanged lines hidden (view full) ---

24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD
31 *
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright

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24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD
31 *
32 * $FreeBSD: head/sys/dev/mpr/mpi/mpi2_ioc.h 283661 2015-05-28 18:24:22Z slm $
32 * $FreeBSD: head/sys/dev/mpr/mpi/mpi2_ioc.h 299263 2016-05-09 16:12:32Z slm $
33 */
34
35/*
36 * Copyright (c) 2000-2015 LSI Corporation.
33 */
34
35/*
36 * Copyright (c) 2000-2015 LSI Corporation.
37 * Copyright (c) 2013-2015 Avago Technologies
37 * Copyright (c) 2013-2016 Avago Technologies
38 * All rights reserved.
38 *
39 *
40 * Name: mpi2_ioc.h
41 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
42 * Creation Date: October 11, 2006
43 *
39 *
40 *
41 * Name: mpi2_ioc.h
42 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
43 * Creation Date: October 11, 2006
44 *
44 * mpi2_ioc.h Version: 02.00.24
45 * mpi2_ioc.h Version: 02.00.27
45 *
46 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
47 * prefix are for use only on MPI v2.5 products, and must not be used
48 * with MPI v2.0 products. Unless otherwise noted, names beginning with
49 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
50 *
51 * Version History
52 * ---------------

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163 * Added ElapsedSeconds field to
164 * MPI2_EVENT_DATA_IR_OPERATION_STATUS.
165 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
166 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
167 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
168 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
169 * Added Encrypted Hash Extended Image.
170 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS.
46 *
47 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
48 * prefix are for use only on MPI v2.5 products, and must not be used
49 * with MPI v2.0 products. Unless otherwise noted, names beginning with
50 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
51 *
52 * Version History
53 * ---------------

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164 * Added ElapsedSeconds field to
165 * MPI2_EVENT_DATA_IR_OPERATION_STATUS.
166 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
167 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
168 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
169 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
170 * Added Encrypted Hash Extended Image.
171 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS.
172 * 11-18-14 02.00.25 Updated copyright information.
173 * 03-16-15 02.00.26 Updated for MPI v2.6.
174 * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and
175 * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT.
176 * Added MPI2_EVENT_PCIE_LINK_COUNTER and
177 * MPI26_EVENT_DATA_PCIE_LINK_COUNTER.
178 * Added MPI26_CTRL_OP_SHUTDOWN.
179 * Added MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG
180 * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS
181 * 08-25-15 02.00.27 Added IC ARCH Class based signature defines
182 *
171 * --------------------------------------------------------------------------
172 */
173
174#ifndef MPI2_IOC_H
175#define MPI2_IOC_H
176
177/*****************************************************************************
178*

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195 U8 Reserved3; /* 0x06 */
196 U8 MsgFlags; /* 0x07 */
197 U8 VP_ID; /* 0x08 */
198 U8 VF_ID; /* 0x09 */
199 U16 Reserved4; /* 0x0A */
200 U16 MsgVersion; /* 0x0C */
201 U16 HeaderVersion; /* 0x0E */
202 U32 Reserved5; /* 0x10 */
183 * --------------------------------------------------------------------------
184 */
185
186#ifndef MPI2_IOC_H
187#define MPI2_IOC_H
188
189/*****************************************************************************
190*

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207 U8 Reserved3; /* 0x06 */
208 U8 MsgFlags; /* 0x07 */
209 U8 VP_ID; /* 0x08 */
210 U8 VF_ID; /* 0x09 */
211 U16 Reserved4; /* 0x0A */
212 U16 MsgVersion; /* 0x0C */
213 U16 HeaderVersion; /* 0x0E */
214 U32 Reserved5; /* 0x10 */
203 U16 Reserved6; /* 0x14 */
204 U8 Reserved7; /* 0x16 */
215 U16 ConfigurationFlags; /* 0x14 */
216 U8 HostPageSize; /* 0x16 */
205 U8 HostMSIxVectors; /* 0x17 */
206 U16 Reserved8; /* 0x18 */
207 U16 SystemRequestFrameSize; /* 0x1A */
208 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
209 U16 ReplyFreeQueueDepth; /* 0x1E */
210 U32 SenseBufferAddressHigh; /* 0x20 */
211 U32 SystemReplyAddressHigh; /* 0x24 */
212 U64 SystemRequestFrameBaseAddress; /* 0x28 */

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324 U16 ProtocolFlags; /* 0x30 */
325 U16 HighPriorityCredit; /* 0x32 */
326 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
327 U8 ReplyFrameSize; /* 0x36 */
328 U8 MaxVolumes; /* 0x37 */
329 U16 MaxDevHandle; /* 0x38 */
330 U16 MaxPersistentEntries; /* 0x3A */
331 U16 MinDevHandle; /* 0x3C */
217 U8 HostMSIxVectors; /* 0x17 */
218 U16 Reserved8; /* 0x18 */
219 U16 SystemRequestFrameSize; /* 0x1A */
220 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
221 U16 ReplyFreeQueueDepth; /* 0x1E */
222 U32 SenseBufferAddressHigh; /* 0x20 */
223 U32 SystemReplyAddressHigh; /* 0x24 */
224 U64 SystemRequestFrameBaseAddress; /* 0x28 */

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336 U16 ProtocolFlags; /* 0x30 */
337 U16 HighPriorityCredit; /* 0x32 */
338 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
339 U8 ReplyFrameSize; /* 0x36 */
340 U8 MaxVolumes; /* 0x37 */
341 U16 MaxDevHandle; /* 0x38 */
342 U16 MaxPersistentEntries; /* 0x3A */
343 U16 MinDevHandle; /* 0x3C */
332 U16 Reserved4; /* 0x3E */
344 U8 CurrentHostPageSize; /* 0x3E */
345 U8 Reserved4; /* 0x3F */
346 U8 SGEModifierMask; /* 0x40 */
347 U8 SGEModifierValue; /* 0x41 */
348 U8 SGEModifierShift; /* 0x42 */
349 U8 Reserved5; /* 0x43 */
333} MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
334 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
335
336/* MsgVersion */
337#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
338#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
339#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
340#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)

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378#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
379#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
380#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
381#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
382#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
383#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
384
385/* ProtocolFlags */
350} MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
351 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
352
353/* MsgVersion */
354#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
355#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
356#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
357#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)

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395#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
396#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
397#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
398#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
399#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
400#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
401
402/* ProtocolFlags */
386#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
387#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
403#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
404#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
388
389
390/****************************************************************************
391* PortFacts message
392****************************************************************************/
393
394/* PortFacts Request message */
395typedef struct _MPI2_PORT_FACTS_REQUEST

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554#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
555#define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
556#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
557#define MPI2_EVENT_SAS_QUIESCE (0x0025)
558#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)
559#define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
560#define MPI2_EVENT_HOST_MESSAGE (0x0028)
561#define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029)
405
406
407/****************************************************************************
408* PortFacts message
409****************************************************************************/
410
411/* PortFacts Request message */
412typedef struct _MPI2_PORT_FACTS_REQUEST

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571#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
572#define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
573#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
574#define MPI2_EVENT_SAS_QUIESCE (0x0025)
575#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)
576#define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
577#define MPI2_EVENT_HOST_MESSAGE (0x0028)
578#define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029)
579#define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034) /* MPI v2.6 and later */
562#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)
563#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)
564
565
566/* Log Entry Added Event data */
567
568/* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
569#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)

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625 U8 Reserved1; /* 0x01 */
626 U16 Reserved2; /* 0x02 */
627 U32 Reserved3; /* 0x04 */
628 U32 HostData[1]; /* 0x08 */
629} MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
630 Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t;
631
632
580#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)
581#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)
582
583
584/* Log Entry Added Event data */
585
586/* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
587#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)

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643 U8 Reserved1; /* 0x01 */
644 U16 Reserved2; /* 0x02 */
645 U32 Reserved3; /* 0x04 */
646 U32 HostData[1]; /* 0x08 */
647} MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
648 Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t;
649
650
633/* Power Performance Change Event */
651/* Power Performance Change Event data */
634
635typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE
636{
637 U8 CurrentPowerMode; /* 0x00 */
638 U8 PreviousPowerMode; /* 0x01 */
639 U16 Reserved1; /* 0x02 */
640} MPI2_EVENT_DATA_POWER_PERF_CHANGE,
641 MPI2_POINTER PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,

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651#define MPI2_EVENT_PM_MODE_MASK (0x07)
652#define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00)
653#define MPI2_EVENT_PM_MODE_UNKNOWN (0x01)
654#define MPI2_EVENT_PM_MODE_FULL_POWER (0x04)
655#define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05)
656#define MPI2_EVENT_PM_MODE_STANDBY (0x06)
657
658
652
653typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE
654{
655 U8 CurrentPowerMode; /* 0x00 */
656 U8 PreviousPowerMode; /* 0x01 */
657 U16 Reserved1; /* 0x02 */
658} MPI2_EVENT_DATA_POWER_PERF_CHANGE,
659 MPI2_POINTER PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,

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669#define MPI2_EVENT_PM_MODE_MASK (0x07)
670#define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00)
671#define MPI2_EVENT_PM_MODE_UNKNOWN (0x01)
672#define MPI2_EVENT_PM_MODE_FULL_POWER (0x04)
673#define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05)
674#define MPI2_EVENT_PM_MODE_STANDBY (0x06)
675
676
677/* Active Cable Exception Event data */
678
679typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT
680{
681 U32 ActiveCablePowerRequirement; /* 0x00 */
682 U8 ReasonCode; /* 0x04 */
683 U8 ReceptacleID; /* 0x05 */
684 U16 Reserved1; /* 0x06 */
685} MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
686 MPI2_POINTER PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
687 Mpi26EventDataActiveCableExcept_t,
688 MPI2_POINTER pMpi26EventDataActiveCableExcept_t;
689
690/* defines for ReasonCode field */
691#define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
692
693
659/* Hard Reset Received Event data */
660
661typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
662{
663 U8 Reserved1; /* 0x00 */
664 U8 Port; /* 0x01 */
665 U16 Reserved2; /* 0x02 */
666} MPI2_EVENT_DATA_HARD_RESET_RECEIVED,

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1125 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */
1126} MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
1127 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
1128
1129/* values for the DescriptorType field */
1130#define MPI2_EVENT_HBD_DT_SAS (0x01)
1131
1132
694/* Hard Reset Received Event data */
695
696typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
697{
698 U8 Reserved1; /* 0x00 */
699 U8 Port; /* 0x01 */
700 U16 Reserved2; /* 0x02 */
701} MPI2_EVENT_DATA_HARD_RESET_RECEIVED,

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1160 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */
1161} MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
1162 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
1163
1164/* values for the DescriptorType field */
1165#define MPI2_EVENT_HBD_DT_SAS (0x01)
1166
1167
1133
1134/****************************************************************************
1135* EventAck message
1136****************************************************************************/
1137
1138/* EventAck Request message */
1139typedef struct _MPI2_EVENT_ACK_REQUEST
1140{
1141 U16 Reserved1; /* 0x00 */

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1343#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1344#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1345#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1346#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1347#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1348#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1349#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1350#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1168/****************************************************************************
1169* EventAck message
1170****************************************************************************/
1171
1172/* EventAck Request message */
1173typedef struct _MPI2_EVENT_ACK_REQUEST
1174{
1175 U16 Reserved1; /* 0x00 */

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1377#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1378#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1379#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1380#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1381#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1382#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1383#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1384#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1385#define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D)
1351
1352/* MPI v2.0 FWUpload TransactionContext Element */
1353typedef struct _MPI2_FW_UPLOAD_TCSGE
1354{
1355 U8 Reserved1; /* 0x00 */
1356 U8 ContextSize; /* 0x01 */
1357 U8 DetailsLength; /* 0x02 */
1358 U8 Flags; /* 0x03 */

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1431 U32 Reserved40; /* 0x40 */
1432 U32 Reserved44; /* 0x44 */
1433 U32 Reserved48; /* 0x48 */
1434 U32 Reserved4C; /* 0x4C */
1435 U32 Reserved50; /* 0x50 */
1436 U32 Reserved54; /* 0x54 */
1437 U32 Reserved58; /* 0x58 */
1438 U32 Reserved5C; /* 0x5C */
1386
1387/* MPI v2.0 FWUpload TransactionContext Element */
1388typedef struct _MPI2_FW_UPLOAD_TCSGE
1389{
1390 U8 Reserved1; /* 0x00 */
1391 U8 ContextSize; /* 0x01 */
1392 U8 DetailsLength; /* 0x02 */
1393 U8 Flags; /* 0x03 */

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1466 U32 Reserved40; /* 0x40 */
1467 U32 Reserved44; /* 0x44 */
1468 U32 Reserved48; /* 0x48 */
1469 U32 Reserved4C; /* 0x4C */
1470 U32 Reserved50; /* 0x50 */
1471 U32 Reserved54; /* 0x54 */
1472 U32 Reserved58; /* 0x58 */
1473 U32 Reserved5C; /* 0x5C */
1439 U32 Reserved60; /* 0x60 */
1474 U32 BootFlags; /* 0x60 */ /* reserved in MPI v2.5 and earlier */
1440 U32 FirmwareVersionNameWhat; /* 0x64 */
1441 U8 FirmwareVersionName[32]; /* 0x68 */
1442 U32 VendorNameWhat; /* 0x88 */
1443 U8 VendorName[32]; /* 0x8C */
1444 U32 PackageNameWhat; /* 0x88 */
1445 U8 PackageName[32]; /* 0x8C */
1446 U32 ReservedD0; /* 0xD0 */
1447 U32 ReservedD4; /* 0xD4 */

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1457 U32 ReservedFC; /* 0xFC */
1458} MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1459 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1460
1461/* Signature field */
1462#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1463#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1464#define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1475 U32 FirmwareVersionNameWhat; /* 0x64 */
1476 U8 FirmwareVersionName[32]; /* 0x68 */
1477 U32 VendorNameWhat; /* 0x88 */
1478 U8 VendorName[32]; /* 0x8C */
1479 U32 PackageNameWhat; /* 0x88 */
1480 U8 PackageName[32]; /* 0x8C */
1481 U32 ReservedD0; /* 0xD0 */
1482 U32 ReservedD4; /* 0xD4 */

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1492 U32 ReservedFC; /* 0xFC */
1493} MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1494 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1495
1496/* Signature field */
1497#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1498#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1499#define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1500#define MPI26_FW_HEADER_SIGNATURE (0xEB000000)
1465
1466/* Signature0 field */
1467#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1468#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1501
1502/* Signature0 field */
1503#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1504#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1505#define MPI26_FW_HEADER_SIGNATURE0_BASE (0x5AEAA500) /* Last byte is defined by architecture */
1506#define MPI26_FW_HEADER_SIGNATURE0_ARC_0 (0x5A)
1507#define MPI26_FW_HEADER_SIGNATURE0_ARC_1 (0x00)
1508#define MPI26_FW_HEADER_SIGNATURE0_ARC_2 (0x01)
1509#define MPI26_FW_HEADER_SIGNATURE0 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_0) // legacy (0x5AEAA55A)
1510#define MPI26_FW_HEADER_SIGNATURE0_3516 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_1)
1469
1470/* Signature1 field */
1471#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1472#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1511
1512/* Signature1 field */
1513#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1514#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1515#define MPI26_FW_HEADER_SIGNATURE1 (0xA55AEAA5)
1473
1474/* Signature2 field */
1475#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1476#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1516
1517/* Signature2 field */
1518#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1519#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1520#define MPI26_FW_HEADER_SIGNATURE2 (0x5AA55AEA)
1477
1478
1479/* defines for using the ProductID field */
1480#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1481#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1482
1483#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1484#define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1485#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1486#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1487
1488
1489#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1490/* SAS ProductID Family bits */
1491#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1492#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1493#define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021)
1521
1522
1523/* defines for using the ProductID field */
1524#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1525#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1526
1527#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1528#define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1529#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1530#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1531
1532
1533#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1534/* SAS ProductID Family bits */
1535#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1536#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1537#define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021)
1538#define MPI26_FW_HEADER_PID_FAMILY_3324_SAS (0x0028)
1539#define MPI26_FW_HEADER_PID_FAMILY_3516_SAS (0x0031)
1494
1495/* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1496
1497/* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1498
1499
1500#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1501#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1540
1541/* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1542
1543/* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1544
1545
1546#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1547#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1548#define MPI26_FW_HEADER_BOOTFLAGS_OFFSET (0x60)
1502#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1503
1504#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1505
1506#define MPI2_FW_HEADER_SIZE (0x100)
1507
1508
1509/* Extended Image Header */

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1607#define MPI2_FLASH_REGION_FIRMWARE (0x01)
1608#define MPI2_FLASH_REGION_BIOS (0x02)
1609#define MPI2_FLASH_REGION_NVDATA (0x03)
1610#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1611#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1612#define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1613#define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1614#define MPI2_FLASH_REGION_MEGARAID (0x09)
1549#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1550
1551#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1552
1553#define MPI2_FW_HEADER_SIZE (0x100)
1554
1555
1556/* Extended Image Header */

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1654#define MPI2_FLASH_REGION_FIRMWARE (0x01)
1655#define MPI2_FLASH_REGION_BIOS (0x02)
1656#define MPI2_FLASH_REGION_NVDATA (0x03)
1657#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1658#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1659#define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1660#define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1661#define MPI2_FLASH_REGION_MEGARAID (0x09)
1615#define MPI2_FLASH_REGION_INIT (0x0A)
1662#define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK (0x0A)
1663#define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK) /* older name */
1664#define MPI2_FLASH_REGION_CBB_BACKUP (0x0D)
1616
1665
1666
1617/* ImageRevision */
1618#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1619
1620
1621
1622/* Supported Devices Extended Image Data */
1623
1624/*

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1849 U16 Reserved4; /* 0x0A */
1850 U16 Reserved5; /* 0x0C */
1851 U16 IOCStatus; /* 0x0E */
1852 U32 IOCLogInfo; /* 0x10 */
1853} MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1854 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
1855
1856
1667/* ImageRevision */
1668#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1669
1670
1671
1672/* Supported Devices Extended Image Data */
1673
1674/*

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1899 U16 Reserved4; /* 0x0A */
1900 U16 Reserved5; /* 0x0C */
1901 U16 IOCStatus; /* 0x0E */
1902 U32 IOCLogInfo; /* 0x10 */
1903} MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1904 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
1905
1906
1907/****************************************************************************
1908* IO Unit Control messages (MPI v2.6 and later only.)
1909****************************************************************************/
1910
1911/* IO Unit Control Request Message */
1912typedef struct _MPI26_IOUNIT_CONTROL_REQUEST
1913{
1914 U8 Operation; /* 0x00 */
1915 U8 Reserved1; /* 0x01 */
1916 U8 ChainOffset; /* 0x02 */
1917 U8 Function; /* 0x03 */
1918 U16 DevHandle; /* 0x04 */
1919 U8 IOCParameter; /* 0x06 */
1920 U8 MsgFlags; /* 0x07 */
1921 U8 VP_ID; /* 0x08 */
1922 U8 VF_ID; /* 0x09 */
1923 U16 Reserved3; /* 0x0A */
1924 U16 Reserved4; /* 0x0C */
1925 U8 PhyNum; /* 0x0E */
1926 U8 PrimFlags; /* 0x0F */
1927 U32 Primitive; /* 0x10 */
1928 U8 LookupMethod; /* 0x14 */
1929 U8 Reserved5; /* 0x15 */
1930 U16 SlotNumber; /* 0x16 */
1931 U64 LookupAddress; /* 0x18 */
1932 U32 IOCParameterValue; /* 0x20 */
1933 U32 Reserved7; /* 0x24 */
1934 U32 Reserved8; /* 0x28 */
1935} MPI26_IOUNIT_CONTROL_REQUEST,
1936 MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REQUEST,
1937 Mpi26IoUnitControlRequest_t, MPI2_POINTER pMpi26IoUnitControlRequest_t;
1938
1939/* values for the Operation field */
1940#define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02)
1941#define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06)
1942#define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07)
1943#define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08)
1944#define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09)
1945#define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A)
1946#define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B)
1947#define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D)
1948#define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E)
1949#define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F)
1950#define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10)
1951#define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11)
1952#define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12)
1953#define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13)
1954#define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14)
1955#define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15)
1956#define MPI26_CTRL_OP_SHUTDOWN (0x16)
1957#define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17)
1958#define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18)
1959#define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19)
1960#define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80)
1961
1962/* values for the PrimFlags field */
1963#define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08)
1964#define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02)
1965#define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01)
1966
1967/* values for the LookupMethod field */
1968#define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01)
1969#define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02)
1970#define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03)
1971
1972
1973/* IO Unit Control Reply Message */
1974typedef struct _MPI26_IOUNIT_CONTROL_REPLY
1975{
1976 U8 Operation; /* 0x00 */
1977 U8 Reserved1; /* 0x01 */
1978 U8 MsgLength; /* 0x02 */
1979 U8 Function; /* 0x03 */
1980 U16 DevHandle; /* 0x04 */
1981 U8 IOCParameter; /* 0x06 */
1982 U8 MsgFlags; /* 0x07 */
1983 U8 VP_ID; /* 0x08 */
1984 U8 VF_ID; /* 0x09 */
1985 U16 Reserved3; /* 0x0A */
1986 U16 Reserved4; /* 0x0C */
1987 U16 IOCStatus; /* 0x0E */
1988 U32 IOCLogInfo; /* 0x10 */
1989} MPI26_IOUNIT_CONTROL_REPLY, MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REPLY,
1990 Mpi26IoUnitControlReply_t, MPI2_POINTER pMpi26IoUnitControlReply_t;
1991
1992
1857#endif
1858
1993#endif
1994