1/*
2 * ----------------------------------------------------------------------------
3 * "THE BEER-WARE LICENSE" (Revision 42):
4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you
5 * can do whatever you want with this stuff. If we meet some day, and you think
6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
7 * ----------------------------------------------------------------------------
8 *
9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $
10 *
11 * Driver for Siemens reference design card "Easy321-R1".
12 *
13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC
14 * controller.
15 *
16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't
17 * check it coming in.
18 *
19 * The FALC54 and MUNICH32X have far too many registers and weird modes for
20 * comfort, so I have not bothered typing it all into a "fooreg.h" file,
21 * you will (badly!) need the documentation anyway if you want to mess with
22 * this gadget.
23 *
| 1/*
2 * ----------------------------------------------------------------------------
3 * "THE BEER-WARE LICENSE" (Revision 42):
4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you
5 * can do whatever you want with this stuff. If we meet some day, and you think
6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
7 * ----------------------------------------------------------------------------
8 *
9 * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $
10 *
11 * Driver for Siemens reference design card "Easy321-R1".
12 *
13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC
14 * controller.
15 *
16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't
17 * check it coming in.
18 *
19 * The FALC54 and MUNICH32X have far too many registers and weird modes for
20 * comfort, so I have not bothered typing it all into a "fooreg.h" file,
21 * you will (badly!) need the documentation anyway if you want to mess with
22 * this gadget.
23 *
|
24 * $FreeBSD: head/sys/pci/if_mn.c 70068 2000-12-15 21:06:55Z bmilekic $
| 24 * $FreeBSD: head/sys/pci/if_mn.c 70159 2000-12-18 20:03:32Z julian $
|
25 */
26
27/*
28 * Stuff to describe the MUNIC32X and FALC54 chips.
29 */
30
31#define M32_CHAN 32 /* We have 32 channels */
32#define M32_TS 32 /* We have 32 timeslots */
33
34#define NG_MN_NODE_TYPE "mn"
35
36#include <sys/param.h>
37#include <sys/kernel.h>
38#include <sys/sysctl.h>
39#include <sys/bus.h>
40#include <sys/mbuf.h>
41#include <sys/systm.h>
42#include <sys/malloc.h>
43
44#include <pci/pcireg.h>
45#include <pci/pcivar.h>
46#include "pci_if.h"
47
48#include <machine/bus.h>
49#include <machine/resource.h>
50
51#include <sys/rman.h>
52
53#include <vm/vm.h>
54#include <vm/pmap.h>
55
56#include <netgraph/ng_message.h>
57#include <netgraph/netgraph.h>
58
59
60static int mn_maxlatency = 1000;
61SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW,
62 &mn_maxlatency, 0,
63 "The number of milliseconds a packet is allowed to spend in the output queue. "
64 "If the output queue is longer than this number of milliseconds when the packet "
65 "arrives for output, the packet will be dropped."
66);
67
68#ifndef NMN
69/* Most machines don't support more than 4 busmaster PCI slots, if even that many */
70#define NMN 4
71#endif
72
73/* From: PEB 20321 data sheet, p187, table 22 */
74struct m32xreg {
75 u_int32_t conf, cmd, stat, imask;
76 u_int32_t fill10, piqba, piql, fill1c;
77 u_int32_t mode1, mode2, ccba, txpoll;
78 u_int32_t tiqba, tiql, riqba, riql;
79 u_int32_t lconf, lccba, fill48, ltran;
80 u_int32_t ltiqba, ltiql, lriqba, lriql;
81 u_int32_t lreg0, lreg1, lreg2, lreg3;
82 u_int32_t lreg4, lreg5, lre6, lstat;
83 u_int32_t gpdir, gpdata, gpod, fill8c;
84 u_int32_t ssccon, sscbr, ssctb, sscrb;
85 u_int32_t ssccse, sscim, fillab, fillac;
86 u_int32_t iomcon1, iomcon2, iomstat, fillbc;
87 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1;
88 u_int32_t iomtmo, iomrmo, filld8, filldc;
89 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3;
90 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7;
91};
92
93/* From: PEB 2254 data sheet, p80, table 10 */
94struct f54wreg {
95 u_int16_t xfifo;
96 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2;
97 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
98 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
99 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
100 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
101 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3;
102 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
103 u_int8_t lim2, fill39[7];
104 u_int8_t fill40[8];
105 u_int8_t fill48[8];
106 u_int8_t fill50[8];
107 u_int8_t fill58[8];
108 u_int8_t dec, fill61, test2, fill63[5];
109 u_int8_t fill68[8];
110 u_int8_t xs[16];
111};
112
113/* From: PEB 2254 data sheet, p117, table 10 */
114struct f54rreg {
115 u_int16_t rfifo;
116 u_int8_t fill2, mode, rah1, rah2, ral1, ral2;
117 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
118 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
119 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
120 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
121 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13;
122 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
123 u_int8_t lim2, fill39[7];
124 u_int8_t fill40[8];
125 u_int8_t fill48[4], frs0, frs1, rsw, rsp;
126 u_int16_t fec, cvc, cec1, ebc;
127 u_int16_t cec2, cec3;
128 u_int8_t rsa4, rsa5, rsa6, rsa7;
129 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis;
130 u_int16_t rbc;
131 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr;
132 u_int8_t rs[16];
133};
134
135/* Transmit & receive descriptors */
136struct trxd {
137 u_int32_t flags;
138 vm_offset_t next;
139 vm_offset_t data;
140 u_int32_t status; /* only used for receive */
141 struct mbuf *m; /* software use only */
142 struct trxd *vnext; /* software use only */
143};
144
145/* Channel specification */
146struct cspec {
147 u_int32_t flags;
148 vm_offset_t rdesc;
149 vm_offset_t tdesc;
150 u_int32_t itbs;
151};
152
153struct m32_mem {
154 vm_offset_t csa;
155 u_int32_t ccb;
156 u_int32_t reserve1[2];
157 u_int32_t ts[M32_TS];
158 struct cspec cs[M32_CHAN];
159 vm_offset_t crxd[M32_CHAN];
160 vm_offset_t ctxd[M32_CHAN];
161};
162
163struct softc;
164struct sockaddr;
165struct rtentry;
166
167static int mn_probe (device_t self);
168static int mn_attach (device_t self);
169static void mn_create_channel(struct softc *sc, int chan);
170static int mn_reset(struct softc *sc);
171static struct trxd * mn_alloc_desc(void);
172static void mn_free_desc(struct trxd *dp);
173static void mn_intr(void *xsc);
174static u_int32_t mn_parse_ts(const char *s, int *nbit);
175#ifdef notyet
176static void m32_dump(struct softc *sc);
177static void f54_dump(struct softc *sc);
178static void mn_fmt_ts(char *p, u_int32_t ts);
179#endif /* notyet */
180
181static ng_constructor_t ngmn_constructor;
182static ng_rcvmsg_t ngmn_rcvmsg;
183static ng_shutdown_t ngmn_shutdown;
184static ng_newhook_t ngmn_newhook;
185static ng_connect_t ngmn_connect;
186static ng_rcvdata_t ngmn_rcvdata;
187static ng_disconnect_t ngmn_disconnect;
188
189static struct ng_type mntypestruct = {
| 25 */
26
27/*
28 * Stuff to describe the MUNIC32X and FALC54 chips.
29 */
30
31#define M32_CHAN 32 /* We have 32 channels */
32#define M32_TS 32 /* We have 32 timeslots */
33
34#define NG_MN_NODE_TYPE "mn"
35
36#include <sys/param.h>
37#include <sys/kernel.h>
38#include <sys/sysctl.h>
39#include <sys/bus.h>
40#include <sys/mbuf.h>
41#include <sys/systm.h>
42#include <sys/malloc.h>
43
44#include <pci/pcireg.h>
45#include <pci/pcivar.h>
46#include "pci_if.h"
47
48#include <machine/bus.h>
49#include <machine/resource.h>
50
51#include <sys/rman.h>
52
53#include <vm/vm.h>
54#include <vm/pmap.h>
55
56#include <netgraph/ng_message.h>
57#include <netgraph/netgraph.h>
58
59
60static int mn_maxlatency = 1000;
61SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW,
62 &mn_maxlatency, 0,
63 "The number of milliseconds a packet is allowed to spend in the output queue. "
64 "If the output queue is longer than this number of milliseconds when the packet "
65 "arrives for output, the packet will be dropped."
66);
67
68#ifndef NMN
69/* Most machines don't support more than 4 busmaster PCI slots, if even that many */
70#define NMN 4
71#endif
72
73/* From: PEB 20321 data sheet, p187, table 22 */
74struct m32xreg {
75 u_int32_t conf, cmd, stat, imask;
76 u_int32_t fill10, piqba, piql, fill1c;
77 u_int32_t mode1, mode2, ccba, txpoll;
78 u_int32_t tiqba, tiql, riqba, riql;
79 u_int32_t lconf, lccba, fill48, ltran;
80 u_int32_t ltiqba, ltiql, lriqba, lriql;
81 u_int32_t lreg0, lreg1, lreg2, lreg3;
82 u_int32_t lreg4, lreg5, lre6, lstat;
83 u_int32_t gpdir, gpdata, gpod, fill8c;
84 u_int32_t ssccon, sscbr, ssctb, sscrb;
85 u_int32_t ssccse, sscim, fillab, fillac;
86 u_int32_t iomcon1, iomcon2, iomstat, fillbc;
87 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1;
88 u_int32_t iomtmo, iomrmo, filld8, filldc;
89 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3;
90 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7;
91};
92
93/* From: PEB 2254 data sheet, p80, table 10 */
94struct f54wreg {
95 u_int16_t xfifo;
96 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2;
97 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
98 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
99 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
100 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
101 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3;
102 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
103 u_int8_t lim2, fill39[7];
104 u_int8_t fill40[8];
105 u_int8_t fill48[8];
106 u_int8_t fill50[8];
107 u_int8_t fill58[8];
108 u_int8_t dec, fill61, test2, fill63[5];
109 u_int8_t fill68[8];
110 u_int8_t xs[16];
111};
112
113/* From: PEB 2254 data sheet, p117, table 10 */
114struct f54rreg {
115 u_int16_t rfifo;
116 u_int8_t fill2, mode, rah1, rah2, ral1, ral2;
117 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
118 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
119 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
120 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
121 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13;
122 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
123 u_int8_t lim2, fill39[7];
124 u_int8_t fill40[8];
125 u_int8_t fill48[4], frs0, frs1, rsw, rsp;
126 u_int16_t fec, cvc, cec1, ebc;
127 u_int16_t cec2, cec3;
128 u_int8_t rsa4, rsa5, rsa6, rsa7;
129 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis;
130 u_int16_t rbc;
131 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr;
132 u_int8_t rs[16];
133};
134
135/* Transmit & receive descriptors */
136struct trxd {
137 u_int32_t flags;
138 vm_offset_t next;
139 vm_offset_t data;
140 u_int32_t status; /* only used for receive */
141 struct mbuf *m; /* software use only */
142 struct trxd *vnext; /* software use only */
143};
144
145/* Channel specification */
146struct cspec {
147 u_int32_t flags;
148 vm_offset_t rdesc;
149 vm_offset_t tdesc;
150 u_int32_t itbs;
151};
152
153struct m32_mem {
154 vm_offset_t csa;
155 u_int32_t ccb;
156 u_int32_t reserve1[2];
157 u_int32_t ts[M32_TS];
158 struct cspec cs[M32_CHAN];
159 vm_offset_t crxd[M32_CHAN];
160 vm_offset_t ctxd[M32_CHAN];
161};
162
163struct softc;
164struct sockaddr;
165struct rtentry;
166
167static int mn_probe (device_t self);
168static int mn_attach (device_t self);
169static void mn_create_channel(struct softc *sc, int chan);
170static int mn_reset(struct softc *sc);
171static struct trxd * mn_alloc_desc(void);
172static void mn_free_desc(struct trxd *dp);
173static void mn_intr(void *xsc);
174static u_int32_t mn_parse_ts(const char *s, int *nbit);
175#ifdef notyet
176static void m32_dump(struct softc *sc);
177static void f54_dump(struct softc *sc);
178static void mn_fmt_ts(char *p, u_int32_t ts);
179#endif /* notyet */
180
181static ng_constructor_t ngmn_constructor;
182static ng_rcvmsg_t ngmn_rcvmsg;
183static ng_shutdown_t ngmn_shutdown;
184static ng_newhook_t ngmn_newhook;
185static ng_connect_t ngmn_connect;
186static ng_rcvdata_t ngmn_rcvdata;
187static ng_disconnect_t ngmn_disconnect;
188
189static struct ng_type mntypestruct = {
|
190 NG_VERSION,
| 190 NG_ABI_VERSION,
|
191 NG_MN_NODE_TYPE,
192 NULL,
193 ngmn_constructor,
194 ngmn_rcvmsg,
195 ngmn_shutdown,
196 ngmn_newhook,
197 NULL,
198 ngmn_connect,
199 ngmn_rcvdata,
200 ngmn_disconnect,
201 NULL
202};
203
204static MALLOC_DEFINE(M_MN, "mn", "Mx driver related");
205
206#define NIQB 64
207
208struct schan {
209 enum {DOWN, UP} state;
210 struct softc *sc;
211 int chan;
212 u_int32_t ts;
213 char name[8];
214 struct trxd *r1, *rl;
215 struct trxd *x1, *xl;
216 hook_p hook;
217
218 time_t last_recv;
219 time_t last_rxerr;
220 time_t last_xmit;
221
222 u_long rx_error;
223
224 u_long short_error;
225 u_long crc_error;
226 u_long dribble_error;
227 u_long long_error;
228 u_long abort_error;
229 u_long overflow_error;
230
231 int last_error;
232 int prev_error;
233
234 u_long tx_pending;
235 u_long tx_limit;
236};
237
238struct softc {
239 int unit;
240 device_t dev;
241 struct resource *irq;
242 void *intrhand;
243 void *m0v, *m1v;
244 vm_offset_t m0p, m1p;
245 struct m32xreg *m32x;
246 struct f54wreg *f54w;
247 struct f54rreg *f54r;
248 struct m32_mem m32_mem;
249 u_int32_t tiqb[NIQB];
250 u_int32_t riqb[NIQB];
251 u_int32_t piqb[NIQB];
252 u_int32_t ltiqb[NIQB];
253 u_int32_t lriqb[NIQB];
254 char name[8];
255 u_int32_t falc_irq, falc_state, framer_state;
256 struct schan *ch[M32_CHAN];
257 char nodename[NG_NODELEN + 1];
258 node_p node;
259
260 u_long cnt_fec;
261 u_long cnt_cvc;
262 u_long cnt_cec1;
263 u_long cnt_ebc;
264 u_long cnt_cec2;
265 u_long cnt_cec3;
266 u_long cnt_rbc;
267};
268
269static int
270ngmn_constructor(node_p *nodep)
271{
272
273 return (EINVAL);
274}
275
276static int
277ngmn_shutdown(node_p nodep)
278{
279
280 return (EINVAL);
281}
282
283static int
| 191 NG_MN_NODE_TYPE,
192 NULL,
193 ngmn_constructor,
194 ngmn_rcvmsg,
195 ngmn_shutdown,
196 ngmn_newhook,
197 NULL,
198 ngmn_connect,
199 ngmn_rcvdata,
200 ngmn_disconnect,
201 NULL
202};
203
204static MALLOC_DEFINE(M_MN, "mn", "Mx driver related");
205
206#define NIQB 64
207
208struct schan {
209 enum {DOWN, UP} state;
210 struct softc *sc;
211 int chan;
212 u_int32_t ts;
213 char name[8];
214 struct trxd *r1, *rl;
215 struct trxd *x1, *xl;
216 hook_p hook;
217
218 time_t last_recv;
219 time_t last_rxerr;
220 time_t last_xmit;
221
222 u_long rx_error;
223
224 u_long short_error;
225 u_long crc_error;
226 u_long dribble_error;
227 u_long long_error;
228 u_long abort_error;
229 u_long overflow_error;
230
231 int last_error;
232 int prev_error;
233
234 u_long tx_pending;
235 u_long tx_limit;
236};
237
238struct softc {
239 int unit;
240 device_t dev;
241 struct resource *irq;
242 void *intrhand;
243 void *m0v, *m1v;
244 vm_offset_t m0p, m1p;
245 struct m32xreg *m32x;
246 struct f54wreg *f54w;
247 struct f54rreg *f54r;
248 struct m32_mem m32_mem;
249 u_int32_t tiqb[NIQB];
250 u_int32_t riqb[NIQB];
251 u_int32_t piqb[NIQB];
252 u_int32_t ltiqb[NIQB];
253 u_int32_t lriqb[NIQB];
254 char name[8];
255 u_int32_t falc_irq, falc_state, framer_state;
256 struct schan *ch[M32_CHAN];
257 char nodename[NG_NODELEN + 1];
258 node_p node;
259
260 u_long cnt_fec;
261 u_long cnt_cvc;
262 u_long cnt_cec1;
263 u_long cnt_ebc;
264 u_long cnt_cec2;
265 u_long cnt_cec3;
266 u_long cnt_rbc;
267};
268
269static int
270ngmn_constructor(node_p *nodep)
271{
272
273 return (EINVAL);
274}
275
276static int
277ngmn_shutdown(node_p nodep)
278{
279
280 return (EINVAL);
281}
282
283static int
|
284ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp, hook_p lasthook)
| 284ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr,
285 struct ng_mesg **rptr, hook_p lasthook)
|
285{
286 struct softc *sc;
| 286{
287 struct softc *sc;
|
| 288 struct ng_mesg *resp = NULL;
|
287 struct schan *sch;
288 char *arg;
289 int pos, i;
290
291 sc = node->private;
292
293 if (msg->header.typecookie != NGM_GENERIC_COOKIE ||
| 289 struct schan *sch;
290 char *arg;
291 int pos, i;
292
293 sc = node->private;
294
295 if (msg->header.typecookie != NGM_GENERIC_COOKIE ||
|
| 296 rptr == NULL || /* temporary */
|
294 msg->header.cmd != NGM_TEXT_STATUS) {
| 297 msg->header.cmd != NGM_TEXT_STATUS) {
|
295 if (resp)
296 *resp = NULL;
| 298 if (rptr)
299 *rptr = NULL;
|
297 FREE(msg, M_NETGRAPH);
298 return (EINVAL);
299 }
| 300 FREE(msg, M_NETGRAPH);
301 return (EINVAL);
302 }
|
300 NG_MKRESPONSE(*resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE,
| 303 NG_MKRESPONSE(resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE,
|
301 M_NOWAIT);
| 304 M_NOWAIT);
|
302 if (*resp == NULL) {
| 305 if (resp == NULL) {
|
303 FREE(msg, M_NETGRAPH);
304 return (ENOMEM);
305 }
| 306 FREE(msg, M_NETGRAPH);
307 return (ENOMEM);
308 }
|
306 arg = (char *)(*resp)->data;
| 309 arg = (char *)resp->data;
|
307 pos = 0;
308 pos += sprintf(pos + arg,"Framer status %b;\n", sc->framer_state, "\20"
309 "\40LOS\37AIS\36LFA\35RRA"
310 "\34AUXP\33NMF\32LMFA\31frs0.0"
311 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
312 "\24TS16LFA\23frs1.2\22XLS\21XLO"
313 "\20RS1\17rsw.6\16RRA\15RY0"
314 "\14RY1\13RY2\12RY3\11RY4"
315 "\10SI1\7SI2\6rsp.5\5rsp.4"
316 "\4rsp.3\3RSIF\2RS13\1RS15");
317 pos += sprintf(pos + arg," Framing errors: %lu", sc->cnt_fec);
318 pos += sprintf(pos + arg," Code Violations: %lu\n", sc->cnt_cvc);
319
320 pos += sprintf(pos + arg," Falc State %b;\n", sc->falc_state, "\20"
321 "\40LOS\37AIS\36LFA\35RRA"
322 "\34AUXP\33NMF\32LMFA\31frs0.0"
323 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
324 "\24TS16LFA\23frs1.2\22XLS\21XLO"
325 "\20RS1\17rsw.6\16RRA\15RY0"
326 "\14RY1\13RY2\12RY3\11RY4"
327 "\10SI1\7SI2\6rsp.5\5rsp.4"
328 "\4rsp.3\3RSIF\2RS13\1RS15");
329 pos += sprintf(pos + arg, " Falc IRQ %b\n", sc->falc_irq, "\20"
330 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
331 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
332 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
333 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
334 for (i = 0; i < M32_CHAN; i++) {
335 if (!sc->ch[i])
336 continue;
337 sch = sc->ch[i];
338
339 pos += sprintf(arg + pos, " Chan %d <%s> ",
340 i, sch->hook->name);
341
342 pos += sprintf(arg + pos, " Last Rx: ");
343 if (sch->last_recv)
344 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_recv);
345 else
346 pos += sprintf(arg + pos, "never");
347
348 pos += sprintf(arg + pos, ", last RxErr: ");
349 if (sch->last_rxerr)
350 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_rxerr);
351 else
352 pos += sprintf(arg + pos, "never");
353
354 pos += sprintf(arg + pos, ", last Tx: ");
355 if (sch->last_xmit)
356 pos += sprintf(arg + pos, "%lu s\n", time_second - sch->last_xmit);
357 else
358 pos += sprintf(arg + pos, "never\n");
359
360 pos += sprintf(arg + pos, " RX error(s) %lu", sch->rx_error);
361 pos += sprintf(arg + pos, " Short: %lu", sch->short_error);
362 pos += sprintf(arg + pos, " CRC: %lu", sch->crc_error);
363 pos += sprintf(arg + pos, " Mod8: %lu", sch->dribble_error);
364 pos += sprintf(arg + pos, " Long: %lu", sch->long_error);
365 pos += sprintf(arg + pos, " Abort: %lu", sch->abort_error);
366 pos += sprintf(arg + pos, " Overflow: %lu\n", sch->overflow_error);
367
368 pos += sprintf(arg + pos, " Last error: %b Prev error: %b\n",
369 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN",
370 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN");
371 pos += sprintf(arg + pos, " Xmit bytes pending %ld\n",
372 sch->tx_pending);
373 }
| 310 pos = 0;
311 pos += sprintf(pos + arg,"Framer status %b;\n", sc->framer_state, "\20"
312 "\40LOS\37AIS\36LFA\35RRA"
313 "\34AUXP\33NMF\32LMFA\31frs0.0"
314 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
315 "\24TS16LFA\23frs1.2\22XLS\21XLO"
316 "\20RS1\17rsw.6\16RRA\15RY0"
317 "\14RY1\13RY2\12RY3\11RY4"
318 "\10SI1\7SI2\6rsp.5\5rsp.4"
319 "\4rsp.3\3RSIF\2RS13\1RS15");
320 pos += sprintf(pos + arg," Framing errors: %lu", sc->cnt_fec);
321 pos += sprintf(pos + arg," Code Violations: %lu\n", sc->cnt_cvc);
322
323 pos += sprintf(pos + arg," Falc State %b;\n", sc->falc_state, "\20"
324 "\40LOS\37AIS\36LFA\35RRA"
325 "\34AUXP\33NMF\32LMFA\31frs0.0"
326 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
327 "\24TS16LFA\23frs1.2\22XLS\21XLO"
328 "\20RS1\17rsw.6\16RRA\15RY0"
329 "\14RY1\13RY2\12RY3\11RY4"
330 "\10SI1\7SI2\6rsp.5\5rsp.4"
331 "\4rsp.3\3RSIF\2RS13\1RS15");
332 pos += sprintf(pos + arg, " Falc IRQ %b\n", sc->falc_irq, "\20"
333 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
334 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
335 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
336 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
337 for (i = 0; i < M32_CHAN; i++) {
338 if (!sc->ch[i])
339 continue;
340 sch = sc->ch[i];
341
342 pos += sprintf(arg + pos, " Chan %d <%s> ",
343 i, sch->hook->name);
344
345 pos += sprintf(arg + pos, " Last Rx: ");
346 if (sch->last_recv)
347 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_recv);
348 else
349 pos += sprintf(arg + pos, "never");
350
351 pos += sprintf(arg + pos, ", last RxErr: ");
352 if (sch->last_rxerr)
353 pos += sprintf(arg + pos, "%lu s", time_second - sch->last_rxerr);
354 else
355 pos += sprintf(arg + pos, "never");
356
357 pos += sprintf(arg + pos, ", last Tx: ");
358 if (sch->last_xmit)
359 pos += sprintf(arg + pos, "%lu s\n", time_second - sch->last_xmit);
360 else
361 pos += sprintf(arg + pos, "never\n");
362
363 pos += sprintf(arg + pos, " RX error(s) %lu", sch->rx_error);
364 pos += sprintf(arg + pos, " Short: %lu", sch->short_error);
365 pos += sprintf(arg + pos, " CRC: %lu", sch->crc_error);
366 pos += sprintf(arg + pos, " Mod8: %lu", sch->dribble_error);
367 pos += sprintf(arg + pos, " Long: %lu", sch->long_error);
368 pos += sprintf(arg + pos, " Abort: %lu", sch->abort_error);
369 pos += sprintf(arg + pos, " Overflow: %lu\n", sch->overflow_error);
370
371 pos += sprintf(arg + pos, " Last error: %b Prev error: %b\n",
372 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN",
373 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN");
374 pos += sprintf(arg + pos, " Xmit bytes pending %ld\n",
375 sch->tx_pending);
376 }
|
374 (*resp)->header.arglen = pos + 1;
| 377 resp->header.arglen = pos + 1;
378
379 /* Take care of synchronous response, if any */
380 if (rptr)
381 *rptr = resp;
382 else if (resp)
383 FREE(resp, M_NETGRAPH); /* Will eventually send the hard way */
384
|
375 FREE(msg, M_NETGRAPH);
376 return (0);
377}
378
379static int
380ngmn_newhook(node_p node, hook_p hook, const char *name)
381{
382 u_int32_t ts, chan;
383 struct softc *sc;
384 int nbit;
385
386 sc = node->private;
387
388 if (name[0] != 't' || name[1] != 's')
389 return (EINVAL);
390
391 ts = mn_parse_ts(name + 2, &nbit);
392 if (ts == 0)
393 return (EINVAL);
394 chan = ffs(ts) - 1;
395 if (!sc->ch[chan])
396 mn_create_channel(sc, chan);
397 else if (sc->ch[chan]->state == UP)
398 return (EBUSY);
399 sc->ch[chan]->ts = ts;
400 sc->ch[chan]->hook = hook;
401 sc->ch[chan]->tx_limit = nbit * 8;
402 hook->private = sc->ch[chan];
403 return(0);
404}
405
406
407static struct trxd *mn_desc_free;
408
409static struct trxd *
410mn_alloc_desc(void)
411{
412 struct trxd *dp;
413
414 dp = mn_desc_free;
415 if (dp)
416 mn_desc_free = dp->vnext;
417 else
418 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT);
419 return (dp);
420}
421
422static void
423mn_free_desc(struct trxd *dp)
424{
425 dp->vnext = mn_desc_free;
426 mn_desc_free = dp;
427}
428
429static u_int32_t
430mn_parse_ts(const char *s, int *nbit)
431{
432 unsigned r;
433 int i, j;
434 char *p;
435
436 r = 0;
437 j = 0;
438 *nbit = 0;
439 while(*s) {
440 i = strtol(s, &p, 0);
441 if (i < 1 || i > 31)
442 return (0);
443 while (j && j < i) {
444 r |= 1 << j++;
445 (*nbit)++;
446 }
447 j = 0;
448 r |= 1 << i;
449 (*nbit)++;
450 if (*p == ',') {
451 s = p + 1;
452 continue;
453 } else if (*p == '-') {
454 j = i;
455 s = p + 1;
456 continue;
457 } else if (!*p) {
458 break;
459 } else {
460 return (0);
461 }
462 }
463 return (r);
464}
465
466#ifdef notyet
467static void
468mn_fmt_ts(char *p, u_int32_t ts)
469{
470 char *s;
471 int j;
472
473 s = "";
474 ts &= 0xfffffffe;
475 for (j = 1; j < 32; j++) {
476 if (!(ts & (1 << j)))
477 continue;
478 sprintf(p, "%s%d", s, j);
479 p += strlen(p);
480 s = ",";
481 if (!(ts & (1 << (j+1))))
482 continue;
483 for (; j < 32; j++)
484 if (!(ts & (1 << (j+1))))
485 break;
486 sprintf(p, "-%d", j);
487 p += strlen(p);
488 s = ",";
489 }
490}
491#endif /* notyet */
492
493/*
494 * OUTPUT
495 */
496
497static int
498ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta,
499 struct mbuf **ret_m, meta_p *ret_meta, struct ng_mesg **resp)
500{
501 struct mbuf *m2;
502 struct trxd *dp, *dp2;
503 struct schan *sch;
504 struct softc *sc;
505 int chan, pitch, len;
506
507 sch = hook->private;
508 sc = sch->sc;
509 chan = sch->chan;
510
511 if (sch->state != UP) {
512 NG_FREE_DATA(m, meta);
513 return (0);
514 }
515 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) {
516 NG_FREE_DATA(m, meta);
517 return (0);
518 }
519 NG_FREE_META(meta);
520 pitch = 0;
521 m2 = m;
522 dp2 = sc->ch[chan]->xl;
523 len = m->m_pkthdr.len;
524 while (len) {
525 dp = mn_alloc_desc();
526 if (!dp) {
527 pitch++;
528 m_freem(m);
529 sc->ch[chan]->xl = dp2;
530 dp = dp2->vnext;
531 while (dp) {
532 dp2 = dp->vnext;
533 mn_free_desc(dp);
534 dp = dp2;
535 }
536 sc->ch[chan]->xl->vnext = 0;
537 break;
538 }
539 dp->data = vtophys(m2->m_data);
540 dp->flags = m2->m_len << 16;
541 dp->flags += 1;
542 len -= m2->m_len;
543 dp->next = vtophys(dp);
544 dp->vnext = 0;
545 sc->ch[chan]->xl->next = vtophys(dp);
546 sc->ch[chan]->xl->vnext = dp;
547 sc->ch[chan]->xl = dp;
548 if (!len) {
549 dp->m = m;
550 dp->flags |= 0xc0000000;
551 dp2->flags &= ~0x40000000;
552 } else {
553 dp->m = 0;
554 m2 = m2->m_next;
555 }
556 }
557 if (pitch)
558 printf("%s%d: Short on mem, pitched %d packets\n",
559 sc->name, chan, pitch);
560 else {
561#if 0
562 printf("%d = %d + %d (%p)\n",
563 sch->tx_pending + m->m_pkthdr.len,
564 sch->tx_pending , m->m_pkthdr.len, m);
565#endif
566 sch->tx_pending += m->m_pkthdr.len;
567 }
568 return (0);
569}
570
571/*
572 * OPEN
573 */
574static int
575ngmn_connect(hook_p hook)
576{
577 int i, nts, chan;
578 struct trxd *dp, *dp2;
579 struct mbuf *m;
580 struct softc *sc;
581 struct schan *sch;
582 u_int32_t u;
583
584 sch = hook->private;
585 chan = sch->chan;
586 sc = sch->sc;
587
588 if (sch->state == UP)
589 return (0);
590 sch->state = UP;
591
592 /* Count and configure the timeslots for this channel */
593 for (nts = i = 0; i < 32; i++)
594 if (sch->ts & (1 << i)) {
595 sc->m32_mem.ts[i] = 0x00ff00ff |
596 (chan << 24) | (chan << 8);
597 nts++;
598 }
599
600 /* Init the receiver & xmitter to HDLC */
601 sc->m32_mem.cs[chan].flags = 0x80e90006;
602 /* Allocate two buffers per timeslot */
603 sc->m32_mem.cs[chan].itbs = nts * 2;
604
605 /* Setup a transmit chain with one descriptor */
606 /* XXX: we actually send a 1 byte packet */
607 dp = mn_alloc_desc();
608 MGETHDR(m, M_WAIT, MT_DATA);
609 if (m == NULL)
610 return ENOBUFS;
611 m->m_pkthdr.len = 0;
612 dp->m = m;
613 dp->flags = 0xc0000000 + (1 << 16);
614 dp->next = vtophys(dp);
615 dp->vnext = 0;
616 dp->data = vtophys(sc->name);
617 sc->m32_mem.cs[chan].tdesc = vtophys(dp);
618 sc->ch[chan]->x1 = dp;
619 sc->ch[chan]->xl = dp;
620
621 /* Setup a receive chain with 5 + NTS descriptors */
622
623 dp = mn_alloc_desc();
624 m = NULL;
625 MGETHDR(m, M_WAIT, MT_DATA);
626 if (m == NULL) {
627 mn_free_desc(dp);
628 return (ENOBUFS);
629 }
630 MCLGET(m, M_WAIT);
631 if ((m->m_flags & M_EXT) == 0) {
632 mn_free_desc(dp);
633 m_freem(m);
634 return (ENOBUFS);
635 }
636 dp->m = m;
637 dp->data = vtophys(m->m_data);
638 dp->flags = 0x40000000;
639 dp->flags += 1600 << 16;
640 dp->next = vtophys(dp);
641 dp->vnext = 0;
642 sc->ch[chan]->rl = dp;
643
644 for (i = 0; i < (nts + 10); i++) {
645 dp2 = dp;
646 dp = mn_alloc_desc();
647 m = NULL;
648 MGETHDR(m, M_WAIT, MT_DATA);
649 if (m == NULL) {
650 mn_free_desc(dp);
651 m_freem(m);
652 return (ENOBUFS);
653 }
654 MCLGET(m, M_WAIT);
655 if ((m->m_flags & M_EXT) == 0) {
656 mn_free_desc(dp);
657 m_freem(m);
658 return (ENOBUFS);
659 }
660 dp->m = m;
661 dp->data = vtophys(m->m_data);
662 dp->flags = 0x00000000;
663 dp->flags += 1600 << 16;
664 dp->next = vtophys(dp2);
665 dp->vnext = dp2;
666 }
667 sc->m32_mem.cs[chan].rdesc = vtophys(dp);
668 sc->ch[chan]->r1 = dp;
669
670 /* Initialize this channel */
671 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
672 sc->m32x->cmd = 0x1;
673 DELAY(1000);
674 u = sc->m32x->stat;
675 if (!(u & 1))
676 printf("%s: init chan %d stat %08x\n", sc->name, chan, u);
677 sc->m32x->stat = 1;
678 /* probably not at splnet, force outward queueing */
679 hook->peer->flags |= HK_QUEUE;
680
681 return (0);
682}
683
684/*
685 * CLOSE
686 */
687static int
688ngmn_disconnect(hook_p hook)
689{
690 int chan, i;
691 struct softc *sc;
692 struct schan *sch;
693 struct trxd *dp, *dp2;
694 u_int32_t u;
695
696 sch = hook->private;
697 chan = sch->chan;
698 sc = sch->sc;
699
700 if (sch->state == DOWN)
701 return (0);
702 sch->state = DOWN;
703
704 /* Set receiver & transmitter off */
705 sc->m32_mem.cs[chan].flags = 0x80920006;
706 sc->m32_mem.cs[chan].itbs = 0;
707
708 /* free the timeslots */
709 for (i = 0; i < 32; i++)
710 if (sc->ch[chan]->ts & (1 << i))
711 sc->m32_mem.ts[i] = 0x20002000;
712
713 /* Initialize this channel */
714 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
715 sc->m32x->cmd = 0x1;
716 DELAY(30);
717 u = sc->m32x->stat;
718 if (!(u & 1))
719 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u);
720 sc->m32x->stat = 1;
721
722 /* Free all receive descriptors and mbufs */
723 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) {
724 if (dp->m)
725 m_freem(dp->m);
726 sc->ch[chan]->r1 = dp2 = dp->vnext;
727 mn_free_desc(dp);
728 }
729
730 /* Free all transmit descriptors and mbufs */
731 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) {
732 if (dp->m) {
733 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len;
734 m_freem(dp->m);
735 }
736 sc->ch[chan]->x1 = dp2 = dp->vnext;
737 mn_free_desc(dp);
738 }
739 return(0);
740}
741
742/*
743 * Create a new channel.
744 */
745static void
746mn_create_channel(struct softc *sc, int chan)
747{
748 struct schan *sch;
749
750 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan],
751 M_MN, M_WAITOK | M_ZERO);
752 sch->sc = sc;
753 sch->state = DOWN;
754 sch->chan = chan;
755 sprintf(sch->name, "%s%d", sc->name, chan);
756 return;
757}
758
759#ifdef notyet
760/*
761 * Dump Munich32x state
762 */
763static void
764m32_dump(struct softc *sc)
765{
766 u_int32_t *tp4;
767 int i, j;
768
769 printf("mn%d: MUNICH32X dump\n", sc->unit);
770 tp4 = (u_int32_t *)sc->m0v;
771 for(j = 0; j < 64; j += 8) {
772 printf("%02x", j * sizeof *tp4);
773 for(i = 0; i < 8; i++)
774 printf(" %08x", tp4[i+j]);
775 printf("\n");
776 }
777 for(j = 0; j < M32_CHAN; j++) {
778 if (!sc->ch[j])
779 continue;
780 printf("CH%d: state %d ts %08x",
781 j, sc->ch[j]->state, sc->ch[j]->ts);
782 printf(" %08x %08x %08x %08x %08x %08x\n",
783 sc->m32_mem.cs[j].flags,
784 sc->m32_mem.cs[j].rdesc,
785 sc->m32_mem.cs[j].tdesc,
786 sc->m32_mem.cs[j].itbs,
787 sc->m32_mem.crxd[j],
788 sc->m32_mem.ctxd[j] );
789 }
790}
791
792/*
793 * Dump Falch54 state
794 */
795static void
796f54_dump(struct softc *sc)
797{
798 u_int8_t *tp1;
799 int i, j;
800
801 printf("%s: FALC54 dump\n", sc->name);
802 tp1 = (u_int8_t *)sc->m1v;
803 for(j = 0; j < 128; j += 16) {
804 printf("%s: %02x |", sc->name, j * sizeof *tp1);
805 for(i = 0; i < 16; i++)
806 printf(" %02x", tp1[i+j]);
807 printf("\n");
808 }
809}
810#endif /* notyet */
811
812/*
813 * Init Munich32x
814 */
815static void
816m32_init(struct softc *sc)
817{
818
819 sc->m32x->conf = 0x00000000;
820 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */
821#if 1
822 sc->m32x->mode2 = 0x00000081;
823 sc->m32x->txpoll = 0xffffffff;
824#else
825 sc->m32x->mode2 = 0x00000101;
826#endif
827 sc->m32x->lconf = 0x6060009B;
828 sc->m32x->imask = 0x00000000;
829}
830
831/*
832 * Init the Falc54
833 */
834static void
835f54_init(struct softc *sc)
836{
837 sc->f54w->ipc = 0x07;
838
839 sc->f54w->xpm0 = 0xbd;
840 sc->f54w->xpm1 = 0x03;
841 sc->f54w->xpm2 = 0x00;
842
843 sc->f54w->imr0 = 0x18; /* RMB, CASC */
844 sc->f54w->imr1 = 0x08; /* XMB */
845 sc->f54w->imr2 = 0x00;
846 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */
847 sc->f54w->imr4 = 0x00;
848
849 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */
850 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */
851 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */
852
853 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */
854 sc->f54w->pcd = 0x0a;
855 sc->f54w->pcr = 0x15;
856 sc->f54w->xsw = 0x9f; /* fmr4 */
857 sc->f54w->xsp = 0x1c; /* fmr5 */
858 sc->f54w->xc0 = 0x07;
859 sc->f54w->xc1 = 0x3d;
860 sc->f54w->rc0 = 0x05;
861 sc->f54w->rc1 = 0x00;
862 sc->f54w->cmdr = 0x51;
863}
864
865static int
866mn_reset(struct softc *sc)
867{
868 u_int32_t u;
869 int i;
870
871 sc->m32x->ccba = vtophys(&sc->m32_mem.csa);
872 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb);
873
874 bzero(sc->tiqb, sizeof sc->tiqb);
875 sc->m32x->tiqba = vtophys(&sc->tiqb);
876 sc->m32x->tiql = NIQB / 16 - 1;
877
878 bzero(sc->riqb, sizeof sc->riqb);
879 sc->m32x->riqba = vtophys(&sc->riqb);
880 sc->m32x->riql = NIQB / 16 - 1;
881
882 bzero(sc->ltiqb, sizeof sc->ltiqb);
883 sc->m32x->ltiqba = vtophys(&sc->ltiqb);
884 sc->m32x->ltiql = NIQB / 16 - 1;
885
886 bzero(sc->lriqb, sizeof sc->lriqb);
887 sc->m32x->lriqba = vtophys(&sc->lriqb);
888 sc->m32x->lriql = NIQB / 16 - 1;
889
890 bzero(sc->piqb, sizeof sc->piqb);
891 sc->m32x->piqba = vtophys(&sc->piqb);
892 sc->m32x->piql = NIQB / 16 - 1;
893
894 m32_init(sc);
895 f54_init(sc);
896
897 u = sc->m32x->stat;
898 sc->m32x->stat = u;
899 sc->m32_mem.ccb = 0x4;
900 sc->m32x->cmd = 0x1;
901 DELAY(1000);
902 u = sc->m32x->stat;
903 sc->m32x->stat = u;
904
905 /* set all timeslots to known state */
906 for (i = 0; i < 32; i++)
907 sc->m32_mem.ts[i] = 0x20002000;
908
909 if (!(u & 1)) {
910 printf(
911"mn%d: WARNING: Controller failed the PCI bus-master test.\n"
912"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n",
913 sc->unit, sc->unit);
914 return (0);
915 }
916 return (1);
917}
918
919/*
920 * FALC54 interrupt handling
921 */
922static void
923f54_intr(struct softc *sc)
924{
925 unsigned g, u, s;
926
927 g = sc->f54r->gis;
928 u = sc->f54r->isr0 << 24;
929 u |= sc->f54r->isr1 << 16;
930 u |= sc->f54r->isr2 << 8;
931 u |= sc->f54r->isr3;
932 sc->falc_irq = u;
933 /* don't chat about the 1 sec heart beat */
934 if (u & ~0x40) {
935#if 0
936 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20"
937 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
938 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
939 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
940 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
941#endif
942 s = sc->f54r->frs0 << 24;
943 s |= sc->f54r->frs1 << 16;
944 s |= sc->f54r->rsw << 8;
945 s |= sc->f54r->rsp;
946 sc->falc_state = s;
947
948 s &= ~0x01844038; /* undefined or static bits */
949 s &= ~0x00009fc7; /* bits we don't care about */
950 s &= ~0x00780000; /* XXX: TS16 related */
951 s &= ~0x06000000; /* XXX: Multiframe related */
952#if 0
953 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20"
954 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0"
955 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO"
956 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4"
957 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15");
958#endif
959 if (s != sc->framer_state) {
960#if 0
961 for (i = 0; i < M32_CHAN; i++) {
962 if (!sc->ch[i])
963 continue;
964 sp = &sc->ch[i]->ifsppp;
965 if (!(sp->pp_if.if_flags & IFF_UP))
966 continue;
967 if (s)
968 timeout((timeout_t *)sp->pp_down, sp, 1 * hz);
969 else
970 timeout((timeout_t *)sp->pp_up, sp, 1 * hz);
971 }
972#endif
973 sc->framer_state = s;
974 }
975 }
976 /* Once per second check error counters */
977 /* XXX: not clear if this is actually ok */
978 if (!(u & 0x40))
979 return;
980 sc->cnt_fec += sc->f54r->fec;
981 sc->cnt_cvc += sc->f54r->cvc;
982 sc->cnt_cec1 += sc->f54r->cec1;
983 sc->cnt_ebc += sc->f54r->ebc;
984 sc->cnt_cec2 += sc->f54r->cec2;
985 sc->cnt_cec3 += sc->f54r->cec3;
986 sc->cnt_rbc += sc->f54r->rbc;
987}
988
989/*
990 * Transmit interrupt for one channel
991 */
992static void
993mn_tx_intr(struct softc *sc, u_int32_t vector)
994{
995 u_int32_t chan;
996 struct trxd *dp;
997 struct mbuf *m;
998
999 chan = vector & 0x1f;
1000 if (!sc->ch[chan])
1001 return;
1002 if (sc->ch[chan]->state != UP) {
1003 printf("%s: tx_intr when not UP\n", sc->name);
1004 return;
1005 }
1006 for (;;) {
1007 dp = sc->ch[chan]->x1;
1008 if (vtophys(dp) == sc->m32_mem.ctxd[chan])
1009 return;
1010 m = dp->m;
1011 if (m) {
1012#if 0
1013 printf("%d = %d - %d (%p)\n",
1014 sc->ch[chan]->tx_pending - m->m_pkthdr.len,
1015 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m);
1016#endif
1017 sc->ch[chan]->tx_pending -= m->m_pkthdr.len;
1018 m_freem(m);
1019 }
1020 sc->ch[chan]->last_xmit = time_second;
1021 sc->ch[chan]->x1 = dp->vnext;
1022 mn_free_desc(dp);
1023 }
1024}
1025
1026/*
1027 * Receive interrupt for one channel
1028 */
1029static void
1030mn_rx_intr(struct softc *sc, u_int32_t vector)
1031{
1032 u_int32_t chan, err;
1033 struct trxd *dp;
1034 struct mbuf *m;
1035 struct schan *sch;
1036
1037 chan = vector & 0x1f;
1038 if (!sc->ch[chan])
1039 return;
1040 sch = sc->ch[chan];
1041 if (sch->state != UP) {
1042 printf("%s: rx_intr when not UP\n", sc->name);
1043 return;
1044 }
1045 vector &= ~0x1f;
1046 if (vector == 0x30000b00)
1047 sch->rx_error++;
1048 for (;;) {
1049 dp = sch->r1;
1050 if (vtophys(dp) == sc->m32_mem.crxd[chan])
1051 return;
1052 m = dp->m;
1053 dp->m = 0;
1054 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff;
1055 err = (dp->status >> 8) & 0xff;
1056 if (!err) {
1057 int error;
1058 NG_SEND_DATA_ONLY(error, sch->hook, m);
1059 sch->last_recv = time_second;
1060 /* we could be down by now... */
1061 if (sch->state != UP)
1062 return;
1063 } else if (err & 0x40) {
1064 sch->short_error++;
1065 } else if (err & 0x10) {
1066 sch->crc_error++;
1067 } else if (err & 0x08) {
1068 sch->dribble_error++;
1069 } else if (err & 0x04) {
1070 sch->long_error++;
1071 } else if (err & 0x02) {
1072 sch->abort_error++;
1073 } else if (err & 0x01) {
1074 sch->overflow_error++;
1075 }
1076 if (err) {
1077 sch->last_rxerr = time_second;
1078 sch->prev_error = sch->last_error;
1079 sch->last_error = err;
1080 }
1081
1082 sc->ch[chan]->r1 = dp->vnext;
1083
1084 /* Replenish desc + mbuf supplies */
1085 if (!m) {
1086 MGETHDR(m, M_DONTWAIT, MT_DATA);
1087 if (m == NULL) {
1088 mn_free_desc(dp);
1089 return; /* ENOBUFS */
1090 }
1091 MCLGET(m, M_DONTWAIT);
1092 if((m->m_flags & M_EXT) == 0) {
1093 mn_free_desc(dp);
1094 m_freem(m);
1095 return; /* ENOBUFS */
1096 }
1097 }
1098 dp->m = m;
1099 dp->data = vtophys(m->m_data);
1100 dp->flags = 0x40000000;
1101 dp->flags += 1600 << 16;
1102 dp->next = vtophys(dp);
1103 dp->vnext = 0;
1104 sc->ch[chan]->rl->next = vtophys(dp);
1105 sc->ch[chan]->rl->vnext = dp;
1106 sc->ch[chan]->rl->flags &= ~0x40000000;
1107 sc->ch[chan]->rl = dp;
1108 }
1109}
1110
1111
1112/*
1113 * Interupt handler
1114 */
1115
1116static void
1117mn_intr(void *xsc)
1118{
1119 struct softc *sc;
1120 u_int32_t stat, lstat, u;
1121 int i, j;
1122
1123 sc = xsc;
1124 stat = sc->m32x->stat;
1125 lstat = sc->m32x->lstat;
1126#if 0
1127 if (!stat && !(lstat & 2))
1128 return;
1129#endif
1130
1131 if (stat & ~0xc200) {
1132 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat);
1133 }
1134
1135 if ((stat & 0x200) || (lstat & 2))
1136 f54_intr(sc);
1137
1138 for (j = i = 0; i < 64; i ++) {
1139 u = sc->riqb[i];
1140 if (u) {
1141 sc->riqb[i] = 0;
1142 mn_rx_intr(sc, u);
1143 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00)
1144 continue;
1145 u &= ~0x30000400; /* bits we don't care about */
1146 if ((u & ~0x1f) == 0x00000900)
1147 continue;
1148 if (!(u & ~0x1f))
1149 continue;
1150 if (!j)
1151 printf("%s*: RIQB:", sc->name);
1152 printf(" [%d]=%08x", i, u);
1153 j++;
1154 }
1155 }
1156 if (j)
1157 printf("\n");
1158
1159 for (j = i = 0; i < 64; i ++) {
1160 u = sc->tiqb[i];
1161 if (u) {
1162 sc->tiqb[i] = 0;
1163 mn_tx_intr(sc, u);
1164 if ((u & ~0x1f) == 0x20000800)
1165 continue;
1166 u &= ~0x20000000; /* bits we don't care about */
1167 if (!u)
1168 continue;
1169 if (!j)
1170 printf("%s*: TIQB:", sc->name);
1171 printf(" [%d]=%08x", i, u);
1172 j++;
1173 }
1174 }
1175 if (j)
1176 printf("\n");
1177 sc->m32x->stat = stat;
1178}
1179
1180static void
1181mn_timeout(void *xsc)
1182{
1183 static int round = 0;
1184 struct softc *sc;
1185
1186 mn_intr(xsc);
1187 sc = xsc;
1188 timeout(mn_timeout, xsc, 10 * hz);
1189 round++;
1190 if (round == 2) {
1191 sc->m32_mem.ccb = 0x00008004;
1192 sc->m32x->cmd = 0x1;
1193 } else if (round > 2) {
1194 printf("%s: timeout\n", sc->name);
1195 }
1196}
1197
1198/*
1199 * PCI initialization stuff
1200 */
1201
1202static int
1203mn_probe (device_t self)
1204{
1205 u_int id = pci_get_devid(self);
1206
1207 if (sizeof (struct m32xreg) != 256) {
1208 printf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg));
1209 return (ENXIO);
1210 }
1211 if (sizeof (struct f54rreg) != 128) {
1212 printf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg));
1213 return (ENXIO);
1214 }
1215 if (sizeof (struct f54wreg) != 128) {
1216 printf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg));
1217 return (ENXIO);
1218 }
1219
1220 if (id != 0x2101110a)
1221 return (ENXIO);
1222
1223 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller");
1224 return (0);
1225}
1226
1227static int
1228mn_attach (device_t self)
1229{
1230 struct softc *sc;
1231 u_int32_t u;
1232 u_int32_t ver;
1233 static int once;
1234 int rid, error;
1235 struct resource *res;
1236
1237 if (!once) {
1238 if (ng_newtype(&mntypestruct))
1239 printf("ng_newtype failed\n");
1240 once++;
1241 }
1242
1243 sc = (struct softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO);
1244 device_set_softc(self, sc);
1245
1246 sc->dev = self;
1247 sc->unit = device_get_unit(self);
1248 sprintf(sc->name, "mn%d", sc->unit);
1249
1250 rid = PCIR_MAPS;
1251 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid,
1252 0, ~0, 1, RF_ACTIVE);
1253 if (res == NULL) {
1254 device_printf(self, "Could not map memory\n");
1255 return ENXIO;
1256 }
1257 sc->m0v = rman_get_virtual(res);
1258 sc->m0p = rman_get_start(res);
1259
1260 rid = PCIR_MAPS + 4;
1261 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid,
1262 0, ~0, 1, RF_ACTIVE);
1263 if (res == NULL) {
1264 device_printf(self, "Could not map memory\n");
1265 return ENXIO;
1266 }
1267 sc->m1v = rman_get_virtual(res);
1268 sc->m1p = rman_get_start(res);
1269
1270 /* Allocate interrupt */
1271 rid = 0;
1272 sc->irq = bus_alloc_resource(self, SYS_RES_IRQ, &rid, 0, ~0,
1273 1, RF_SHAREABLE | RF_ACTIVE);
1274
1275 if (sc->irq == NULL) {
1276 printf("couldn't map interrupt\n");
1277 return(ENXIO);
1278 }
1279
1280 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, mn_intr, sc, &sc->intrhand);
1281
1282 if (error) {
1283 printf("couldn't set up irq\n");
1284 return(ENXIO);
1285 }
1286
1287 u = pci_read_config(self, PCIR_COMMAND, 1);
1288 printf("%x\n", u);
1289 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1);
1290#if 0
1291 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4);
1292#endif
1293 u = pci_read_config(self, PCIR_COMMAND, 1);
1294 printf("%x\n", u);
1295
1296 ver = pci_read_config(self, PCI_CLASS_REG, 4);
1297
1298 sc->m32x = (struct m32xreg *) sc->m0v;
1299 sc->f54w = (struct f54wreg *) sc->m1v;
1300 sc->f54r = (struct f54rreg *) sc->m1v;
1301
1302 /* We must reset before poking at FALC54 registers */
1303 u = mn_reset(sc);
1304 if (!u)
1305 return (0);
1306
1307 printf("mn%d: Munich32X", sc->unit);
1308 switch (ver & 0xff) {
1309 case 0x13:
1310 printf(" Rev 2.2");
1311 break;
1312 default:
1313 printf(" Rev 0x%x\n", ver & 0xff);
1314 }
1315 printf(", Falc54");
1316 switch (sc->f54r->vstr) {
1317 case 0:
1318 printf(" Rev < 1.3\n");
1319 break;
1320 case 1:
1321 printf(" Rev 1.3\n");
1322 break;
1323 case 2:
1324 printf(" Rev 1.4\n");
1325 break;
1326 case 0x10:
1327 printf("-LH Rev 1.1\n");
1328 break;
1329 case 0x13:
1330 printf("-LH Rev 1.3\n");
1331 break;
1332 default:
1333 printf(" Rev 0x%x\n", sc->f54r->vstr);
1334 }
1335
1336 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) {
1337 printf("ng_make_node_common failed\n");
1338 return (0);
1339 }
1340 sc->node->private = sc;
1341 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit);
1342 if (ng_name_node(sc->node, sc->nodename)) {
1343 ng_rmnode(sc->node);
1344 ng_unref(sc->node);
1345 return (0);
1346 }
1347
1348 return (0);
1349}
1350
1351
1352static device_method_t mn_methods[] = {
1353 /* Device interface */
1354 DEVMETHOD(device_probe, mn_probe),
1355 DEVMETHOD(device_attach, mn_attach),
1356 DEVMETHOD(device_suspend, bus_generic_suspend),
1357 DEVMETHOD(device_resume, bus_generic_resume),
1358 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1359
1360 {0, 0}
1361};
1362
1363static driver_t mn_driver = {
1364 "mn",
1365 mn_methods,
1366 0
1367};
1368
1369static devclass_t mn_devclass;
1370
1371DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0);
| 385 FREE(msg, M_NETGRAPH);
386 return (0);
387}
388
389static int
390ngmn_newhook(node_p node, hook_p hook, const char *name)
391{
392 u_int32_t ts, chan;
393 struct softc *sc;
394 int nbit;
395
396 sc = node->private;
397
398 if (name[0] != 't' || name[1] != 's')
399 return (EINVAL);
400
401 ts = mn_parse_ts(name + 2, &nbit);
402 if (ts == 0)
403 return (EINVAL);
404 chan = ffs(ts) - 1;
405 if (!sc->ch[chan])
406 mn_create_channel(sc, chan);
407 else if (sc->ch[chan]->state == UP)
408 return (EBUSY);
409 sc->ch[chan]->ts = ts;
410 sc->ch[chan]->hook = hook;
411 sc->ch[chan]->tx_limit = nbit * 8;
412 hook->private = sc->ch[chan];
413 return(0);
414}
415
416
417static struct trxd *mn_desc_free;
418
419static struct trxd *
420mn_alloc_desc(void)
421{
422 struct trxd *dp;
423
424 dp = mn_desc_free;
425 if (dp)
426 mn_desc_free = dp->vnext;
427 else
428 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT);
429 return (dp);
430}
431
432static void
433mn_free_desc(struct trxd *dp)
434{
435 dp->vnext = mn_desc_free;
436 mn_desc_free = dp;
437}
438
439static u_int32_t
440mn_parse_ts(const char *s, int *nbit)
441{
442 unsigned r;
443 int i, j;
444 char *p;
445
446 r = 0;
447 j = 0;
448 *nbit = 0;
449 while(*s) {
450 i = strtol(s, &p, 0);
451 if (i < 1 || i > 31)
452 return (0);
453 while (j && j < i) {
454 r |= 1 << j++;
455 (*nbit)++;
456 }
457 j = 0;
458 r |= 1 << i;
459 (*nbit)++;
460 if (*p == ',') {
461 s = p + 1;
462 continue;
463 } else if (*p == '-') {
464 j = i;
465 s = p + 1;
466 continue;
467 } else if (!*p) {
468 break;
469 } else {
470 return (0);
471 }
472 }
473 return (r);
474}
475
476#ifdef notyet
477static void
478mn_fmt_ts(char *p, u_int32_t ts)
479{
480 char *s;
481 int j;
482
483 s = "";
484 ts &= 0xfffffffe;
485 for (j = 1; j < 32; j++) {
486 if (!(ts & (1 << j)))
487 continue;
488 sprintf(p, "%s%d", s, j);
489 p += strlen(p);
490 s = ",";
491 if (!(ts & (1 << (j+1))))
492 continue;
493 for (; j < 32; j++)
494 if (!(ts & (1 << (j+1))))
495 break;
496 sprintf(p, "-%d", j);
497 p += strlen(p);
498 s = ",";
499 }
500}
501#endif /* notyet */
502
503/*
504 * OUTPUT
505 */
506
507static int
508ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta,
509 struct mbuf **ret_m, meta_p *ret_meta, struct ng_mesg **resp)
510{
511 struct mbuf *m2;
512 struct trxd *dp, *dp2;
513 struct schan *sch;
514 struct softc *sc;
515 int chan, pitch, len;
516
517 sch = hook->private;
518 sc = sch->sc;
519 chan = sch->chan;
520
521 if (sch->state != UP) {
522 NG_FREE_DATA(m, meta);
523 return (0);
524 }
525 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) {
526 NG_FREE_DATA(m, meta);
527 return (0);
528 }
529 NG_FREE_META(meta);
530 pitch = 0;
531 m2 = m;
532 dp2 = sc->ch[chan]->xl;
533 len = m->m_pkthdr.len;
534 while (len) {
535 dp = mn_alloc_desc();
536 if (!dp) {
537 pitch++;
538 m_freem(m);
539 sc->ch[chan]->xl = dp2;
540 dp = dp2->vnext;
541 while (dp) {
542 dp2 = dp->vnext;
543 mn_free_desc(dp);
544 dp = dp2;
545 }
546 sc->ch[chan]->xl->vnext = 0;
547 break;
548 }
549 dp->data = vtophys(m2->m_data);
550 dp->flags = m2->m_len << 16;
551 dp->flags += 1;
552 len -= m2->m_len;
553 dp->next = vtophys(dp);
554 dp->vnext = 0;
555 sc->ch[chan]->xl->next = vtophys(dp);
556 sc->ch[chan]->xl->vnext = dp;
557 sc->ch[chan]->xl = dp;
558 if (!len) {
559 dp->m = m;
560 dp->flags |= 0xc0000000;
561 dp2->flags &= ~0x40000000;
562 } else {
563 dp->m = 0;
564 m2 = m2->m_next;
565 }
566 }
567 if (pitch)
568 printf("%s%d: Short on mem, pitched %d packets\n",
569 sc->name, chan, pitch);
570 else {
571#if 0
572 printf("%d = %d + %d (%p)\n",
573 sch->tx_pending + m->m_pkthdr.len,
574 sch->tx_pending , m->m_pkthdr.len, m);
575#endif
576 sch->tx_pending += m->m_pkthdr.len;
577 }
578 return (0);
579}
580
581/*
582 * OPEN
583 */
584static int
585ngmn_connect(hook_p hook)
586{
587 int i, nts, chan;
588 struct trxd *dp, *dp2;
589 struct mbuf *m;
590 struct softc *sc;
591 struct schan *sch;
592 u_int32_t u;
593
594 sch = hook->private;
595 chan = sch->chan;
596 sc = sch->sc;
597
598 if (sch->state == UP)
599 return (0);
600 sch->state = UP;
601
602 /* Count and configure the timeslots for this channel */
603 for (nts = i = 0; i < 32; i++)
604 if (sch->ts & (1 << i)) {
605 sc->m32_mem.ts[i] = 0x00ff00ff |
606 (chan << 24) | (chan << 8);
607 nts++;
608 }
609
610 /* Init the receiver & xmitter to HDLC */
611 sc->m32_mem.cs[chan].flags = 0x80e90006;
612 /* Allocate two buffers per timeslot */
613 sc->m32_mem.cs[chan].itbs = nts * 2;
614
615 /* Setup a transmit chain with one descriptor */
616 /* XXX: we actually send a 1 byte packet */
617 dp = mn_alloc_desc();
618 MGETHDR(m, M_WAIT, MT_DATA);
619 if (m == NULL)
620 return ENOBUFS;
621 m->m_pkthdr.len = 0;
622 dp->m = m;
623 dp->flags = 0xc0000000 + (1 << 16);
624 dp->next = vtophys(dp);
625 dp->vnext = 0;
626 dp->data = vtophys(sc->name);
627 sc->m32_mem.cs[chan].tdesc = vtophys(dp);
628 sc->ch[chan]->x1 = dp;
629 sc->ch[chan]->xl = dp;
630
631 /* Setup a receive chain with 5 + NTS descriptors */
632
633 dp = mn_alloc_desc();
634 m = NULL;
635 MGETHDR(m, M_WAIT, MT_DATA);
636 if (m == NULL) {
637 mn_free_desc(dp);
638 return (ENOBUFS);
639 }
640 MCLGET(m, M_WAIT);
641 if ((m->m_flags & M_EXT) == 0) {
642 mn_free_desc(dp);
643 m_freem(m);
644 return (ENOBUFS);
645 }
646 dp->m = m;
647 dp->data = vtophys(m->m_data);
648 dp->flags = 0x40000000;
649 dp->flags += 1600 << 16;
650 dp->next = vtophys(dp);
651 dp->vnext = 0;
652 sc->ch[chan]->rl = dp;
653
654 for (i = 0; i < (nts + 10); i++) {
655 dp2 = dp;
656 dp = mn_alloc_desc();
657 m = NULL;
658 MGETHDR(m, M_WAIT, MT_DATA);
659 if (m == NULL) {
660 mn_free_desc(dp);
661 m_freem(m);
662 return (ENOBUFS);
663 }
664 MCLGET(m, M_WAIT);
665 if ((m->m_flags & M_EXT) == 0) {
666 mn_free_desc(dp);
667 m_freem(m);
668 return (ENOBUFS);
669 }
670 dp->m = m;
671 dp->data = vtophys(m->m_data);
672 dp->flags = 0x00000000;
673 dp->flags += 1600 << 16;
674 dp->next = vtophys(dp2);
675 dp->vnext = dp2;
676 }
677 sc->m32_mem.cs[chan].rdesc = vtophys(dp);
678 sc->ch[chan]->r1 = dp;
679
680 /* Initialize this channel */
681 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
682 sc->m32x->cmd = 0x1;
683 DELAY(1000);
684 u = sc->m32x->stat;
685 if (!(u & 1))
686 printf("%s: init chan %d stat %08x\n", sc->name, chan, u);
687 sc->m32x->stat = 1;
688 /* probably not at splnet, force outward queueing */
689 hook->peer->flags |= HK_QUEUE;
690
691 return (0);
692}
693
694/*
695 * CLOSE
696 */
697static int
698ngmn_disconnect(hook_p hook)
699{
700 int chan, i;
701 struct softc *sc;
702 struct schan *sch;
703 struct trxd *dp, *dp2;
704 u_int32_t u;
705
706 sch = hook->private;
707 chan = sch->chan;
708 sc = sch->sc;
709
710 if (sch->state == DOWN)
711 return (0);
712 sch->state = DOWN;
713
714 /* Set receiver & transmitter off */
715 sc->m32_mem.cs[chan].flags = 0x80920006;
716 sc->m32_mem.cs[chan].itbs = 0;
717
718 /* free the timeslots */
719 for (i = 0; i < 32; i++)
720 if (sc->ch[chan]->ts & (1 << i))
721 sc->m32_mem.ts[i] = 0x20002000;
722
723 /* Initialize this channel */
724 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
725 sc->m32x->cmd = 0x1;
726 DELAY(30);
727 u = sc->m32x->stat;
728 if (!(u & 1))
729 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u);
730 sc->m32x->stat = 1;
731
732 /* Free all receive descriptors and mbufs */
733 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) {
734 if (dp->m)
735 m_freem(dp->m);
736 sc->ch[chan]->r1 = dp2 = dp->vnext;
737 mn_free_desc(dp);
738 }
739
740 /* Free all transmit descriptors and mbufs */
741 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) {
742 if (dp->m) {
743 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len;
744 m_freem(dp->m);
745 }
746 sc->ch[chan]->x1 = dp2 = dp->vnext;
747 mn_free_desc(dp);
748 }
749 return(0);
750}
751
752/*
753 * Create a new channel.
754 */
755static void
756mn_create_channel(struct softc *sc, int chan)
757{
758 struct schan *sch;
759
760 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan],
761 M_MN, M_WAITOK | M_ZERO);
762 sch->sc = sc;
763 sch->state = DOWN;
764 sch->chan = chan;
765 sprintf(sch->name, "%s%d", sc->name, chan);
766 return;
767}
768
769#ifdef notyet
770/*
771 * Dump Munich32x state
772 */
773static void
774m32_dump(struct softc *sc)
775{
776 u_int32_t *tp4;
777 int i, j;
778
779 printf("mn%d: MUNICH32X dump\n", sc->unit);
780 tp4 = (u_int32_t *)sc->m0v;
781 for(j = 0; j < 64; j += 8) {
782 printf("%02x", j * sizeof *tp4);
783 for(i = 0; i < 8; i++)
784 printf(" %08x", tp4[i+j]);
785 printf("\n");
786 }
787 for(j = 0; j < M32_CHAN; j++) {
788 if (!sc->ch[j])
789 continue;
790 printf("CH%d: state %d ts %08x",
791 j, sc->ch[j]->state, sc->ch[j]->ts);
792 printf(" %08x %08x %08x %08x %08x %08x\n",
793 sc->m32_mem.cs[j].flags,
794 sc->m32_mem.cs[j].rdesc,
795 sc->m32_mem.cs[j].tdesc,
796 sc->m32_mem.cs[j].itbs,
797 sc->m32_mem.crxd[j],
798 sc->m32_mem.ctxd[j] );
799 }
800}
801
802/*
803 * Dump Falch54 state
804 */
805static void
806f54_dump(struct softc *sc)
807{
808 u_int8_t *tp1;
809 int i, j;
810
811 printf("%s: FALC54 dump\n", sc->name);
812 tp1 = (u_int8_t *)sc->m1v;
813 for(j = 0; j < 128; j += 16) {
814 printf("%s: %02x |", sc->name, j * sizeof *tp1);
815 for(i = 0; i < 16; i++)
816 printf(" %02x", tp1[i+j]);
817 printf("\n");
818 }
819}
820#endif /* notyet */
821
822/*
823 * Init Munich32x
824 */
825static void
826m32_init(struct softc *sc)
827{
828
829 sc->m32x->conf = 0x00000000;
830 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */
831#if 1
832 sc->m32x->mode2 = 0x00000081;
833 sc->m32x->txpoll = 0xffffffff;
834#else
835 sc->m32x->mode2 = 0x00000101;
836#endif
837 sc->m32x->lconf = 0x6060009B;
838 sc->m32x->imask = 0x00000000;
839}
840
841/*
842 * Init the Falc54
843 */
844static void
845f54_init(struct softc *sc)
846{
847 sc->f54w->ipc = 0x07;
848
849 sc->f54w->xpm0 = 0xbd;
850 sc->f54w->xpm1 = 0x03;
851 sc->f54w->xpm2 = 0x00;
852
853 sc->f54w->imr0 = 0x18; /* RMB, CASC */
854 sc->f54w->imr1 = 0x08; /* XMB */
855 sc->f54w->imr2 = 0x00;
856 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */
857 sc->f54w->imr4 = 0x00;
858
859 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */
860 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */
861 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */
862
863 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */
864 sc->f54w->pcd = 0x0a;
865 sc->f54w->pcr = 0x15;
866 sc->f54w->xsw = 0x9f; /* fmr4 */
867 sc->f54w->xsp = 0x1c; /* fmr5 */
868 sc->f54w->xc0 = 0x07;
869 sc->f54w->xc1 = 0x3d;
870 sc->f54w->rc0 = 0x05;
871 sc->f54w->rc1 = 0x00;
872 sc->f54w->cmdr = 0x51;
873}
874
875static int
876mn_reset(struct softc *sc)
877{
878 u_int32_t u;
879 int i;
880
881 sc->m32x->ccba = vtophys(&sc->m32_mem.csa);
882 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb);
883
884 bzero(sc->tiqb, sizeof sc->tiqb);
885 sc->m32x->tiqba = vtophys(&sc->tiqb);
886 sc->m32x->tiql = NIQB / 16 - 1;
887
888 bzero(sc->riqb, sizeof sc->riqb);
889 sc->m32x->riqba = vtophys(&sc->riqb);
890 sc->m32x->riql = NIQB / 16 - 1;
891
892 bzero(sc->ltiqb, sizeof sc->ltiqb);
893 sc->m32x->ltiqba = vtophys(&sc->ltiqb);
894 sc->m32x->ltiql = NIQB / 16 - 1;
895
896 bzero(sc->lriqb, sizeof sc->lriqb);
897 sc->m32x->lriqba = vtophys(&sc->lriqb);
898 sc->m32x->lriql = NIQB / 16 - 1;
899
900 bzero(sc->piqb, sizeof sc->piqb);
901 sc->m32x->piqba = vtophys(&sc->piqb);
902 sc->m32x->piql = NIQB / 16 - 1;
903
904 m32_init(sc);
905 f54_init(sc);
906
907 u = sc->m32x->stat;
908 sc->m32x->stat = u;
909 sc->m32_mem.ccb = 0x4;
910 sc->m32x->cmd = 0x1;
911 DELAY(1000);
912 u = sc->m32x->stat;
913 sc->m32x->stat = u;
914
915 /* set all timeslots to known state */
916 for (i = 0; i < 32; i++)
917 sc->m32_mem.ts[i] = 0x20002000;
918
919 if (!(u & 1)) {
920 printf(
921"mn%d: WARNING: Controller failed the PCI bus-master test.\n"
922"mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n",
923 sc->unit, sc->unit);
924 return (0);
925 }
926 return (1);
927}
928
929/*
930 * FALC54 interrupt handling
931 */
932static void
933f54_intr(struct softc *sc)
934{
935 unsigned g, u, s;
936
937 g = sc->f54r->gis;
938 u = sc->f54r->isr0 << 24;
939 u |= sc->f54r->isr1 << 16;
940 u |= sc->f54r->isr2 << 8;
941 u |= sc->f54r->isr3;
942 sc->falc_irq = u;
943 /* don't chat about the 1 sec heart beat */
944 if (u & ~0x40) {
945#if 0
946 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20"
947 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
948 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
949 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
950 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
951#endif
952 s = sc->f54r->frs0 << 24;
953 s |= sc->f54r->frs1 << 16;
954 s |= sc->f54r->rsw << 8;
955 s |= sc->f54r->rsp;
956 sc->falc_state = s;
957
958 s &= ~0x01844038; /* undefined or static bits */
959 s &= ~0x00009fc7; /* bits we don't care about */
960 s &= ~0x00780000; /* XXX: TS16 related */
961 s &= ~0x06000000; /* XXX: Multiframe related */
962#if 0
963 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20"
964 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0"
965 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO"
966 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4"
967 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15");
968#endif
969 if (s != sc->framer_state) {
970#if 0
971 for (i = 0; i < M32_CHAN; i++) {
972 if (!sc->ch[i])
973 continue;
974 sp = &sc->ch[i]->ifsppp;
975 if (!(sp->pp_if.if_flags & IFF_UP))
976 continue;
977 if (s)
978 timeout((timeout_t *)sp->pp_down, sp, 1 * hz);
979 else
980 timeout((timeout_t *)sp->pp_up, sp, 1 * hz);
981 }
982#endif
983 sc->framer_state = s;
984 }
985 }
986 /* Once per second check error counters */
987 /* XXX: not clear if this is actually ok */
988 if (!(u & 0x40))
989 return;
990 sc->cnt_fec += sc->f54r->fec;
991 sc->cnt_cvc += sc->f54r->cvc;
992 sc->cnt_cec1 += sc->f54r->cec1;
993 sc->cnt_ebc += sc->f54r->ebc;
994 sc->cnt_cec2 += sc->f54r->cec2;
995 sc->cnt_cec3 += sc->f54r->cec3;
996 sc->cnt_rbc += sc->f54r->rbc;
997}
998
999/*
1000 * Transmit interrupt for one channel
1001 */
1002static void
1003mn_tx_intr(struct softc *sc, u_int32_t vector)
1004{
1005 u_int32_t chan;
1006 struct trxd *dp;
1007 struct mbuf *m;
1008
1009 chan = vector & 0x1f;
1010 if (!sc->ch[chan])
1011 return;
1012 if (sc->ch[chan]->state != UP) {
1013 printf("%s: tx_intr when not UP\n", sc->name);
1014 return;
1015 }
1016 for (;;) {
1017 dp = sc->ch[chan]->x1;
1018 if (vtophys(dp) == sc->m32_mem.ctxd[chan])
1019 return;
1020 m = dp->m;
1021 if (m) {
1022#if 0
1023 printf("%d = %d - %d (%p)\n",
1024 sc->ch[chan]->tx_pending - m->m_pkthdr.len,
1025 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m);
1026#endif
1027 sc->ch[chan]->tx_pending -= m->m_pkthdr.len;
1028 m_freem(m);
1029 }
1030 sc->ch[chan]->last_xmit = time_second;
1031 sc->ch[chan]->x1 = dp->vnext;
1032 mn_free_desc(dp);
1033 }
1034}
1035
1036/*
1037 * Receive interrupt for one channel
1038 */
1039static void
1040mn_rx_intr(struct softc *sc, u_int32_t vector)
1041{
1042 u_int32_t chan, err;
1043 struct trxd *dp;
1044 struct mbuf *m;
1045 struct schan *sch;
1046
1047 chan = vector & 0x1f;
1048 if (!sc->ch[chan])
1049 return;
1050 sch = sc->ch[chan];
1051 if (sch->state != UP) {
1052 printf("%s: rx_intr when not UP\n", sc->name);
1053 return;
1054 }
1055 vector &= ~0x1f;
1056 if (vector == 0x30000b00)
1057 sch->rx_error++;
1058 for (;;) {
1059 dp = sch->r1;
1060 if (vtophys(dp) == sc->m32_mem.crxd[chan])
1061 return;
1062 m = dp->m;
1063 dp->m = 0;
1064 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff;
1065 err = (dp->status >> 8) & 0xff;
1066 if (!err) {
1067 int error;
1068 NG_SEND_DATA_ONLY(error, sch->hook, m);
1069 sch->last_recv = time_second;
1070 /* we could be down by now... */
1071 if (sch->state != UP)
1072 return;
1073 } else if (err & 0x40) {
1074 sch->short_error++;
1075 } else if (err & 0x10) {
1076 sch->crc_error++;
1077 } else if (err & 0x08) {
1078 sch->dribble_error++;
1079 } else if (err & 0x04) {
1080 sch->long_error++;
1081 } else if (err & 0x02) {
1082 sch->abort_error++;
1083 } else if (err & 0x01) {
1084 sch->overflow_error++;
1085 }
1086 if (err) {
1087 sch->last_rxerr = time_second;
1088 sch->prev_error = sch->last_error;
1089 sch->last_error = err;
1090 }
1091
1092 sc->ch[chan]->r1 = dp->vnext;
1093
1094 /* Replenish desc + mbuf supplies */
1095 if (!m) {
1096 MGETHDR(m, M_DONTWAIT, MT_DATA);
1097 if (m == NULL) {
1098 mn_free_desc(dp);
1099 return; /* ENOBUFS */
1100 }
1101 MCLGET(m, M_DONTWAIT);
1102 if((m->m_flags & M_EXT) == 0) {
1103 mn_free_desc(dp);
1104 m_freem(m);
1105 return; /* ENOBUFS */
1106 }
1107 }
1108 dp->m = m;
1109 dp->data = vtophys(m->m_data);
1110 dp->flags = 0x40000000;
1111 dp->flags += 1600 << 16;
1112 dp->next = vtophys(dp);
1113 dp->vnext = 0;
1114 sc->ch[chan]->rl->next = vtophys(dp);
1115 sc->ch[chan]->rl->vnext = dp;
1116 sc->ch[chan]->rl->flags &= ~0x40000000;
1117 sc->ch[chan]->rl = dp;
1118 }
1119}
1120
1121
1122/*
1123 * Interupt handler
1124 */
1125
1126static void
1127mn_intr(void *xsc)
1128{
1129 struct softc *sc;
1130 u_int32_t stat, lstat, u;
1131 int i, j;
1132
1133 sc = xsc;
1134 stat = sc->m32x->stat;
1135 lstat = sc->m32x->lstat;
1136#if 0
1137 if (!stat && !(lstat & 2))
1138 return;
1139#endif
1140
1141 if (stat & ~0xc200) {
1142 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat);
1143 }
1144
1145 if ((stat & 0x200) || (lstat & 2))
1146 f54_intr(sc);
1147
1148 for (j = i = 0; i < 64; i ++) {
1149 u = sc->riqb[i];
1150 if (u) {
1151 sc->riqb[i] = 0;
1152 mn_rx_intr(sc, u);
1153 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00)
1154 continue;
1155 u &= ~0x30000400; /* bits we don't care about */
1156 if ((u & ~0x1f) == 0x00000900)
1157 continue;
1158 if (!(u & ~0x1f))
1159 continue;
1160 if (!j)
1161 printf("%s*: RIQB:", sc->name);
1162 printf(" [%d]=%08x", i, u);
1163 j++;
1164 }
1165 }
1166 if (j)
1167 printf("\n");
1168
1169 for (j = i = 0; i < 64; i ++) {
1170 u = sc->tiqb[i];
1171 if (u) {
1172 sc->tiqb[i] = 0;
1173 mn_tx_intr(sc, u);
1174 if ((u & ~0x1f) == 0x20000800)
1175 continue;
1176 u &= ~0x20000000; /* bits we don't care about */
1177 if (!u)
1178 continue;
1179 if (!j)
1180 printf("%s*: TIQB:", sc->name);
1181 printf(" [%d]=%08x", i, u);
1182 j++;
1183 }
1184 }
1185 if (j)
1186 printf("\n");
1187 sc->m32x->stat = stat;
1188}
1189
1190static void
1191mn_timeout(void *xsc)
1192{
1193 static int round = 0;
1194 struct softc *sc;
1195
1196 mn_intr(xsc);
1197 sc = xsc;
1198 timeout(mn_timeout, xsc, 10 * hz);
1199 round++;
1200 if (round == 2) {
1201 sc->m32_mem.ccb = 0x00008004;
1202 sc->m32x->cmd = 0x1;
1203 } else if (round > 2) {
1204 printf("%s: timeout\n", sc->name);
1205 }
1206}
1207
1208/*
1209 * PCI initialization stuff
1210 */
1211
1212static int
1213mn_probe (device_t self)
1214{
1215 u_int id = pci_get_devid(self);
1216
1217 if (sizeof (struct m32xreg) != 256) {
1218 printf("MN: sizeof(struct m32xreg) = %d, should have been 256\n", sizeof (struct m32xreg));
1219 return (ENXIO);
1220 }
1221 if (sizeof (struct f54rreg) != 128) {
1222 printf("MN: sizeof(struct f54rreg) = %d, should have been 128\n", sizeof (struct f54rreg));
1223 return (ENXIO);
1224 }
1225 if (sizeof (struct f54wreg) != 128) {
1226 printf("MN: sizeof(struct f54wreg) = %d, should have been 128\n", sizeof (struct f54wreg));
1227 return (ENXIO);
1228 }
1229
1230 if (id != 0x2101110a)
1231 return (ENXIO);
1232
1233 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller");
1234 return (0);
1235}
1236
1237static int
1238mn_attach (device_t self)
1239{
1240 struct softc *sc;
1241 u_int32_t u;
1242 u_int32_t ver;
1243 static int once;
1244 int rid, error;
1245 struct resource *res;
1246
1247 if (!once) {
1248 if (ng_newtype(&mntypestruct))
1249 printf("ng_newtype failed\n");
1250 once++;
1251 }
1252
1253 sc = (struct softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO);
1254 device_set_softc(self, sc);
1255
1256 sc->dev = self;
1257 sc->unit = device_get_unit(self);
1258 sprintf(sc->name, "mn%d", sc->unit);
1259
1260 rid = PCIR_MAPS;
1261 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid,
1262 0, ~0, 1, RF_ACTIVE);
1263 if (res == NULL) {
1264 device_printf(self, "Could not map memory\n");
1265 return ENXIO;
1266 }
1267 sc->m0v = rman_get_virtual(res);
1268 sc->m0p = rman_get_start(res);
1269
1270 rid = PCIR_MAPS + 4;
1271 res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid,
1272 0, ~0, 1, RF_ACTIVE);
1273 if (res == NULL) {
1274 device_printf(self, "Could not map memory\n");
1275 return ENXIO;
1276 }
1277 sc->m1v = rman_get_virtual(res);
1278 sc->m1p = rman_get_start(res);
1279
1280 /* Allocate interrupt */
1281 rid = 0;
1282 sc->irq = bus_alloc_resource(self, SYS_RES_IRQ, &rid, 0, ~0,
1283 1, RF_SHAREABLE | RF_ACTIVE);
1284
1285 if (sc->irq == NULL) {
1286 printf("couldn't map interrupt\n");
1287 return(ENXIO);
1288 }
1289
1290 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, mn_intr, sc, &sc->intrhand);
1291
1292 if (error) {
1293 printf("couldn't set up irq\n");
1294 return(ENXIO);
1295 }
1296
1297 u = pci_read_config(self, PCIR_COMMAND, 1);
1298 printf("%x\n", u);
1299 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1);
1300#if 0
1301 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4);
1302#endif
1303 u = pci_read_config(self, PCIR_COMMAND, 1);
1304 printf("%x\n", u);
1305
1306 ver = pci_read_config(self, PCI_CLASS_REG, 4);
1307
1308 sc->m32x = (struct m32xreg *) sc->m0v;
1309 sc->f54w = (struct f54wreg *) sc->m1v;
1310 sc->f54r = (struct f54rreg *) sc->m1v;
1311
1312 /* We must reset before poking at FALC54 registers */
1313 u = mn_reset(sc);
1314 if (!u)
1315 return (0);
1316
1317 printf("mn%d: Munich32X", sc->unit);
1318 switch (ver & 0xff) {
1319 case 0x13:
1320 printf(" Rev 2.2");
1321 break;
1322 default:
1323 printf(" Rev 0x%x\n", ver & 0xff);
1324 }
1325 printf(", Falc54");
1326 switch (sc->f54r->vstr) {
1327 case 0:
1328 printf(" Rev < 1.3\n");
1329 break;
1330 case 1:
1331 printf(" Rev 1.3\n");
1332 break;
1333 case 2:
1334 printf(" Rev 1.4\n");
1335 break;
1336 case 0x10:
1337 printf("-LH Rev 1.1\n");
1338 break;
1339 case 0x13:
1340 printf("-LH Rev 1.3\n");
1341 break;
1342 default:
1343 printf(" Rev 0x%x\n", sc->f54r->vstr);
1344 }
1345
1346 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) {
1347 printf("ng_make_node_common failed\n");
1348 return (0);
1349 }
1350 sc->node->private = sc;
1351 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit);
1352 if (ng_name_node(sc->node, sc->nodename)) {
1353 ng_rmnode(sc->node);
1354 ng_unref(sc->node);
1355 return (0);
1356 }
1357
1358 return (0);
1359}
1360
1361
1362static device_method_t mn_methods[] = {
1363 /* Device interface */
1364 DEVMETHOD(device_probe, mn_probe),
1365 DEVMETHOD(device_attach, mn_attach),
1366 DEVMETHOD(device_suspend, bus_generic_suspend),
1367 DEVMETHOD(device_resume, bus_generic_resume),
1368 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1369
1370 {0, 0}
1371};
1372
1373static driver_t mn_driver = {
1374 "mn",
1375 mn_methods,
1376 0
1377};
1378
1379static devclass_t mn_devclass;
1380
1381DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0);
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