| ciphyreg.h (170365) | ciphyreg.h (220938) |
|---|---|
| 1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/dev/mii/ciphyreg.h 170365 2007-06-06 06:55:49Z yongari $ | 32 * $FreeBSD: head/sys/dev/mii/ciphyreg.h 220938 2011-04-22 09:22:27Z marius $ |
| 33 */ 34 35#ifndef _DEV_MII_CIPHYREG_H_ 36#define _DEV_MII_CIPHYREG_H_ 37 38/* 39 * Register definitions for the Cicada CS8201 10/100/1000 gigE copper 40 * PHY, embedded within the VIA Networks VT6122 controller. --- 22 unchanged lines hidden (view full) --- 63#define CIPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */ 64#define CIPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */ 65#define CIPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */ 66#define CIPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */ 67#define CIPHY_BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */ 68#define CIPHY_BMSR_EXTSTS 0x0100 /* Extended status present */ 69#define CIPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */ 70#define CIPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */ | 33 */ 34 35#ifndef _DEV_MII_CIPHYREG_H_ 36#define _DEV_MII_CIPHYREG_H_ 37 38/* 39 * Register definitions for the Cicada CS8201 10/100/1000 gigE copper 40 * PHY, embedded within the VIA Networks VT6122 controller. --- 22 unchanged lines hidden (view full) --- 63#define CIPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */ 64#define CIPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */ 65#define CIPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */ 66#define CIPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */ 67#define CIPHY_BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */ 68#define CIPHY_BMSR_EXTSTS 0x0100 /* Extended status present */ 69#define CIPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */ 70#define CIPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */ |
| 71#define CIPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */ | 71#define CIPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occurred */ |
| 72#define CIPHY_BMSR_ANEG 0x0008 /* Autoneg capable */ 73#define CIPHY_BMSR_LINK 0x0004 /* Link status */ 74#define CIPHY_BMSR_JABBER 0x0002 /* Jabber detected */ 75#define CIPHY_BMSR_EXT 0x0001 /* Extended capability */ 76 77/* PHY ID registers */ 78#define CIPHY_MII_PHYIDR1 0x02 79#define CIPHY_MII_PHYIDR2 0x03 --- 85 unchanged lines hidden (view full) --- 165#define CIPHY_MII_1000STS1 0x0F 166#define CIPHY_1000STS1_1000XFDX 0x8000 /* 1000baseX FDX capable */ 167#define CIPHY_1000STS1_1000XHDX 0x4000 /* 1000baseX HDX capable */ 168#define CIPHY_1000STS1_1000TFDX 0x2000 /* 1000baseT FDX capable */ 169#define CIPHY_1000STS1_1000THDX 0x1000 /* 1000baseT HDX capable */ 170 171/* Vendor-specific PHY registers */ 172 | 72#define CIPHY_BMSR_ANEG 0x0008 /* Autoneg capable */ 73#define CIPHY_BMSR_LINK 0x0004 /* Link status */ 74#define CIPHY_BMSR_JABBER 0x0002 /* Jabber detected */ 75#define CIPHY_BMSR_EXT 0x0001 /* Extended capability */ 76 77/* PHY ID registers */ 78#define CIPHY_MII_PHYIDR1 0x02 79#define CIPHY_MII_PHYIDR2 0x03 --- 85 unchanged lines hidden (view full) --- 165#define CIPHY_MII_1000STS1 0x0F 166#define CIPHY_1000STS1_1000XFDX 0x8000 /* 1000baseX FDX capable */ 167#define CIPHY_1000STS1_1000XHDX 0x4000 /* 1000baseX HDX capable */ 168#define CIPHY_1000STS1_1000TFDX 0x2000 /* 1000baseT FDX capable */ 169#define CIPHY_1000STS1_1000THDX 0x1000 /* 1000baseT HDX capable */ 170 171/* Vendor-specific PHY registers */ 172 |
| 173/* 100baseTX status extention register */ | 173/* 100baseTX status extension register */ |
| 174#define CIPHY_MII_100STS 0x10 175#define CIPHY_100STS_DESLCK 0x8000 /* descrambler locked */ 176#define CIPHY_100STS_LKCERR 0x4000 /* lock error detected/lock lost */ 177#define CIPHY_100STS_DISC 0x2000 /* disconnect state */ 178#define CIPHY_100STS_LINK 0x1000 /* current link state */ 179#define CIPHY_100STS_RXERR 0x0800 /* receive error detected */ 180#define CIPHY_100STS_TXERR 0x0400 /* transmit error detected */ 181#define CIPHY_100STS_SSDERR 0x0200 /* false carrier error detected */ 182#define CIPHY_100STS_ESDERR 0x0100 /* premature end of stream error */ 183 | 174#define CIPHY_MII_100STS 0x10 175#define CIPHY_100STS_DESLCK 0x8000 /* descrambler locked */ 176#define CIPHY_100STS_LKCERR 0x4000 /* lock error detected/lock lost */ 177#define CIPHY_100STS_DISC 0x2000 /* disconnect state */ 178#define CIPHY_100STS_LINK 0x1000 /* current link state */ 179#define CIPHY_100STS_RXERR 0x0800 /* receive error detected */ 180#define CIPHY_100STS_TXERR 0x0400 /* transmit error detected */ 181#define CIPHY_100STS_SSDERR 0x0200 /* false carrier error detected */ 182#define CIPHY_100STS_ESDERR 0x0100 /* premature end of stream error */ 183 |
| 184/* 1000BT status extention register #2 */ | 184/* 1000BT status extension register #2 */ |
| 185#define CIPHY_MII_1000STS2 0x11 186#define CIPHY_1000STS2_DESLCK 0x8000 /* descrambler locked */ 187#define CIPHY_1000STS2_LKCERR 0x4000 /* lock error detected/lock lost */ 188#define CIPHY_1000STS2_DISC 0x2000 /* disconnect state */ 189#define CIPHY_1000STS2_LINK 0x1000 /* current link state */ 190#define CIPHY_1000STS2_RXERR 0x0800 /* receive error detected */ 191#define CIPHY_1000STS2_TXERR 0x0400 /* transmit error detected */ 192#define CIPHY_1000STS2_SSDERR 0x0200 /* false carrier error detected */ 193#define CIPHY_1000STS2_ESDERR 0x0100 /* premature end of stream error */ | 185#define CIPHY_MII_1000STS2 0x11 186#define CIPHY_1000STS2_DESLCK 0x8000 /* descrambler locked */ 187#define CIPHY_1000STS2_LKCERR 0x4000 /* lock error detected/lock lost */ 188#define CIPHY_1000STS2_DISC 0x2000 /* disconnect state */ 189#define CIPHY_1000STS2_LINK 0x1000 /* current link state */ 190#define CIPHY_1000STS2_RXERR 0x0800 /* receive error detected */ 191#define CIPHY_1000STS2_TXERR 0x0400 /* transmit error detected */ 192#define CIPHY_1000STS2_SSDERR 0x0200 /* false carrier error detected */ 193#define CIPHY_1000STS2_ESDERR 0x0100 /* premature end of stream error */ |
| 194#define CIPHY_1000STS2_CARREXT 0x0080 /* carrier extention err detected */ | 194#define CIPHY_1000STS2_CARREXT 0x0080 /* carrier extension err detected */ |
| 195#define CIPHY_1000STS2_BCM5400 0x0040 /* non-complient BCM5400 detected */ 196 197/* Bypass control register */ 198#define CIPHY_MII_BYPASS 0x12 199#define CIPHY_BYPASS_TX 0x8000 /* transmit disable */ 200#define CIPHY_BYPASS_4B5B 0x4000 /* bypass the 4B5B encoder */ 201#define CIPHY_BYPASS_SCRAM 0x2000 /* bypass scrambler */ 202#define CIPHY_BYPASS_DSCAM 0x1000 /* bypass descrambler */ --- 124 unchanged lines hidden (view full) --- 327#define CIPHY_LED_FDXFORCE 0x0200 /* Force on duplex LED */ 328#define CIPHY_LED_FDXDIS 0x0100 /* Disable duplex LED */ 329#define CIPHY_LED_ACTFORCE 0x0080 /* Force on activity LED */ 330#define CIPHY_LED_ACTDIS 0x0040 /* Disable activity LED */ 331#define CIPHY_LED_PULSE 0x0008 /* LED pulse enable */ 332#define CIPHY_LED_LINKACTBLINK 0x0004 /* enable link/activity LED blink */ 333#define CIPHY_LED_BLINKRATE 0x0002 /* blink rate 0=10hz, 1=5hz */ 334 | 195#define CIPHY_1000STS2_BCM5400 0x0040 /* non-complient BCM5400 detected */ 196 197/* Bypass control register */ 198#define CIPHY_MII_BYPASS 0x12 199#define CIPHY_BYPASS_TX 0x8000 /* transmit disable */ 200#define CIPHY_BYPASS_4B5B 0x4000 /* bypass the 4B5B encoder */ 201#define CIPHY_BYPASS_SCRAM 0x2000 /* bypass scrambler */ 202#define CIPHY_BYPASS_DSCAM 0x1000 /* bypass descrambler */ --- 124 unchanged lines hidden (view full) --- 327#define CIPHY_LED_FDXFORCE 0x0200 /* Force on duplex LED */ 328#define CIPHY_LED_FDXDIS 0x0100 /* Disable duplex LED */ 329#define CIPHY_LED_ACTFORCE 0x0080 /* Force on activity LED */ 330#define CIPHY_LED_ACTDIS 0x0040 /* Disable activity LED */ 331#define CIPHY_LED_PULSE 0x0008 /* LED pulse enable */ 332#define CIPHY_LED_LINKACTBLINK 0x0004 /* enable link/activity LED blink */ 333#define CIPHY_LED_BLINKRATE 0x0002 /* blink rate 0=10hz, 1=5hz */ 334 |
| 335/* Auxilliary control and status register */ | 335/* Auxiliary control and status register */ |
| 336#define CIPHY_MII_AUXCSR 0x1C 337#define CIPHY_AUXCSR_ANEGDONE 0x8000 /* Autoneg complete */ 338#define CIPHY_AUXCSR_ANEGOFF 0x4000 /* Autoneg disabled */ 339#define CIPHY_AUXCSR_XOVER 0x2000 /* MDI/MDI-X crossover indication */ 340#define CIPHY_AUXCSR_PAIRSWAP 0x1000 /* pair swap indication */ 341#define CIPHY_AUXCSR_APOLARITY 0x0800 /* polarity inversion pair A */ 342#define CIPHY_AUXCSR_BPOLARITY 0x0400 /* polarity inversion pair B */ 343#define CIPHY_AUXCSR_CPOLARITY 0x0200 /* polarity inversion pair C */ --- 18 unchanged lines hidden --- | 336#define CIPHY_MII_AUXCSR 0x1C 337#define CIPHY_AUXCSR_ANEGDONE 0x8000 /* Autoneg complete */ 338#define CIPHY_AUXCSR_ANEGOFF 0x4000 /* Autoneg disabled */ 339#define CIPHY_AUXCSR_XOVER 0x2000 /* MDI/MDI-X crossover indication */ 340#define CIPHY_AUXCSR_PAIRSWAP 0x1000 /* pair swap indication */ 341#define CIPHY_AUXCSR_APOLARITY 0x0800 /* polarity inversion pair A */ 342#define CIPHY_AUXCSR_BPOLARITY 0x0400 /* polarity inversion pair B */ 343#define CIPHY_AUXCSR_CPOLARITY 0x0200 /* polarity inversion pair C */ --- 18 unchanged lines hidden --- |