| brgphyreg.h (212306) | brgphyreg.h (212307) |
|---|---|
| 1/*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/dev/mii/brgphyreg.h 212306 2010-09-07 22:44:29Z yongari $ | 32 * $FreeBSD: head/sys/dev/mii/brgphyreg.h 212307 2010-09-07 23:08:38Z yongari $ |
| 33 */ 34 35#ifndef _DEV_MII_BRGPHYREG_H_ 36#define _DEV_MII_BRGPHYREG_H_ 37 38/* 39 * Broadcom BCM5400 registers 40 */ 41 | 33 */ 34 35#ifndef _DEV_MII_BRGPHYREG_H_ 36#define _DEV_MII_BRGPHYREG_H_ 37 38/* 39 * Broadcom BCM5400 registers 40 */ 41 |
| 42#define BRGPHY_MII_BMCR 0x00 43#define BRGPHY_BMCR_RESET 0x8000 44#define BRGPHY_BMCR_LOOP 0x4000 45#define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */ 46#define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */ 47#define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */ 48#define BRGPHY_BMCR_ISO 0x0400 /* Isolate */ | 42#define BRGPHY_MII_BMCR 0x00 43#define BRGPHY_BMCR_RESET 0x8000 44#define BRGPHY_BMCR_LOOP 0x4000 45#define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */ 46#define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */ 47#define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */ 48#define BRGPHY_BMCR_ISO 0x0400 /* Isolate */ |
| 49#define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */ | 49#define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */ |
| 50#define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */ 51#define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */ 52#define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */ | 50#define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */ 51#define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */ 52#define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */ |
| 53 | 53 |
| 54#define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */ 55#define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */ 56#define BRGPHY_S10 0 /* 10mbps */ | 54#define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */ 55#define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */ 56#define BRGPHY_S10 0 /* 10mbps */ |
| 57 58#define BRGPHY_MII_BMSR 0x01 59#define BRGPHY_BMSR_EXTSTS 0x0100 /* Extended status present */ 60#define BRGPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */ 61#define BRGPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */ 62#define BRGPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */ 63#define BRGPHY_BMSR_ANEG 0x0008 /* Autoneg capable */ 64#define BRGPHY_BMSR_LINK 0x0004 /* Link status */ --- 197 unchanged lines hidden (view full) --- 262#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */ 263#define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */ 264 265/*******************************************************/ 266/* Begin: Shared SerDes PHY register definitions */ 267/*******************************************************/ 268 269/* SerDes autoneg is different from copper */ | 57 58#define BRGPHY_MII_BMSR 0x01 59#define BRGPHY_BMSR_EXTSTS 0x0100 /* Extended status present */ 60#define BRGPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */ 61#define BRGPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */ 62#define BRGPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */ 63#define BRGPHY_BMSR_ANEG 0x0008 /* Autoneg capable */ 64#define BRGPHY_BMSR_LINK 0x0004 /* Link status */ --- 197 unchanged lines hidden (view full) --- 262#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */ 263#define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */ 264 265/*******************************************************/ 266/* Begin: Shared SerDes PHY register definitions */ 267/*******************************************************/ 268 269/* SerDes autoneg is different from copper */ |
| 270#define BRGPHY_SERDES_ANAR 0x04 271#define BRGPHY_SERDES_ANAR_FDX 0x0020 272#define BRGPHY_SERDES_ANAR_HDX 0x0040 273#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7) 274#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7) 275#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7) 276#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7) | 270#define BRGPHY_SERDES_ANAR 0x04 271#define BRGPHY_SERDES_ANAR_FDX 0x0020 272#define BRGPHY_SERDES_ANAR_HDX 0x0040 273#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7) 274#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7) 275#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7) 276#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7) |
| 277 | 277 |
| 278#define BRGPHY_SERDES_ANLPAR 0x05 279#define BRGPHY_SERDES_ANLPAR_FDX 0x0020 280#define BRGPHY_SERDES_ANLPAR_HDX 0x0040 281#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7) 282#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7) 283#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7) 284#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7) | 278#define BRGPHY_SERDES_ANLPAR 0x05 279#define BRGPHY_SERDES_ANLPAR_FDX 0x0020 280#define BRGPHY_SERDES_ANLPAR_HDX 0x0040 281#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7) 282#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7) 283#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7) 284#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7) |
| 285 286/*******************************************************/ 287/* End: Shared SerDes PHY register definitions */ 288/*******************************************************/ 289 290/*******************************************************/ 291/* Begin: PHY register values for the 5706 PHY */ 292/*******************************************************/ 293 294/* 295 * Shadow register 0x1C, bit 15 is write enable, 296 * bits 14-10 select function (0x00 to 0x1F). 297 */ | 285 286/*******************************************************/ 287/* End: Shared SerDes PHY register definitions */ 288/*******************************************************/ 289 290/*******************************************************/ 291/* Begin: PHY register values for the 5706 PHY */ 292/*******************************************************/ 293 294/* 295 * Shadow register 0x1C, bit 15 is write enable, 296 * bits 14-10 select function (0x00 to 0x1F). 297 */ |
| 298#define BRGPHY_MII_SHADOW_1C 0x1C 299#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000 300#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00 | 298#define BRGPHY_MII_SHADOW_1C 0x1C 299#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000 300#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00 |
| 301 302/* Shadow 0x1C Mode Control Register (select value 0x1F) */ | 301 302/* Shadow 0x1C Mode Control Register (select value 0x1F) */ |
| 303#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10) | 303#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10) |
| 304/* When set, Regs 0-0x0F are 1000X, else 1000T */ | 304/* When set, Regs 0-0x0F are 1000X, else 1000T */ |
| 305#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001 | 305#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001 |
| 306 | 306 |
| 307#define BRGPHY_MII_TEST1 0x1E 308#define BRGPHY_TEST1_TRIM_EN 0x0010 309#define BRGPHY_TEST1_CRC_EN 0x8000 | 307#define BRGPHY_MII_TEST1 0x1E 308#define BRGPHY_TEST1_TRIM_EN 0x0010 309#define BRGPHY_TEST1_CRC_EN 0x8000 |
| 310 | 310 |
| 311#define BRGPHY_MII_TEST2 0x1F | 311#define BRGPHY_MII_TEST2 0x1F |
| 312 313/*******************************************************/ 314/* End: PHY register values for the 5706 PHY */ 315/*******************************************************/ 316 317/*******************************************************/ 318/* Begin: PHY register values for the 5708S SerDes PHY */ 319/*******************************************************/ 320 321/* Autoneg Next Page Transmit 1 Regiser */ | 312 313/*******************************************************/ 314/* End: PHY register values for the 5706 PHY */ 315/*******************************************************/ 316 317/*******************************************************/ 318/* Begin: PHY register values for the 5708S SerDes PHY */ 319/*******************************************************/ 320 321/* Autoneg Next Page Transmit 1 Regiser */ |
| 322#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B 323#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001 | 322#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B 323#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001 |
| 324 325/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */ | 324 325/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */ |
| 326#define BRGPHY_5708S_BLOCK_ADDR 0x1f 327#define BRGPHY_5708S_DIG_PG0 0x0000 328#define BRGPHY_5708S_DIG3_PG2 0x0002 329#define BRGPHY_5708S_TX_MISC_PG5 0x0005 | 326#define BRGPHY_5708S_BLOCK_ADDR 0x1f 327#define BRGPHY_5708S_DIG_PG0 0x0000 328#define BRGPHY_5708S_DIG3_PG2 0x0002 329#define BRGPHY_5708S_TX_MISC_PG5 0x0005 |
| 330 331/* 5708S SerDes "Digital" Registers (page 0) */ | 330 331/* 5708S SerDes "Digital" Registers (page 0) */ |
| 332#define BRGPHY_5708S_PG0_1000X_CTL1 0x10 333#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010 334#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001 | 332#define BRGPHY_5708S_PG0_1000X_CTL1 0x10 333#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010 334#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001 |
| 335 | 335 |
| 336#define BRGPHY_5708S_PG0_1000X_STAT1 0x14 337#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002 338#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004 339#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018 340#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3) 341#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3) 342#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3) 343#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3) | 336#define BRGPHY_5708S_PG0_1000X_STAT1 0x14 337#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002 338#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004 339#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018 340#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3) 341#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3) 342#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3) 343#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3) |
| 344 345 | 344 345 |
| 346#define BRGPHY_5708S_PG0_1000X_CTL2 0x11 347#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001 | 346#define BRGPHY_5708S_PG0_1000X_CTL2 0x11 347#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001 |
| 348 349/* 5708S SerDes "Digital 3" Registers (page 2) */ | 348 349/* 5708S SerDes "Digital 3" Registers (page 2) */ |
| 350#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10 351#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001 | 350#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10 351#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001 |
| 352 353/* 5708S SerDes "TX Misc" Registers (page 5) */ | 352 353/* 5708S SerDes "TX Misc" Registers (page 5) */ |
| 354#define BRGPHY_5708S_PG5_2500STATUS1 0x10 355#define BRGPHY_5708S_PG5_TXACTL1 0x15 356#define BRGPHY_5708S_PG5_TXACTL3 0x17 | 354#define BRGPHY_5708S_PG5_2500STATUS1 0x10 355#define BRGPHY_5708S_PG5_TXACTL1 0x15 356#define BRGPHY_5708S_PG5_TXACTL3 0x17 |
| 357 358/*******************************************************/ 359/* End: PHY register values for the 5708S SerDes PHY */ 360/*******************************************************/ 361 362/*******************************************************/ 363/* Begin: PHY register values for the 5709S SerDes PHY */ 364/*******************************************************/ 365 366/* 5709S SerDes "General Purpose Status" Registers */ | 357 358/*******************************************************/ 359/* End: PHY register values for the 5708S SerDes PHY */ 360/*******************************************************/ 361 362/*******************************************************/ 363/* Begin: PHY register values for the 5709S SerDes PHY */ 364/*******************************************************/ 365 366/* 5709S SerDes "General Purpose Status" Registers */ |
| 367#define BRGPHY_BLOCK_ADDR_GP_STATUS 0x8120 368#define BRGPHY_GP_STATUS_TOP_ANEG_STATUS 0x1B 369#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK 0x3F00 370#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10 0x0000 371#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100 0x0100 372#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G 0x0200 373#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G 0x0300 374#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1GKX 0x0D00 375#define BRGPHY_GP_STATUS_TOP_ANEG_FDX 0x0008 376#define BRGPHY_GP_STATUS_TOP_ANEG_LINK_UP 0x0004 377#define BRGPHY_GP_STATUS_TOP_ANEG_CL73_COMP 0x0001 | 367#define BRGPHY_BLOCK_ADDR_GP_STATUS 0x8120 368#define BRGPHY_GP_STATUS_TOP_ANEG_STATUS 0x1B 369#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK 0x3F00 370#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10 0x0000 371#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100 0x0100 372#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G 0x0200 373#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G 0x0300 374#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1GKX 0x0D00 375#define BRGPHY_GP_STATUS_TOP_ANEG_FDX 0x0008 376#define BRGPHY_GP_STATUS_TOP_ANEG_LINK_UP 0x0004 377#define BRGPHY_GP_STATUS_TOP_ANEG_CL73_COMP 0x0001 |
| 378 379/* 5709S SerDes "SerDes Digital" Registers */ | 378 379/* 5709S SerDes "SerDes Digital" Registers */ |
| 380#define BRGPHY_BLOCK_ADDR_SERDES_DIG 0x8300 381#define BRGPHY_SERDES_DIG_1000X_CTL1 0x0010 382#define BRGPHY_SD_DIG_1000X_CTL1_AUTODET 0x0010 383#define BRGPHY_SD_DIG_1000X_CTL1_FIBER 0x0001 | 380#define BRGPHY_BLOCK_ADDR_SERDES_DIG 0x8300 381#define BRGPHY_SERDES_DIG_1000X_CTL1 0x0010 382#define BRGPHY_SD_DIG_1000X_CTL1_AUTODET 0x0010 383#define BRGPHY_SD_DIG_1000X_CTL1_FIBER 0x0001 |
| 384 385/* 5709S SerDes "Over 1G" Registers */ | 384 385/* 5709S SerDes "Over 1G" Registers */ |
| 386#define BRGPHY_BLOCK_ADDR_OVER_1G 0x8320 387#define BRGPHY_OVER_1G_UNFORMAT_PG1 0x19 | 386#define BRGPHY_BLOCK_ADDR_OVER_1G 0x8320 387#define BRGPHY_OVER_1G_UNFORMAT_PG1 0x19 |
| 388 389/* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */ | 388 389/* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */ |
| 390#define BRGPHY_BLOCK_ADDR_MRBE 0x8350 391#define BRGPHY_MRBE_MSG_PG5_NP 0x10 392#define BRGPHY_MRBE_MSG_PG5_NP_MBRE 0x0001 393#define BRGPHY_MRBE_MSG_PG5_NP_T2 0x0001 | 390#define BRGPHY_BLOCK_ADDR_MRBE 0x8350 391#define BRGPHY_MRBE_MSG_PG5_NP 0x10 392#define BRGPHY_MRBE_MSG_PG5_NP_MBRE 0x0001 393#define BRGPHY_MRBE_MSG_PG5_NP_T2 0x0001 |
| 394 395/* 5709S SerDes "IEEE Clause 73 User B0" Registers */ | 394 395/* 5709S SerDes "IEEE Clause 73 User B0" Registers */ |
| 396#define BRGPHY_BLOCK_ADDR_CL73_USER_B0 0x8370 397#define BRGPHY_CL73_USER_B0_MBRE_CTL1 0x12 | 396#define BRGPHY_BLOCK_ADDR_CL73_USER_B0 0x8370 397#define BRGPHY_CL73_USER_B0_MBRE_CTL1 0x12 |
| 398#define BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP 0x2000 399#define BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR 0x4000 | 398#define BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP 0x2000 399#define BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR 0x4000 |
| 400#define BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG 0x8000 | 400#define BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG 0x8000 |
| 401 402/* 5709S SerDes "IEEE Clause 73 User B0" Registers */ | 401 402/* 5709S SerDes "IEEE Clause 73 User B0" Registers */ |
| 403#define BRGPHY_BLOCK_ADDR_ADDR_EXT 0xFFD0 | 403#define BRGPHY_BLOCK_ADDR_ADDR_EXT 0xFFD0 |
| 404 405/* 5709S SerDes "Combo IEEE 0" Registers */ | 404 405/* 5709S SerDes "Combo IEEE 0" Registers */ |
| 406#define BRGPHY_BLOCK_ADDR_COMBO_IEEE0 0xFFE0 | 406#define BRGPHY_BLOCK_ADDR_COMBO_IEEE0 0xFFE0 |
| 407 | 407 |
| 408#define BRGPHY_ADDR_EXT 0x1E 409#define BRGPHY_BLOCK_ADDR 0x1F | 408#define BRGPHY_ADDR_EXT 0x1E 409#define BRGPHY_BLOCK_ADDR 0x1F |
| 410 | 410 |
| 411#define BRGPHY_ADDR_EXT_AN_MMD 0x3800 | 411#define BRGPHY_ADDR_EXT_AN_MMD 0x3800 |
| 412 413/*******************************************************/ 414/* End: PHY register values for the 5709S SerDes PHY */ 415/*******************************************************/ 416 417#define BRGPHY_INTRS \ 418 ~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG) 419 420#endif /* _DEV_BRGPHY_MIIREG_H_ */ | 412 413/*******************************************************/ 414/* End: PHY register values for the 5709S SerDes PHY */ 415/*******************************************************/ 416 417#define BRGPHY_INTRS \ 418 ~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG) 419 420#endif /* _DEV_BRGPHY_MIIREG_H_ */ |