| brgphy.c (207391) | brgphy.c (212307) |
|---|---|
| 1/*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> |
| 34__FBSDID("$FreeBSD: head/sys/dev/mii/brgphy.c 207391 2010-04-29 22:00:57Z davidch $"); | 34__FBSDID("$FreeBSD: head/sys/dev/mii/brgphy.c 212307 2010-09-07 23:08:38Z yongari $"); |
| 35 36/* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> --- 92 unchanged lines hidden (view full) --- 135 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755), 136 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787), 137 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S), 138 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX), 139 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722), 140 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784), 141 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C), 142 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761), | 35 36/* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> --- 92 unchanged lines hidden (view full) --- 135 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755), 136 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787), 137 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S), 138 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX), 139 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722), 140 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784), 141 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C), 142 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761), |
| 143 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S), | 143 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S), |
| 144 MII_PHY_DESC(BROADCOM2, BCM5906), 145 MII_PHY_END 146}; 147 148#define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21" 149#define HS21_BCM_CHIPID 0x57081021 150 151static int --- 85 unchanged lines hidden (view full) --- 237 break; 238 } break; 239 case MII_OUI_xxBROADCOM_ALT1: 240 switch (bsc->mii_model) { 241 case MII_MODEL_xxBROADCOM_ALT1_BCM5708S: 242 bsc->serdes_flags |= BRGPHY_5708S; 243 sc->mii_flags |= MIIF_HAVEFIBER; 244 break; | 144 MII_PHY_DESC(BROADCOM2, BCM5906), 145 MII_PHY_END 146}; 147 148#define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21" 149#define HS21_BCM_CHIPID 0x57081021 150 151static int --- 85 unchanged lines hidden (view full) --- 237 break; 238 } break; 239 case MII_OUI_xxBROADCOM_ALT1: 240 switch (bsc->mii_model) { 241 case MII_MODEL_xxBROADCOM_ALT1_BCM5708S: 242 bsc->serdes_flags |= BRGPHY_5708S; 243 sc->mii_flags |= MIIF_HAVEFIBER; 244 break; |
| 245 case MII_MODEL_xxBROADCOM_ALT1_BCM5709S: 246 bsc->serdes_flags |= BRGPHY_5709S; 247 sc->mii_flags |= MIIF_HAVEFIBER; 248 break; 249 } break; | 245 case MII_MODEL_xxBROADCOM_ALT1_BCM5709S: 246 bsc->serdes_flags |= BRGPHY_5709S; 247 sc->mii_flags |= MIIF_HAVEFIBER; 248 break; 249 } 250 break; |
| 250 default: 251 device_printf(dev, "Unrecognized OUI for PHY!\n"); 252 } 253 254 ifp = sc->mii_pdata->mii_ifp; 255 256 /* Find the MAC driver associated with this PHY. */ 257 if (strcmp(ifp->if_dname, "bge") == 0) { --- 374 unchanged lines hidden (view full) --- 632 else 633 mii->mii_media_active |= IFM_HDX; 634 } 635 636 } else if (bsc->serdes_flags & BRGPHY_5708S) { 637 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 638 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 639 | 251 default: 252 device_printf(dev, "Unrecognized OUI for PHY!\n"); 253 } 254 255 ifp = sc->mii_pdata->mii_ifp; 256 257 /* Find the MAC driver associated with this PHY. */ 258 if (strcmp(ifp->if_dname, "bge") == 0) { --- 374 unchanged lines hidden (view full) --- 633 else 634 mii->mii_media_active |= IFM_HDX; 635 } 636 637 } else if (bsc->serdes_flags & BRGPHY_5708S) { 638 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 639 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 640 |
| 640 /* Check for MRBE auto-negotiated speed results. */ | 641 /* Check for MRBE auto-negotiated speed results. */ |
| 641 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 642 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 643 mii->mii_media_active |= IFM_10_FL; break; 644 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 645 mii->mii_media_active |= IFM_100_FX; break; 646 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 647 mii->mii_media_active |= IFM_1000_SX; break; 648 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 649 mii->mii_media_active |= IFM_2500_SX; break; 650 } 651 | 642 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 643 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 644 mii->mii_media_active |= IFM_10_FL; break; 645 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 646 mii->mii_media_active |= IFM_100_FX; break; 647 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 648 mii->mii_media_active |= IFM_1000_SX; break; 649 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 650 mii->mii_media_active |= IFM_2500_SX; break; 651 } 652 |
| 652 /* Check for MRBE auto-negotiated duplex results. */ | 653 /* Check for MRBE auto-negotiated duplex results. */ |
| 653 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 654 mii->mii_media_active |= IFM_FDX; 655 else 656 mii->mii_media_active |= IFM_HDX; 657 | 654 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 655 mii->mii_media_active |= IFM_FDX; 656 else 657 mii->mii_media_active |= IFM_HDX; 658 |
| 658 } else if (bsc->serdes_flags & BRGPHY_5709S) { | 659 } else if (bsc->serdes_flags & BRGPHY_5709S) { |
| 659 | 660 |
| 660 /* Select GP Status Block of the AN MMD, get autoneg results. */ 661 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); | 661 /* Select GP Status Block of the AN MMD, get autoneg results. */ 662 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); |
| 662 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 663 | 663 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 664 |
| 664 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 665 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); | 665 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 666 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); |
| 666 | 667 |
| 667 /* Check for MRBE auto-negotiated speed results. */ 668 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 669 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 670 mii->mii_media_active |= IFM_10_FL; break; 671 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 672 mii->mii_media_active |= IFM_100_FX; break; 673 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 674 mii->mii_media_active |= IFM_1000_SX; break; 675 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 676 mii->mii_media_active |= IFM_2500_SX; break; | 668 /* Check for MRBE auto-negotiated speed results. */ 669 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 670 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 671 mii->mii_media_active |= IFM_10_FL; break; 672 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 673 mii->mii_media_active |= IFM_100_FX; break; 674 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 675 mii->mii_media_active |= IFM_1000_SX; break; 676 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 677 mii->mii_media_active |= IFM_2500_SX; break; |
| 677 } 678 | 678 } 679 |
| 679 /* Check for MRBE auto-negotiated duplex results. */ | 680 /* Check for MRBE auto-negotiated duplex results. */ |
| 680 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 681 mii->mii_media_active |= IFM_FDX; 682 else 683 mii->mii_media_active |= IFM_HDX; | 681 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 682 mii->mii_media_active |= IFM_FDX; 683 else 684 mii->mii_media_active |= IFM_HDX; |
| 684 } | 685 } |
| 685 686 } 687 688 /* Todo: Change bge to use these settings. */ 689 690 /* Fetch flow control settings from the copper PHY. */ 691 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 692 /* Set FLAG0 if RX is enabled and FLAG1 if TX is enabled */ --- 429 unchanged lines hidden (view full) --- 1122 bce_sc->bce_port_hw_cfg & 1123 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1124 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1125 BRGPHY_5708S_DIG_PG0); 1126 } 1127 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1128 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1129 | 686 687 } 688 689 /* Todo: Change bge to use these settings. */ 690 691 /* Fetch flow control settings from the copper PHY. */ 692 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 693 /* Set FLAG0 if RX is enabled and FLAG1 if TX is enabled */ --- 429 unchanged lines hidden (view full) --- 1123 bce_sc->bce_port_hw_cfg & 1124 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1125 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1126 BRGPHY_5708S_DIG_PG0); 1127 } 1128 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1129 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1130 |
| 1130 /* Select the SerDes Digital block of the AN MMD. */ 1131 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); | 1131 /* Select the SerDes Digital block of the AN MMD. */ 1132 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); |
| 1132 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1133 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1134 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1135 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1136 | 1133 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1134 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1135 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1136 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1137 |
| 1137 /* Select the Over 1G block of the AN MMD. */ | 1138 /* Select the Over 1G block of the AN MMD. */ |
| 1138 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1139 | 1139 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1140 |
| 1140 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1141 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); | 1141 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1142 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); |
| 1142 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1143 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1144 else 1145 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1146 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1147 | 1143 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1144 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1145 else 1146 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1147 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1148 |
| 1148 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ | 1149 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ |
| 1149 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1150 | 1150 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1151 |
| 1151 /* Enable MRBE speed autoneg. */ 1152 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); | 1152 /* Enable MRBE speed autoneg. */ 1153 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); |
| 1153 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1154 BRGPHY_MRBE_MSG_PG5_NP_T2; 1155 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1156 | 1154 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1155 BRGPHY_MRBE_MSG_PG5_NP_T2; 1156 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1157 |
| 1157 /* Select the Clause 73 User B0 block of the AN MMD. */ 1158 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); | 1158 /* Select the Clause 73 User B0 block of the AN MMD. */ 1159 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); |
| 1159 | 1160 |
| 1160 /* Enable MRBE speed autoneg. */ | 1161 /* Enable MRBE speed autoneg. */ |
| 1161 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1162 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1163 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1164 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1165 | 1162 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1163 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1164 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1165 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1166 |
| 1166 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1167 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); | 1167 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1168 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); |
| 1168 1169 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1170 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1171 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1172 brgphy_fixup_disable_early_dac(sc); | 1169 1170 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1171 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1172 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1173 brgphy_fixup_disable_early_dac(sc); |
| 1173 | 1174 |
| 1174 brgphy_jumbo_settings(sc, ifp->if_mtu); 1175 brgphy_ethernet_wirespeed(sc); 1176 } else { 1177 brgphy_fixup_ber_bug(sc); 1178 brgphy_jumbo_settings(sc, ifp->if_mtu); 1179 brgphy_ethernet_wirespeed(sc); 1180 } 1181 1182 } 1183} 1184 | 1175 brgphy_jumbo_settings(sc, ifp->if_mtu); 1176 brgphy_ethernet_wirespeed(sc); 1177 } else { 1178 brgphy_fixup_ber_bug(sc); 1179 brgphy_jumbo_settings(sc, ifp->if_mtu); 1180 brgphy_ethernet_wirespeed(sc); 1181 } 1182 1183 } 1184} 1185 |