135 MII_PHY_DESC(BROADCOM2, BCM5482),
136 MII_PHY_DESC(BROADCOM2, BCM5708S),
137 MII_PHY_DESC(BROADCOM2, BCM5709C),
138 MII_PHY_DESC(BROADCOM2, BCM5709S),
139 MII_PHY_DESC(BROADCOM2, BCM5709CAX),
140 MII_PHY_DESC(BROADCOM2, BCM5722),
141 MII_PHY_DESC(BROADCOM2, BCM5755),
142 MII_PHY_DESC(BROADCOM2, BCM5754),
143 MII_PHY_DESC(BROADCOM2, BCM5761),
144 MII_PHY_DESC(BROADCOM2, BCM5784),
145#ifdef notyet /* better handled by ukphy(4) until WARs are implemented */
146 MII_PHY_DESC(BROADCOM2, BCM5785),
147#endif
148 MII_PHY_DESC(BROADCOM3, BCM5717C),
149 MII_PHY_DESC(BROADCOM3, BCM5719C),
150 MII_PHY_DESC(BROADCOM3, BCM5720C),
151 MII_PHY_DESC(BROADCOM3, BCM57765),
152 MII_PHY_DESC(BROADCOM3, BCM57780),
153 MII_PHY_DESC(BROADCOM4, BCM5725C),
154 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
155 MII_PHY_END
156};
157
158static const struct mii_phy_funcs brgphy_funcs = {
159 brgphy_service,
160 brgphy_status,
161 brgphy_reset
162};
163
164static const struct hs21_type {
165 const uint32_t id;
166 const char *prod;
167} hs21_type_lists[] = {
168 { 0x57081021, "IBM eServer BladeCenter HS21" },
169 { 0x57081011, "IBM eServer BladeCenter HS21 -[8853PAU]-" },
170};
171
172static int
173detect_hs21(struct bce_softc *bce_sc)
174{
175 char *sysenv;
176 int found, i;
177
178 found = 0;
179 sysenv = kern_getenv("smbios.system.product");
180 if (sysenv == NULL)
181 return (found);
182 for (i = 0; i < nitems(hs21_type_lists); i++) {
183 if (bce_sc->bce_chipid == hs21_type_lists[i].id &&
184 strncmp(sysenv, hs21_type_lists[i].prod,
185 strlen(hs21_type_lists[i].prod)) == 0) {
186 found++;
187 break;
188 }
189 }
190 freeenv(sysenv);
191 return (found);
192}
193
194/* Search for our PHY in the list of known PHYs */
195static int
196brgphy_probe(device_t dev)
197{
198
199 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
200}
201
202/* Attach the PHY to the MII bus */
203static int
204brgphy_attach(device_t dev)
205{
206 struct brgphy_softc *bsc;
207 struct bge_softc *bge_sc = NULL;
208 struct bce_softc *bce_sc = NULL;
209 struct mii_softc *sc;
210
211 bsc = device_get_softc(dev);
212 sc = &bsc->mii_sc;
213
214 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
215 &brgphy_funcs, 0);
216
217 bsc->serdes_flags = 0;
218
219 /* Find the MAC driver associated with this PHY. */
220 if (mii_dev_mac_match(dev, "bge"))
221 bge_sc = mii_dev_mac_softc(dev);
222 else if (mii_dev_mac_match(dev, "bce"))
223 bce_sc = mii_dev_mac_softc(dev);
224
225 /* Handle any special cases based on the PHY ID */
226 switch (sc->mii_mpd_oui) {
227 case MII_OUI_BROADCOM:
228 switch (sc->mii_mpd_model) {
229 case MII_MODEL_BROADCOM_BCM5706:
230 case MII_MODEL_BROADCOM_BCM5714:
231 /*
232 * The 5464 PHY used in the 5706 supports both copper
233 * and fiber interfaces over GMII. Need to check the
234 * shadow registers to see which mode is actually
235 * in effect, and therefore whether we have 5706C or
236 * 5706S.
237 */
238 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
239 BRGPHY_SHADOW_1C_MODE_CTRL);
240 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
241 BRGPHY_SHADOW_1C_ENA_1000X) {
242 bsc->serdes_flags |= BRGPHY_5706S;
243 sc->mii_flags |= MIIF_HAVEFIBER;
244 }
245 break;
246 }
247 break;
248 case MII_OUI_BROADCOM2:
249 switch (sc->mii_mpd_model) {
250 case MII_MODEL_BROADCOM2_BCM5708S:
251 bsc->serdes_flags |= BRGPHY_5708S;
252 sc->mii_flags |= MIIF_HAVEFIBER;
253 break;
254 case MII_MODEL_BROADCOM2_BCM5709S:
255 /*
256 * XXX
257 * 5720S and 5709S shares the same PHY id.
258 * Assume 5720S PHY if parent device is bge(4).
259 */
260 if (bge_sc != NULL)
261 bsc->serdes_flags |= BRGPHY_5708S;
262 else
263 bsc->serdes_flags |= BRGPHY_5709S;
264 sc->mii_flags |= MIIF_HAVEFIBER;
265 break;
266 }
267 break;
268 }
269
270 PHY_RESET(sc);
271
272 /* Read the PHY's capabilities. */
273 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
274 if (sc->mii_capabilities & BMSR_EXTSTAT)
275 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
276 device_printf(dev, " ");
277
278 /* Add the supported media types */
279 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
280 mii_phy_add_media(sc);
281 printf("\n");
282 } else {
283 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
284 ifmedia_add(&sc->mii_pdata->mii_media,
285 IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
286 0, NULL);
287 printf("1000baseSX-FDX, ");
288 /*
289 * 2.5G support is a software enabled feature
290 * on the 5708S and 5709S.
291 */
292 if (bce_sc && (bce_sc->bce_phy_flags &
293 BCE_PHY_2_5G_CAPABLE_FLAG)) {
294 ifmedia_add(&sc->mii_pdata->mii_media,
295 IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX,
296 sc->mii_inst), 0, NULL);
297 printf("2500baseSX-FDX, ");
298 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
299 (detect_hs21(bce_sc) != 0)) {
300 /*
301 * There appears to be certain silicon revision
302 * in IBM HS21 blades that is having issues with
303 * this driver wating for the auto-negotiation to
304 * complete. This happens with a specific chip id
305 * only and when the 1000baseSX-FDX is the only
306 * mode. Workaround this issue since it's unlikely
307 * to be ever addressed.
308 */
309 printf("auto-neg workaround, ");
310 bsc->serdes_flags |= BRGPHY_NOANWAIT;
311 }
312 ifmedia_add(&sc->mii_pdata->mii_media, IFM_MAKEWORD(IFM_ETHER,
313 IFM_AUTO, 0, sc->mii_inst), 0, NULL);
314 printf("auto\n");
315 }
316
317 MIIBUS_MEDIAINIT(sc->mii_dev);
318 return (0);
319}
320
321static int
322brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
323{
324 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
325 int val;
326
327 switch (cmd) {
328 case MII_POLLSTAT:
329 break;
330 case MII_MEDIACHG:
331 /* Todo: Why is this here? Is it really needed? */
332 PHY_RESET(sc); /* XXX hardware bug work-around */
333
334 switch (IFM_SUBTYPE(ife->ifm_media)) {
335 case IFM_AUTO:
336 brgphy_mii_phy_auto(sc, ife->ifm_media);
337 break;
338 case IFM_2500_SX:
339 case IFM_1000_SX:
340 case IFM_1000_T:
341 case IFM_100_TX:
342 case IFM_10_T:
343 brgphy_setmedia(sc, ife->ifm_media);
344 break;
345 default:
346 return (EINVAL);
347 }
348 break;
349 case MII_TICK:
350 /* Bail if autoneg isn't in process. */
351 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
352 sc->mii_ticks = 0;
353 break;
354 }
355
356 /*
357 * Check to see if we have link. If we do, we don't
358 * need to restart the autonegotiation process.
359 */
360 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
361 if (val & BMSR_LINK) {
362 sc->mii_ticks = 0; /* Reset autoneg timer. */
363 break;
364 }
365
366 /* Announce link loss right after it happens. */
367 if (sc->mii_ticks++ == 0)
368 break;
369
370 /* Only retry autonegotiation every mii_anegticks seconds. */
371 if (sc->mii_ticks <= sc->mii_anegticks)
372 break;
373
374
375 /* Retry autonegotiation */
376 sc->mii_ticks = 0;
377 brgphy_mii_phy_auto(sc, ife->ifm_media);
378 break;
379 }
380
381 /* Update the media status. */
382 PHY_STATUS(sc);
383
384 /*
385 * Callback if something changed. Note that we need to poke
386 * the DSP on the Broadcom PHYs if the media changes.
387 */
388 if (sc->mii_media_active != mii->mii_media_active ||
389 sc->mii_media_status != mii->mii_media_status ||
390 cmd == MII_MEDIACHG) {
391 switch (sc->mii_mpd_oui) {
392 case MII_OUI_BROADCOM:
393 switch (sc->mii_mpd_model) {
394 case MII_MODEL_BROADCOM_BCM5400:
395 bcm5401_load_dspcode(sc);
396 break;
397 case MII_MODEL_BROADCOM_BCM5401:
398 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
399 bcm5401_load_dspcode(sc);
400 break;
401 case MII_MODEL_BROADCOM_BCM5411:
402 bcm5411_load_dspcode(sc);
403 break;
404 case MII_MODEL_BROADCOM_BCM54K2:
405 bcm54k2_load_dspcode(sc);
406 break;
407 }
408 break;
409 }
410 }
411 mii_phy_update(sc, cmd);
412 return (0);
413}
414
415/****************************************************************************/
416/* Sets the PHY link speed. */
417/* */
418/* Returns: */
419/* None */
420/****************************************************************************/
421static void
422brgphy_setmedia(struct mii_softc *sc, int media)
423{
424 int bmcr = 0, gig;
425
426 switch (IFM_SUBTYPE(media)) {
427 case IFM_2500_SX:
428 break;
429 case IFM_1000_SX:
430 case IFM_1000_T:
431 bmcr = BRGPHY_S1000;
432 break;
433 case IFM_100_TX:
434 bmcr = BRGPHY_S100;
435 break;
436 case IFM_10_T:
437 default:
438 bmcr = BRGPHY_S10;
439 break;
440 }
441
442 if ((media & IFM_FDX) != 0) {
443 bmcr |= BRGPHY_BMCR_FDX;
444 gig = BRGPHY_1000CTL_AFD;
445 } else {
446 gig = BRGPHY_1000CTL_AHD;
447 }
448
449 /* Force loopback to disconnect PHY from Ethernet medium. */
450 brgphy_enable_loopback(sc);
451
452 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
453 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
454
455 if (IFM_SUBTYPE(media) != IFM_1000_T &&
456 IFM_SUBTYPE(media) != IFM_1000_SX) {
457 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
458 return;
459 }
460
461 if (IFM_SUBTYPE(media) == IFM_1000_T) {
462 gig |= BRGPHY_1000CTL_MSE;
463 if ((media & IFM_ETH_MASTER) != 0)
464 gig |= BRGPHY_1000CTL_MSC;
465 }
466 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
467 PHY_WRITE(sc, BRGPHY_MII_BMCR,
468 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
469}
470
471/****************************************************************************/
472/* Set the media status based on the PHY settings. */
473/* */
474/* Returns: */
475/* None */
476/****************************************************************************/
477static void
478brgphy_status(struct mii_softc *sc)
479{
480 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
481 struct mii_data *mii = sc->mii_pdata;
482 int aux, bmcr, bmsr, val, xstat;
483 u_int flowstat;
484
485 mii->mii_media_status = IFM_AVALID;
486 mii->mii_media_active = IFM_ETHER;
487
488 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
489 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
490
491 if (bmcr & BRGPHY_BMCR_LOOP) {
492 mii->mii_media_active |= IFM_LOOP;
493 }
494
495 if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
496 (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
497 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
498 /* Erg, still trying, I guess... */
499 mii->mii_media_active |= IFM_NONE;
500 return;
501 }
502
503 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
504 /*
505 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS
506 * wedges at least the PHY of BCM5704 (but not others).
507 */
508 flowstat = mii_phy_flowstatus(sc);
509 xstat = PHY_READ(sc, BRGPHY_MII_1000STS);
510 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
511
512 /* If copper link is up, get the negotiated speed/duplex. */
513 if (aux & BRGPHY_AUXSTS_LINK) {
514 mii->mii_media_status |= IFM_ACTIVE;
515 switch (aux & BRGPHY_AUXSTS_AN_RES) {
516 case BRGPHY_RES_1000FD:
517 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break;
518 case BRGPHY_RES_1000HD:
519 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break;
520 case BRGPHY_RES_100FD:
521 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
522 case BRGPHY_RES_100T4:
523 mii->mii_media_active |= IFM_100_T4; break;
524 case BRGPHY_RES_100HD:
525 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break;
526 case BRGPHY_RES_10FD:
527 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
528 case BRGPHY_RES_10HD:
529 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
530 default:
531 mii->mii_media_active |= IFM_NONE; break;
532 }
533
534 if ((mii->mii_media_active & IFM_FDX) != 0)
535 mii->mii_media_active |= flowstat;
536
537 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T &&
538 (xstat & BRGPHY_1000STS_MSR) != 0)
539 mii->mii_media_active |= IFM_ETH_MASTER;
540 }
541 } else {
542 /* Todo: Add support for flow control. */
543 /* If serdes link is up, get the negotiated speed/duplex. */
544 if (bmsr & BRGPHY_BMSR_LINK) {
545 mii->mii_media_status |= IFM_ACTIVE;
546 }
547
548 /* Check the link speed/duplex based on the PHY type. */
549 if (bsc->serdes_flags & BRGPHY_5706S) {
550 mii->mii_media_active |= IFM_1000_SX;
551
552 /* If autoneg enabled, read negotiated duplex settings */
553 if (bmcr & BRGPHY_BMCR_AUTOEN) {
554 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
555 if (val & BRGPHY_SERDES_ANAR_FDX)
556 mii->mii_media_active |= IFM_FDX;
557 else
558 mii->mii_media_active |= IFM_HDX;
559 }
560 } else if (bsc->serdes_flags & BRGPHY_5708S) {
561 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
562 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
563
564 /* Check for MRBE auto-negotiated speed results. */
565 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
566 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
567 mii->mii_media_active |= IFM_10_FL; break;
568 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
569 mii->mii_media_active |= IFM_100_FX; break;
570 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
571 mii->mii_media_active |= IFM_1000_SX; break;
572 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
573 mii->mii_media_active |= IFM_2500_SX; break;
574 }
575
576 /* Check for MRBE auto-negotiated duplex results. */
577 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
578 mii->mii_media_active |= IFM_FDX;
579 else
580 mii->mii_media_active |= IFM_HDX;
581 } else if (bsc->serdes_flags & BRGPHY_5709S) {
582 /* Select GP Status Block of the AN MMD, get autoneg results. */
583 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
584 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
585
586 /* Restore IEEE0 block (assumed in all brgphy(4) code). */
587 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
588
589 /* Check for MRBE auto-negotiated speed results. */
590 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
591 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
592 mii->mii_media_active |= IFM_10_FL; break;
593 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
594 mii->mii_media_active |= IFM_100_FX; break;
595 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
596 mii->mii_media_active |= IFM_1000_SX; break;
597 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
598 mii->mii_media_active |= IFM_2500_SX; break;
599 }
600
601 /* Check for MRBE auto-negotiated duplex results. */
602 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
603 mii->mii_media_active |= IFM_FDX;
604 else
605 mii->mii_media_active |= IFM_HDX;
606 }
607 }
608}
609
610static void
611brgphy_mii_phy_auto(struct mii_softc *sc, int media)
612{
613 int anar, ktcr = 0;
614
615 PHY_RESET(sc);
616
617 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
618 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
619 if ((media & IFM_FLOW) != 0 ||
620 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
621 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP;
622 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar);
623 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
624 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)
625 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
626 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
627 PHY_READ(sc, BRGPHY_MII_1000CTL);
628 } else {
629 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX;
630 if ((media & IFM_FLOW) != 0 ||
631 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
632 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE;
633 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar);
634 }
635
636 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN |
637 BRGPHY_BMCR_STARTNEG);
638 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
639}
640
641/* Enable loopback to force the link down. */
642static void
643brgphy_enable_loopback(struct mii_softc *sc)
644{
645 int i;
646
647 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
648 for (i = 0; i < 15000; i++) {
649 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
650 break;
651 DELAY(10);
652 }
653}
654
655/* Turn off tap power management on 5401. */
656static void
657bcm5401_load_dspcode(struct mii_softc *sc)
658{
659 static const struct {
660 int reg;
661 uint16_t val;
662 } dspcode[] = {
663 { BRGPHY_MII_AUXCTL, 0x0c20 },
664 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
665 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
666 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
667 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
668 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
669 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
670 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
671 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
672 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
673 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
674 { 0, 0 },
675 };
676 int i;
677
678 for (i = 0; dspcode[i].reg != 0; i++)
679 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
680 DELAY(40);
681}
682
683static void
684bcm5411_load_dspcode(struct mii_softc *sc)
685{
686 static const struct {
687 int reg;
688 uint16_t val;
689 } dspcode[] = {
690 { 0x1c, 0x8c23 },
691 { 0x1c, 0x8ca3 },
692 { 0x1c, 0x8c23 },
693 { 0, 0 },
694 };
695 int i;
696
697 for (i = 0; dspcode[i].reg != 0; i++)
698 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
699}
700
701void
702bcm54k2_load_dspcode(struct mii_softc *sc)
703{
704 static const struct {
705 int reg;
706 uint16_t val;
707 } dspcode[] = {
708 { 4, 0x01e1 },
709 { 9, 0x0300 },
710 { 0, 0 },
711 };
712 int i;
713
714 for (i = 0; dspcode[i].reg != 0; i++)
715 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
716
717}
718
719static void
720brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
721{
722 static const struct {
723 int reg;
724 uint16_t val;
725 } dspcode[] = {
726 { 0x1c, 0x8d68 },
727 { 0x1c, 0x8d68 },
728 { 0, 0 },
729 };
730 int i;
731
732 for (i = 0; dspcode[i].reg != 0; i++)
733 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
734}
735
736static void
737brgphy_fixup_adc_bug(struct mii_softc *sc)
738{
739 static const struct {
740 int reg;
741 uint16_t val;
742 } dspcode[] = {
743 { BRGPHY_MII_AUXCTL, 0x0c00 },
744 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
745 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
746 { 0, 0 },
747 };
748 int i;
749
750 for (i = 0; dspcode[i].reg != 0; i++)
751 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
752}
753
754static void
755brgphy_fixup_adjust_trim(struct mii_softc *sc)
756{
757 static const struct {
758 int reg;
759 uint16_t val;
760 } dspcode[] = {
761 { BRGPHY_MII_AUXCTL, 0x0c00 },
762 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
763 { BRGPHY_MII_DSP_RW_PORT, 0x110b },
764 { BRGPHY_MII_TEST1, 0x0014 },
765 { BRGPHY_MII_AUXCTL, 0x0400 },
766 { 0, 0 },
767 };
768 int i;
769
770 for (i = 0; dspcode[i].reg != 0; i++)
771 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
772}
773
774static void
775brgphy_fixup_ber_bug(struct mii_softc *sc)
776{
777 static const struct {
778 int reg;
779 uint16_t val;
780 } dspcode[] = {
781 { BRGPHY_MII_AUXCTL, 0x0c00 },
782 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
783 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
784 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
785 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
786 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
787 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
788 { BRGPHY_MII_AUXCTL, 0x0400 },
789 { 0, 0 },
790 };
791 int i;
792
793 for (i = 0; dspcode[i].reg != 0; i++)
794 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
795}
796
797static void
798brgphy_fixup_crc_bug(struct mii_softc *sc)
799{
800 static const struct {
801 int reg;
802 uint16_t val;
803 } dspcode[] = {
804 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 },
805 { 0x1c, 0x8c68 },
806 { 0x1c, 0x8d68 },
807 { 0x1c, 0x8c68 },
808 { 0, 0 },
809 };
810 int i;
811
812 for (i = 0; dspcode[i].reg != 0; i++)
813 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
814}
815
816static void
817brgphy_fixup_jitter_bug(struct mii_softc *sc)
818{
819 static const struct {
820 int reg;
821 uint16_t val;
822 } dspcode[] = {
823 { BRGPHY_MII_AUXCTL, 0x0c00 },
824 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
825 { BRGPHY_MII_DSP_RW_PORT, 0x010b },
826 { BRGPHY_MII_AUXCTL, 0x0400 },
827 { 0, 0 },
828 };
829 int i;
830
831 for (i = 0; dspcode[i].reg != 0; i++)
832 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
833}
834
835static void
836brgphy_fixup_disable_early_dac(struct mii_softc *sc)
837{
838 uint32_t val;
839
840 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
841 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
842 val &= ~(1 << 8);
843 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
844
845}
846
847static void
848brgphy_ethernet_wirespeed(struct mii_softc *sc)
849{
850 uint32_t val;
851
852 /* Enable Ethernet@WireSpeed. */
853 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
854 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
855 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
856}
857
858static void
859brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
860{
861 uint32_t val;
862
863 /* Set or clear jumbo frame settings in the PHY. */
864 if (mtu > ETHER_MAX_LEN) {
865 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) {
866 /* BCM5401 PHY cannot read-modify-write. */
867 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
868 } else {
869 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
870 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
871 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
872 val | BRGPHY_AUXCTL_LONG_PKT);
873 }
874
875 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
876 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
877 val | BRGPHY_PHY_EXTCTL_HIGH_LA);
878 } else {
879 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
880 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
881 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
882 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
883
884 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
885 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
886 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
887 }
888}
889
890static void
891brgphy_reset(struct mii_softc *sc)
892{
893 struct bge_softc *bge_sc = NULL;
894 struct bce_softc *bce_sc = NULL;
895 if_t ifp;
896 int i, val;
897
898 /*
899 * Perform a reset. Note that at least some Broadcom PHYs default to
900 * being powered down as well as isolated after a reset but don't work
901 * if one or both of these bits are cleared. However, they just work
902 * fine if both bits remain set, so we don't use mii_phy_reset() here.
903 */
904 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
905
906 /* Wait 100ms for it to complete. */
907 for (i = 0; i < 100; i++) {
908 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0)
909 break;
910 DELAY(1000);
911 }
912
913 /* Handle any PHY specific procedures following the reset. */
914 switch (sc->mii_mpd_oui) {
915 case MII_OUI_BROADCOM:
916 switch (sc->mii_mpd_model) {
917 case MII_MODEL_BROADCOM_BCM5400:
918 bcm5401_load_dspcode(sc);
919 break;
920 case MII_MODEL_BROADCOM_BCM5401:
921 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
922 bcm5401_load_dspcode(sc);
923 break;
924 case MII_MODEL_BROADCOM_BCM5411:
925 bcm5411_load_dspcode(sc);
926 break;
927 case MII_MODEL_BROADCOM_BCM54K2:
928 bcm54k2_load_dspcode(sc);
929 break;
930 }
931 break;
932 case MII_OUI_BROADCOM3:
933 switch (sc->mii_mpd_model) {
934 case MII_MODEL_BROADCOM3_BCM5717C:
935 case MII_MODEL_BROADCOM3_BCM5719C:
936 case MII_MODEL_BROADCOM3_BCM5720C:
937 case MII_MODEL_BROADCOM3_BCM57765:
938 return;
939 }
940 break;
941 case MII_OUI_BROADCOM4:
942 return;
943 }
944
945 ifp = sc->mii_pdata->mii_ifp;
946
947 /* Find the driver associated with this PHY. */
948 if (mii_phy_mac_match(sc, "bge"))
949 bge_sc = mii_phy_mac_softc(sc);
950 else if (mii_phy_mac_match(sc, "bce"))
951 bce_sc = mii_phy_mac_softc(sc);
952
953 if (bge_sc) {
954 /* Fix up various bugs */
955 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
956 brgphy_fixup_5704_a0_bug(sc);
957 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
958 brgphy_fixup_adc_bug(sc);
959 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
960 brgphy_fixup_adjust_trim(sc);
961 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
962 brgphy_fixup_ber_bug(sc);
963 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
964 brgphy_fixup_crc_bug(sc);
965 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
966 brgphy_fixup_jitter_bug(sc);
967
968 if (bge_sc->bge_flags & BGE_FLAG_JUMBO)
969 brgphy_jumbo_settings(sc, if_getmtu(ifp));
970
971 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0)
972 brgphy_ethernet_wirespeed(sc);
973
974 /* Enable Link LED on Dell boxes */
975 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
976 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
977 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
978 ~BRGPHY_PHY_EXTCTL_3_LED);
979 }
980
981 /* Adjust output voltage (From Linux driver) */
982 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
983 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
984 } else if (bce_sc) {
985 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
986 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
987
988 /* Store autoneg capabilities/results in digital block (Page 0) */
989 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
990 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
991 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
992 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
993
994 /* Enable fiber mode and autodetection */
995 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
996 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
997 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
998 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
999
1000 /* Enable parallel detection */
1001 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
1002 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
1003 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
1004
1005 /* Advertise 2.5G support through next page during autoneg */
1006 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1007 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
1008 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
1009 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
1010
1011 /* Increase TX signal amplitude */
1012 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1013 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1014 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1015 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1016 BRGPHY_5708S_TX_MISC_PG5);
1017 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1018 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1019 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1020 BRGPHY_5708S_DIG_PG0);
1021 }
1022
1023 /* Backplanes use special driver/pre-driver/pre-emphasis values. */
1024 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1025 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1026 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1027 BRGPHY_5708S_TX_MISC_PG5);
1028 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1029 bce_sc->bce_port_hw_cfg &
1030 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1031 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1032 BRGPHY_5708S_DIG_PG0);
1033 }
1034 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1035 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1036
1037 /* Select the SerDes Digital block of the AN MMD. */
1038 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1039 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1040 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1041 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1042 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1043
1044 /* Select the Over 1G block of the AN MMD. */
1045 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1046
1047 /* Enable autoneg "Next Page" to advertise 2.5G support. */
1048 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1049 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1050 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1051 else
1052 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1053 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1054
1055 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1056 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1057
1058 /* Enable MRBE speed autoneg. */
1059 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1060 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1061 BRGPHY_MRBE_MSG_PG5_NP_T2;
1062 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1063
1064 /* Select the Clause 73 User B0 block of the AN MMD. */
1065 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1066
1067 /* Enable MRBE speed autoneg. */
1068 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1069 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1070 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1071 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1072
1073 /* Restore IEEE0 block (assumed in all brgphy(4) code). */
1074 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1075 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1076 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1077 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1078 brgphy_fixup_disable_early_dac(sc);
1079
1080 brgphy_jumbo_settings(sc, if_getmtu(ifp));
1081 brgphy_ethernet_wirespeed(sc);
1082 } else {
1083 brgphy_fixup_ber_bug(sc);
1084 brgphy_jumbo_settings(sc, if_getmtu(ifp));
1085 brgphy_ethernet_wirespeed(sc);
1086 }
1087 }
1088}
| 140 MII_PHY_DESC(BROADCOM2, BCM5482),
141 MII_PHY_DESC(BROADCOM2, BCM5708S),
142 MII_PHY_DESC(BROADCOM2, BCM5709C),
143 MII_PHY_DESC(BROADCOM2, BCM5709S),
144 MII_PHY_DESC(BROADCOM2, BCM5709CAX),
145 MII_PHY_DESC(BROADCOM2, BCM5722),
146 MII_PHY_DESC(BROADCOM2, BCM5755),
147 MII_PHY_DESC(BROADCOM2, BCM5754),
148 MII_PHY_DESC(BROADCOM2, BCM5761),
149 MII_PHY_DESC(BROADCOM2, BCM5784),
150#ifdef notyet /* better handled by ukphy(4) until WARs are implemented */
151 MII_PHY_DESC(BROADCOM2, BCM5785),
152#endif
153 MII_PHY_DESC(BROADCOM3, BCM5717C),
154 MII_PHY_DESC(BROADCOM3, BCM5719C),
155 MII_PHY_DESC(BROADCOM3, BCM5720C),
156 MII_PHY_DESC(BROADCOM3, BCM57765),
157 MII_PHY_DESC(BROADCOM3, BCM57780),
158 MII_PHY_DESC(BROADCOM4, BCM5725C),
159 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
160 MII_PHY_END
161};
162
163static const struct mii_phy_funcs brgphy_funcs = {
164 brgphy_service,
165 brgphy_status,
166 brgphy_reset
167};
168
169static const struct hs21_type {
170 const uint32_t id;
171 const char *prod;
172} hs21_type_lists[] = {
173 { 0x57081021, "IBM eServer BladeCenter HS21" },
174 { 0x57081011, "IBM eServer BladeCenter HS21 -[8853PAU]-" },
175};
176
177static int
178detect_hs21(struct bce_softc *bce_sc)
179{
180 char *sysenv;
181 int found, i;
182
183 found = 0;
184 sysenv = kern_getenv("smbios.system.product");
185 if (sysenv == NULL)
186 return (found);
187 for (i = 0; i < nitems(hs21_type_lists); i++) {
188 if (bce_sc->bce_chipid == hs21_type_lists[i].id &&
189 strncmp(sysenv, hs21_type_lists[i].prod,
190 strlen(hs21_type_lists[i].prod)) == 0) {
191 found++;
192 break;
193 }
194 }
195 freeenv(sysenv);
196 return (found);
197}
198
199/* Search for our PHY in the list of known PHYs */
200static int
201brgphy_probe(device_t dev)
202{
203
204 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
205}
206
207/* Attach the PHY to the MII bus */
208static int
209brgphy_attach(device_t dev)
210{
211 struct brgphy_softc *bsc;
212 struct bge_softc *bge_sc = NULL;
213 struct bce_softc *bce_sc = NULL;
214 struct mii_softc *sc;
215
216 bsc = device_get_softc(dev);
217 sc = &bsc->mii_sc;
218
219 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
220 &brgphy_funcs, 0);
221
222 bsc->serdes_flags = 0;
223
224 /* Find the MAC driver associated with this PHY. */
225 if (mii_dev_mac_match(dev, "bge"))
226 bge_sc = mii_dev_mac_softc(dev);
227 else if (mii_dev_mac_match(dev, "bce"))
228 bce_sc = mii_dev_mac_softc(dev);
229
230 /* Handle any special cases based on the PHY ID */
231 switch (sc->mii_mpd_oui) {
232 case MII_OUI_BROADCOM:
233 switch (sc->mii_mpd_model) {
234 case MII_MODEL_BROADCOM_BCM5706:
235 case MII_MODEL_BROADCOM_BCM5714:
236 /*
237 * The 5464 PHY used in the 5706 supports both copper
238 * and fiber interfaces over GMII. Need to check the
239 * shadow registers to see which mode is actually
240 * in effect, and therefore whether we have 5706C or
241 * 5706S.
242 */
243 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
244 BRGPHY_SHADOW_1C_MODE_CTRL);
245 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
246 BRGPHY_SHADOW_1C_ENA_1000X) {
247 bsc->serdes_flags |= BRGPHY_5706S;
248 sc->mii_flags |= MIIF_HAVEFIBER;
249 }
250 break;
251 }
252 break;
253 case MII_OUI_BROADCOM2:
254 switch (sc->mii_mpd_model) {
255 case MII_MODEL_BROADCOM2_BCM5708S:
256 bsc->serdes_flags |= BRGPHY_5708S;
257 sc->mii_flags |= MIIF_HAVEFIBER;
258 break;
259 case MII_MODEL_BROADCOM2_BCM5709S:
260 /*
261 * XXX
262 * 5720S and 5709S shares the same PHY id.
263 * Assume 5720S PHY if parent device is bge(4).
264 */
265 if (bge_sc != NULL)
266 bsc->serdes_flags |= BRGPHY_5708S;
267 else
268 bsc->serdes_flags |= BRGPHY_5709S;
269 sc->mii_flags |= MIIF_HAVEFIBER;
270 break;
271 }
272 break;
273 }
274
275 PHY_RESET(sc);
276
277 /* Read the PHY's capabilities. */
278 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
279 if (sc->mii_capabilities & BMSR_EXTSTAT)
280 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
281 device_printf(dev, " ");
282
283 /* Add the supported media types */
284 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
285 mii_phy_add_media(sc);
286 printf("\n");
287 } else {
288 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
289 ifmedia_add(&sc->mii_pdata->mii_media,
290 IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
291 0, NULL);
292 printf("1000baseSX-FDX, ");
293 /*
294 * 2.5G support is a software enabled feature
295 * on the 5708S and 5709S.
296 */
297 if (bce_sc && (bce_sc->bce_phy_flags &
298 BCE_PHY_2_5G_CAPABLE_FLAG)) {
299 ifmedia_add(&sc->mii_pdata->mii_media,
300 IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX,
301 sc->mii_inst), 0, NULL);
302 printf("2500baseSX-FDX, ");
303 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
304 (detect_hs21(bce_sc) != 0)) {
305 /*
306 * There appears to be certain silicon revision
307 * in IBM HS21 blades that is having issues with
308 * this driver wating for the auto-negotiation to
309 * complete. This happens with a specific chip id
310 * only and when the 1000baseSX-FDX is the only
311 * mode. Workaround this issue since it's unlikely
312 * to be ever addressed.
313 */
314 printf("auto-neg workaround, ");
315 bsc->serdes_flags |= BRGPHY_NOANWAIT;
316 }
317 ifmedia_add(&sc->mii_pdata->mii_media, IFM_MAKEWORD(IFM_ETHER,
318 IFM_AUTO, 0, sc->mii_inst), 0, NULL);
319 printf("auto\n");
320 }
321
322 MIIBUS_MEDIAINIT(sc->mii_dev);
323 return (0);
324}
325
326static int
327brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
328{
329 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
330 int val;
331
332 switch (cmd) {
333 case MII_POLLSTAT:
334 break;
335 case MII_MEDIACHG:
336 /* Todo: Why is this here? Is it really needed? */
337 PHY_RESET(sc); /* XXX hardware bug work-around */
338
339 switch (IFM_SUBTYPE(ife->ifm_media)) {
340 case IFM_AUTO:
341 brgphy_mii_phy_auto(sc, ife->ifm_media);
342 break;
343 case IFM_2500_SX:
344 case IFM_1000_SX:
345 case IFM_1000_T:
346 case IFM_100_TX:
347 case IFM_10_T:
348 brgphy_setmedia(sc, ife->ifm_media);
349 break;
350 default:
351 return (EINVAL);
352 }
353 break;
354 case MII_TICK:
355 /* Bail if autoneg isn't in process. */
356 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
357 sc->mii_ticks = 0;
358 break;
359 }
360
361 /*
362 * Check to see if we have link. If we do, we don't
363 * need to restart the autonegotiation process.
364 */
365 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
366 if (val & BMSR_LINK) {
367 sc->mii_ticks = 0; /* Reset autoneg timer. */
368 break;
369 }
370
371 /* Announce link loss right after it happens. */
372 if (sc->mii_ticks++ == 0)
373 break;
374
375 /* Only retry autonegotiation every mii_anegticks seconds. */
376 if (sc->mii_ticks <= sc->mii_anegticks)
377 break;
378
379
380 /* Retry autonegotiation */
381 sc->mii_ticks = 0;
382 brgphy_mii_phy_auto(sc, ife->ifm_media);
383 break;
384 }
385
386 /* Update the media status. */
387 PHY_STATUS(sc);
388
389 /*
390 * Callback if something changed. Note that we need to poke
391 * the DSP on the Broadcom PHYs if the media changes.
392 */
393 if (sc->mii_media_active != mii->mii_media_active ||
394 sc->mii_media_status != mii->mii_media_status ||
395 cmd == MII_MEDIACHG) {
396 switch (sc->mii_mpd_oui) {
397 case MII_OUI_BROADCOM:
398 switch (sc->mii_mpd_model) {
399 case MII_MODEL_BROADCOM_BCM5400:
400 bcm5401_load_dspcode(sc);
401 break;
402 case MII_MODEL_BROADCOM_BCM5401:
403 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
404 bcm5401_load_dspcode(sc);
405 break;
406 case MII_MODEL_BROADCOM_BCM5411:
407 bcm5411_load_dspcode(sc);
408 break;
409 case MII_MODEL_BROADCOM_BCM54K2:
410 bcm54k2_load_dspcode(sc);
411 break;
412 }
413 break;
414 }
415 }
416 mii_phy_update(sc, cmd);
417 return (0);
418}
419
420/****************************************************************************/
421/* Sets the PHY link speed. */
422/* */
423/* Returns: */
424/* None */
425/****************************************************************************/
426static void
427brgphy_setmedia(struct mii_softc *sc, int media)
428{
429 int bmcr = 0, gig;
430
431 switch (IFM_SUBTYPE(media)) {
432 case IFM_2500_SX:
433 break;
434 case IFM_1000_SX:
435 case IFM_1000_T:
436 bmcr = BRGPHY_S1000;
437 break;
438 case IFM_100_TX:
439 bmcr = BRGPHY_S100;
440 break;
441 case IFM_10_T:
442 default:
443 bmcr = BRGPHY_S10;
444 break;
445 }
446
447 if ((media & IFM_FDX) != 0) {
448 bmcr |= BRGPHY_BMCR_FDX;
449 gig = BRGPHY_1000CTL_AFD;
450 } else {
451 gig = BRGPHY_1000CTL_AHD;
452 }
453
454 /* Force loopback to disconnect PHY from Ethernet medium. */
455 brgphy_enable_loopback(sc);
456
457 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
458 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
459
460 if (IFM_SUBTYPE(media) != IFM_1000_T &&
461 IFM_SUBTYPE(media) != IFM_1000_SX) {
462 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
463 return;
464 }
465
466 if (IFM_SUBTYPE(media) == IFM_1000_T) {
467 gig |= BRGPHY_1000CTL_MSE;
468 if ((media & IFM_ETH_MASTER) != 0)
469 gig |= BRGPHY_1000CTL_MSC;
470 }
471 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
472 PHY_WRITE(sc, BRGPHY_MII_BMCR,
473 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
474}
475
476/****************************************************************************/
477/* Set the media status based on the PHY settings. */
478/* */
479/* Returns: */
480/* None */
481/****************************************************************************/
482static void
483brgphy_status(struct mii_softc *sc)
484{
485 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
486 struct mii_data *mii = sc->mii_pdata;
487 int aux, bmcr, bmsr, val, xstat;
488 u_int flowstat;
489
490 mii->mii_media_status = IFM_AVALID;
491 mii->mii_media_active = IFM_ETHER;
492
493 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
494 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
495
496 if (bmcr & BRGPHY_BMCR_LOOP) {
497 mii->mii_media_active |= IFM_LOOP;
498 }
499
500 if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
501 (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
502 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
503 /* Erg, still trying, I guess... */
504 mii->mii_media_active |= IFM_NONE;
505 return;
506 }
507
508 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
509 /*
510 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS
511 * wedges at least the PHY of BCM5704 (but not others).
512 */
513 flowstat = mii_phy_flowstatus(sc);
514 xstat = PHY_READ(sc, BRGPHY_MII_1000STS);
515 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
516
517 /* If copper link is up, get the negotiated speed/duplex. */
518 if (aux & BRGPHY_AUXSTS_LINK) {
519 mii->mii_media_status |= IFM_ACTIVE;
520 switch (aux & BRGPHY_AUXSTS_AN_RES) {
521 case BRGPHY_RES_1000FD:
522 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break;
523 case BRGPHY_RES_1000HD:
524 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break;
525 case BRGPHY_RES_100FD:
526 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
527 case BRGPHY_RES_100T4:
528 mii->mii_media_active |= IFM_100_T4; break;
529 case BRGPHY_RES_100HD:
530 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break;
531 case BRGPHY_RES_10FD:
532 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
533 case BRGPHY_RES_10HD:
534 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
535 default:
536 mii->mii_media_active |= IFM_NONE; break;
537 }
538
539 if ((mii->mii_media_active & IFM_FDX) != 0)
540 mii->mii_media_active |= flowstat;
541
542 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T &&
543 (xstat & BRGPHY_1000STS_MSR) != 0)
544 mii->mii_media_active |= IFM_ETH_MASTER;
545 }
546 } else {
547 /* Todo: Add support for flow control. */
548 /* If serdes link is up, get the negotiated speed/duplex. */
549 if (bmsr & BRGPHY_BMSR_LINK) {
550 mii->mii_media_status |= IFM_ACTIVE;
551 }
552
553 /* Check the link speed/duplex based on the PHY type. */
554 if (bsc->serdes_flags & BRGPHY_5706S) {
555 mii->mii_media_active |= IFM_1000_SX;
556
557 /* If autoneg enabled, read negotiated duplex settings */
558 if (bmcr & BRGPHY_BMCR_AUTOEN) {
559 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
560 if (val & BRGPHY_SERDES_ANAR_FDX)
561 mii->mii_media_active |= IFM_FDX;
562 else
563 mii->mii_media_active |= IFM_HDX;
564 }
565 } else if (bsc->serdes_flags & BRGPHY_5708S) {
566 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
567 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
568
569 /* Check for MRBE auto-negotiated speed results. */
570 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
571 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
572 mii->mii_media_active |= IFM_10_FL; break;
573 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
574 mii->mii_media_active |= IFM_100_FX; break;
575 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
576 mii->mii_media_active |= IFM_1000_SX; break;
577 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
578 mii->mii_media_active |= IFM_2500_SX; break;
579 }
580
581 /* Check for MRBE auto-negotiated duplex results. */
582 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
583 mii->mii_media_active |= IFM_FDX;
584 else
585 mii->mii_media_active |= IFM_HDX;
586 } else if (bsc->serdes_flags & BRGPHY_5709S) {
587 /* Select GP Status Block of the AN MMD, get autoneg results. */
588 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
589 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
590
591 /* Restore IEEE0 block (assumed in all brgphy(4) code). */
592 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
593
594 /* Check for MRBE auto-negotiated speed results. */
595 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
596 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
597 mii->mii_media_active |= IFM_10_FL; break;
598 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
599 mii->mii_media_active |= IFM_100_FX; break;
600 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
601 mii->mii_media_active |= IFM_1000_SX; break;
602 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
603 mii->mii_media_active |= IFM_2500_SX; break;
604 }
605
606 /* Check for MRBE auto-negotiated duplex results. */
607 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
608 mii->mii_media_active |= IFM_FDX;
609 else
610 mii->mii_media_active |= IFM_HDX;
611 }
612 }
613}
614
615static void
616brgphy_mii_phy_auto(struct mii_softc *sc, int media)
617{
618 int anar, ktcr = 0;
619
620 PHY_RESET(sc);
621
622 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
623 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
624 if ((media & IFM_FLOW) != 0 ||
625 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
626 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP;
627 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar);
628 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
629 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)
630 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
631 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
632 PHY_READ(sc, BRGPHY_MII_1000CTL);
633 } else {
634 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX;
635 if ((media & IFM_FLOW) != 0 ||
636 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
637 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE;
638 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar);
639 }
640
641 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN |
642 BRGPHY_BMCR_STARTNEG);
643 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
644}
645
646/* Enable loopback to force the link down. */
647static void
648brgphy_enable_loopback(struct mii_softc *sc)
649{
650 int i;
651
652 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
653 for (i = 0; i < 15000; i++) {
654 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
655 break;
656 DELAY(10);
657 }
658}
659
660/* Turn off tap power management on 5401. */
661static void
662bcm5401_load_dspcode(struct mii_softc *sc)
663{
664 static const struct {
665 int reg;
666 uint16_t val;
667 } dspcode[] = {
668 { BRGPHY_MII_AUXCTL, 0x0c20 },
669 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
670 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
671 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
672 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
673 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
674 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
675 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
676 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
677 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
678 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
679 { 0, 0 },
680 };
681 int i;
682
683 for (i = 0; dspcode[i].reg != 0; i++)
684 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
685 DELAY(40);
686}
687
688static void
689bcm5411_load_dspcode(struct mii_softc *sc)
690{
691 static const struct {
692 int reg;
693 uint16_t val;
694 } dspcode[] = {
695 { 0x1c, 0x8c23 },
696 { 0x1c, 0x8ca3 },
697 { 0x1c, 0x8c23 },
698 { 0, 0 },
699 };
700 int i;
701
702 for (i = 0; dspcode[i].reg != 0; i++)
703 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
704}
705
706void
707bcm54k2_load_dspcode(struct mii_softc *sc)
708{
709 static const struct {
710 int reg;
711 uint16_t val;
712 } dspcode[] = {
713 { 4, 0x01e1 },
714 { 9, 0x0300 },
715 { 0, 0 },
716 };
717 int i;
718
719 for (i = 0; dspcode[i].reg != 0; i++)
720 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
721
722}
723
724static void
725brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
726{
727 static const struct {
728 int reg;
729 uint16_t val;
730 } dspcode[] = {
731 { 0x1c, 0x8d68 },
732 { 0x1c, 0x8d68 },
733 { 0, 0 },
734 };
735 int i;
736
737 for (i = 0; dspcode[i].reg != 0; i++)
738 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
739}
740
741static void
742brgphy_fixup_adc_bug(struct mii_softc *sc)
743{
744 static const struct {
745 int reg;
746 uint16_t val;
747 } dspcode[] = {
748 { BRGPHY_MII_AUXCTL, 0x0c00 },
749 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
750 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
751 { 0, 0 },
752 };
753 int i;
754
755 for (i = 0; dspcode[i].reg != 0; i++)
756 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
757}
758
759static void
760brgphy_fixup_adjust_trim(struct mii_softc *sc)
761{
762 static const struct {
763 int reg;
764 uint16_t val;
765 } dspcode[] = {
766 { BRGPHY_MII_AUXCTL, 0x0c00 },
767 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
768 { BRGPHY_MII_DSP_RW_PORT, 0x110b },
769 { BRGPHY_MII_TEST1, 0x0014 },
770 { BRGPHY_MII_AUXCTL, 0x0400 },
771 { 0, 0 },
772 };
773 int i;
774
775 for (i = 0; dspcode[i].reg != 0; i++)
776 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
777}
778
779static void
780brgphy_fixup_ber_bug(struct mii_softc *sc)
781{
782 static const struct {
783 int reg;
784 uint16_t val;
785 } dspcode[] = {
786 { BRGPHY_MII_AUXCTL, 0x0c00 },
787 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
788 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
789 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
790 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
791 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
792 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
793 { BRGPHY_MII_AUXCTL, 0x0400 },
794 { 0, 0 },
795 };
796 int i;
797
798 for (i = 0; dspcode[i].reg != 0; i++)
799 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
800}
801
802static void
803brgphy_fixup_crc_bug(struct mii_softc *sc)
804{
805 static const struct {
806 int reg;
807 uint16_t val;
808 } dspcode[] = {
809 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 },
810 { 0x1c, 0x8c68 },
811 { 0x1c, 0x8d68 },
812 { 0x1c, 0x8c68 },
813 { 0, 0 },
814 };
815 int i;
816
817 for (i = 0; dspcode[i].reg != 0; i++)
818 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
819}
820
821static void
822brgphy_fixup_jitter_bug(struct mii_softc *sc)
823{
824 static const struct {
825 int reg;
826 uint16_t val;
827 } dspcode[] = {
828 { BRGPHY_MII_AUXCTL, 0x0c00 },
829 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
830 { BRGPHY_MII_DSP_RW_PORT, 0x010b },
831 { BRGPHY_MII_AUXCTL, 0x0400 },
832 { 0, 0 },
833 };
834 int i;
835
836 for (i = 0; dspcode[i].reg != 0; i++)
837 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
838}
839
840static void
841brgphy_fixup_disable_early_dac(struct mii_softc *sc)
842{
843 uint32_t val;
844
845 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
846 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
847 val &= ~(1 << 8);
848 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
849
850}
851
852static void
853brgphy_ethernet_wirespeed(struct mii_softc *sc)
854{
855 uint32_t val;
856
857 /* Enable Ethernet@WireSpeed. */
858 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
859 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
860 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
861}
862
863static void
864brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
865{
866 uint32_t val;
867
868 /* Set or clear jumbo frame settings in the PHY. */
869 if (mtu > ETHER_MAX_LEN) {
870 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) {
871 /* BCM5401 PHY cannot read-modify-write. */
872 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
873 } else {
874 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
875 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
876 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
877 val | BRGPHY_AUXCTL_LONG_PKT);
878 }
879
880 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
881 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
882 val | BRGPHY_PHY_EXTCTL_HIGH_LA);
883 } else {
884 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
885 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
886 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
887 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
888
889 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
890 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
891 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
892 }
893}
894
895static void
896brgphy_reset(struct mii_softc *sc)
897{
898 struct bge_softc *bge_sc = NULL;
899 struct bce_softc *bce_sc = NULL;
900 if_t ifp;
901 int i, val;
902
903 /*
904 * Perform a reset. Note that at least some Broadcom PHYs default to
905 * being powered down as well as isolated after a reset but don't work
906 * if one or both of these bits are cleared. However, they just work
907 * fine if both bits remain set, so we don't use mii_phy_reset() here.
908 */
909 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
910
911 /* Wait 100ms for it to complete. */
912 for (i = 0; i < 100; i++) {
913 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0)
914 break;
915 DELAY(1000);
916 }
917
918 /* Handle any PHY specific procedures following the reset. */
919 switch (sc->mii_mpd_oui) {
920 case MII_OUI_BROADCOM:
921 switch (sc->mii_mpd_model) {
922 case MII_MODEL_BROADCOM_BCM5400:
923 bcm5401_load_dspcode(sc);
924 break;
925 case MII_MODEL_BROADCOM_BCM5401:
926 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
927 bcm5401_load_dspcode(sc);
928 break;
929 case MII_MODEL_BROADCOM_BCM5411:
930 bcm5411_load_dspcode(sc);
931 break;
932 case MII_MODEL_BROADCOM_BCM54K2:
933 bcm54k2_load_dspcode(sc);
934 break;
935 }
936 break;
937 case MII_OUI_BROADCOM3:
938 switch (sc->mii_mpd_model) {
939 case MII_MODEL_BROADCOM3_BCM5717C:
940 case MII_MODEL_BROADCOM3_BCM5719C:
941 case MII_MODEL_BROADCOM3_BCM5720C:
942 case MII_MODEL_BROADCOM3_BCM57765:
943 return;
944 }
945 break;
946 case MII_OUI_BROADCOM4:
947 return;
948 }
949
950 ifp = sc->mii_pdata->mii_ifp;
951
952 /* Find the driver associated with this PHY. */
953 if (mii_phy_mac_match(sc, "bge"))
954 bge_sc = mii_phy_mac_softc(sc);
955 else if (mii_phy_mac_match(sc, "bce"))
956 bce_sc = mii_phy_mac_softc(sc);
957
958 if (bge_sc) {
959 /* Fix up various bugs */
960 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
961 brgphy_fixup_5704_a0_bug(sc);
962 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
963 brgphy_fixup_adc_bug(sc);
964 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
965 brgphy_fixup_adjust_trim(sc);
966 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
967 brgphy_fixup_ber_bug(sc);
968 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
969 brgphy_fixup_crc_bug(sc);
970 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
971 brgphy_fixup_jitter_bug(sc);
972
973 if (bge_sc->bge_flags & BGE_FLAG_JUMBO)
974 brgphy_jumbo_settings(sc, if_getmtu(ifp));
975
976 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0)
977 brgphy_ethernet_wirespeed(sc);
978
979 /* Enable Link LED on Dell boxes */
980 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
981 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
982 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
983 ~BRGPHY_PHY_EXTCTL_3_LED);
984 }
985
986 /* Adjust output voltage (From Linux driver) */
987 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
988 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
989 } else if (bce_sc) {
990 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
991 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
992
993 /* Store autoneg capabilities/results in digital block (Page 0) */
994 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
995 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
996 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
997 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
998
999 /* Enable fiber mode and autodetection */
1000 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
1001 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
1002 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
1003 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
1004
1005 /* Enable parallel detection */
1006 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
1007 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
1008 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
1009
1010 /* Advertise 2.5G support through next page during autoneg */
1011 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1012 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
1013 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
1014 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
1015
1016 /* Increase TX signal amplitude */
1017 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1018 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1019 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1020 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1021 BRGPHY_5708S_TX_MISC_PG5);
1022 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1023 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1024 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1025 BRGPHY_5708S_DIG_PG0);
1026 }
1027
1028 /* Backplanes use special driver/pre-driver/pre-emphasis values. */
1029 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1030 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1031 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1032 BRGPHY_5708S_TX_MISC_PG5);
1033 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1034 bce_sc->bce_port_hw_cfg &
1035 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1036 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1037 BRGPHY_5708S_DIG_PG0);
1038 }
1039 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1040 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1041
1042 /* Select the SerDes Digital block of the AN MMD. */
1043 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1044 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1045 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1046 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1047 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1048
1049 /* Select the Over 1G block of the AN MMD. */
1050 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1051
1052 /* Enable autoneg "Next Page" to advertise 2.5G support. */
1053 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1054 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1055 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1056 else
1057 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1058 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1059
1060 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1061 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1062
1063 /* Enable MRBE speed autoneg. */
1064 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1065 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1066 BRGPHY_MRBE_MSG_PG5_NP_T2;
1067 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1068
1069 /* Select the Clause 73 User B0 block of the AN MMD. */
1070 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1071
1072 /* Enable MRBE speed autoneg. */
1073 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1074 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1075 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1076 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1077
1078 /* Restore IEEE0 block (assumed in all brgphy(4) code). */
1079 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1080 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1081 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1082 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1083 brgphy_fixup_disable_early_dac(sc);
1084
1085 brgphy_jumbo_settings(sc, if_getmtu(ifp));
1086 brgphy_ethernet_wirespeed(sc);
1087 } else {
1088 brgphy_fixup_ber_bug(sc);
1089 brgphy_jumbo_settings(sc, if_getmtu(ifp));
1090 brgphy_ethernet_wirespeed(sc);
1091 }
1092 }
1093}
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