1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
|
30
31/*
32 * Driver for the Attansic/Atheros F1 10/100/1000 PHY.
33 */
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/module.h>
39#include <sys/socket.h>
40#include <sys/bus.h>
41
42#include <net/if.h>
43#include <net/if_media.h>
44
45#include <dev/mii/mii.h>
46#include <dev/mii/miivar.h>
47#include "miidevs.h"
48
49#include <dev/mii/atphyreg.h>
50
51#include "miibus_if.h"
52
53static int atphy_probe(device_t);
54static int atphy_attach(device_t);
55
56static device_method_t atphy_methods[] = {
57 /* Device interface. */
58 DEVMETHOD(device_probe, atphy_probe),
59 DEVMETHOD(device_attach, atphy_attach),
60 DEVMETHOD(device_detach, mii_phy_detach),
61 DEVMETHOD(device_shutdown, bus_generic_shutdown),
62 DEVMETHOD_END
63};
64
65static devclass_t atphy_devclass;
66static driver_t atphy_driver = {
67 "atphy",
68 atphy_methods,
69 sizeof(struct mii_softc)
70};
71
72DRIVER_MODULE(atphy, miibus, atphy_driver, atphy_devclass, 0, 0);
73
74static int atphy_service(struct mii_softc *, struct mii_data *, int);
75static void atphy_status(struct mii_softc *);
76static void atphy_reset(struct mii_softc *);
77static uint16_t atphy_anar(struct ifmedia_entry *);
78static int atphy_setmedia(struct mii_softc *, int);
79
80static const struct mii_phydesc atphys[] = {
81 MII_PHY_DESC(xxATHEROS, F1),
82 MII_PHY_DESC(xxATHEROS, F1_7),
| 30
31/*
32 * Driver for the Attansic/Atheros F1 10/100/1000 PHY.
33 */
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/module.h>
39#include <sys/socket.h>
40#include <sys/bus.h>
41
42#include <net/if.h>
43#include <net/if_media.h>
44
45#include <dev/mii/mii.h>
46#include <dev/mii/miivar.h>
47#include "miidevs.h"
48
49#include <dev/mii/atphyreg.h>
50
51#include "miibus_if.h"
52
53static int atphy_probe(device_t);
54static int atphy_attach(device_t);
55
56static device_method_t atphy_methods[] = {
57 /* Device interface. */
58 DEVMETHOD(device_probe, atphy_probe),
59 DEVMETHOD(device_attach, atphy_attach),
60 DEVMETHOD(device_detach, mii_phy_detach),
61 DEVMETHOD(device_shutdown, bus_generic_shutdown),
62 DEVMETHOD_END
63};
64
65static devclass_t atphy_devclass;
66static driver_t atphy_driver = {
67 "atphy",
68 atphy_methods,
69 sizeof(struct mii_softc)
70};
71
72DRIVER_MODULE(atphy, miibus, atphy_driver, atphy_devclass, 0, 0);
73
74static int atphy_service(struct mii_softc *, struct mii_data *, int);
75static void atphy_status(struct mii_softc *);
76static void atphy_reset(struct mii_softc *);
77static uint16_t atphy_anar(struct ifmedia_entry *);
78static int atphy_setmedia(struct mii_softc *, int);
79
80static const struct mii_phydesc atphys[] = {
81 MII_PHY_DESC(xxATHEROS, F1),
82 MII_PHY_DESC(xxATHEROS, F1_7),
|
83 MII_PHY_DESC(xxATHEROS, F2),
84 MII_PHY_END
85};
86
87static const struct mii_phy_funcs atphy_funcs = {
88 atphy_service,
89 atphy_status,
90 atphy_reset
91};
92
93static int
94atphy_probe(device_t dev)
95{
96
97 return (mii_phy_dev_probe(dev, atphys, BUS_PROBE_DEFAULT));
98}
99
100static int
101atphy_attach(device_t dev)
102{
103
104 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &atphy_funcs, 1);
105 return (0);
106}
107
108static int
109atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
110{
111 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
112 uint16_t anar, bmcr, bmsr;
113
114 switch (cmd) {
115 case MII_POLLSTAT:
116 break;
117
118 case MII_MEDIACHG:
119 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO ||
120 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
121 atphy_setmedia(sc, ife->ifm_media);
122 break;
123 }
124
125 bmcr = 0;
126 switch (IFM_SUBTYPE(ife->ifm_media)) {
127 case IFM_100_TX:
128 bmcr = BMCR_S100;
129 break;
130 case IFM_10_T:
131 bmcr = BMCR_S10;
132 break;
133 case IFM_NONE:
134 bmcr = PHY_READ(sc, MII_BMCR);
135 /*
136 * XXX
137 * Due to an unknown reason powering down PHY resulted
138 * in unexpected results such as inaccessibility of
139 * hardware of freshly rebooted system. Disable
140 * powering down PHY until I got more information for
141 * Attansic/Atheros PHY hardwares.
142 */
143 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
144 goto done;
145 default:
146 return (EINVAL);
147 }
148
149 anar = atphy_anar(ife);
150 if ((ife->ifm_media & IFM_FDX) != 0) {
151 bmcr |= BMCR_FDX;
152 if ((ife->ifm_media & IFM_FLOW) != 0 ||
153 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
154 anar |= ANAR_PAUSE_TOWARDS;
155 }
156
157 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX |
158 EXTSR_1000THDX)) != 0)
159 PHY_WRITE(sc, MII_100T2CR, 0);
160 PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA);
161
162 /*
163 * Reset the PHY so all changes take effect.
164 */
165 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN |
166 BMCR_STARTNEG);
167done:
168 break;
169
170 case MII_TICK:
171 /*
172 * Only used for autonegotiation.
173 */
174 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
175 sc->mii_ticks = 0;
176 break;
177 }
178
179 /*
180 * Check for link.
181 * Read the status register twice; BMSR_LINK is latch-low.
182 */
183 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
184 if (bmsr & BMSR_LINK) {
185 sc->mii_ticks = 0;
186 break;
187 }
188
189 /* Announce link loss right after it happens. */
190 if (sc->mii_ticks++ == 0)
191 break;
192 if (sc->mii_ticks <= sc->mii_anegticks)
193 return (0);
194
195 sc->mii_ticks = 0;
196 atphy_setmedia(sc, ife->ifm_media);
197 break;
198 }
199
200 /* Update the media status. */
201 PHY_STATUS(sc);
202
203 /* Callback if something changed. */
204 mii_phy_update(sc, cmd);
205 return (0);
206}
207
208static void
209atphy_status(struct mii_softc *sc)
210{
211 struct mii_data *mii = sc->mii_pdata;
212 uint32_t bmsr, bmcr, ssr;
213
214 mii->mii_media_status = IFM_AVALID;
215 mii->mii_media_active = IFM_ETHER;
216
217 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
218 if ((bmsr & BMSR_LINK) != 0)
219 mii->mii_media_status |= IFM_ACTIVE;
220
221 bmcr = PHY_READ(sc, MII_BMCR);
222 if ((bmcr & BMCR_ISO) != 0) {
223 mii->mii_media_active |= IFM_NONE;
224 mii->mii_media_status = 0;
225 return;
226 }
227
228 if ((bmcr & BMCR_LOOP) != 0)
229 mii->mii_media_active |= IFM_LOOP;
230
231 ssr = PHY_READ(sc, ATPHY_SSR);
232 if ((ssr & ATPHY_SSR_SPD_DPLX_RESOLVED) == 0) {
233 /* Erg, still trying, I guess... */
234 mii->mii_media_active |= IFM_NONE;
235 return;
236 }
237
238 switch (ssr & ATPHY_SSR_SPEED_MASK) {
239 case ATPHY_SSR_1000MBS:
240 mii->mii_media_active |= IFM_1000_T;
241 /*
242 * atphy(4) has a valid link so reset mii_ticks.
243 * Resetting mii_ticks is needed in order to
244 * detect link loss after auto-negotiation.
245 */
246 sc->mii_ticks = 0;
247 break;
248 case ATPHY_SSR_100MBS:
249 mii->mii_media_active |= IFM_100_TX;
250 sc->mii_ticks = 0;
251 break;
252 case ATPHY_SSR_10MBS:
253 mii->mii_media_active |= IFM_10_T;
254 sc->mii_ticks = 0;
255 break;
256 default:
257 mii->mii_media_active |= IFM_NONE;
258 return;
259 }
260
261 if ((ssr & ATPHY_SSR_DUPLEX) != 0)
262 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
263 else
264 mii->mii_media_active |= IFM_HDX;
265
266 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
267 (PHY_READ(sc, MII_100T2SR) & GTSR_MS_RES) != 0)
268 mii->mii_media_active |= IFM_ETH_MASTER;
269}
270
271static void
272atphy_reset(struct mii_softc *sc)
273{
274 struct ifmedia_entry *ife = sc->mii_pdata->mii_media.ifm_cur;
275 uint32_t reg;
276 int i;
277
278 /* Take PHY out of power down mode. */
279 PHY_WRITE(sc, 29, 0x29);
280 PHY_WRITE(sc, 30, 0);
281
282 reg = PHY_READ(sc, ATPHY_SCR);
283 /* Enable automatic crossover. */
284 reg |= ATPHY_SCR_AUTO_X_MODE;
285 /* Disable power down. */
286 reg &= ~ATPHY_SCR_MAC_PDOWN;
287 /* Enable CRS on Tx. */
288 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;
289 /* Auto correction for reversed cable polarity. */
290 reg |= ATPHY_SCR_POLARITY_REVERSAL;
291 PHY_WRITE(sc, ATPHY_SCR, reg);
292
293 /* Workaround F1 bug to reset phy. */
294 atphy_setmedia(sc, ife == NULL ? IFM_AUTO : ife->ifm_media);
295
296 for (i = 0; i < 1000; i++) {
297 DELAY(1);
298 if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
299 break;
300 }
301}
302
303static uint16_t
304atphy_anar(struct ifmedia_entry *ife)
305{
306 uint16_t anar;
307
308 anar = 0;
309 switch (IFM_SUBTYPE(ife->ifm_media)) {
310 case IFM_AUTO:
311 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
312 return (anar);
313 case IFM_1000_T:
314 return (anar);
315 case IFM_100_TX:
316 anar |= ANAR_TX;
317 break;
318 case IFM_10_T:
319 anar |= ANAR_10;
320 break;
321 default:
322 return (0);
323 }
324
325 if ((ife->ifm_media & IFM_FDX) != 0) {
326 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX)
327 anar |= ANAR_TX_FD;
328 else
329 anar |= ANAR_10_FD;
330 }
331
332 return (anar);
333}
334
335static int
336atphy_setmedia(struct mii_softc *sc, int media)
337{
338 uint16_t anar;
339
340 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
341 if ((IFM_SUBTYPE(media) == IFM_AUTO || (media & IFM_FDX) != 0) &&
342 ((media & IFM_FLOW) != 0 ||
343 (sc->mii_flags & MIIF_FORCEPAUSE) != 0))
344 anar |= ANAR_PAUSE_TOWARDS;
345 PHY_WRITE(sc, MII_ANAR, anar);
346 if ((sc->mii_extcapabilities &
347 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
348 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
349 GTCR_ADV_1000THDX);
350 else if (sc->mii_mpd_model == MII_MODEL_xxATHEROS_F1) {
351 /*
352 * AR8132 has 10/100 PHY and the PHY uses the same
353 * model number of F1 gigabit PHY. The PHY has no
354 * ability to establish gigabit link so explicitly
355 * disable 1000baseT configuration for the PHY.
356 * Otherwise, there is a case that atphy(4) could
357 * not establish a link against gigabit link partner
358 * unless the link partner supports down-shifting.
359 */
360 PHY_WRITE(sc, MII_100T2CR, 0);
361 }
362 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
363
364 return (EJUSTRETURN);
365}
| 84 MII_PHY_DESC(xxATHEROS, F2),
85 MII_PHY_END
86};
87
88static const struct mii_phy_funcs atphy_funcs = {
89 atphy_service,
90 atphy_status,
91 atphy_reset
92};
93
94static int
95atphy_probe(device_t dev)
96{
97
98 return (mii_phy_dev_probe(dev, atphys, BUS_PROBE_DEFAULT));
99}
100
101static int
102atphy_attach(device_t dev)
103{
104
105 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &atphy_funcs, 1);
106 return (0);
107}
108
109static int
110atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
111{
112 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
113 uint16_t anar, bmcr, bmsr;
114
115 switch (cmd) {
116 case MII_POLLSTAT:
117 break;
118
119 case MII_MEDIACHG:
120 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO ||
121 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
122 atphy_setmedia(sc, ife->ifm_media);
123 break;
124 }
125
126 bmcr = 0;
127 switch (IFM_SUBTYPE(ife->ifm_media)) {
128 case IFM_100_TX:
129 bmcr = BMCR_S100;
130 break;
131 case IFM_10_T:
132 bmcr = BMCR_S10;
133 break;
134 case IFM_NONE:
135 bmcr = PHY_READ(sc, MII_BMCR);
136 /*
137 * XXX
138 * Due to an unknown reason powering down PHY resulted
139 * in unexpected results such as inaccessibility of
140 * hardware of freshly rebooted system. Disable
141 * powering down PHY until I got more information for
142 * Attansic/Atheros PHY hardwares.
143 */
144 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
145 goto done;
146 default:
147 return (EINVAL);
148 }
149
150 anar = atphy_anar(ife);
151 if ((ife->ifm_media & IFM_FDX) != 0) {
152 bmcr |= BMCR_FDX;
153 if ((ife->ifm_media & IFM_FLOW) != 0 ||
154 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
155 anar |= ANAR_PAUSE_TOWARDS;
156 }
157
158 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX |
159 EXTSR_1000THDX)) != 0)
160 PHY_WRITE(sc, MII_100T2CR, 0);
161 PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA);
162
163 /*
164 * Reset the PHY so all changes take effect.
165 */
166 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN |
167 BMCR_STARTNEG);
168done:
169 break;
170
171 case MII_TICK:
172 /*
173 * Only used for autonegotiation.
174 */
175 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
176 sc->mii_ticks = 0;
177 break;
178 }
179
180 /*
181 * Check for link.
182 * Read the status register twice; BMSR_LINK is latch-low.
183 */
184 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
185 if (bmsr & BMSR_LINK) {
186 sc->mii_ticks = 0;
187 break;
188 }
189
190 /* Announce link loss right after it happens. */
191 if (sc->mii_ticks++ == 0)
192 break;
193 if (sc->mii_ticks <= sc->mii_anegticks)
194 return (0);
195
196 sc->mii_ticks = 0;
197 atphy_setmedia(sc, ife->ifm_media);
198 break;
199 }
200
201 /* Update the media status. */
202 PHY_STATUS(sc);
203
204 /* Callback if something changed. */
205 mii_phy_update(sc, cmd);
206 return (0);
207}
208
209static void
210atphy_status(struct mii_softc *sc)
211{
212 struct mii_data *mii = sc->mii_pdata;
213 uint32_t bmsr, bmcr, ssr;
214
215 mii->mii_media_status = IFM_AVALID;
216 mii->mii_media_active = IFM_ETHER;
217
218 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
219 if ((bmsr & BMSR_LINK) != 0)
220 mii->mii_media_status |= IFM_ACTIVE;
221
222 bmcr = PHY_READ(sc, MII_BMCR);
223 if ((bmcr & BMCR_ISO) != 0) {
224 mii->mii_media_active |= IFM_NONE;
225 mii->mii_media_status = 0;
226 return;
227 }
228
229 if ((bmcr & BMCR_LOOP) != 0)
230 mii->mii_media_active |= IFM_LOOP;
231
232 ssr = PHY_READ(sc, ATPHY_SSR);
233 if ((ssr & ATPHY_SSR_SPD_DPLX_RESOLVED) == 0) {
234 /* Erg, still trying, I guess... */
235 mii->mii_media_active |= IFM_NONE;
236 return;
237 }
238
239 switch (ssr & ATPHY_SSR_SPEED_MASK) {
240 case ATPHY_SSR_1000MBS:
241 mii->mii_media_active |= IFM_1000_T;
242 /*
243 * atphy(4) has a valid link so reset mii_ticks.
244 * Resetting mii_ticks is needed in order to
245 * detect link loss after auto-negotiation.
246 */
247 sc->mii_ticks = 0;
248 break;
249 case ATPHY_SSR_100MBS:
250 mii->mii_media_active |= IFM_100_TX;
251 sc->mii_ticks = 0;
252 break;
253 case ATPHY_SSR_10MBS:
254 mii->mii_media_active |= IFM_10_T;
255 sc->mii_ticks = 0;
256 break;
257 default:
258 mii->mii_media_active |= IFM_NONE;
259 return;
260 }
261
262 if ((ssr & ATPHY_SSR_DUPLEX) != 0)
263 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
264 else
265 mii->mii_media_active |= IFM_HDX;
266
267 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
268 (PHY_READ(sc, MII_100T2SR) & GTSR_MS_RES) != 0)
269 mii->mii_media_active |= IFM_ETH_MASTER;
270}
271
272static void
273atphy_reset(struct mii_softc *sc)
274{
275 struct ifmedia_entry *ife = sc->mii_pdata->mii_media.ifm_cur;
276 uint32_t reg;
277 int i;
278
279 /* Take PHY out of power down mode. */
280 PHY_WRITE(sc, 29, 0x29);
281 PHY_WRITE(sc, 30, 0);
282
283 reg = PHY_READ(sc, ATPHY_SCR);
284 /* Enable automatic crossover. */
285 reg |= ATPHY_SCR_AUTO_X_MODE;
286 /* Disable power down. */
287 reg &= ~ATPHY_SCR_MAC_PDOWN;
288 /* Enable CRS on Tx. */
289 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;
290 /* Auto correction for reversed cable polarity. */
291 reg |= ATPHY_SCR_POLARITY_REVERSAL;
292 PHY_WRITE(sc, ATPHY_SCR, reg);
293
294 /* Workaround F1 bug to reset phy. */
295 atphy_setmedia(sc, ife == NULL ? IFM_AUTO : ife->ifm_media);
296
297 for (i = 0; i < 1000; i++) {
298 DELAY(1);
299 if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
300 break;
301 }
302}
303
304static uint16_t
305atphy_anar(struct ifmedia_entry *ife)
306{
307 uint16_t anar;
308
309 anar = 0;
310 switch (IFM_SUBTYPE(ife->ifm_media)) {
311 case IFM_AUTO:
312 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
313 return (anar);
314 case IFM_1000_T:
315 return (anar);
316 case IFM_100_TX:
317 anar |= ANAR_TX;
318 break;
319 case IFM_10_T:
320 anar |= ANAR_10;
321 break;
322 default:
323 return (0);
324 }
325
326 if ((ife->ifm_media & IFM_FDX) != 0) {
327 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX)
328 anar |= ANAR_TX_FD;
329 else
330 anar |= ANAR_10_FD;
331 }
332
333 return (anar);
334}
335
336static int
337atphy_setmedia(struct mii_softc *sc, int media)
338{
339 uint16_t anar;
340
341 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
342 if ((IFM_SUBTYPE(media) == IFM_AUTO || (media & IFM_FDX) != 0) &&
343 ((media & IFM_FLOW) != 0 ||
344 (sc->mii_flags & MIIF_FORCEPAUSE) != 0))
345 anar |= ANAR_PAUSE_TOWARDS;
346 PHY_WRITE(sc, MII_ANAR, anar);
347 if ((sc->mii_extcapabilities &
348 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
349 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
350 GTCR_ADV_1000THDX);
351 else if (sc->mii_mpd_model == MII_MODEL_xxATHEROS_F1) {
352 /*
353 * AR8132 has 10/100 PHY and the PHY uses the same
354 * model number of F1 gigabit PHY. The PHY has no
355 * ability to establish gigabit link so explicitly
356 * disable 1000baseT configuration for the PHY.
357 * Otherwise, there is a case that atphy(4) could
358 * not establish a link against gigabit link partner
359 * unless the link partner supports down-shifting.
360 */
361 PHY_WRITE(sc, MII_100T2CR, 0);
362 }
363 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
364
365 return (EJUSTRETURN);
366}
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