| if_mgevar.h (258780) | if_mgevar.h (289945) |
|---|---|
| 1/*- 2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * | 1/*- 2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * |
| 31 * $FreeBSD: head/sys/dev/mge/if_mgevar.h 258780 2013-11-30 22:17:27Z eadler $ | 31 * $FreeBSD: head/sys/dev/mge/if_mgevar.h 289945 2015-10-25 22:00:56Z zbb $ |
| 32 */ 33 34#ifndef __IF_MGE_H__ 35#define __IF_MGE_H__ 36 | 32 */ 33 34#ifndef __IF_MGE_H__ 35#define __IF_MGE_H__ 36 |
| 37#include <arm/mv/mvvar.h> 38 |
|
| 37#define MGE_INTR_COUNT 5 /* ETH controller occupies 5 IRQ lines */ 38#define MGE_TX_DESC_NUM 256 39#define MGE_RX_DESC_NUM 256 40#define MGE_RX_QUEUE_NUM 8 41#define MGE_RX_DEFAULT_QUEUE 0 42 43#define MGE_CHECKSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 44 --- 21 unchanged lines hidden (view full) --- 66 struct ifnet *ifp; /* per-interface network data */ 67 68 phandle_t node; 69 70 device_t dev; 71 device_t miibus; 72 73 struct mii_data *mii; | 39#define MGE_INTR_COUNT 5 /* ETH controller occupies 5 IRQ lines */ 40#define MGE_TX_DESC_NUM 256 41#define MGE_RX_DESC_NUM 256 42#define MGE_RX_QUEUE_NUM 8 43#define MGE_RX_DEFAULT_QUEUE 0 44 45#define MGE_CHECKSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 46 --- 21 unchanged lines hidden (view full) --- 68 struct ifnet *ifp; /* per-interface network data */ 69 70 phandle_t node; 71 72 device_t dev; 73 device_t miibus; 74 75 struct mii_data *mii; |
| 76 struct ifmedia mge_ifmedia; |
|
| 74 struct resource *res[1 + MGE_INTR_COUNT]; /* resources */ 75 void *ih_cookie[MGE_INTR_COUNT]; /* interrupt handlers cookies */ 76 struct mtx transmit_lock; /* transmitter lock */ 77 struct mtx receive_lock; /* receiver lock */ 78 79 uint32_t mge_if_flags; 80 uint32_t mge_media_status; 81 --- 19 unchanged lines hidden (view full) --- 101 uint32_t mge_tx_arb_cfg; 102 uint32_t mge_tx_tok_cfg; 103 uint32_t mge_tx_tok_cnt; 104 uint16_t mge_mtu; 105 int mge_ver; 106 int mge_intr_cnt; 107 uint8_t mge_hw_csum; 108 | 77 struct resource *res[1 + MGE_INTR_COUNT]; /* resources */ 78 void *ih_cookie[MGE_INTR_COUNT]; /* interrupt handlers cookies */ 79 struct mtx transmit_lock; /* transmitter lock */ 80 struct mtx receive_lock; /* receiver lock */ 81 82 uint32_t mge_if_flags; 83 uint32_t mge_media_status; 84 --- 19 unchanged lines hidden (view full) --- 104 uint32_t mge_tx_arb_cfg; 105 uint32_t mge_tx_tok_cfg; 106 uint32_t mge_tx_tok_cnt; 107 uint16_t mge_mtu; 108 int mge_ver; 109 int mge_intr_cnt; 110 uint8_t mge_hw_csum; 111 |
| 112 int phy_attached; 113 int switch_attached; |
|
| 109 struct mge_softc *phy_sc; 110}; 111 112 113/* bus access macros */ 114#define MGE_READ(sc,reg) bus_read_4((sc)->res[0], (reg)) 115#define MGE_WRITE(sc,reg,val) bus_write_4((sc)->res[0], (reg), (val)) 116 --- 28 unchanged lines hidden (view full) --- 145 MGE_TRANSMIT_UNLOCK(sc); \ 146} while (0) 147 148#define MGE_GLOBAL_LOCK_ASSERT(sc) do { \ 149 MGE_TRANSMIT_LOCK_ASSERT(sc); \ 150 MGE_RECEIVE_LOCK_ASSERT(sc); \ 151} while (0) 152 | 114 struct mge_softc *phy_sc; 115}; 116 117 118/* bus access macros */ 119#define MGE_READ(sc,reg) bus_read_4((sc)->res[0], (reg)) 120#define MGE_WRITE(sc,reg,val) bus_write_4((sc)->res[0], (reg), (val)) 121 --- 28 unchanged lines hidden (view full) --- 150 MGE_TRANSMIT_UNLOCK(sc); \ 151} while (0) 152 153#define MGE_GLOBAL_LOCK_ASSERT(sc) do { \ 154 MGE_TRANSMIT_LOCK_ASSERT(sc); \ 155 MGE_RECEIVE_LOCK_ASSERT(sc); \ 156} while (0) 157 |
| 158#define MGE_SMI_LOCK() do { \ 159 sx_assert(&sx_smi, SA_UNLOCKED); \ 160 sx_xlock(&sx_smi); \ 161} while (0) 162 163#define MGE_SMI_UNLOCK() sx_unlock(&sx_smi) 164#define MGE_SMI_LOCK_ASSERT() sx_assert(&sx_smi, SA_XLOCKED) 165 |
|
| 153/* SMI-related macros */ 154#define MGE_REG_PHYDEV 0x000 155#define MGE_REG_SMI 0x004 156#define MGE_SMI_READ (1 << 26) 157#define MGE_SMI_WRITE (0 << 26) 158#define MGE_SMI_READVALID (1 << 27) 159#define MGE_SMI_BUSY (1 << 28) 160 | 166/* SMI-related macros */ 167#define MGE_REG_PHYDEV 0x000 168#define MGE_REG_SMI 0x004 169#define MGE_SMI_READ (1 << 26) 170#define MGE_SMI_WRITE (0 << 26) 171#define MGE_SMI_READVALID (1 << 27) 172#define MGE_SMI_BUSY (1 << 28) 173 |
| 174#define MGE_SMI_MASK 0x1fffffff 175#define MGE_SMI_DATA_MASK 0xffff 176#define MGE_SMI_DELAY 1000 177 178#define MGE_SWITCH_PHYDEV 6 179 180/* Internal Switch SMI Command */ 181 182#define SW_SMI_READ_CMD(phy, reg) ((1 << 15) | (1 << 12) | (1 << 11) | (phy << 5) | reg) 183#define SW_SMI_WRITE_CMD(phy, reg) ((1 << 15) | (1 << 12) | (1 << 10) | (phy << 5) | reg) 184 |
|
| 161/* TODO verify the timings and retries count w/specs */ 162#define MGE_SMI_READ_RETRIES 1000 163#define MGE_SMI_READ_DELAY 100 164#define MGE_SMI_WRITE_RETRIES 1000 165#define MGE_SMI_WRITE_DELAY 100 166 167/* MGE registers */ 168#define MGE_INT_CAUSE 0x080 --- 186 unchanged lines hidden --- | 185/* TODO verify the timings and retries count w/specs */ 186#define MGE_SMI_READ_RETRIES 1000 187#define MGE_SMI_READ_DELAY 100 188#define MGE_SMI_WRITE_RETRIES 1000 189#define MGE_SMI_WRITE_DELAY 100 190 191/* MGE registers */ 192#define MGE_INT_CAUSE 0x080 --- 186 unchanged lines hidden --- |