| if_jmereg.h (215847) | if_jmereg.h (216551) |
|---|---|
| 1/*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 10 unchanged lines hidden (view full) --- 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * | 1/*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 10 unchanged lines hidden (view full) --- 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * |
| 27 * $FreeBSD: head/sys/dev/jme/if_jmereg.h 215847 2010-11-26 01:48:29Z yongari $ | 27 * $FreeBSD: head/sys/dev/jme/if_jmereg.h 216551 2010-12-18 23:52:50Z yongari $ |
| 28 */ 29 30#ifndef _IF_JMEREG_H 31#define _IF_JMEREG_H 32 33/* 34 * JMicron Inc. PCI vendor ID 35 */ --- 22 unchanged lines hidden (view full) --- 58#define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */ 59 60#define JME_PCI_BAR3 0x20 /* 64KB memory window. */ 61 62#define JME_PCI_EROM 0x30 63 64#define JME_PCI_DBG 0x9C 65 | 28 */ 29 30#ifndef _IF_JMEREG_H 31#define _IF_JMEREG_H 32 33/* 34 * JMicron Inc. PCI vendor ID 35 */ --- 22 unchanged lines hidden (view full) --- 58#define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */ 59 60#define JME_PCI_BAR3 0x20 /* 64KB memory window. */ 61 62#define JME_PCI_EROM 0x30 63 64#define JME_PCI_DBG 0x9C 65 |
| 66#define JME_PCI_PAR0 0xA4 /* JMC25x/JMC26x REVFM >= 5 */ 67 68#define JME_PCI_PAR1 0xA8 /* JMC25x/JMC26x REVFM >= 5 */ 69 |
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| 66#define JME_PCI_SPI 0xB0 67 68#define SPI_ENB 0x00000010 69#define SPI_SO_STATUS 0x00000008 70#define SPI_SI_CTRL 0x00000004 71#define SPI_SCK_CTRL 0x00000002 72#define SPI_CS_N_CTRL 0x00000001 73 | 70#define JME_PCI_SPI 0xB0 71 72#define SPI_ENB 0x00000010 73#define SPI_SO_STATUS 0x00000008 74#define SPI_SI_CTRL 0x00000004 75#define SPI_SCK_CTRL 0x00000002 76#define SPI_CS_N_CTRL 0x00000001 77 |
| 78#define JME_EFUSE_CTL1 0xB8 79#define EFUSE_CTL1_DATA_MASK 0xF0000000 80#define EFUSE_CTL1_EXECUTE 0x08000000 81#define EFUSE_CTL1_CMD_AUTOLOAD 0x02000000 82#define EFUSE_CTL1_CMD_READ 0x04000000 83#define EFUSE_CTL1_CMD_BLOW 0x06000000 84#define EFUSE_CTL1_CMD_MASK 0x06000000 85#define EFUSE_CTL1_AUTOLOAD_ERR 0x00010000 86#define EFUSE_CTL1_BYTE_SEL_MASK 0x0000FF00 87#define EFUSE_CTL1_BIT_SEL_MASK 0x00000070 88#define EFUSE_CTL1_AUTOLAOD_DONE 0x00000001 89 90#define JME_EFUSE_CTL2 0xBC 91#define EFUSE_CTL2_RESET 0x00008000 92 |
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| 74#define JME_PCI_PHYCFG0 0xC0 75 76#define JME_PCI_PHYCFG1 0xC4 77 78#define JME_PCI_PHYCFG2 0xC8 79 80#define JME_PCI_PHYCFG3 0xCC 81 82#define JME_PCI_PIPECTL1 0xD0 83 84#define JME_PCI_PIPECTL2 0xD4 85 86/* PCIe link error/status. */ 87#define JME_PCI_LES 0xD8 88 | 93#define JME_PCI_PHYCFG0 0xC0 94 95#define JME_PCI_PHYCFG1 0xC4 96 97#define JME_PCI_PHYCFG2 0xC8 98 99#define JME_PCI_PHYCFG3 0xCC 100 101#define JME_PCI_PIPECTL1 0xD0 102 103#define JME_PCI_PIPECTL2 0xD4 104 105/* PCIe link error/status. */ 106#define JME_PCI_LES 0xD8 107 |
| 89/* propeietary register 0. */ | 108/* Proprietary register 0. */ |
| 90#define JME_PCI_PE0 0xE0 91#define PE0_SPI_EXIST 0x00200000 92#define PE0_PME_D0 0x00100000 93#define PE0_PME_D3H 0x00080000 94#define PE0_PME_SPI_PAD 0x00040000 95#define PE0_MASK_ASPM 0x00020000 96#define PE0_EEPROM_RW_DIS 0x00008000 97#define PE0_PCI_INTA 0x00001000 --- 12 unchanged lines hidden (view full) --- 110#define PE0_MSIX_SIZE_DEF 0x00000700 111#define PE0_MSIX_CAP_DIS 0x00000080 112#define PE0_MSI_PVMC_ENB 0x00000040 113#define PE0_LCAP_EXIT_LAT_MASK 0x00000038 114#define PE0_LCAP_EXIT_LAT_DEF 0x00000038 115#define PE0_PM_AUXC_MASK 0x00000007 116#define PE0_PM_AUXC_DEF 0x00000007 117 | 109#define JME_PCI_PE0 0xE0 110#define PE0_SPI_EXIST 0x00200000 111#define PE0_PME_D0 0x00100000 112#define PE0_PME_D3H 0x00080000 113#define PE0_PME_SPI_PAD 0x00040000 114#define PE0_MASK_ASPM 0x00020000 115#define PE0_EEPROM_RW_DIS 0x00008000 116#define PE0_PCI_INTA 0x00001000 --- 12 unchanged lines hidden (view full) --- 129#define PE0_MSIX_SIZE_DEF 0x00000700 130#define PE0_MSIX_CAP_DIS 0x00000080 131#define PE0_MSI_PVMC_ENB 0x00000040 132#define PE0_LCAP_EXIT_LAT_MASK 0x00000038 133#define PE0_LCAP_EXIT_LAT_DEF 0x00000038 134#define PE0_PM_AUXC_MASK 0x00000007 135#define PE0_PM_AUXC_DEF 0x00000007 136 |
| 137/* Proprietary register 1. */ |
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| 118#define JME_PCI_PE1 0xE4 | 138#define JME_PCI_PE1 0xE4 |
| 139#define PE1_GIGA_PDOWN_MASK 0x0000C000 140#define PE1_GIGA_PDOWN_DIS 0x00000000 141#define PE1_GIGA_PDOWN_D3 0x00004000 142#define PE1_GIGA_PDOWN_PCIE_SHUTDOWN 0x00008000 143#define PE1_GIGA_PDOWN_PCIE_IDDQ 0x0000C000 |
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| 119 | 144 |
| 145#define JME_EFUSE_EEPROM 0xE8 146#define JME_EFUSE_EEPROM_WRITE 0x80000000 147#define JME_EFUSE_EEPROM_FUNC_MASK 0x70000000 148#define JME_EFUSE_EEPROM_PAGE_MASK 0x0F000000 149#define JME_EFUSE_EEPROM_ADDR_MASK 0x00FF0000 150#define JME_EFUSE_EEPROM_DATA_MASK 0x0000FF00 151#define JME_EFUSE_EEPROM_SMBSTAT_MASK 0x000000FF 152#define JME_EFUSE_EEPROM_FUNC_SHIFT 28 153#define JME_EFUSE_EEPROM_PAGE_SHIFT 24 154#define JME_EFUSE_EEPROM_ADDR_SHIFT 16 155#define JME_EFUSE_EEPROM_DATA_SHIFT 8 156#define JME_EFUSE_EEPROM_SMBSTAT_SHIFT 0 157 158#define JME_EFUSE_EEPROM_FUNC0 0 159#define JME_EFUSE_EEPROM_PAGE_BAR0 0 160#define JME_EFUSE_EEPROM_PAGE_BAR1 1 161#define JME_EFUSE_EEPROM_PAGE_BAR2 2 162 |
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| 120#define JME_PCI_PHYTEST 0xF8 121 122#define JME_PCI_GPR 0xFC 123 124/* 125 * JMC Register Map. 126 * ----------------------------------------------------------------------- 127 * Register Size IO space Memory space --- 179 unchanged lines hidden (view full) --- 307#define RXMAC_ALLMULTI 0x00000080 308#define RXMAC_MULTICAST_FILTER 0x00000040 309#define RXMAC_COLL_DET_ENB 0x00000020 310#define RXMAC_FC_ENB 0x00000008 311#define RXMAC_VLAN_ENB 0x00000004 312#define RXMAC_PAD_10BYTES 0x00000002 313#define RXMAC_CSUM_ENB 0x00000001 314 | 163#define JME_PCI_PHYTEST 0xF8 164 165#define JME_PCI_GPR 0xFC 166 167/* 168 * JMC Register Map. 169 * ----------------------------------------------------------------------- 170 * Register Size IO space Memory space --- 179 unchanged lines hidden (view full) --- 350#define RXMAC_ALLMULTI 0x00000080 351#define RXMAC_MULTICAST_FILTER 0x00000040 352#define RXMAC_COLL_DET_ENB 0x00000020 353#define RXMAC_FC_ENB 0x00000008 354#define RXMAC_VLAN_ENB 0x00000004 355#define RXMAC_PAD_10BYTES 0x00000002 356#define RXMAC_CSUM_ENB 0x00000001 357 |
| 315/* Rx unicast MAC address. */ | 358/* Rx unicast MAC address. Read-only on JMC25x/JMC26x REVFM >= 5 */ |
| 316#define JME_PAR0 0x0038 317#define JME_PAR1 0x003C 318 319/* Rx multicast address hash table. */ 320#define JME_MAR0 0x0040 321#define JME_MAR1 0x0044 322 323/* Wakeup frame output data port. */ --- 126 unchanged lines hidden (view full) --- 450#define JME_GIGARALO 0x0408 451#define JME_GIGARAHI 0x040C 452#define JME_GIGARBLO 0x0410 453#define JME_GIGARBHI 0x0414 454#define JME_GIGARCLO 0x0418 455#define JME_GIGARCHI 0x041C 456#define JME_GIGARDLO 0x0420 457#define JME_GIGARDHI 0x0424 | 359#define JME_PAR0 0x0038 360#define JME_PAR1 0x003C 361 362/* Rx multicast address hash table. */ 363#define JME_MAR0 0x0040 364#define JME_MAR1 0x0044 365 366/* Wakeup frame output data port. */ --- 126 unchanged lines hidden (view full) --- 493#define JME_GIGARALO 0x0408 494#define JME_GIGARAHI 0x040C 495#define JME_GIGARBLO 0x0410 496#define JME_GIGARBHI 0x0414 497#define JME_GIGARCLO 0x0418 498#define JME_GIGARCHI 0x041C 499#define JME_GIGARDLO 0x0420 500#define JME_GIGARDHI 0x0424 |
| 501#define JME_PHYPOWDN 0x0424 /* JMC250/JMC260 REVFM >= 5 */ |
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| 458 459/* BIST status and control. */ 460#define JME_GIGACSR 0x0428 461#define GIGACSR_STATUS 0x40000000 462#define GIGACSR_CTRL_MASK 0x30000000 463#define GIGACSR_CTRL_DEFAULT 0x30000000 464#define GIGACSR_TX_CLK_MASK 0x0F000000 465#define GIGACSR_RX_CLK_MASK 0x00F00000 --- 156 unchanged lines hidden (view full) --- 622#define GPREG0_INTR_EVENT_ENB 0x00000080 623#define GPREG0_PME_ENB 0x00000020 624#define GPREG0_PHY_ADDR_MASK 0x0000001F 625#define GPREG0_PHY_ADDR_SHIFT 0 626#define GPREG0_PHY_ADDR 1 627 628/* General purpose register 1. */ 629#define JME_GPREG1 0x080C | 502 503/* BIST status and control. */ 504#define JME_GIGACSR 0x0428 505#define GIGACSR_STATUS 0x40000000 506#define GIGACSR_CTRL_MASK 0x30000000 507#define GIGACSR_CTRL_DEFAULT 0x30000000 508#define GIGACSR_TX_CLK_MASK 0x0F000000 509#define GIGACSR_RX_CLK_MASK 0x00F00000 --- 156 unchanged lines hidden (view full) --- 666#define GPREG0_INTR_EVENT_ENB 0x00000080 667#define GPREG0_PME_ENB 0x00000020 668#define GPREG0_PHY_ADDR_MASK 0x0000001F 669#define GPREG0_PHY_ADDR_SHIFT 0 670#define GPREG0_PHY_ADDR 1 671 672/* General purpose register 1. */ 673#define JME_GPREG1 0x080C |
| 674#define GPREG1_RX_MAC_CLK_DIS 0x04000000 /* JMC250/JMC260 REVFM >= 2 */ |
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| 630#define GPREG1_RSS_IPV6_10_100 0x00000040 /* JMC250 A2 */ 631#define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */ 632#define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */ 633#define GPREG1_INTDLY_UNIT_1US 0x00000010 /* JMC250 A1, A2 */ 634#define GPREG1_INTDLY_UNIT_256NS 0x00000008 /* JMC250 A1, A2 */ 635#define GPREG1_INTDLY_UNIT_16NS 0x00000000 /* JMC250 A1, A2 */ 636#define GPREG1_INTDLY_MASK 0x00000007 637 --- 173 unchanged lines hidden (view full) --- 811 812/* Shadow status base address high/low. */ 813#define JME_SHBASE_ADDR_HI 0x0848 814#define JME_SHBASE_ADDR_LO 0x084C 815#define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 816#define SHBASE_POST_FORCE 0x00000002 817#define SHBASE_POST_ENB 0x00000001 818 | 675#define GPREG1_RSS_IPV6_10_100 0x00000040 /* JMC250 A2 */ 676#define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */ 677#define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */ 678#define GPREG1_INTDLY_UNIT_1US 0x00000010 /* JMC250 A1, A2 */ 679#define GPREG1_INTDLY_UNIT_256NS 0x00000008 /* JMC250 A1, A2 */ 680#define GPREG1_INTDLY_UNIT_16NS 0x00000000 /* JMC250 A1, A2 */ 681#define GPREG1_INTDLY_MASK 0x00000007 682 --- 173 unchanged lines hidden (view full) --- 856 857/* Shadow status base address high/low. */ 858#define JME_SHBASE_ADDR_HI 0x0848 859#define JME_SHBASE_ADDR_LO 0x084C 860#define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 861#define SHBASE_POST_FORCE 0x00000002 862#define SHBASE_POST_ENB 0x00000001 863 |
| 864#define JME_PCDRX_BASE 0x0850 865#define JME_PCDRX_END 0x0857 866#define PCDRX_REG(x) (JME_PCDRX_BASE + (((x) / 2) * 4)) 867#define PCDRX1_TO_THROTTLE_MASK 0xFF000000 868#define PCDRX1_TO_MASK 0x00FF0000 869#define PCDRX0_TO_THROTTLE_MASK 0x0000FF00 870#define PCDRX0_TO_MASK 0x000000FF 871#define PCDRX1_TO_THROTTLE_SHIFT 24 872#define PCDRX1_TO_SHIFT 16 873#define PCDRX0_TO_THROTTLE_SHIFT 8 874#define PCDRX0_TO_SHIFT 0 875#define PCDRX_TO_MIN 1 876#define PCDRX_TO_MAX 255 877 878#define JME_PCDTX 0x0858 879#define PCDTX_TO_THROTTLE_MASK 0x0000FF00 880#define PCDTX_TO_MASK 0x000000FF 881#define PCDTX_TO_THROTTLE_SHIFT 8 882#define PCDTX_TO_SHIFT 0 883#define PCDTX_TO_MIN 1 884#define PCDTX_TO_MAX 255 885 886#define JME_PCCPCD_STAT 0x085C 887#define PCCPCD_STAT_RX3_MASK 0xFF000000 888#define PCCPCD_STAT_RX2_MASK 0x00FF0000 889#define PCCPCD_STAT_RX1_MASK 0x0000FF00 890#define PCCPCD_STAT_RX0_MASK 0x000000FF 891#define PCCPCD_STAT_RX3_SHIFT 24 892#define PCCPCD_STAT_RX2_SHIFT 16 893#define PCCPCD_STAT_RX1_SHIFT 8 894#define PCCPCD_STAT_RX0_SHIFT 0 895 896/* TX data throughput in KB. */ 897#define JME_TX_THROUGHPUT 0x0860 898#define TX_THROUGHPUT_MASK 0x000FFFFF 899 900/* RX data throughput in KB. */ 901#define JME_RX_THROUGHPUT 0x0864 902#define RX_THROUGHPUT_MASK 0x000FFFFF 903 904#define JME_LPI_CTL 0x086C 905#define LPI_STAT_ANC_ANF 0x00000010 906#define LPI_STAT_AN_TIMEOUT 0x00000008 907#define LPI_STAT_RX_LPI 0x00000004 908#define LPI_INT_ENB 0x00000002 909#define LPI_REQ 0x00000001 910 |
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| 819/* Timer 1 and 2. */ 820#define JME_TIMER1 0x0870 821#define JME_TIMER2 0x0874 822#define TIMER_ENB 0x01000000 823#define TIMER_CNT_MASK 0x00FFFFFF 824#define TIMER_CNT_SHIFT 0 825#define TIMER_UNIT 1024 /* 1024us */ 826 | 911/* Timer 1 and 2. */ 912#define JME_TIMER1 0x0870 913#define JME_TIMER2 0x0874 914#define TIMER_ENB 0x01000000 915#define TIMER_CNT_MASK 0x00FFFFFF 916#define TIMER_CNT_SHIFT 0 917#define TIMER_UNIT 1024 /* 1024us */ 918 |
| 919/* Timer 3. */ 920#define JME_TIMER3 0x0878 921#define TIMER3_TIMEOUT 0x00010000 922#define TIMER3_TIMEOUT_COUNT_MASK 0x0000FF00 /* 130ms unit */ 923#define TIMER3_TIMEOUT_VAL_MASK 0x000000E0 924#define TIMER3_ENB 0x00000001 925#define TIMER3_TIMEOUT_COUNT_SHIFT 8 926#define TIMER3_TIMEOUT_VALUE_SHIFT 1 927 |
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| 827/* Aggresive power mode control. */ 828#define JME_APMC 0x087C 829#define APMC_PCIE_SDOWN_STAT 0x80000000 830#define APMC_PCIE_SDOWN_ENB 0x40000000 831#define APMC_PSEUDO_HOT_PLUG 0x20000000 832#define APMC_EXT_PLUGIN_ENB 0x04000000 833#define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 834#define APMC_DIS_SRAM 0x00000004 --- 239 unchanged lines hidden --- | 928/* Aggresive power mode control. */ 929#define JME_APMC 0x087C 930#define APMC_PCIE_SDOWN_STAT 0x80000000 931#define APMC_PCIE_SDOWN_ENB 0x40000000 932#define APMC_PSEUDO_HOT_PLUG 0x20000000 933#define APMC_EXT_PLUGIN_ENB 0x04000000 934#define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 935#define APMC_DIS_SRAM 0x00000004 --- 239 unchanged lines hidden --- |