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if_jme.c (216550) if_jme.c (216551)
1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/dev/jme/if_jme.c 216550 2010-12-18 23:26:38Z yongari $");
29__FBSDID("$FreeBSD: head/sys/dev/jme/if_jme.c 216551 2010-12-18 23:52:50Z yongari $");
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bus.h>
34#include <sys/endian.h>
35#include <sys/kernel.h>
36#include <sys/malloc.h>
37#include <sys/mbuf.h>

--- 54 unchanged lines hidden (view full) ---

92 * Devices supported by this driver.
93 */
94static struct jme_dev {
95 uint16_t jme_vendorid;
96 uint16_t jme_deviceid;
97 const char *jme_name;
98} jme_devs[] = {
99 { VENDORID_JMICRON, DEVICEID_JMC250,
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bus.h>
34#include <sys/endian.h>
35#include <sys/kernel.h>
36#include <sys/malloc.h>
37#include <sys/mbuf.h>

--- 54 unchanged lines hidden (view full) ---

92 * Devices supported by this driver.
93 */
94static struct jme_dev {
95 uint16_t jme_vendorid;
96 uint16_t jme_deviceid;
97 const char *jme_name;
98} jme_devs[] = {
99 { VENDORID_JMICRON, DEVICEID_JMC250,
100 "JMicron Inc, JMC250 Gigabit Ethernet" },
100 "JMicron Inc, JMC25x Gigabit Ethernet" },
101 { VENDORID_JMICRON, DEVICEID_JMC260,
101 { VENDORID_JMICRON, DEVICEID_JMC260,
102 "JMicron Inc, JMC260 Fast Ethernet" },
102 "JMicron Inc, JMC26x Fast Ethernet" },
103};
104
105static int jme_miibus_readreg(device_t, int, int);
106static int jme_miibus_writereg(device_t, int, int, int);
107static void jme_miibus_statchg(device_t);
108static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
109static int jme_mediachange(struct ifnet *);
110static int jme_probe(device_t);
111static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
112static int jme_eeprom_macaddr(struct jme_softc *);
103};
104
105static int jme_miibus_readreg(device_t, int, int);
106static int jme_miibus_writereg(device_t, int, int, int);
107static void jme_miibus_statchg(device_t);
108static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
109static int jme_mediachange(struct ifnet *);
110static int jme_probe(device_t);
111static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
112static int jme_eeprom_macaddr(struct jme_softc *);
113static int jme_efuse_macaddr(struct jme_softc *);
113static void jme_reg_macaddr(struct jme_softc *);
114static void jme_reg_macaddr(struct jme_softc *);
115static void jme_set_macaddr(struct jme_softc *, uint8_t *);
114static void jme_map_intr_vector(struct jme_softc *);
115static int jme_attach(device_t);
116static int jme_detach(device_t);
117static void jme_sysctl_node(struct jme_softc *);
118static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int);
119static int jme_dma_alloc(struct jme_softc *);
120static void jme_dma_free(struct jme_softc *);
121static int jme_shutdown(device_t);

--- 25 unchanged lines hidden (view full) ---

147static void jme_init_tx_ring(struct jme_softc *);
148static void jme_init_ssb(struct jme_softc *);
149static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *);
150static void jme_set_vlan(struct jme_softc *);
151static void jme_set_filter(struct jme_softc *);
152static void jme_stats_clear(struct jme_softc *);
153static void jme_stats_save(struct jme_softc *);
154static void jme_stats_update(struct jme_softc *);
116static void jme_map_intr_vector(struct jme_softc *);
117static int jme_attach(device_t);
118static int jme_detach(device_t);
119static void jme_sysctl_node(struct jme_softc *);
120static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int);
121static int jme_dma_alloc(struct jme_softc *);
122static void jme_dma_free(struct jme_softc *);
123static int jme_shutdown(device_t);

--- 25 unchanged lines hidden (view full) ---

149static void jme_init_tx_ring(struct jme_softc *);
150static void jme_init_ssb(struct jme_softc *);
151static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *);
152static void jme_set_vlan(struct jme_softc *);
153static void jme_set_filter(struct jme_softc *);
154static void jme_stats_clear(struct jme_softc *);
155static void jme_stats_save(struct jme_softc *);
156static void jme_stats_update(struct jme_softc *);
157static void jme_phy_down(struct jme_softc *);
158static void jme_phy_up(struct jme_softc *);
155static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
156static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS);
157static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
158static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS);
159static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
160static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS);
161
162

--- 264 unchanged lines hidden (view full) ---

427 if (match == ETHER_ADDR_LEN) {
428 bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN);
429 return (0);
430 }
431
432 return (ENOENT);
433}
434
159static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
160static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS);
161static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
162static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS);
163static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
164static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS);
165
166

--- 264 unchanged lines hidden (view full) ---

431 if (match == ETHER_ADDR_LEN) {
432 bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN);
433 return (0);
434 }
435
436 return (ENOENT);
437}
438
439static int
440jme_efuse_macaddr(struct jme_softc *sc)
441{
442 uint32_t reg;
443 int i;
444
445 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
446 if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR | EFUSE_CTL1_AUTOLAOD_DONE)) !=
447 EFUSE_CTL1_AUTOLAOD_DONE)
448 return (ENOENT);
449 /* Reset eFuse controller. */
450 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4);
451 reg |= EFUSE_CTL2_RESET;
452 pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4);
453 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4);
454 reg &= ~EFUSE_CTL2_RESET;
455 pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4);
456
457 /* Have eFuse reload station address to MAC controller. */
458 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
459 reg &= ~EFUSE_CTL1_CMD_MASK;
460 reg |= EFUSE_CTL1_CMD_AUTOLOAD | EFUSE_CTL1_EXECUTE;
461 pci_write_config(sc->jme_dev, JME_EFUSE_CTL1, reg, 4);
462
463 /*
464 * Verify completion of eFuse autload command. It should be
465 * completed within 108us.
466 */
467 DELAY(110);
468 for (i = 10; i > 0; i--) {
469 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
470 if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR |
471 EFUSE_CTL1_AUTOLAOD_DONE)) != EFUSE_CTL1_AUTOLAOD_DONE) {
472 DELAY(20);
473 continue;
474 }
475 if ((reg & EFUSE_CTL1_EXECUTE) == 0)
476 break;
477 /* Station address loading is still in progress. */
478 DELAY(20);
479 }
480 if (i == 0) {
481 device_printf(sc->jme_dev, "eFuse autoload timed out.\n");
482 return (ETIMEDOUT);
483 }
484
485 return (0);
486}
487
435static void
436jme_reg_macaddr(struct jme_softc *sc)
437{
438 uint32_t par0, par1;
439
440 /* Read station address. */
441 par0 = CSR_READ_4(sc, JME_PAR0);
442 par1 = CSR_READ_4(sc, JME_PAR1);
443 par1 &= 0xFFFF;
444 if ((par0 == 0 && par1 == 0) ||
445 (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) {
446 device_printf(sc->jme_dev,
447 "Failed to retrieve Ethernet address.\n");
448 } else {
488static void
489jme_reg_macaddr(struct jme_softc *sc)
490{
491 uint32_t par0, par1;
492
493 /* Read station address. */
494 par0 = CSR_READ_4(sc, JME_PAR0);
495 par1 = CSR_READ_4(sc, JME_PAR1);
496 par1 &= 0xFFFF;
497 if ((par0 == 0 && par1 == 0) ||
498 (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) {
499 device_printf(sc->jme_dev,
500 "Failed to retrieve Ethernet address.\n");
501 } else {
502 /*
503 * For controllers that use eFuse, the station address
504 * could also be extracted from JME_PCI_PAR0 and
505 * JME_PCI_PAR1 registers in PCI configuration space.
506 * Each register holds exactly half of station address(24bits)
507 * so use JME_PAR0, JME_PAR1 registers instead.
508 */
449 sc->jme_eaddr[0] = (par0 >> 0) & 0xFF;
450 sc->jme_eaddr[1] = (par0 >> 8) & 0xFF;
451 sc->jme_eaddr[2] = (par0 >> 16) & 0xFF;
452 sc->jme_eaddr[3] = (par0 >> 24) & 0xFF;
453 sc->jme_eaddr[4] = (par1 >> 0) & 0xFF;
454 sc->jme_eaddr[5] = (par1 >> 8) & 0xFF;
455 }
456}
457
458static void
509 sc->jme_eaddr[0] = (par0 >> 0) & 0xFF;
510 sc->jme_eaddr[1] = (par0 >> 8) & 0xFF;
511 sc->jme_eaddr[2] = (par0 >> 16) & 0xFF;
512 sc->jme_eaddr[3] = (par0 >> 24) & 0xFF;
513 sc->jme_eaddr[4] = (par1 >> 0) & 0xFF;
514 sc->jme_eaddr[5] = (par1 >> 8) & 0xFF;
515 }
516}
517
518static void
519jme_set_macaddr(struct jme_softc *sc, uint8_t *eaddr)
520{
521 uint32_t val;
522 int i;
523
524 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) {
525 /*
526 * Avoid reprogramming station address if the address
527 * is the same as previous one. Note, reprogrammed
528 * station address is permanent as if it was written
529 * to EEPROM. So if station address was changed by
530 * admistrator it's possible to lose factory configured
531 * address when driver fails to restore its address.
532 * (e.g. reboot or system crash)
533 */
534 if (bcmp(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN) != 0) {
535 for (i = 0; i < ETHER_ADDR_LEN; i++) {
536 val = JME_EFUSE_EEPROM_FUNC0 <<
537 JME_EFUSE_EEPROM_FUNC_SHIFT;
538 val |= JME_EFUSE_EEPROM_PAGE_BAR1 <<
539 JME_EFUSE_EEPROM_PAGE_SHIFT;
540 val |= (JME_PAR0 + i) <<
541 JME_EFUSE_EEPROM_ADDR_SHIFT;
542 val |= eaddr[i] << JME_EFUSE_EEPROM_DATA_SHIFT;
543 pci_write_config(sc->jme_dev, JME_EFUSE_EEPROM,
544 val | JME_EFUSE_EEPROM_WRITE, 4);
545 }
546 }
547 } else {
548 CSR_WRITE_4(sc, JME_PAR0,
549 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
550 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
551 }
552}
553
554static void
459jme_map_intr_vector(struct jme_softc *sc)
460{
461 uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES];
462
463 bzero(map, sizeof(map));
464
465 /* Map Tx interrupts source to MSI/MSIX vector 2. */
466 map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] =

--- 62 unchanged lines hidden (view full) ---

529jme_attach(device_t dev)
530{
531 struct jme_softc *sc;
532 struct ifnet *ifp;
533 struct mii_softc *miisc;
534 struct mii_data *mii;
535 uint32_t reg;
536 uint16_t burst;
555jme_map_intr_vector(struct jme_softc *sc)
556{
557 uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES];
558
559 bzero(map, sizeof(map));
560
561 /* Map Tx interrupts source to MSI/MSIX vector 2. */
562 map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] =

--- 62 unchanged lines hidden (view full) ---

625jme_attach(device_t dev)
626{
627 struct jme_softc *sc;
628 struct ifnet *ifp;
629 struct mii_softc *miisc;
630 struct mii_data *mii;
631 uint32_t reg;
632 uint16_t burst;
537 int error, i, msic, msixc, pmc;
633 int error, i, mii_flags, msic, msixc, pmc;
538
539 error = 0;
540 sc = device_get_softc(dev);
541 sc->jme_dev = dev;
542
543 mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
544 MTX_DEF);
545 callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0);

--- 85 unchanged lines hidden (view full) ---

631 }
632 if (sc->jme_chip_rev == 0xFF) {
633 device_printf(dev, "Unknown chip revision : 0x%02x\n",
634 sc->jme_rev);
635 error = ENXIO;
636 goto fail;
637 }
638
634
635 error = 0;
636 sc = device_get_softc(dev);
637 sc->jme_dev = dev;
638
639 mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
640 MTX_DEF);
641 callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0);

--- 85 unchanged lines hidden (view full) ---

727 }
728 if (sc->jme_chip_rev == 0xFF) {
729 device_printf(dev, "Unknown chip revision : 0x%02x\n",
730 sc->jme_rev);
731 error = ENXIO;
732 goto fail;
733 }
734
735 /* Identify controller features and bugs. */
639 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) {
640 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 &&
641 CHIPMODE_REVFM(sc->jme_chip_rev) == 2)
642 sc->jme_flags |= JME_FLAG_DMA32BIT;
736 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) {
737 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 &&
738 CHIPMODE_REVFM(sc->jme_chip_rev) == 2)
739 sc->jme_flags |= JME_FLAG_DMA32BIT;
643 sc->jme_flags |= JME_FLAG_TXCLK;
740 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5)
741 sc->jme_flags |= JME_FLAG_EFUSE | JME_FLAG_PCCPCD;
742 sc->jme_flags |= JME_FLAG_TXCLK | JME_FLAG_RXCLK;
644 sc->jme_flags |= JME_FLAG_HWMIB;
645 }
646
647 /* Reset the ethernet controller. */
648 jme_reset(sc);
649
650 /* Get station address. */
743 sc->jme_flags |= JME_FLAG_HWMIB;
744 }
745
746 /* Reset the ethernet controller. */
747 jme_reset(sc);
748
749 /* Get station address. */
651 reg = CSR_READ_4(sc, JME_SMBCSR);
652 if ((reg & SMBCSR_EEPROM_PRESENT) != 0)
653 error = jme_eeprom_macaddr(sc);
654 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
655 if (error != 0 && (bootverbose))
750 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) {
751 error = jme_efuse_macaddr(sc);
752 if (error == 0)
753 jme_reg_macaddr(sc);
754 } else {
755 error = ENOENT;
756 reg = CSR_READ_4(sc, JME_SMBCSR);
757 if ((reg & SMBCSR_EEPROM_PRESENT) != 0)
758 error = jme_eeprom_macaddr(sc);
759 if (error != 0 && bootverbose)
656 device_printf(sc->jme_dev,
657 "ethernet hardware address not found in EEPROM.\n");
760 device_printf(sc->jme_dev,
761 "ethernet hardware address not found in EEPROM.\n");
658 jme_reg_macaddr(sc);
762 if (error != 0)
763 jme_reg_macaddr(sc);
659 }
660
661 /*
662 * Save PHY address.
663 * Integrated JR0211 has fixed PHY address whereas FPGA version
664 * requires PHY probing to get correct PHY address.
665 */
666 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) {

--- 56 unchanged lines hidden (view full) ---

723 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
724 ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO;
725 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
726 sc->jme_flags |= JME_FLAG_PMCAP;
727 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
728 }
729 ifp->if_capenable = ifp->if_capabilities;
730
764 }
765
766 /*
767 * Save PHY address.
768 * Integrated JR0211 has fixed PHY address whereas FPGA version
769 * requires PHY probing to get correct PHY address.
770 */
771 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) {

--- 56 unchanged lines hidden (view full) ---

828 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
829 ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO;
830 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
831 sc->jme_flags |= JME_FLAG_PMCAP;
832 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
833 }
834 ifp->if_capenable = ifp->if_capabilities;
835
836 /* Wakeup PHY. */
837 jme_phy_up(sc);
838 mii_flags = MIIF_DOPAUSE;
839 /* Ask PHY calibration to PHY driver. */
840 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5)
841 mii_flags |= MIIF_MACPRIV0;
731 /* Set up MII bus. */
732 error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange,
733 jme_mediastatus, BMSR_DEFCAPMASK,
734 sc->jme_flags & JME_FLAG_FPGA ? MII_PHY_ANY : sc->jme_phyaddr,
842 /* Set up MII bus. */
843 error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange,
844 jme_mediastatus, BMSR_DEFCAPMASK,
845 sc->jme_flags & JME_FLAG_FPGA ? MII_PHY_ANY : sc->jme_phyaddr,
735 MII_OFFSET_ANY, MIIF_DOPAUSE);
846 MII_OFFSET_ANY, mii_flags);
736 if (error != 0) {
737 device_printf(dev, "attaching PHYs failed\n");
738 goto fail;
739 }
740
741 /*
742 * Force PHY to FPGA mode.
743 */

--- 76 unchanged lines hidden (view full) ---

820 JME_LOCK(sc);
821 sc->jme_flags |= JME_FLAG_DETACH;
822 jme_stop(sc);
823 JME_UNLOCK(sc);
824 callout_drain(&sc->jme_tick_ch);
825 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
826 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task);
827 taskqueue_drain(taskqueue_swi, &sc->jme_link_task);
847 if (error != 0) {
848 device_printf(dev, "attaching PHYs failed\n");
849 goto fail;
850 }
851
852 /*
853 * Force PHY to FPGA mode.
854 */

--- 76 unchanged lines hidden (view full) ---

931 JME_LOCK(sc);
932 sc->jme_flags |= JME_FLAG_DETACH;
933 jme_stop(sc);
934 JME_UNLOCK(sc);
935 callout_drain(&sc->jme_tick_ch);
936 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
937 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task);
938 taskqueue_drain(taskqueue_swi, &sc->jme_link_task);
939 /* Restore possibly modified station address. */
940 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0)
941 jme_set_macaddr(sc, sc->jme_eaddr);
828 ether_ifdetach(ifp);
829 }
830
831 if (sc->jme_tq != NULL) {
832 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
833 taskqueue_free(sc->jme_tq);
834 sc->jme_tq = NULL;
835 }

--- 644 unchanged lines hidden (view full) ---

1480 JME_LOCK_ASSERT(sc);
1481
1482 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1483 /* Remove Tx MAC/offload clock to save more power. */
1484 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1485 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1486 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1487 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
942 ether_ifdetach(ifp);
943 }
944
945 if (sc->jme_tq != NULL) {
946 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
947 taskqueue_free(sc->jme_tq);
948 sc->jme_tq = NULL;
949 }

--- 644 unchanged lines hidden (view full) ---

1594 JME_LOCK_ASSERT(sc);
1595
1596 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1597 /* Remove Tx MAC/offload clock to save more power. */
1598 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1599 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1600 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1601 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
1602 if ((sc->jme_flags & JME_FLAG_RXCLK) != 0)
1603 CSR_WRITE_4(sc, JME_GPREG1,
1604 CSR_READ_4(sc, JME_GPREG1) | GPREG1_RX_MAC_CLK_DIS);
1488 /* No PME capability, PHY power down. */
1605 /* No PME capability, PHY power down. */
1489 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1490 MII_BMCR, BMCR_PDOWN);
1606 jme_phy_down(sc);
1491 return;
1492 }
1493
1494 ifp = sc->jme_ifp;
1495 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1496 pmcs = CSR_READ_4(sc, JME_PMCS);
1497 pmcs &= ~PMCS_WOL_ENB_MASK;
1498 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {

--- 15 unchanged lines hidden (view full) ---

1514 /* Request PME. */
1515 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1516 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1517 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1518 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1519 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1520 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1521 /* No WOL, PHY power down. */
1607 return;
1608 }
1609
1610 ifp = sc->jme_ifp;
1611 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1612 pmcs = CSR_READ_4(sc, JME_PMCS);
1613 pmcs &= ~PMCS_WOL_ENB_MASK;
1614 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {

--- 15 unchanged lines hidden (view full) ---

1630 /* Request PME. */
1631 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1632 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1633 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1634 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1635 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1636 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1637 /* No WOL, PHY power down. */
1522 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1523 MII_BMCR, BMCR_PDOWN);
1638 jme_phy_down(sc);
1524 }
1525}
1526
1527static int
1528jme_suspend(device_t dev)
1529{
1530 struct jme_softc *sc;
1531

--- 21 unchanged lines hidden (view full) ---

1553 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1554 pmstat = pci_read_config(sc->jme_dev,
1555 pmc + PCIR_POWER_STATUS, 2);
1556 /* Disable PME clear PME status. */
1557 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1558 pci_write_config(sc->jme_dev,
1559 pmc + PCIR_POWER_STATUS, pmstat, 2);
1560 }
1639 }
1640}
1641
1642static int
1643jme_suspend(device_t dev)
1644{
1645 struct jme_softc *sc;
1646

--- 21 unchanged lines hidden (view full) ---

1668 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1669 pmstat = pci_read_config(sc->jme_dev,
1670 pmc + PCIR_POWER_STATUS, 2);
1671 /* Disable PME clear PME status. */
1672 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1673 pci_write_config(sc->jme_dev,
1674 pmc + PCIR_POWER_STATUS, pmstat, 2);
1675 }
1676 /* Wakeup PHY. */
1677 jme_phy_up(sc);
1561 ifp = sc->jme_ifp;
1562 if ((ifp->if_flags & IFF_UP) != 0) {
1563 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1564 jme_init_locked(sc);
1565 }
1566
1567 JME_UNLOCK(sc);
1568

--- 636 unchanged lines hidden (view full) ---

2205 paddr = JME_RX_RING_ADDR(sc, 0);
2206 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2207 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2208
2209 /* Restart receiver/transmitter. */
2210 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
2211 RXCSR_RXQ_START);
2212 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
1678 ifp = sc->jme_ifp;
1679 if ((ifp->if_flags & IFF_UP) != 0) {
1680 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1681 jme_init_locked(sc);
1682 }
1683
1684 JME_UNLOCK(sc);
1685

--- 636 unchanged lines hidden (view full) ---

2322 paddr = JME_RX_RING_ADDR(sc, 0);
2323 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2324 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2325
2326 /* Restart receiver/transmitter. */
2327 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
2328 RXCSR_RXQ_START);
2329 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
2330 /* Lastly enable TX/RX clock. */
2331 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
2332 CSR_WRITE_4(sc, JME_GHC,
2333 CSR_READ_4(sc, JME_GHC) & ~GHC_TX_MAC_CLK_DIS);
2334 if ((sc->jme_flags & JME_FLAG_RXCLK) != 0)
2335 CSR_WRITE_4(sc, JME_GPREG1,
2336 CSR_READ_4(sc, JME_GPREG1) & ~GPREG1_RX_MAC_CLK_DIS);
2213 }
2214
2215 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2216 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2217 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2218 /* Unblock execution of task. */
2219 taskqueue_unblock(sc->jme_tq);
2220 /* Reenable interrupts. */

--- 362 unchanged lines hidden (view full) ---

2583 jme_stats_update(sc);
2584 jme_watchdog(sc);
2585 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2586}
2587
2588static void
2589jme_reset(struct jme_softc *sc)
2590{
2337 }
2338
2339 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2340 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2341 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2342 /* Unblock execution of task. */
2343 taskqueue_unblock(sc->jme_tq);
2344 /* Reenable interrupts. */

--- 362 unchanged lines hidden (view full) ---

2707 jme_stats_update(sc);
2708 jme_watchdog(sc);
2709 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2710}
2711
2712static void
2713jme_reset(struct jme_softc *sc)
2714{
2715 uint32_t ghc, gpreg;
2591
2592 /* Stop receiver, transmitter. */
2593 jme_stop_rx(sc);
2594 jme_stop_tx(sc);
2716
2717 /* Stop receiver, transmitter. */
2718 jme_stop_rx(sc);
2719 jme_stop_tx(sc);
2720
2721 /* Reset controller. */
2595 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2722 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2723 CSR_READ_4(sc, JME_GHC);
2596 DELAY(10);
2724 DELAY(10);
2597 CSR_WRITE_4(sc, JME_GHC, 0);
2725 /*
2726 * Workaround Rx FIFO overruns seen under certain conditions.
2727 * Explicitly synchorize TX/RX clock. TX/RX clock should be
2728 * enabled only after enabling TX/RX MACs.
2729 */
2730 if ((sc->jme_flags & (JME_FLAG_TXCLK | JME_FLAG_RXCLK)) != 0) {
2731 /* Disable TX clock. */
2732 CSR_WRITE_4(sc, JME_GHC, GHC_RESET | GHC_TX_MAC_CLK_DIS);
2733 /* Disable RX clock. */
2734 gpreg = CSR_READ_4(sc, JME_GPREG1);
2735 CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS);
2736 gpreg = CSR_READ_4(sc, JME_GPREG1);
2737 /* De-assert RESET but still disable TX clock. */
2738 CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS);
2739 ghc = CSR_READ_4(sc, JME_GHC);
2740
2741 /* Enable TX clock. */
2742 CSR_WRITE_4(sc, JME_GHC, ghc & ~GHC_TX_MAC_CLK_DIS);
2743 /* Enable RX clock. */
2744 CSR_WRITE_4(sc, JME_GPREG1, gpreg & ~GPREG1_RX_MAC_CLK_DIS);
2745 CSR_READ_4(sc, JME_GPREG1);
2746
2747 /* Disable TX/RX clock again. */
2748 CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS);
2749 CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS);
2750 } else
2751 CSR_WRITE_4(sc, JME_GHC, 0);
2752 CSR_READ_4(sc, JME_GHC);
2753 DELAY(10);
2598}
2599
2600static void
2601jme_init(void *xsc)
2602{
2603 struct jme_softc *sc;
2604
2605 sc = (struct jme_softc *)xsc;
2606 JME_LOCK(sc);
2607 jme_init_locked(sc);
2608 JME_UNLOCK(sc);
2609}
2610
2611static void
2612jme_init_locked(struct jme_softc *sc)
2613{
2614 struct ifnet *ifp;
2615 struct mii_data *mii;
2754}
2755
2756static void
2757jme_init(void *xsc)
2758{
2759 struct jme_softc *sc;
2760
2761 sc = (struct jme_softc *)xsc;
2762 JME_LOCK(sc);
2763 jme_init_locked(sc);
2764 JME_UNLOCK(sc);
2765}
2766
2767static void
2768jme_init_locked(struct jme_softc *sc)
2769{
2770 struct ifnet *ifp;
2771 struct mii_data *mii;
2616 uint8_t eaddr[ETHER_ADDR_LEN];
2617 bus_addr_t paddr;
2618 uint32_t reg;
2619 int error;
2620
2621 JME_LOCK_ASSERT(sc);
2622
2623 ifp = sc->jme_ifp;
2624 mii = device_get_softc(sc->jme_miibus);

--- 19 unchanged lines hidden (view full) ---

2644 jme_stop(sc);
2645 return;
2646 }
2647 jme_init_tx_ring(sc);
2648 /* Initialize shadow status block. */
2649 jme_init_ssb(sc);
2650
2651 /* Reprogram the station address. */
2772 bus_addr_t paddr;
2773 uint32_t reg;
2774 int error;
2775
2776 JME_LOCK_ASSERT(sc);
2777
2778 ifp = sc->jme_ifp;
2779 mii = device_get_softc(sc->jme_miibus);

--- 19 unchanged lines hidden (view full) ---

2799 jme_stop(sc);
2800 return;
2801 }
2802 jme_init_tx_ring(sc);
2803 /* Initialize shadow status block. */
2804 jme_init_ssb(sc);
2805
2806 /* Reprogram the station address. */
2652 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2653 CSR_WRITE_4(sc, JME_PAR0,
2654 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2655 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2807 jme_set_macaddr(sc, IF_LLADDR(sc->jme_ifp));
2656
2657 /*
2658 * Configure Tx queue.
2659 * Tx priority queue weight value : 0
2660 * Tx FIFO threshold for processing next packet : 16QW
2661 * Maximum Tx DMA length : 512
2662 * Allow Tx DMA burst.
2663 */

--- 121 unchanged lines hidden (view full) ---

2785
2786 /* Configure Rx queue 0 packet completion coalescing. */
2787 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
2788 PCCRX_COAL_TO_MASK;
2789 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
2790 PCCRX_COAL_PKT_MASK;
2791 CSR_WRITE_4(sc, JME_PCCRX0, reg);
2792
2808
2809 /*
2810 * Configure Tx queue.
2811 * Tx priority queue weight value : 0
2812 * Tx FIFO threshold for processing next packet : 16QW
2813 * Maximum Tx DMA length : 512
2814 * Allow Tx DMA burst.
2815 */

--- 121 unchanged lines hidden (view full) ---

2937
2938 /* Configure Rx queue 0 packet completion coalescing. */
2939 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
2940 PCCRX_COAL_TO_MASK;
2941 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
2942 PCCRX_COAL_PKT_MASK;
2943 CSR_WRITE_4(sc, JME_PCCRX0, reg);
2944
2945 /*
2946 * Configure PCD(Packet Completion Deferring). It seems PCD
2947 * generates an interrupt when the time interval between two
2948 * back-to-back incoming/outgoing packet is long enough for
2949 * it to reach its timer value 0. The arrival of new packets
2950 * after timer has started causes the PCD timer to restart.
2951 * Unfortunately, it's not clear how PCD is useful at this
2952 * moment, so just use the same of PCC parameters.
2953 */
2954 if ((sc->jme_flags & JME_FLAG_PCCPCD) != 0) {
2955 sc->jme_rx_pcd_to = sc->jme_rx_coal_to;
2956 if (sc->jme_rx_coal_to > PCDRX_TO_MAX)
2957 sc->jme_rx_pcd_to = PCDRX_TO_MAX;
2958 sc->jme_tx_pcd_to = sc->jme_tx_coal_to;
2959 if (sc->jme_tx_coal_to > PCDTX_TO_MAX)
2960 sc->jme_tx_pcd_to = PCDTX_TO_MAX;
2961 reg = sc->jme_rx_pcd_to << PCDRX0_TO_THROTTLE_SHIFT;
2962 reg |= sc->jme_rx_pcd_to << PCDRX0_TO_SHIFT;
2963 CSR_WRITE_4(sc, PCDRX_REG(0), reg);
2964 reg = sc->jme_tx_pcd_to << PCDTX_TO_THROTTLE_SHIFT;
2965 reg |= sc->jme_tx_pcd_to << PCDTX_TO_SHIFT;
2966 CSR_WRITE_4(sc, JME_PCDTX, reg);
2967 }
2968
2793 /* Configure shadow status block but don't enable posting. */
2794 paddr = sc->jme_rdata.jme_ssb_block_paddr;
2795 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2796 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2797
2798 /* Disable Timer 1 and Timer 2. */
2799 CSR_WRITE_4(sc, JME_TIMER1, 0);
2800 CSR_WRITE_4(sc, JME_TIMER2, 0);

--- 389 unchanged lines hidden (view full) ---

3190 stat->rx_mii_errs += ostat->rx_mii_errs;
3191 stat->rx_fifo_oflows += ostat->rx_fifo_oflows;
3192 stat->rx_desc_empty += ostat->rx_desc_empty;
3193 stat->rx_bad_frames += ostat->rx_bad_frames;
3194 stat->tx_good_frames += ostat->tx_good_frames;
3195 stat->tx_bad_frames += ostat->tx_bad_frames;
3196}
3197
2969 /* Configure shadow status block but don't enable posting. */
2970 paddr = sc->jme_rdata.jme_ssb_block_paddr;
2971 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2972 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2973
2974 /* Disable Timer 1 and Timer 2. */
2975 CSR_WRITE_4(sc, JME_TIMER1, 0);
2976 CSR_WRITE_4(sc, JME_TIMER2, 0);

--- 389 unchanged lines hidden (view full) ---

3366 stat->rx_mii_errs += ostat->rx_mii_errs;
3367 stat->rx_fifo_oflows += ostat->rx_fifo_oflows;
3368 stat->rx_desc_empty += ostat->rx_desc_empty;
3369 stat->rx_bad_frames += ostat->rx_bad_frames;
3370 stat->tx_good_frames += ostat->tx_good_frames;
3371 stat->tx_bad_frames += ostat->tx_bad_frames;
3372}
3373
3374static void
3375jme_phy_down(struct jme_softc *sc)
3376{
3377 uint32_t reg;
3378
3379 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, BMCR_PDOWN);
3380 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) {
3381 reg = CSR_READ_4(sc, JME_PHYPOWDN);
3382 reg |= 0x0000000F;
3383 CSR_WRITE_4(sc, JME_PHYPOWDN, reg);
3384 reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4);
3385 reg &= ~PE1_GIGA_PDOWN_MASK;
3386 reg |= PE1_GIGA_PDOWN_D3;
3387 pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4);
3388 }
3389}
3390
3391static void
3392jme_phy_up(struct jme_softc *sc)
3393{
3394 uint32_t reg;
3395 uint16_t bmcr;
3396
3397 bmcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR);
3398 bmcr &= ~BMCR_PDOWN;
3399 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, bmcr);
3400 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) {
3401 reg = CSR_READ_4(sc, JME_PHYPOWDN);
3402 reg &= ~0x0000000F;
3403 CSR_WRITE_4(sc, JME_PHYPOWDN, reg);
3404 reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4);
3405 reg &= ~PE1_GIGA_PDOWN_MASK;
3406 reg |= PE1_GIGA_PDOWN_DIS;
3407 pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4);
3408 }
3409}
3410
3198static int
3199sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3200{
3201 int error, value;
3202
3203 if (arg1 == NULL)
3204 return (EINVAL);
3205 value = *(int *)arg1;

--- 44 unchanged lines hidden --- 		3411static int
3412sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3413{
3414 int error, value;
3415
3416 if (arg1 == NULL)
3417 return (EINVAL);
3418 value = *(int *)arg1;

--- 44 unchanged lines hidden ---