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ixgbe_x540.c (247822) ixgbe_x540.c (251964)
1/******************************************************************************
2
3 Copyright (c) 2001-2013, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2013, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 247822 2013-03-04 23:07:40Z jfv $*/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 251964 2013-06-18 21:28:19Z jfv $*/
34
35#include "ixgbe_x540.h"
36#include "ixgbe_type.h"
37#include "ixgbe_api.h"
38#include "ixgbe_common.h"
39#include "ixgbe_phy.h"
40
34
35#include "ixgbe_x540.h"
36#include "ixgbe_type.h"
37#include "ixgbe_api.h"
38#include "ixgbe_common.h"
39#include "ixgbe_phy.h"
40
41static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
42static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
43static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
44static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
45
46/**
47 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
48 * @hw: pointer to hardware structure
49 *

--- 87 unchanged lines hidden (view full) ---

137
138 /* LEDs */
139 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
140 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
141
142 /* Manageability interface */
143 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
144
41static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
42static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
43static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
44
45/**
46 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
47 * @hw: pointer to hardware structure
48 *

--- 87 unchanged lines hidden (view full) ---

136
137 /* LEDs */
138 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
139 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
140
141 /* Manageability interface */
142 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
143
144 mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
145
145 return ret_val;
146}
147
148/**
149 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
150 * @hw: pointer to hardware structure
151 * @speed: pointer to link speed
152 * @autoneg: TRUE when autoneg or autotry is enabled

--- 68 unchanged lines hidden (view full) ---

221 usec_delay(1);
222 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
223 if (!(ctrl & IXGBE_CTRL_RST_MASK))
224 break;
225 }
226
227 if (ctrl & IXGBE_CTRL_RST_MASK) {
228 status = IXGBE_ERR_RESET_FAILED;
146 return ret_val;
147}
148
149/**
150 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
151 * @hw: pointer to hardware structure
152 * @speed: pointer to link speed
153 * @autoneg: TRUE when autoneg or autotry is enabled

--- 68 unchanged lines hidden (view full) ---

222 usec_delay(1);
223 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
224 if (!(ctrl & IXGBE_CTRL_RST_MASK))
225 break;
226 }
227
228 if (ctrl & IXGBE_CTRL_RST_MASK) {
229 status = IXGBE_ERR_RESET_FAILED;
229 DEBUGOUT("Reset polling failed to complete.\n");
230 ERROR_REPORT1(IXGBE_ERROR_POLLING,
231 "Reset polling failed to complete.\n");
230 }
231 msec_delay(100);
232
233 /*
234 * Double resets are required for recovery from certain error
235 * conditions. Between resets, it is necessary to stall to allow time
236 * for any pending HW events to complete.
237 */

--- 129 unchanged lines hidden (view full) ---

367 * Reads a 16 bit word from the EEPROM using the EERD register.
368 **/
369s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
370{
371 s32 status = IXGBE_SUCCESS;
372
373 DEBUGFUNC("ixgbe_read_eerd_X540");
374 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
232 }
233 msec_delay(100);
234
235 /*
236 * Double resets are required for recovery from certain error
237 * conditions. Between resets, it is necessary to stall to allow time
238 * for any pending HW events to complete.
239 */

--- 129 unchanged lines hidden (view full) ---

369 * Reads a 16 bit word from the EEPROM using the EERD register.
370 **/
371s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
372{
373 s32 status = IXGBE_SUCCESS;
374
375 DEBUGFUNC("ixgbe_read_eerd_X540");
376 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
375 IXGBE_SUCCESS)
377 IXGBE_SUCCESS) {
376 status = ixgbe_read_eerd_generic(hw, offset, data);
378 status = ixgbe_read_eerd_generic(hw, offset, data);
377 else
379 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
380 } else {
378 status = IXGBE_ERR_SWFW_SYNC;
381 status = IXGBE_ERR_SWFW_SYNC;
382 }
379
383
380 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
381 return status;
382}
383
384/**
385 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
386 * @hw: pointer to hardware structure
387 * @offset: offset of word in the EEPROM to read
388 * @words: number of words
389 * @data: word(s) read from the EEPROM
390 *
391 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
392 **/
393s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
394 u16 offset, u16 words, u16 *data)
395{
396 s32 status = IXGBE_SUCCESS;
397
398 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
399 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
384 return status;
385}
386
387/**
388 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
389 * @hw: pointer to hardware structure
390 * @offset: offset of word in the EEPROM to read
391 * @words: number of words
392 * @data: word(s) read from the EEPROM
393 *
394 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
395 **/
396s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
397 u16 offset, u16 words, u16 *data)
398{
399 s32 status = IXGBE_SUCCESS;
400
401 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
402 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
400 IXGBE_SUCCESS)
403 IXGBE_SUCCESS) {
401 status = ixgbe_read_eerd_buffer_generic(hw, offset,
402 words, data);
404 status = ixgbe_read_eerd_buffer_generic(hw, offset,
405 words, data);
403 else
406 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
407 } else {
404 status = IXGBE_ERR_SWFW_SYNC;
408 status = IXGBE_ERR_SWFW_SYNC;
409 }
405
410
406 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
407 return status;
408}
409
410/**
411 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
412 * @hw: pointer to hardware structure
413 * @offset: offset of word in the EEPROM to write
414 * @data: word write to the EEPROM
415 *
416 * Write a 16 bit word to the EEPROM using the EEWR register.
417 **/
418s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
419{
420 s32 status = IXGBE_SUCCESS;
421
422 DEBUGFUNC("ixgbe_write_eewr_X540");
423 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
411 return status;
412}
413
414/**
415 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
416 * @hw: pointer to hardware structure
417 * @offset: offset of word in the EEPROM to write
418 * @data: word write to the EEPROM
419 *
420 * Write a 16 bit word to the EEPROM using the EEWR register.
421 **/
422s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
423{
424 s32 status = IXGBE_SUCCESS;
425
426 DEBUGFUNC("ixgbe_write_eewr_X540");
427 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
424 IXGBE_SUCCESS)
428 IXGBE_SUCCESS) {
425 status = ixgbe_write_eewr_generic(hw, offset, data);
429 status = ixgbe_write_eewr_generic(hw, offset, data);
426 else
430 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
431 } else {
427 status = IXGBE_ERR_SWFW_SYNC;
432 status = IXGBE_ERR_SWFW_SYNC;
433 }
428
434
429 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
430 return status;
431}
432
433/**
434 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
435 * @hw: pointer to hardware structure
436 * @offset: offset of word in the EEPROM to write
437 * @words: number of words
438 * @data: word(s) write to the EEPROM
439 *
440 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
441 **/
442s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
443 u16 offset, u16 words, u16 *data)
444{
445 s32 status = IXGBE_SUCCESS;
446
447 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
448 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
435 return status;
436}
437
438/**
439 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
440 * @hw: pointer to hardware structure
441 * @offset: offset of word in the EEPROM to write
442 * @words: number of words
443 * @data: word(s) write to the EEPROM
444 *
445 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
446 **/
447s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
448 u16 offset, u16 words, u16 *data)
449{
450 s32 status = IXGBE_SUCCESS;
451
452 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
453 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
449 IXGBE_SUCCESS)
454 IXGBE_SUCCESS) {
450 status = ixgbe_write_eewr_buffer_generic(hw, offset,
451 words, data);
455 status = ixgbe_write_eewr_buffer_generic(hw, offset,
456 words, data);
452 else
457 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
458 } else {
453 status = IXGBE_ERR_SWFW_SYNC;
459 status = IXGBE_ERR_SWFW_SYNC;
460 }
454
461
455 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
456 return status;
457}
458
459/**
460 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
461 *
462 * This function does not use synchronization for EERD and EEWR. It can
463 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.

--- 109 unchanged lines hidden (view full) ---

573 */
574 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
575 &read_checksum);
576
577 /*
578 * Verify read checksum from EEPROM is the same as
579 * calculated checksum
580 */
462 return status;
463}
464
465/**
466 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
467 *
468 * This function does not use synchronization for EERD and EEWR. It can
469 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.

--- 109 unchanged lines hidden (view full) ---

579 */
580 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
581 &read_checksum);
582
583 /*
584 * Verify read checksum from EEPROM is the same as
585 * calculated checksum
586 */
581 if (read_checksum != checksum)
587 if (read_checksum != checksum) {
582 status = IXGBE_ERR_EEPROM_CHECKSUM;
588 status = IXGBE_ERR_EEPROM_CHECKSUM;
589 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
590 "Invalid EEPROM checksum");
591 }
583
584 /* If the user cares, return the calculated checksum */
585 if (checksum_val)
586 *checksum_val = checksum;
592
593 /* If the user cares, return the calculated checksum */
594 if (checksum_val)
595 *checksum_val = checksum;
596 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
587 } else {
588 status = IXGBE_ERR_SWFW_SYNC;
589 }
590
597 } else {
598 status = IXGBE_ERR_SWFW_SYNC;
599 }
600
591 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
592out:
593 return status;
594}
595
596/**
597 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
598 * @hw: pointer to hardware structure
599 *

--- 24 unchanged lines hidden (view full) ---

624
625 /*
626 * Do not use hw->eeprom.ops.write because we do not want to
627 * take the synchronization semaphores twice here.
628 */
629 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
630 checksum);
631
601out:
602 return status;
603}
604
605/**
606 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
607 * @hw: pointer to hardware structure
608 *

--- 24 unchanged lines hidden (view full) ---

633
634 /*
635 * Do not use hw->eeprom.ops.write because we do not want to
636 * take the synchronization semaphores twice here.
637 */
638 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
639 checksum);
640
632 if (status == IXGBE_SUCCESS)
633 status = ixgbe_update_flash_X540(hw);
634 else
641 if (status == IXGBE_SUCCESS)
642 status = ixgbe_update_flash_X540(hw);
643 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
644 } else {
635 status = IXGBE_ERR_SWFW_SYNC;
636 }
637
645 status = IXGBE_ERR_SWFW_SYNC;
646 }
647
638 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
639
640 return status;
641}
642
643/**
644 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
645 * @hw: pointer to hardware structure
646 *
647 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
648 * EEPROM from shadow RAM to the flash device.
649 **/
648 return status;
649}
650
651/**
652 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
653 * @hw: pointer to hardware structure
654 *
655 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
656 * EEPROM from shadow RAM to the flash device.
657 **/
650static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
658s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
651{
652 u32 flup;
653 s32 status = IXGBE_ERR_EEPROM;
654
655 DEBUGFUNC("ixgbe_update_flash_X540");
656
657 status = ixgbe_poll_flash_update_done_X540(hw);
658 if (status == IXGBE_ERR_EEPROM) {

--- 5 unchanged lines hidden (view full) ---

664 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
665
666 status = ixgbe_poll_flash_update_done_X540(hw);
667 if (status == IXGBE_SUCCESS)
668 DEBUGOUT("Flash update complete\n");
669 else
670 DEBUGOUT("Flash update time out\n");
671
659{
660 u32 flup;
661 s32 status = IXGBE_ERR_EEPROM;
662
663 DEBUGFUNC("ixgbe_update_flash_X540");
664
665 status = ixgbe_poll_flash_update_done_X540(hw);
666 if (status == IXGBE_ERR_EEPROM) {

--- 5 unchanged lines hidden (view full) ---

672 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
673
674 status = ixgbe_poll_flash_update_done_X540(hw);
675 if (status == IXGBE_SUCCESS)
676 DEBUGOUT("Flash update complete\n");
677 else
678 DEBUGOUT("Flash update time out\n");
679
672 if (hw->revision_id == 0) {
680 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
673 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
674
675 if (flup & IXGBE_EEC_SEC1VAL) {
676 flup |= IXGBE_EEC_FLUP;
677 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
678 }
679
680 status = ixgbe_poll_flash_update_done_X540(hw);

--- 24 unchanged lines hidden (view full) ---

705 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
706 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
707 if (reg & IXGBE_EEC_FLUDONE) {
708 status = IXGBE_SUCCESS;
709 break;
710 }
711 usec_delay(5);
712 }
681 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
682
683 if (flup & IXGBE_EEC_SEC1VAL) {
684 flup |= IXGBE_EEC_FLUP;
685 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
686 }
687
688 status = ixgbe_poll_flash_update_done_X540(hw);

--- 24 unchanged lines hidden (view full) ---

713 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
714 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
715 if (reg & IXGBE_EEC_FLUDONE) {
716 status = IXGBE_SUCCESS;
717 break;
718 }
719 usec_delay(5);
720 }
721
722 if (i == IXGBE_FLUDONE_ATTEMPTS)
723 ERROR_REPORT1(IXGBE_ERROR_POLLING,
724 "Flash update status polling timed out");
725
713 return status;
714}
715
716/**
717 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
718 * @hw: pointer to hardware structure
719 * @mask: Mask to specify which semaphore to acquire
720 *

--- 29 unchanged lines hidden (view full) ---

750 goto out;
751 }
752
753 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
754 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
755 swfw_sync |= swmask;
756 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
757 ixgbe_release_swfw_sync_semaphore(hw);
726 return status;
727}
728
729/**
730 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
731 * @hw: pointer to hardware structure
732 * @mask: Mask to specify which semaphore to acquire
733 *

--- 29 unchanged lines hidden (view full) ---

763 goto out;
764 }
765
766 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
767 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
768 swfw_sync |= swmask;
769 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
770 ixgbe_release_swfw_sync_semaphore(hw);
758 msec_delay(5);
759 goto out;
760 } else {
761 /*
762 * Firmware currently using resource (fwmask), hardware
763 * currently using resource (hwmask), or other software
764 * thread currently using resource (swmask)
765 */
766 ixgbe_release_swfw_sync_semaphore(hw);
767 msec_delay(5);
768 }
769 }
770
771 /* Failed to get SW only semaphore */
772 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
773 ret_val = IXGBE_ERR_SWFW_SYNC;
771 goto out;
772 } else {
773 /*
774 * Firmware currently using resource (fwmask), hardware
775 * currently using resource (hwmask), or other software
776 * thread currently using resource (swmask)
777 */
778 ixgbe_release_swfw_sync_semaphore(hw);
779 msec_delay(5);
780 }
781 }
782
783 /* Failed to get SW only semaphore */
784 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
785 ret_val = IXGBE_ERR_SWFW_SYNC;
786 ERROR_REPORT1(IXGBE_ERROR_POLLING,
787 "Failed to get SW only semaphore");
774 goto out;
775 }
776
777 /* If the resource is not released by the FW/HW the SW can assume that
788 goto out;
789 }
790
791 /* If the resource is not released by the FW/HW the SW can assume that
778 * the FW/HW malfunctions. In that case the SW should sets the SW bit(s)
792 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
779 * of the requested resource(s) while ignoring the corresponding FW/HW
780 * bits in the SW_FW_SYNC register.
781 */
782 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
783 if (swfw_sync & (fwmask | hwmask)) {
784 if (ixgbe_get_swfw_sync_semaphore(hw)) {
785 ret_val = IXGBE_ERR_SWFW_SYNC;
786 goto out;
787 }
788
789 swfw_sync |= swmask;
790 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
791 ixgbe_release_swfw_sync_semaphore(hw);
792 msec_delay(5);
793 }
793 * of the requested resource(s) while ignoring the corresponding FW/HW
794 * bits in the SW_FW_SYNC register.
795 */
796 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
797 if (swfw_sync & (fwmask | hwmask)) {
798 if (ixgbe_get_swfw_sync_semaphore(hw)) {
799 ret_val = IXGBE_ERR_SWFW_SYNC;
800 goto out;
801 }
802
803 swfw_sync |= swmask;
804 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
805 ixgbe_release_swfw_sync_semaphore(hw);
806 msec_delay(5);
807 }
808 /* If the resource is not released by other SW the SW can assume that
809 * the other SW malfunctions. In that case the SW should clear all SW
810 * flags that it does not own and then repeat the whole process once
811 * again.
812 */
813 else if (swfw_sync & swmask) {
814 ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM |
815 IXGBE_GSSR_PHY0_SM | IXGBE_GSSR_PHY1_SM |
816 IXGBE_GSSR_MAC_CSR_SM);
817 ret_val = IXGBE_ERR_SWFW_SYNC;
818 }
794
795out:
796 return ret_val;
797}
798
799/**
800 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
801 * @hw: pointer to hardware structure

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813
814 ixgbe_get_swfw_sync_semaphore(hw);
815
816 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
817 swfw_sync &= ~swmask;
818 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
819
820 ixgbe_release_swfw_sync_semaphore(hw);
819
820out:
821 return ret_val;
822}
823
824/**
825 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
826 * @hw: pointer to hardware structure

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838
839 ixgbe_get_swfw_sync_semaphore(hw);
840
841 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
842 swfw_sync &= ~swmask;
843 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
844
845 ixgbe_release_swfw_sync_semaphore(hw);
821 msec_delay(5);
822}
823
824/**
825 * ixgbe_get_nvm_semaphore - Get hardware semaphore
826 * @hw: pointer to hardware structure
827 *
828 * Sets the hardware semaphores so SW/FW can gain control of shared resources
829 **/

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860 usec_delay(50);
861 }
862
863 /*
864 * Release semaphores and return error if SW NVM semaphore
865 * was not granted because we don't have access to the EEPROM
866 */
867 if (i >= timeout) {
846}
847
848/**
849 * ixgbe_get_nvm_semaphore - Get hardware semaphore
850 * @hw: pointer to hardware structure
851 *
852 * Sets the hardware semaphores so SW/FW can gain control of shared resources
853 **/

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884 usec_delay(50);
885 }
886
887 /*
888 * Release semaphores and return error if SW NVM semaphore
889 * was not granted because we don't have access to the EEPROM
890 */
891 if (i >= timeout) {
868 DEBUGOUT("REGSMP Software NVM semaphore not "
869 "granted.\n");
892 ERROR_REPORT1(IXGBE_ERROR_POLLING,
893 "REGSMP Software NVM semaphore not granted.\n");
870 ixgbe_release_swfw_sync_semaphore(hw);
871 status = IXGBE_ERR_EEPROM;
872 }
873 } else {
894 ixgbe_release_swfw_sync_semaphore(hw);
895 status = IXGBE_ERR_EEPROM;
896 }
897 } else {
874 DEBUGOUT("Software semaphore SMBI between device drivers "
875 "not granted.\n");
898 ERROR_REPORT1(IXGBE_ERROR_POLLING,
899 "Software semaphore SMBI between device drivers "
900 "not granted.\n");
876 }
877
878 return status;
879}
880
881/**
882 * ixgbe_release_nvm_semaphore - Release hardware semaphore
883 * @hw: pointer to hardware structure

--- 92 unchanged lines hidden --- 		901 }
902
903 return status;
904}
905
906/**
907 * ixgbe_release_nvm_semaphore - Release hardware semaphore
908 * @hw: pointer to hardware structure

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