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ixgbe_type.h (172043) ixgbe_type.h (179055)
1/*******************************************************************************
1/******************************************************************************
2
2
3 Copyright (c) 2001-2007, Intel Corporation
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 12 unchanged lines hidden (view full) ---

24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
33/* $FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 172043 2007-09-04 02:31:35Z jfv $ */
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 179055 2008-05-16 18:46:30Z jfv $*/
34
35#ifndef _IXGBE_TYPE_H_
36#define _IXGBE_TYPE_H_
37
38#include "ixgbe_osdep.h"
39
40/* Vendor ID */
41#define IXGBE_INTEL_VENDOR_ID 0x8086
42
43/* Device IDs */
44#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
45#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
34
35#ifndef _IXGBE_TYPE_H_
36#define _IXGBE_TYPE_H_
37
38#include "ixgbe_osdep.h"
39
40/* Vendor ID */
41#define IXGBE_INTEL_VENDOR_ID 0x8086
42
43/* Device IDs */
44#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
45#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
46#define IXGBE_DEV_ID_82598AT 0x10C8
47#define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10D7
46#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
48#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
49#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
50#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
51#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
52#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
47
48/* General Registers */
49#define IXGBE_CTRL 0x00000
50#define IXGBE_STATUS 0x00008
51#define IXGBE_CTRL_EXT 0x00018
52#define IXGBE_ESDP 0x00020
53#define IXGBE_EODSDP 0x00028
54#define IXGBE_LEDCTL 0x00200

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69
70/* Interrupt Registers */
71#define IXGBE_EICR 0x00800
72#define IXGBE_EICS 0x00808
73#define IXGBE_EIMS 0x00880
74#define IXGBE_EIMC 0x00888
75#define IXGBE_EIAC 0x00810
76#define IXGBE_EIAM 0x00890
53
54/* General Registers */
55#define IXGBE_CTRL 0x00000
56#define IXGBE_STATUS 0x00008
57#define IXGBE_CTRL_EXT 0x00018
58#define IXGBE_ESDP 0x00020
59#define IXGBE_EODSDP 0x00028
60#define IXGBE_LEDCTL 0x00200

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75
76/* Interrupt Registers */
77#define IXGBE_EICR 0x00800
78#define IXGBE_EICS 0x00808
79#define IXGBE_EIMS 0x00880
80#define IXGBE_EIMC 0x00888
81#define IXGBE_EIAC 0x00810
82#define IXGBE_EIAM 0x00890
77#define IXGBE_EITR(_i) (0x00820 + ((_i) * 4)) /* 0x820-0x86c */
78#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
83#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : (0x012300 + ((_i) * 4)))
84#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
79#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
80#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
85#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
86#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
81#define IXGBE_PBACL 0x11068
87#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
82#define IXGBE_GPIE 0x00898
83
84/* Flow Control Registers */
85#define IXGBE_PFCTOP 0x03008
86#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
87#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
88#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
89#define IXGBE_FCRTV 0x032A0
90#define IXGBE_TFCS 0x0CE00
91
92/* Receive DMA Registers */
88#define IXGBE_GPIE 0x00898
89
90/* Flow Control Registers */
91#define IXGBE_PFCTOP 0x03008
92#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
93#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
94#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
95#define IXGBE_FCRTV 0x032A0
96#define IXGBE_TFCS 0x0CE00
97
98/* Receive DMA Registers */
93#define IXGBE_RDBAL(_i) (0x01000 + ((_i) * 0x40)) /* 64 of each (0-63)*/
94#define IXGBE_RDBAH(_i) (0x01004 + ((_i) * 0x40))
95#define IXGBE_RDLEN(_i) (0x01008 + ((_i) * 0x40))
96#define IXGBE_RDH(_i) (0x01010 + ((_i) * 0x40))
97#define IXGBE_RDT(_i) (0x01018 + ((_i) * 0x40))
98#define IXGBE_RXDCTL(_i) (0x01028 + ((_i) * 0x40))
99#define IXGBE_SRRCTL(_i) (0x02100 + ((_i) * 4))
100 /* array of 16 (0x02100-0x0213C) */
101#define IXGBE_DCA_RXCTRL(_i) (0x02200 + ((_i) * 4))
102 /* array of 16 (0x02200-0x0223C) */
99#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : (0x0D000 + ((_i - 64) * 0x40)))
100#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : (0x0D004 + ((_i - 64) * 0x40)))
101#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : (0x0D008 + ((_i - 64) * 0x40)))
102#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : (0x0D010 + ((_i - 64) * 0x40)))
103#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : (0x0D018 + ((_i - 64) * 0x40)))
104#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : (0x0D028 + ((_i - 64) * 0x40)))
105/*
106 * Split and Replication Receive Control Registers
107 * 00-15 : 0x02100 + n*4
108 * 16-64 : 0x01014 + n*0x40
109 * 64-127: 0x0D014 + (n-64)*0x40
110 */
111#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
112 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
113 (0x0D014 + ((_i - 64) * 0x40))))
114/*
115 * Rx DCA Control Register:
116 * 00-15 : 0x02200 + n*4
117 * 16-64 : 0x0100C + n*0x40
118 * 64-127: 0x0D00C + (n-64)*0x40
119 */
120#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
121 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
122 (0x0D00C + ((_i - 64) * 0x40))))
103#define IXGBE_RDRXCTL 0x02F00
104#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
123#define IXGBE_RDRXCTL 0x02F00
124#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
105 /* 8 of these 0x03C00 - 0x03C1C */
125 /* 8 of these 0x03C00 - 0x03C1C */
106#define IXGBE_RXCTRL 0x03000
107#define IXGBE_DROPEN 0x03D04
108#define IXGBE_RXPBSIZE_SHIFT 10
109
110/* Receive Registers */
111#define IXGBE_RXCSUM 0x05000
112#define IXGBE_RFCTL 0x05008
126#define IXGBE_RXCTRL 0x03000
127#define IXGBE_DROPEN 0x03D04
128#define IXGBE_RXPBSIZE_SHIFT 10
129
130/* Receive Registers */
131#define IXGBE_RXCSUM 0x05000
132#define IXGBE_RFCTL 0x05008
133/* Multicast Table Array - 128 entries */
113#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
134#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
114 /* Multicast Table Array - 128 entries */
115#define IXGBE_RAL(_i) (0x05400 + ((_i) * 8)) /* 16 of these (0-15) */
116#define IXGBE_RAH(_i) (0x05404 + ((_i) * 8)) /* 16 of these (0-15) */
117#define IXGBE_PSRTYPE 0x05480
118 /* 0x5480-0x54BC Packet split receive type */
135#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : (0x0A200 + ((_i) * 8)))
136#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : (0x0A204 + ((_i) * 8)))
137/* Packet split receive type */
138#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : (0x0EA00 + ((_i) * 4)))
139/* array of 4096 1-bit vlan filters */
119#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
140#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
120 /* array of 4096 1-bit vlan filters */
141/*array of 4096 4-bit vlan vmdq indices */
121#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
142#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
122 /*array of 4096 4-bit vlan vmdq indicies */
123#define IXGBE_FCTRL 0x05080
124#define IXGBE_VLNCTRL 0x05088
125#define IXGBE_MCSTCTRL 0x05090
126#define IXGBE_MRQC 0x05818
143#define IXGBE_FCTRL 0x05080
144#define IXGBE_VLNCTRL 0x05088
145#define IXGBE_MCSTCTRL 0x05090
146#define IXGBE_MRQC 0x05818
127#define IXGBE_VMD_CTL 0x0581C
128#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
129#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
130#define IXGBE_IMIRVP 0x05AC0
147#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
148#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
149#define IXGBE_IMIRVP 0x05AC0
150#define IXGBE_VMD_CTL 0x0581C
131#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
132#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
133
151#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
152#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
153
154
134/* Transmit DMA registers */
155/* Transmit DMA registers */
135#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40))/* 32 of these (0-31)*/
156#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
136#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
137#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
138#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
139#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
140#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
141#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
142#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
143#define IXGBE_DTXCTL 0x07E00
157#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
158#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
159#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
160#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
161#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
162#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
163#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
164#define IXGBE_DTXCTL 0x07E00
144#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4))
145 /* there are 16 of these (0-15) */
165
166#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
146#define IXGBE_TIPG 0x0CB00
167#define IXGBE_TIPG 0x0CB00
147#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) *0x04))
148 /* there are 8 of these */
168#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) *0x04)) /* 8 of these */
149#define IXGBE_MNGTXMAP 0x0CD10
150#define IXGBE_TIPG_FIBER_DEFAULT 3
151#define IXGBE_TXPBSIZE_SHIFT 10
152
153/* Wake up registers */
154#define IXGBE_WUC 0x05800
155#define IXGBE_WUFC 0x05808
156#define IXGBE_WUS 0x05810

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168#define IXGBE_RUPPBMR 0x050A0
169#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
170#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
171#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
172#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
173#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
174#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
175
169#define IXGBE_MNGTXMAP 0x0CD10
170#define IXGBE_TIPG_FIBER_DEFAULT 3
171#define IXGBE_TXPBSIZE_SHIFT 10
172
173/* Wake up registers */
174#define IXGBE_WUC 0x05800
175#define IXGBE_WUFC 0x05808
176#define IXGBE_WUS 0x05810

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188#define IXGBE_RUPPBMR 0x050A0
189#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
190#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
191#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
192#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
193#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
194#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
195
196/* LinkSec (MacSec) Registers */
197#define IXGBE_LSECTXCTRL 0x08A04
198#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
199#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
200#define IXGBE_LSECTXSA 0x08A10
201#define IXGBE_LSECTXPN0 0x08A14
202#define IXGBE_LSECTXPN1 0x08A18
203#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
204#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
205#define IXGBE_LSECRXCTRL 0x08F04
206#define IXGBE_LSECRXSCL 0x08F08
207#define IXGBE_LSECRXSCH 0x08F0C
208#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
209#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
210#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
211
212/* IpSec Registers */
213#define IXGBE_IPSTXIDX 0x08900
214#define IXGBE_IPSTXSALT 0x08904
215#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
216#define IXGBE_IPSRXIDX 0x08E00
217#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
218#define IXGBE_IPSRXSPI 0x08E14
219#define IXGBE_IPSRXIPIDX 0x08E18
220#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
221#define IXGBE_IPSRXSALT 0x08E2C
222#define IXGBE_IPSRXMOD 0x08E30
223
224
176/* Stats registers */
177#define IXGBE_CRCERRS 0x04000
178#define IXGBE_ILLERRC 0x04004
179#define IXGBE_ERRBC 0x04008
180#define IXGBE_MSPDC 0x04010
181#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
182#define IXGBE_MLFC 0x04034
183#define IXGBE_MRFC 0x04038

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222#define IXGBE_PTC511 0x040E4
223#define IXGBE_PTC1023 0x040E8
224#define IXGBE_PTC1522 0x040EC
225#define IXGBE_MPTC 0x040F0
226#define IXGBE_BPTC 0x040F4
227#define IXGBE_XEC 0x04120
228
229#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */
225/* Stats registers */
226#define IXGBE_CRCERRS 0x04000
227#define IXGBE_ILLERRC 0x04004
228#define IXGBE_ERRBC 0x04008
229#define IXGBE_MSPDC 0x04010
230#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
231#define IXGBE_MLFC 0x04034
232#define IXGBE_MRFC 0x04038

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271#define IXGBE_PTC511 0x040E4
272#define IXGBE_PTC1023 0x040E8
273#define IXGBE_PTC1522 0x040EC
274#define IXGBE_MPTC 0x040F0
275#define IXGBE_BPTC 0x040F4
276#define IXGBE_XEC 0x04120
277
278#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */
230#define IXGBE_TQSMR(_i) (0x07300 + ((_i) * 4)) /* 8 of these */
279#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : (0x08600 + ((_i) * 4)))
231
232#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
233#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
234#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
235#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
236
237/* Management */
238#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */

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380
381#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
382#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
383#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
384#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
385
386#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
387#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
280
281#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
282#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
283#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
284#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
285
286/* Management */
287#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */

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429
430#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
431#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
432#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
433#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
434
435#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
436#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
388#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* TX Desc writeback RO bit */
437#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
389#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
390
391/* MSCA Bit Masks */
392#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
393#define IXGBE_MSCA_NP_ADDR_SHIFT 0
394#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */
395#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */
396#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */

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428#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
429
430/* Device Type definitions for new protocol MDIO commands */
431#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
432#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
433#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
434#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
435#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
438#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
439
440/* MSCA Bit Masks */
441#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
442#define IXGBE_MSCA_NP_ADDR_SHIFT 0
443#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */
444#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */
445#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */

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477#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
478
479/* Device Type definitions for new protocol MDIO commands */
480#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
481#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
482#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
483#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
484#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
485#define IXGBE_TWINAX_DEV 1
436
437#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
438
439#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
440#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
441#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
442#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
443#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
444#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
445
446#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
447#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
448#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
449#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
450#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
451#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
486
487#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
488
489#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
490#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
491#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
492#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
493#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
494#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
495
496#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
497#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
498#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
499#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
500#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
501#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
452#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Abilty Reg */
502#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */
453#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
454#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
455
503#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
504#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
505
506/* MII clause 22/28 definitions */
507#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
508
509#define IXGBE_MII_SPEED_SELECTION_REG 0x10
510#define IXGBE_MII_RESTART 0x200
511#define IXGBE_MII_AUTONEG_COMPLETE 0x20
512#define IXGBE_MII_AUTONEG_REG 0x0
513
456#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
457#define IXGBE_MAX_PHY_ADDR 32
458
459/* PHY IDs*/
514#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
515#define IXGBE_MAX_PHY_ADDR 32
516
517/* PHY IDs*/
518#define TN1010_PHY_ID 0x00A19410
519#define TNX_FW_REV 0xB
460#define QT2022_PHY_ID 0x0043A400
520#define QT2022_PHY_ID 0x0043A400
521#define ATH_PHY_ID 0x03429050
461
522
523/* PHY Types */
524#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
525
526/* Special PHY Init Routine */
527#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
528#define IXGBE_CONTROL_MASK_NL 0xF000
529#define IXGBE_DATA_MASK_NL 0x0FFF
530#define IXGBE_CONTROL_SHIFT_NL 12
531#define IXGBE_DELAY_NL 0
532#define IXGBE_DATA_NL 1
533#define IXGBE_CONTROL_NL 0x000F
534#define IXGBE_CONTROL_EOL_NL 0x0FFF
535#define IXGBE_CONTROL_SOL_NL 0x0000
536
462/* General purpose Interrupt Enable */
537/* General purpose Interrupt Enable */
463#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
464#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
465#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
466#define IXGBE_GPIE_EIAME 0x40000000
467#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
538#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
539#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
540#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
541#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
542#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
543#define IXGBE_GPIE_EIAME 0x40000000
544#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
468
469/* Transmit Flow Control status */
470#define IXGBE_TFCS_TXOFF 0x00000001
471#define IXGBE_TFCS_TXOFF0 0x00000100
472#define IXGBE_TFCS_TXOFF1 0x00000200
473#define IXGBE_TFCS_TXOFF2 0x00000400
474#define IXGBE_TFCS_TXOFF3 0x00000800
475#define IXGBE_TFCS_TXOFF4 0x00001000

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520/* FCRTL Bit Masks */
521#define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */
522#define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */
523
524/* PAP bit masks*/
525#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
526
527/* RMCS Bit Masks */
545
546/* Transmit Flow Control status */
547#define IXGBE_TFCS_TXOFF 0x00000001
548#define IXGBE_TFCS_TXOFF0 0x00000100
549#define IXGBE_TFCS_TXOFF1 0x00000200
550#define IXGBE_TFCS_TXOFF2 0x00000400
551#define IXGBE_TFCS_TXOFF3 0x00000800
552#define IXGBE_TFCS_TXOFF4 0x00001000

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597/* FCRTL Bit Masks */
598#define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */
599#define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */
600
601/* PAP bit masks*/
602#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
603
604/* RMCS Bit Masks */
528#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recylce Mode enable */
605#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */
529/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
530#define IXGBE_RMCS_RAC 0x00000004
531#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
532#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */
533#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */
534#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
535
606/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
607#define IXGBE_RMCS_RAC 0x00000004
608#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
609#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */
610#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */
611#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
612
613
536/* Interrupt register bitmasks */
537
538/* Extended Interrupt Cause Read */
539#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
614/* Interrupt register bitmasks */
615
616/* Extended Interrupt Cause Read */
617#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
618#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
619#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
540#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
620#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
541#define IXGBE_EICR_MNG 0x00400000 /* Managability Event Interrupt */
621#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
542#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
543#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
544#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
545#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
546
547/* Extended Interrupt Cause Set */
548#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
622#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
623#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
624#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
625#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
626
627/* Extended Interrupt Cause Set */
628#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
629#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* Gen Purpose Interrupt on SDP0 */
630#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* Gen Purpose Interrupt on SDP1 */
549#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
631#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
550#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
551#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
552#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
553#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
554#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
555#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
556
557/* Extended Interrupt Mask Set */
558#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
632#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
633#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
634#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
635#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
636#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
637
638/* Extended Interrupt Mask Set */
639#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
640#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* Gen Purpose Interrupt on SDP0 */
641#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* Gen Purpose Interrupt on SDP1 */
559#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
560#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
561#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
562#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
563#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
564#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
565
566/* Extended Interrupt Mask Clear */
567#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
642#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
643#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
644#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
645#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
646#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
647#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
648
649/* Extended Interrupt Mask Clear */
650#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
651#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* Gen Purpose Interrupt on SDP0 */
652#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* Gen Purpose Interrupt on SDP1 */
568#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
569#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
570#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
571#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Error */
572#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
573#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
574
575#define IXGBE_EIMS_ENABLE_MASK ( \
653#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
654#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
655#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
656#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Error */
657#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
658#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
659
660#define IXGBE_EIMS_ENABLE_MASK ( \
576 IXGBE_EIMS_RTX_QUEUE | \
577 IXGBE_EIMS_LSC | \
578 IXGBE_EIMS_TCP_TIMER | \
579 IXGBE_EIMS_OTHER)
661 IXGBE_EIMS_RTX_QUEUE | \
662 IXGBE_EIMS_LSC | \
663 IXGBE_EIMS_TCP_TIMER | \
664 IXGBE_EIMS_OTHER)
580
665
581/* Immediate Interrupt RX (A.K.A. Low Latency Interrupt) */
666/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
582#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
583#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
584#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
585#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
586#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
587#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
588#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
589#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */

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610
611/* VLAN Control Bit Masks */
612#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
613#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
614#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
615#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
616#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
617
667#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
668#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
669#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
670#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
671#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
672#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
673#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
674#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */

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695
696/* VLAN Control Bit Masks */
697#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
698#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
699#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
700#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
701#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
702
703
618#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
619
620/* STATUS Bit Masks */
621#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
622#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
623
624#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
625#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */

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692#define IXGBE_LINKS_1G_AN_EN 0x00100000
693#define IXGBE_LINKS_KX_AN_IDLE 0x00080000
694#define IXGBE_LINKS_1G_SYNC 0x00040000
695#define IXGBE_LINKS_10G_ALIGN 0x00020000
696#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
697#define IXGBE_LINKS_TL_FAULT 0x00001000
698#define IXGBE_LINKS_SIGNAL 0x00000F00
699
704#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
705
706/* STATUS Bit Masks */
707#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
708#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
709
710#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
711#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */

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778#define IXGBE_LINKS_1G_AN_EN 0x00100000
779#define IXGBE_LINKS_KX_AN_IDLE 0x00080000
780#define IXGBE_LINKS_1G_SYNC 0x00040000
781#define IXGBE_LINKS_10G_ALIGN 0x00020000
782#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
783#define IXGBE_LINKS_TL_FAULT 0x00001000
784#define IXGBE_LINKS_SIGNAL 0x00000F00
785
786#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
700#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
701
702#define FIBER_LINK_UP_LIMIT 50
703
704/* PCS1GLSTA Bit Masks */
705#define IXGBE_PCS1GLSTA_LINK_OK 1
706#define IXGBE_PCS1GLSTA_SYNK_OK 0x10
707#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000

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765#define IXGBE_PCIE_CONFIG1_PTR 0x08
766#define IXGBE_CORE0_PTR 0x09
767#define IXGBE_CORE1_PTR 0x0A
768#define IXGBE_MAC0_PTR 0x0B
769#define IXGBE_MAC1_PTR 0x0C
770#define IXGBE_CSR0_CONFIG_PTR 0x0D
771#define IXGBE_CSR1_CONFIG_PTR 0x0E
772#define IXGBE_FW_PTR 0x0F
787#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
788
789#define FIBER_LINK_UP_LIMIT 50
790
791/* PCS1GLSTA Bit Masks */
792#define IXGBE_PCS1GLSTA_LINK_OK 1
793#define IXGBE_PCS1GLSTA_SYNK_OK 0x10
794#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000

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852#define IXGBE_PCIE_CONFIG1_PTR 0x08
853#define IXGBE_CORE0_PTR 0x09
854#define IXGBE_CORE1_PTR 0x0A
855#define IXGBE_MAC0_PTR 0x0B
856#define IXGBE_MAC1_PTR 0x0C
857#define IXGBE_CSR0_CONFIG_PTR 0x0D
858#define IXGBE_CSR1_CONFIG_PTR 0x0E
859#define IXGBE_FW_PTR 0x0F
860#define IXGBE_PBANUM0_PTR 0x15
861#define IXGBE_PBANUM1_PTR 0x16
773
774/* Legacy EEPROM word offsets */
775#define IXGBE_ISCSI_BOOT_CAPS 0x0033
776#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
777#define IXGBE_ISCSI_SETUP_PORT_1 0x0034
778
779/* EEPROM Commands - SPI */
780#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
781#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
782#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
783#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
784#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
785#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
862
863/* Legacy EEPROM word offsets */
864#define IXGBE_ISCSI_BOOT_CAPS 0x0033
865#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
866#define IXGBE_ISCSI_SETUP_PORT_1 0x0034
867
868/* EEPROM Commands - SPI */
869#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
870#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
871#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
872#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
873#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
874#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
786/* EEPROM reset Write Enbale latch */
875/* EEPROM reset Write Enable latch */
787#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
788#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
789#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
790#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
791#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
792#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
793
794/* EEPROM Read Register */

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819#define IXGBE_PCI_LINK_SPEED_2500 0x1
820#define IXGBE_PCI_LINK_SPEED_5000 0x2
821#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
822#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
823
824/* Number of 100 microseconds we wait for PCI Express master disable */
825#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
826
876#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
877#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
878#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
879#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
880#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
881#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
882
883/* EEPROM Read Register */

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908#define IXGBE_PCI_LINK_SPEED_2500 0x1
909#define IXGBE_PCI_LINK_SPEED_5000 0x2
910#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
911#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
912
913/* Number of 100 microseconds we wait for PCI Express master disable */
914#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
915
827/* PHY Types */
828#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
829
830/* Check whether address is multicast. This is little-endian specific check.*/
831#define IXGBE_IS_MULTICAST(Address) \
916/* Check whether address is multicast. This is little-endian specific check.*/
917#define IXGBE_IS_MULTICAST(Address) \
832 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
918 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
833
834/* Check whether an address is broadcast. */
835#define IXGBE_IS_BROADCAST(Address) \
919
920/* Check whether an address is broadcast. */
921#define IXGBE_IS_BROADCAST(Address) \
836 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
837 (((u8 *)(Address))[1] == ((u8)0xff)))
922 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
923 (((u8 *)(Address))[1] == ((u8)0xff)))
838
839/* RAH */
840#define IXGBE_RAH_VIND_MASK 0x003C0000
841#define IXGBE_RAH_VIND_SHIFT 18
842#define IXGBE_RAH_AV 0x80000000
843
924
925/* RAH */
926#define IXGBE_RAH_VIND_MASK 0x003C0000
927#define IXGBE_RAH_VIND_SHIFT 18
928#define IXGBE_RAH_AV 0x80000000
929
844/* Filters */
845#define IXGBE_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
846#define IXGBE_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
847
848/* Header split receive */
849#define IXGBE_RFCTL_ISCSI_DIS 0x00000001
850#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
851#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
852#define IXGBE_RFCTL_NFSW_DIS 0x00000040
853#define IXGBE_RFCTL_NFSR_DIS 0x00000080
854#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
855#define IXGBE_RFCTL_NFS_VER_SHIFT 8

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880#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
881
882#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
883#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
884#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
885#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
886#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
887#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
930/* Header split receive */
931#define IXGBE_RFCTL_ISCSI_DIS 0x00000001
932#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
933#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
934#define IXGBE_RFCTL_NFSW_DIS 0x00000040
935#define IXGBE_RFCTL_NFSR_DIS 0x00000080
936#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
937#define IXGBE_RFCTL_NFS_VER_SHIFT 8

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962#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
963
964#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
965#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
966#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
967#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
968#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
969#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
888/* Receive Priority Flow Control Enbale */
970/* Receive Priority Flow Control Enable */
889#define IXGBE_FCTRL_RPFCE 0x00004000
890#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
891
892/* Multiple Receive Queue Control */
893#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
894#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
895#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
896#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000

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910#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
911#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
912#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
913#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
914
915/* Receive Descriptor bit definitions */
916#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
917#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
971#define IXGBE_FCTRL_RPFCE 0x00004000
972#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
973
974/* Multiple Receive Queue Control */
975#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
976#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
977#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
978#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000

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992#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
993#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
994#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
995#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
996
997/* Receive Descriptor bit definitions */
998#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
999#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
918#define IXGBE_RXD_STAT_IXSM 0x04 /* Ignore checksum */
919#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
1000#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
920#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
1001#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
921#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
922#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
923#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
924#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
925#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
926#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
927#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
928#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */

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988#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
989#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
990#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
991#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
992#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
993
994/* Masks to determine if packets should be dropped due to frame errors */
995#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
1002#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
1003#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
1004#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
1005#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
1006#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
1007#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
1008#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
1009#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */

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1069#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
1070#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
1071#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
1072#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
1073#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
1074
1075/* Masks to determine if packets should be dropped due to frame errors */
1076#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
996 IXGBE_RXD_ERR_CE | \
997 IXGBE_RXD_ERR_LE | \
998 IXGBE_RXD_ERR_PE | \
999 IXGBE_RXD_ERR_OSE | \
1000 IXGBE_RXD_ERR_USE)
1077 IXGBE_RXD_ERR_CE | \
1078 IXGBE_RXD_ERR_LE | \
1079 IXGBE_RXD_ERR_PE | \
1080 IXGBE_RXD_ERR_OSE | \
1081 IXGBE_RXD_ERR_USE)
1001
1002#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
1082
1083#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
1003 IXGBE_RXDADV_ERR_CE | \
1004 IXGBE_RXDADV_ERR_LE | \
1005 IXGBE_RXDADV_ERR_PE | \
1006 IXGBE_RXDADV_ERR_OSE | \
1007 IXGBE_RXDADV_ERR_USE)
1084 IXGBE_RXDADV_ERR_CE | \
1085 IXGBE_RXDADV_ERR_LE | \
1086 IXGBE_RXDADV_ERR_PE | \
1087 IXGBE_RXDADV_ERR_OSE | \
1088 IXGBE_RXDADV_ERR_USE)
1008
1009/* Multicast bit mask */
1010#define IXGBE_MCSTCTRL_MFE 0x4
1011
1012/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
1013#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
1014#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
1015#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
1016
1017/* Vlan-specific macros */
1018#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
1019#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
1020#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
1021#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
1022
1089
1090/* Multicast bit mask */
1091#define IXGBE_MCSTCTRL_MFE 0x4
1092
1093/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
1094#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
1095#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
1096#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
1097
1098/* Vlan-specific macros */
1099#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
1100#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
1101#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
1102#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
1103
1104#ifndef __le16
1105/* Little Endian defines */
1106#define __le8 u8
1107#define __le16 u16
1108#define __le32 u32
1109#define __le64 u64
1110
1111#endif
1112
1113
1023/* Transmit Descriptor - Legacy */
1024struct ixgbe_legacy_tx_desc {
1025 u64 buffer_addr; /* Address of the descriptor's data buffer */
1026 union {
1114/* Transmit Descriptor - Legacy */
1115struct ixgbe_legacy_tx_desc {
1116 u64 buffer_addr; /* Address of the descriptor's data buffer */
1117 union {
1027 u32 data;
1118 __le32 data;
1028 struct {
1119 struct {
1029 u16 length; /* Data buffer length */
1030 u8 cso; /* Checksum offset */
1031 u8 cmd; /* Descriptor control */
1120 __le16 length; /* Data buffer length */
1121 __le8 cso; /* Checksum offset */
1122 __le8 cmd; /* Descriptor control */
1032 } flags;
1033 } lower;
1034 union {
1123 } flags;
1124 } lower;
1125 union {
1035 u32 data;
1126 __le32 data;
1036 struct {
1127 struct {
1037 u8 status; /* Descriptor status */
1038 u8 css; /* Checksum start */
1039 u16 vlan;
1128 __le8 status; /* Descriptor status */
1129 __le8 css; /* Checksum start */
1130 __le16 vlan;
1040 } fields;
1041 } upper;
1042};
1043
1044/* Transmit Descriptor - Advanced */
1045union ixgbe_adv_tx_desc {
1046 struct {
1131 } fields;
1132 } upper;
1133};
1134
1135/* Transmit Descriptor - Advanced */
1136union ixgbe_adv_tx_desc {
1137 struct {
1047 u64 buffer_addr; /* Address of descriptor's data buf */
1048 u32 cmd_type_len;
1049 u32 olinfo_status;
1138 __le64 buffer_addr; /* Address of descriptor's data buf */
1139 __le32 cmd_type_len;
1140 __le32 olinfo_status;
1050 } read;
1051 struct {
1141 } read;
1142 struct {
1052 u64 rsvd; /* Reserved */
1053 u32 nxtseq_seed;
1054 u32 status;
1143 __le64 rsvd; /* Reserved */
1144 __le32 nxtseq_seed;
1145 __le32 status;
1055 } wb;
1056};
1057
1058/* Receive Descriptor - Legacy */
1059struct ixgbe_legacy_rx_desc {
1146 } wb;
1147};
1148
1149/* Receive Descriptor - Legacy */
1150struct ixgbe_legacy_rx_desc {
1060 u64 buffer_addr; /* Address of the descriptor's data buffer */
1061 u16 length; /* Length of data DMAed into data buffer */
1062 u16 csum; /* Packet checksum */
1063 u8 status; /* Descriptor status */
1064 u8 errors; /* Descriptor Errors */
1065 u16 vlan;
1151 __le64 buffer_addr; /* Address of the descriptor's data buffer */
1152 __le16 length; /* Length of data DMAed into data buffer */
1153 __le16 csum; /* Packet checksum */
1154 __le8 status; /* Descriptor status */
1155 __le8 errors; /* Descriptor Errors */
1156 __le16 vlan;
1066};
1067
1068/* Receive Descriptor - Advanced */
1069union ixgbe_adv_rx_desc {
1070 struct {
1157};
1158
1159/* Receive Descriptor - Advanced */
1160union ixgbe_adv_rx_desc {
1161 struct {
1071 u64 pkt_addr; /* Packet buffer address */
1072 u64 hdr_addr; /* Header buffer address */
1162 __le64 pkt_addr; /* Packet buffer address */
1163 __le64 hdr_addr; /* Header buffer address */
1073 } read;
1074 struct {
1075 struct {
1164 } read;
1165 struct {
1166 struct {
1076 struct {
1077 u16 pkt_info; /* RSS type, Packet type */
1078 u16 hdr_info; /* Split Header, header len */
1167 union {
1168 __le32 data;
1169 struct {
1170 __le16 pkt_info; /* RSS type, Packet type */
1171 __le16 hdr_info; /* Split Header, header len */
1172 } hs_rss;
1079 } lo_dword;
1080 union {
1173 } lo_dword;
1174 union {
1081 u32 rss; /* RSS Hash */
1175 __le32 rss; /* RSS Hash */
1082 struct {
1176 struct {
1083 u16 ip_id; /* IP id */
1084 u16 csum; /* Packet Checksum */
1177 __le16 ip_id; /* IP id */
1178 __le16 csum; /* Packet Checksum */
1085 } csum_ip;
1086 } hi_dword;
1087 } lower;
1088 struct {
1179 } csum_ip;
1180 } hi_dword;
1181 } lower;
1182 struct {
1089 u32 status_error; /* ext status/error */
1090 u16 length; /* Packet length */
1091 u16 vlan; /* VLAN tag */
1183 __le32 status_error; /* ext status/error */
1184 __le16 length; /* Packet length */
1185 __le16 vlan; /* VLAN tag */
1092 } upper;
1093 } wb; /* writeback */
1094};
1095
1096/* Context descriptors */
1097struct ixgbe_adv_tx_context_desc {
1186 } upper;
1187 } wb; /* writeback */
1188};
1189
1190/* Context descriptors */
1191struct ixgbe_adv_tx_context_desc {
1098 u32 vlan_macip_lens;
1099 u32 seqnum_seed;
1100 u32 type_tucmd_mlhl;
1101 u32 mss_l4len_idx;
1192 __le32 vlan_macip_lens;
1193 __le32 seqnum_seed;
1194 __le32 type_tucmd_mlhl;
1195 __le32 mss_l4len_idx;
1102};
1103
1104/* Adv Transmit Descriptor Config Masks */
1105#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buffer length(bytes) */
1106#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
1107#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
1108#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
1109#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
1110#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
1196};
1197
1198/* Adv Transmit Descriptor Config Masks */
1199#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buffer length(bytes) */
1200#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
1201#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
1202#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
1203#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
1204#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
1111#define IXGBE_ADVTXD_DCMD_RDMA 0x04000000 /* RDMA */
1112#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
1113#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
1114#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
1115#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
1116#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
1117#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
1118#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED present in WB */
1119#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
1120#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
1205#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
1206#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
1207#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
1208#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
1209#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
1210#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
1211#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED present in WB */
1212#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
1213#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
1214#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */
1121#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
1122#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
1215#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
1216#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
1123 IXGBE_ADVTXD_POPTS_SHIFT)
1217 IXGBE_ADVTXD_POPTS_SHIFT)
1124#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
1218#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
1125 IXGBE_ADVTXD_POPTS_SHIFT)
1126#define IXGBE_ADVTXD_POPTS_EOM 0x00000400 /* Enable L bit-RDMA DDP hdr */
1127#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
1128#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
1129#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
1130#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/
1131#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
1132#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
1133#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
1134#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
1135#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
1136#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
1137#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
1138#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
1139#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */
1140#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
1141#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
1219 IXGBE_ADVTXD_POPTS_SHIFT)
1220#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
1221#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
1222#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
1223#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
1224#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
1225#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
1226#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
1227#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
1228#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
1229#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
1230#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
1231#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
1232#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
1233#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */
1234#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
1235#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
1142
1143/* Autonegotiation advertised speeds */
1144typedef u32 ixgbe_autoneg_advertised;
1145/* Link speed */
1146typedef u32 ixgbe_link_speed;
1147#define IXGBE_LINK_SPEED_UNKNOWN 0
1148#define IXGBE_LINK_SPEED_100_FULL 0x0008
1149#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
1150#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
1236
1237/* Autonegotiation advertised speeds */
1238typedef u32 ixgbe_autoneg_advertised;
1239/* Link speed */
1240typedef u32 ixgbe_link_speed;
1241#define IXGBE_LINK_SPEED_UNKNOWN 0
1242#define IXGBE_LINK_SPEED_100_FULL 0x0008
1243#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
1244#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
1245#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
1246 IXGBE_LINK_SPEED_10GB_FULL)
1151
1247
1152
1153enum ixgbe_eeprom_type {
1154 ixgbe_eeprom_uninitialized = 0,
1155 ixgbe_eeprom_spi,
1156 ixgbe_eeprom_none /* No NVM support */
1157};
1158
1159enum ixgbe_mac_type {
1160 ixgbe_mac_unknown = 0,
1161 ixgbe_mac_82598EB,
1162 ixgbe_num_macs
1163};
1164
1165enum ixgbe_phy_type {
1166 ixgbe_phy_unknown = 0,
1248enum ixgbe_eeprom_type {
1249 ixgbe_eeprom_uninitialized = 0,
1250 ixgbe_eeprom_spi,
1251 ixgbe_eeprom_none /* No NVM support */
1252};
1253
1254enum ixgbe_mac_type {
1255 ixgbe_mac_unknown = 0,
1256 ixgbe_mac_82598EB,
1257 ixgbe_num_macs
1258};
1259
1260enum ixgbe_phy_type {
1261 ixgbe_phy_unknown = 0,
1262 ixgbe_phy_tn,
1167 ixgbe_phy_qt,
1263 ixgbe_phy_qt,
1168 ixgbe_phy_xaui
1264 ixgbe_phy_xaui,
1265 ixgbe_phy_nl,
1266 ixgbe_phy_generic
1169};
1170
1171enum ixgbe_media_type {
1172 ixgbe_media_type_unknown = 0,
1173 ixgbe_media_type_fiber,
1174 ixgbe_media_type_copper,
1267};
1268
1269enum ixgbe_media_type {
1270 ixgbe_media_type_unknown = 0,
1271 ixgbe_media_type_fiber,
1272 ixgbe_media_type_copper,
1175 ixgbe_media_type_backplane
1273 ixgbe_media_type_backplane,
1274 ixgbe_media_type_virtual
1176};
1177
1178/* Flow Control Settings */
1179enum ixgbe_fc_type {
1180 ixgbe_fc_none = 0,
1181 ixgbe_fc_rx_pause,
1182 ixgbe_fc_tx_pause,
1183 ixgbe_fc_full,

--- 22 unchanged lines hidden (view full) ---

1206 ixgbe_bus_speed_reserved
1207};
1208
1209/* PCI bus widths */
1210enum ixgbe_bus_width {
1211 ixgbe_bus_width_unknown = 0,
1212 ixgbe_bus_width_pcie_x1,
1213 ixgbe_bus_width_pcie_x2,
1275};
1276
1277/* Flow Control Settings */
1278enum ixgbe_fc_type {
1279 ixgbe_fc_none = 0,
1280 ixgbe_fc_rx_pause,
1281 ixgbe_fc_tx_pause,
1282 ixgbe_fc_full,

--- 22 unchanged lines hidden (view full) ---

1305 ixgbe_bus_speed_reserved
1306};
1307
1308/* PCI bus widths */
1309enum ixgbe_bus_width {
1310 ixgbe_bus_width_unknown = 0,
1311 ixgbe_bus_width_pcie_x1,
1312 ixgbe_bus_width_pcie_x2,
1214 ixgbe_bus_width_pcie_x4,
1215 ixgbe_bus_width_pcie_x8,
1313 ixgbe_bus_width_pcie_x4 = 4,
1314 ixgbe_bus_width_pcie_x8 = 8,
1216 ixgbe_bus_width_32,
1217 ixgbe_bus_width_64,
1218 ixgbe_bus_width_reserved
1219};
1220
1315 ixgbe_bus_width_32,
1316 ixgbe_bus_width_64,
1317 ixgbe_bus_width_reserved
1318};
1319
1221struct ixgbe_eeprom_info {
1222 enum ixgbe_eeprom_type type;
1223 u16 word_size;
1224 u16 address_bits;
1225};
1226
1227struct ixgbe_addr_filter_info {
1228 u32 num_mc_addrs;
1229 u32 rar_used_count;
1230 u32 mc_addr_in_rar_count;
1231 u32 mta_in_use;
1320struct ixgbe_addr_filter_info {
1321 u32 num_mc_addrs;
1322 u32 rar_used_count;
1323 u32 mc_addr_in_rar_count;
1324 u32 mta_in_use;
1325 u32 overflow_promisc;
1326 bool user_set_promisc;
1232};
1233
1234/* Bus parameters */
1235struct ixgbe_bus_info {
1236 enum ixgbe_bus_speed speed;
1237 enum ixgbe_bus_width width;
1238 enum ixgbe_bus_type type;
1239};

--- 63 unchanged lines hidden (view full) ---

1303 u64 rqsmr[16];
1304 u64 tqsmr[8];
1305 u64 qprc[16];
1306 u64 qptc[16];
1307 u64 qbrc[16];
1308 u64 qbtc[16];
1309};
1310
1327};
1328
1329/* Bus parameters */
1330struct ixgbe_bus_info {
1331 enum ixgbe_bus_speed speed;
1332 enum ixgbe_bus_width width;
1333 enum ixgbe_bus_type type;
1334};

--- 63 unchanged lines hidden (view full) ---

1398 u64 rqsmr[16];
1399 u64 tqsmr[8];
1400 u64 qprc[16];
1401 u64 qptc[16];
1402 u64 qbrc[16];
1403 u64 qbtc[16];
1404};
1405
1311
1312/* forward declaration */
1313struct ixgbe_hw;
1314
1406/* forward declaration */
1407struct ixgbe_hw;
1408
1409/* iterator type for walking multicast address lists */
1410typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
1411 u32 *vmdq);
1412
1315/* Function pointer table */
1413/* Function pointer table */
1316struct ixgbe_functions
1317{
1318 s32 (*ixgbe_func_init_hw)(struct ixgbe_hw *);
1319 s32 (*ixgbe_func_reset_hw)(struct ixgbe_hw *);
1320 s32 (*ixgbe_func_start_hw)(struct ixgbe_hw *);
1321 s32 (*ixgbe_func_clear_hw_cntrs)(struct ixgbe_hw *);
1322 enum ixgbe_media_type (*ixgbe_func_get_media_type)(struct ixgbe_hw *);
1323 s32 (*ixgbe_func_get_mac_addr)(struct ixgbe_hw *, u8 *);
1324 u32 (*ixgbe_func_get_num_of_tx_queues)(struct ixgbe_hw *);
1325 u32 (*ixgbe_func_get_num_of_rx_queues)(struct ixgbe_hw *);
1326 s32 (*ixgbe_func_stop_adapter)(struct ixgbe_hw *);
1327 s32 (*ixgbe_func_get_bus_info)(struct ixgbe_hw *);
1328 s32 (*ixgbe_func_read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
1329 s32 (*ixgbe_func_write_analog_reg8)(struct ixgbe_hw*, u32, u8);
1330 /* PHY */
1331 s32 (*ixgbe_func_identify_phy)(struct ixgbe_hw *);
1332 s32 (*ixgbe_func_reset_phy)(struct ixgbe_hw *);
1333 s32 (*ixgbe_func_read_phy_reg)(struct ixgbe_hw *, u32, u32, u16 *);
1334 s32 (*ixgbe_func_write_phy_reg)(struct ixgbe_hw *, u32, u32, u16);
1335 s32 (*ixgbe_func_setup_phy_link)(struct ixgbe_hw *);
1336 s32 (*ixgbe_func_setup_phy_link_speed)(struct ixgbe_hw *,
1337 ixgbe_link_speed,
1338 bool, bool);
1339 s32 (*ixgbe_func_check_phy_link)(struct ixgbe_hw *, ixgbe_link_speed *,
1340 bool *);
1414struct ixgbe_eeprom_operations {
1415 s32 (*init_params)(struct ixgbe_hw *);
1416 s32 (*read)(struct ixgbe_hw *, u16, u16 *);
1417 s32 (*write)(struct ixgbe_hw *, u16, u16);
1418 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
1419 s32 (*update_checksum)(struct ixgbe_hw *);
1420};
1341
1421
1422struct ixgbe_mac_operations {
1423 s32 (*init_hw)(struct ixgbe_hw *);
1424 s32 (*reset_hw)(struct ixgbe_hw *);
1425 s32 (*start_hw)(struct ixgbe_hw *);
1426 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
1427 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
1428 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
1429 s32 (*stop_adapter)(struct ixgbe_hw *);
1430 s32 (*get_bus_info)(struct ixgbe_hw *);
1431 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
1432 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
1433
1342 /* Link */
1434 /* Link */
1343 s32 (*ixgbe_func_setup_link)(struct ixgbe_hw *);
1344 s32 (*ixgbe_func_setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed,
1345 bool, bool);
1346 s32 (*ixgbe_func_check_link)(struct ixgbe_hw *, ixgbe_link_speed *,
1347 bool *);
1348 s32 (*ixgbe_func_get_link_settings)(struct ixgbe_hw *,
1349 ixgbe_link_speed *,
1350 bool *);
1435 s32 (*setup_link)(struct ixgbe_hw *);
1436 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
1437 bool);
1438 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
1439 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
1440 bool *);
1351
1352 /* LED */
1441
1442 /* LED */
1353 s32 (*ixgbe_func_led_on)(struct ixgbe_hw *, u32);
1354 s32 (*ixgbe_func_led_off)(struct ixgbe_hw *, u32);
1355 s32 (*ixgbe_func_blink_led_start)(struct ixgbe_hw *, u32);
1356 s32 (*ixgbe_func_blink_led_stop)(struct ixgbe_hw *, u32);
1443 s32 (*led_on)(struct ixgbe_hw *, u32);
1444 s32 (*led_off)(struct ixgbe_hw *, u32);
1445 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
1446 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
1357
1447
1358 /* EEPROM */
1359 s32 (*ixgbe_func_init_eeprom_params)(struct ixgbe_hw *);
1360 s32 (*ixgbe_func_read_eeprom)(struct ixgbe_hw *, u16, u16 *);
1361 s32 (*ixgbe_func_write_eeprom)(struct ixgbe_hw *, u16, u16);
1362 s32 (*ixgbe_func_validate_eeprom_checksum)(struct ixgbe_hw *, u16 *);
1363 s32 (*ixgbe_func_update_eeprom_checksum)(struct ixgbe_hw *);
1364
1365 /* RAR, Multicast, VLAN */
1448 /* RAR, Multicast, VLAN */
1366 s32 (*ixgbe_func_set_rar)(struct ixgbe_hw *, u32, u8 *, u32 , u32);
1367 s32 (*ixgbe_func_init_rx_addrs)(struct ixgbe_hw *);
1368 u32 (*ixgbe_func_get_num_rx_addrs)(struct ixgbe_hw *);
1369 s32 (*ixgbe_func_update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
1370 u32);
1371 s32 (*ixgbe_func_enable_mc)(struct ixgbe_hw *);
1372 s32 (*ixgbe_func_disable_mc)(struct ixgbe_hw *);
1373 s32 (*ixgbe_func_clear_vfta)(struct ixgbe_hw *);
1374 s32 (*ixgbe_func_set_vfta)(struct ixgbe_hw *, u32, u32, bool);
1449 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
1450 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
1451 s32 (*init_rx_addrs)(struct ixgbe_hw *);
1452 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
1453 ixgbe_mc_addr_itr);
1454 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
1455 ixgbe_mc_addr_itr);
1456 s32 (*enable_mc)(struct ixgbe_hw *);
1457 s32 (*disable_mc)(struct ixgbe_hw *);
1458 s32 (*clear_vfta)(struct ixgbe_hw *);
1459 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
1375
1376 /* Flow Control */
1460
1461 /* Flow Control */
1377 s32 (*ixgbe_func_setup_fc)(struct ixgbe_hw *, s32);
1462 s32 (*setup_fc)(struct ixgbe_hw *, s32);
1378};
1379
1463};
1464
1465struct ixgbe_phy_operations {
1466 s32 (*identify)(struct ixgbe_hw *);
1467 s32 (*reset)(struct ixgbe_hw *);
1468 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
1469 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
1470 s32 (*setup_link)(struct ixgbe_hw *);
1471 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
1472 bool);
1473 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
1474 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
1475};
1476
1477struct ixgbe_eeprom_info {
1478 struct ixgbe_eeprom_operations ops;
1479 enum ixgbe_eeprom_type type;
1480 u16 word_size;
1481 u16 address_bits;
1482};
1483
1380struct ixgbe_mac_info {
1484struct ixgbe_mac_info {
1381 enum ixgbe_mac_type type;
1382 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
1383 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
1384 s32 mc_filter_type;
1385 u32 link_attach_type;
1386 u32 link_mode_select;
1387 bool link_settings_loaded;
1388 bool autoneg;
1389 bool autoneg_failed;
1485 struct ixgbe_mac_operations ops;
1486 enum ixgbe_mac_type type;
1487 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
1488 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
1489 s32 mc_filter_type;
1490 u32 mcft_size;
1491 u32 vft_size;
1492 u32 num_rar_entries;
1493 u32 max_tx_queues;
1494 u32 max_rx_queues;
1495 u32 link_attach_type;
1496 u32 link_mode_select;
1497 bool link_settings_loaded;
1498 bool autoneg;
1499 bool autoneg_failed;
1390};
1391
1392struct ixgbe_phy_info {
1500};
1501
1502struct ixgbe_phy_info {
1503 struct ixgbe_phy_operations ops;
1393 enum ixgbe_phy_type type;
1394 u32 addr;
1395 u32 id;
1396 u32 revision;
1397 enum ixgbe_media_type media_type;
1504 enum ixgbe_phy_type type;
1505 u32 addr;
1506 u32 id;
1507 u32 revision;
1508 enum ixgbe_media_type media_type;
1509 bool reset_disable;
1398 ixgbe_autoneg_advertised autoneg_advertised;
1399 bool autoneg_wait_to_complete;
1400};
1401
1402struct ixgbe_hw {
1403 u8 *hw_addr;
1404 void *back;
1510 ixgbe_autoneg_advertised autoneg_advertised;
1511 bool autoneg_wait_to_complete;
1512};
1513
1514struct ixgbe_hw {
1515 u8 *hw_addr;
1516 void *back;
1405 struct ixgbe_functions func;
1406 struct ixgbe_mac_info mac;
1407 struct ixgbe_addr_filter_info addr_ctrl;
1408 struct ixgbe_fc_info fc;
1409 struct ixgbe_phy_info phy;
1410 struct ixgbe_eeprom_info eeprom;
1411 struct ixgbe_bus_info bus;
1412 u16 device_id;
1413 u16 vendor_id;
1414 u16 subsystem_device_id;
1415 u16 subsystem_vendor_id;
1416 u8 revision_id;
1417 bool adapter_stopped;
1418};
1419
1517 struct ixgbe_mac_info mac;
1518 struct ixgbe_addr_filter_info addr_ctrl;
1519 struct ixgbe_fc_info fc;
1520 struct ixgbe_phy_info phy;
1521 struct ixgbe_eeprom_info eeprom;
1522 struct ixgbe_bus_info bus;
1523 u16 device_id;
1524 u16 vendor_id;
1525 u16 subsystem_device_id;
1526 u16 subsystem_vendor_id;
1527 u8 revision_id;
1528 bool adapter_stopped;
1529};
1530
1420
1421#define ixgbe_func_from_hw_struct(hw, _func) hw->func._func
1422
1423#define ixgbe_call_func(hw, func, params, error) \
1531#define ixgbe_call_func(hw, func, params, error) \
1424 (ixgbe_func_from_hw_struct(hw, func) != NULL) ? \
1425 ixgbe_func_from_hw_struct(hw, func) params: error
1532 (func != NULL) ? func params: error
1426
1427/* Error Codes */
1428#define IXGBE_SUCCESS 0
1429#define IXGBE_ERR_EEPROM -1
1430#define IXGBE_ERR_EEPROM_CHECKSUM -2
1431#define IXGBE_ERR_PHY -3
1432#define IXGBE_ERR_CONFIG -4
1433#define IXGBE_ERR_PARAM -5

--- 6 unchanged lines hidden (view full) ---

1440#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
1441#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
1442#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
1443#define IXGBE_ERR_RESET_FAILED -15
1444#define IXGBE_ERR_SWFW_SYNC -16
1445#define IXGBE_ERR_PHY_ADDR_INVALID -17
1446#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
1447
1533
1534/* Error Codes */
1535#define IXGBE_SUCCESS 0
1536#define IXGBE_ERR_EEPROM -1
1537#define IXGBE_ERR_EEPROM_CHECKSUM -2
1538#define IXGBE_ERR_PHY -3
1539#define IXGBE_ERR_CONFIG -4
1540#define IXGBE_ERR_PARAM -5

--- 6 unchanged lines hidden (view full) ---

1547#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
1548#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
1549#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
1550#define IXGBE_ERR_RESET_FAILED -15
1551#define IXGBE_ERR_SWFW_SYNC -16
1552#define IXGBE_ERR_PHY_ADDR_INVALID -17
1553#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
1554
1448#ifndef UNREFERENCED_PARAMETER
1449#define UNREFERENCED_PARAMETER(_p)
1555#define UNREFERENCED_PARAMETER(_p)
1450#endif
1451
1452#endif /* _IXGBE_TYPE_H_ */
1556
1557#endif /* _IXGBE_TYPE_H_ */