| ixgbe_phy.h (181003) | ixgbe_phy.h (185352) |
|---|---|
| 1/****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 1/****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.h 181003 2008-07-30 18:15:18Z jfv $*/ | 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.h 185352 2008-11-26 23:41:18Z jfv $*/ |
| 34 35#ifndef _IXGBE_PHY_H_ 36#define _IXGBE_PHY_H_ 37 38#include "ixgbe_type.h" | 34 35#ifndef _IXGBE_PHY_H_ 36#define _IXGBE_PHY_H_ 37 38#include "ixgbe_type.h" |
| 39#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0 |
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| 39 | 40 |
| 41/* EEPROM byte offsets */ 42#define IXGBE_SFF_IDENTIFIER 0x0 43#define IXGBE_SFF_IDENTIFIER_SFP 0x3 44#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25 45#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26 46#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27 47#define IXGBE_SFF_1GBE_COMP_CODES 0x6 48#define IXGBE_SFF_10GBE_COMP_CODES 0x3 49#define IXGBE_SFF_TRANSMISSION_MEDIA 0x9 50 51/* Bitmasks */ 52#define IXGBE_SFF_TWIN_AX_CAPABLE 0x80 53#define IXGBE_SFF_1GBASESX_CAPABLE 0x1 54#define IXGBE_SFF_10GBASESR_CAPABLE 0x10 55#define IXGBE_SFF_10GBASELR_CAPABLE 0x20 56#define IXGBE_I2C_EEPROM_READ_MASK 0x100 57#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3 58#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0 59#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1 60#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2 61#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 62 63/* Bit-shift macros */ 64#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 12 65#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 8 66#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 4 67 68/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ 69#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600 70#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500 71#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00 72 73/* I2C SDA and SCL timing parameters for standard mode */ 74#define IXGBE_I2C_T_HD_STA 4 75#define IXGBE_I2C_T_LOW 5 76#define IXGBE_I2C_T_HIGH 4 77#define IXGBE_I2C_T_SU_STA 5 78#define IXGBE_I2C_T_HD_DATA 5 79#define IXGBE_I2C_T_SU_DATA 1 80#define IXGBE_I2C_T_RISE 1 81#define IXGBE_I2C_T_FALL 1 82#define IXGBE_I2C_T_SU_STO 4 83#define IXGBE_I2C_T_BUF 5 84 85 |
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| 40s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); 41bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); 42enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 43s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 44s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); 45s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); 46s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 47 u32 device_type, u16 *phy_data); --- 7 unchanged lines hidden (view full) --- 55 56/* PHY specific */ 57s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, 58 ixgbe_link_speed *speed, 59 bool *link_up); 60s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 61 u16 *firmware_version); 62 | 86s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); 87bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); 88enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 89s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 90s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); 91s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw); 92s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 93 u32 device_type, u16 *phy_data); --- 7 unchanged lines hidden (view full) --- 101 102/* PHY specific */ 103s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, 104 ixgbe_link_speed *speed, 105 bool *link_up); 106s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 107 u16 *firmware_version); 108 |
| 109s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw); 110s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); 111s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 112 u16 *list_offset, 113 u16 *data_offset); |
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| 63#endif /* _IXGBE_PHY_H_ */ | 114#endif /* _IXGBE_PHY_H_ */ |