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< /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 181003 2008-07-30 18:15:18Z jfv $*/
---
> /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 185352 2008-11-26 23:41:18Z jfv $*/
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> phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic;
> phy->sfp_type = ixgbe_sfp_type_unknown;
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<
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> case ATH_PHY_ID:
> phy_type = ixgbe_phy_nl;
> break;
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< if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
---
> if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
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< }
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< if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
---
> if (speed & IXGBE_LINK_SPEED_10GB_FULL)
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< }
< if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
---
>
> if (speed & IXGBE_LINK_SPEED_1GB_FULL)
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< }
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> /**
> * ixgbe_reset_phy_nl - Performs a PHY reset
> * @hw: pointer to hardware structure
> **/
> s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
> {
> u16 phy_offset, control, eword, edata, block_crc;
> bool end_data = FALSE;
> u16 list_offset, data_offset;
> u16 phy_data = 0;
> s32 ret_val = IXGBE_SUCCESS;
> u32 i;
>
> hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
> IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
>
> /* reset the PHY and poll for completion */
> hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
> IXGBE_MDIO_PHY_XS_DEV_TYPE,
> (phy_data | IXGBE_MDIO_PHY_XS_RESET));
>
> for (i = 0; i < 100; i++) {
> hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
> IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
> if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
> break;
> msec_delay(10);
> }
>
> if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
> DEBUGOUT("PHY reset did not complete.\n");
> ret_val = IXGBE_ERR_PHY;
> goto out;
> }
>
> /* Get init offsets */
> ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
> &data_offset);
> if (ret_val != IXGBE_SUCCESS)
> goto out;
>
> ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
> data_offset++;
> while (!end_data) {
> /*
> * Read control word from PHY init contents offset
> */
> ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
> control = (eword & IXGBE_CONTROL_MASK_NL) >>
> IXGBE_CONTROL_SHIFT_NL;
> edata = eword & IXGBE_DATA_MASK_NL;
> switch (control) {
> case IXGBE_DELAY_NL:
> data_offset++;
> DEBUGOUT1("DELAY: %d MS\n", edata);
> msec_delay(edata);
> break;
> case IXGBE_DATA_NL:
> DEBUGOUT("DATA: \n");
> data_offset++;
> hw->eeprom.ops.read(hw, data_offset++,
> &phy_offset);
> for (i = 0; i < edata; i++) {
> hw->eeprom.ops.read(hw, data_offset, &eword);
> hw->phy.ops.write_reg(hw, phy_offset,
> IXGBE_TWINAX_DEV, eword);
> DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
> phy_offset);
> data_offset++;
> phy_offset++;
> }
> break;
> case IXGBE_CONTROL_NL:
> data_offset++;
> DEBUGOUT("CONTROL: \n");
> if (edata == IXGBE_CONTROL_EOL_NL) {
> DEBUGOUT("EOL\n");
> end_data = TRUE;
> } else if (edata == IXGBE_CONTROL_SOL_NL) {
> DEBUGOUT("SOL\n");
> } else {
> DEBUGOUT("Bad control value\n");
> ret_val = IXGBE_ERR_PHY;
> goto out;
> }
> break;
> default:
> DEBUGOUT("Bad control type\n");
> ret_val = IXGBE_ERR_PHY;
> goto out;
> }
> }
>
> out:
> return ret_val;
> }
>
> /**
> * ixgbe_identify_sfp_module_generic - Identifies SFP modules
> * @hw: pointer to hardware structure
> *
> * Searches for and identifies the SFP module and assigns appropriate PHY type.
> **/
> s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
> {
> s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
> u32 vendor_oui = 0;
> u8 identifier = 0;
> u8 comp_codes_1g = 0;
> u8 comp_codes_10g = 0;
> u8 oui_bytes[4] = {0, 0, 0, 0};
> u8 transmission_media = 0;
>
> status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
> &identifier);
>
> if (status == IXGBE_ERR_SFP_NOT_PRESENT) {
> hw->phy.sfp_type = ixgbe_sfp_type_not_present;
> goto out;
> }
>
> if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
> hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
> &comp_codes_1g);
> hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
> &comp_codes_10g);
> hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_TRANSMISSION_MEDIA,
> &transmission_media);
>
> /* ID Module
> * =========
> * 0 SFP_DA_CU
> * 1 SFP_SR
> * 2 SFP_LR
> */
> if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
> hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
> else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
> hw->phy.sfp_type = ixgbe_sfp_type_sr;
> else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
> hw->phy.sfp_type = ixgbe_sfp_type_lr;
> else
> hw->phy.sfp_type = ixgbe_sfp_type_unknown;
>
> /* Determine if the SFP+ PHY is dual speed or not. */
> if ((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
> (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE))
> hw->phy.multispeed_fiber = TRUE;
> /* Determine PHY vendor */
> if (hw->phy.type == ixgbe_phy_unknown) {
> hw->phy.id = identifier;
> hw->phy.ops.read_i2c_eeprom(hw,
> IXGBE_SFF_VENDOR_OUI_BYTE0,
> &oui_bytes[0]);
> hw->phy.ops.read_i2c_eeprom(hw,
> IXGBE_SFF_VENDOR_OUI_BYTE1,
> &oui_bytes[1]);
> hw->phy.ops.read_i2c_eeprom(hw,
> IXGBE_SFF_VENDOR_OUI_BYTE2,
> &oui_bytes[2]);
>
> vendor_oui =
> ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
> (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
> (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
>
> switch (vendor_oui) {
> case IXGBE_SFF_VENDOR_OUI_TYCO:
> if (transmission_media &
> IXGBE_SFF_TWIN_AX_CAPABLE)
> hw->phy.type = ixgbe_phy_tw_tyco;
> break;
> case IXGBE_SFF_VENDOR_OUI_FTL:
> hw->phy.type = ixgbe_phy_sfp_ftl;
> break;
> case IXGBE_SFF_VENDOR_OUI_AVAGO:
> hw->phy.type = ixgbe_phy_sfp_avago;
> break;
> default:
> if (transmission_media &
> IXGBE_SFF_TWIN_AX_CAPABLE)
> hw->phy.type = ixgbe_phy_tw_unknown;
> else
> hw->phy.type = ixgbe_phy_sfp_unknown;
> break;
> }
> }
> status = IXGBE_SUCCESS;
> }
>
> out:
> return status;
> }
>
> /**
> * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
> * @hw: pointer to hardware structure
> * @list_offset: offset to the SFP ID list
> * @data_offset: offset to the SFP data block
> *
> * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
> * so it returns the offsets to the phy init sequence block.
> **/
> s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
> u16 *list_offset,
> u16 *data_offset)
> {
> u16 sfp_id;
>
> if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
> return IXGBE_ERR_SFP_NOT_SUPPORTED;
>
> if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
> return IXGBE_ERR_SFP_NOT_PRESENT;
>
> if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
> (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
> return IXGBE_ERR_SFP_NOT_SUPPORTED;
>
> /* Read offset to PHY init contents */
> hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
>
> if ((!*list_offset) || (*list_offset == 0xFFFF))
> return IXGBE_ERR_PHY;
>
> /* Shift offset to first ID word */
> (*list_offset)++;
>
> /*
> * Find the matching SFP ID in the EEPROM
> * and program the init sequence
> */
> hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
>
> while (sfp_id != IXGBE_PHY_INIT_END_NL) {
> if (sfp_id == hw->phy.sfp_type) {
> (*list_offset)++;
> hw->eeprom.ops.read(hw, *list_offset, data_offset);
> if ((!*data_offset) || (*data_offset == 0xFFFF)) {
> DEBUGOUT("SFP+ module not supported\n");
> return IXGBE_ERR_SFP_NOT_SUPPORTED;
> } else {
> break;
> }
> } else {
> (*list_offset) += 2;
> if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
> return IXGBE_ERR_PHY;
> }
> }
>
> if (sfp_id == IXGBE_PHY_INIT_END_NL) {
> DEBUGOUT("No matching SFP+ module found\n");
> return IXGBE_ERR_SFP_NOT_SUPPORTED;
> }
>
> return IXGBE_SUCCESS;
> }
>