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1/******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 247056 2013-02-20 21:16:50Z des $*/
34
35#include "ixgbe_api.h"
36#include "ixgbe_common.h"
37#include "ixgbe_phy.h"
38
39static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49static bool ixgbe_get_i2c_data(u32 *i2cctl);
50
51/**
52 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
53 * @hw: pointer to the hardware structure
54 *
55 * Initialize the function pointers.
56 **/
57s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)

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66 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
67 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
68 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
69 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
70 phy->ops.check_link = NULL;
71 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
72 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
73 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
74 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
75 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
76 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
77 phy->ops.identify_sfp = &ixgbe_identify_module_generic;
78 phy->sfp_type = ixgbe_sfp_type_unknown;
79 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
80 return IXGBE_SUCCESS;
81}

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558
559 return status;
560}
561
562/**
563 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
564 * @hw: pointer to hardware structure
565 * @speed: new link speed
566 * @autoneg: TRUE if autonegotiation enabled
567 **/
568s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
569 ixgbe_link_speed speed,
570 bool autoneg,
571 bool autoneg_wait_to_complete)
572{
573 UNREFERENCED_2PARAMETER(autoneg, autoneg_wait_to_complete);
574
575 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
576
577 /*
578 * Clear autoneg_advertised and set new values based on input link
579 * speed.
580 */
581 hw->phy.autoneg_advertised = 0;

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964 status = IXGBE_ERR_SFP_NOT_PRESENT;
965 goto out;
966 }
967
968 status = hw->phy.ops.read_i2c_eeprom(hw,
969 IXGBE_SFF_IDENTIFIER,
970 &identifier);
971
972 if (status == IXGBE_ERR_SWFW_SYNC ||
973 status == IXGBE_ERR_I2C ||
974 status == IXGBE_ERR_SFP_NOT_PRESENT)
975 goto err_read_i2c_eeprom;
976
977 /* LAN ID is needed for sfp_type determination */
978 hw->mac.ops.set_lan_id(hw);
979
980 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
981 hw->phy.type = ixgbe_phy_sfp_unsupported;
982 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
983 } else {
984 status = hw->phy.ops.read_i2c_eeprom(hw,
985 IXGBE_SFF_1GBE_COMP_CODES,
986 &comp_codes_1g);
987
988 if (status == IXGBE_ERR_SWFW_SYNC ||
989 status == IXGBE_ERR_I2C ||
990 status == IXGBE_ERR_SFP_NOT_PRESENT)
991 goto err_read_i2c_eeprom;
992
993 status = hw->phy.ops.read_i2c_eeprom(hw,
994 IXGBE_SFF_10GBE_COMP_CODES,
995 &comp_codes_10g);
996
997 if (status == IXGBE_ERR_SWFW_SYNC ||
998 status == IXGBE_ERR_I2C ||
999 status == IXGBE_ERR_SFP_NOT_PRESENT)
1000 goto err_read_i2c_eeprom;
1001 status = hw->phy.ops.read_i2c_eeprom(hw,
1002 IXGBE_SFF_CABLE_TECHNOLOGY,
1003 &cable_tech);
1004
1005 if (status == IXGBE_ERR_SWFW_SYNC ||
1006 status == IXGBE_ERR_I2C ||
1007 status == IXGBE_ERR_SFP_NOT_PRESENT)
1008 goto err_read_i2c_eeprom;
1009
1010 /* ID Module
1011 * =========
1012 * 0 SFP_DA_CU
1013 * 1 SFP_SR
1014 * 2 SFP_LR
1015 * 3 SFP_DA_CORE0 - 82599-specific

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1097
1098 /* Determine PHY vendor */
1099 if (hw->phy.type != ixgbe_phy_nl) {
1100 hw->phy.id = identifier;
1101 status = hw->phy.ops.read_i2c_eeprom(hw,
1102 IXGBE_SFF_VENDOR_OUI_BYTE0,
1103 &oui_bytes[0]);
1104
1105 if (status == IXGBE_ERR_SWFW_SYNC ||
1106 status == IXGBE_ERR_I2C ||
1107 status == IXGBE_ERR_SFP_NOT_PRESENT)
1108 goto err_read_i2c_eeprom;
1109
1110 status = hw->phy.ops.read_i2c_eeprom(hw,
1111 IXGBE_SFF_VENDOR_OUI_BYTE1,
1112 &oui_bytes[1]);
1113
1114 if (status == IXGBE_ERR_SWFW_SYNC ||
1115 status == IXGBE_ERR_I2C ||
1116 status == IXGBE_ERR_SFP_NOT_PRESENT)
1117 goto err_read_i2c_eeprom;
1118
1119 status = hw->phy.ops.read_i2c_eeprom(hw,
1120 IXGBE_SFF_VENDOR_OUI_BYTE2,
1121 &oui_bytes[2]);
1122
1123 if (status == IXGBE_ERR_SWFW_SYNC ||
1124 status == IXGBE_ERR_I2C ||
1125 status == IXGBE_ERR_SFP_NOT_PRESENT)
1126 goto err_read_i2c_eeprom;
1127
1128 vendor_oui =
1129 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1130 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1131 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1132
1133 switch (vendor_oui) {

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1328 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1329
1330 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1331 IXGBE_I2C_EEPROM_DEV_ADDR,
1332 eeprom_data);
1333}
1334
1335/**
1336 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1337 * @hw: pointer to hardware structure
1338 * @byte_offset: EEPROM byte offset to write
1339 * @eeprom_data: value to write
1340 *
1341 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1342 **/
1343s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,

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1420 status = ixgbe_clock_out_i2c_bit(hw, nack);
1421 if (status != IXGBE_SUCCESS)
1422 goto fail;
1423
1424 ixgbe_i2c_stop(hw);
1425 break;
1426
1427fail:
1428 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1429 msec_delay(100);
1430 ixgbe_i2c_bus_clear(hw);
1431 retry++;
1432 if (retry < max_retry)
1433 DEBUGOUT("I2C byte read error - Retrying.\n");
1434 else
1435 DEBUGOUT("I2C byte read error.\n");
1436
1437 } while (retry < max_retry);
1438

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