1/******************************************************************************
2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 181003 2008-07-30 18:15:18Z jfv $*/
34
35#include "ixgbe_api.h"
36#include "ixgbe_common.h"
37#include "ixgbe_phy.h"
38
39/**
40 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
41 * @hw: pointer to the hardware structure

--- 8 unchanged lines hidden (view full) ---

50 phy->ops.identify = &ixgbe_identify_phy_generic;
51 phy->ops.reset = &ixgbe_reset_phy_generic;
52 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
53 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
54 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
55 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
56 phy->ops.check_link = NULL;
57 phy->ops.get_firmware_version = NULL;
58
59 return IXGBE_SUCCESS;
60}
61
62/**
63 * ixgbe_identify_phy_generic - Get physical layer module
64 * @hw: pointer to hardware structure
65 *

--- 60 unchanged lines hidden (view full) ---

126 if (status == IXGBE_SUCCESS) {
127 hw->phy.id = (u32)(phy_id_high << 16);
128 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
129 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
130 &phy_id_low);
131 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
132 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
133 }
134
135 return status;
136}
137
138/**
139 * ixgbe_get_phy_type_from_id - Get the phy type
140 * @hw: pointer to hardware structure
141 *
142 **/
143enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
144{
145 enum ixgbe_phy_type phy_type;
146
147 switch (phy_id) {
148 case TN1010_PHY_ID:
149 phy_type = ixgbe_phy_tn;
150 break;
151 case QT2022_PHY_ID:
152 phy_type = ixgbe_phy_qt;
153 break;
154 default:
155 phy_type = ixgbe_phy_unknown;
156 break;
157 }
158
159 DEBUGOUT1("phy type found is %d\n", phy_type);
160 return phy_type;
161}

--- 50 unchanged lines hidden (view full) ---

212 * The MDI Command bit will clear when the operation is
213 * complete
214 */
215 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
216 usec_delay(10);
217
218 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
219
220 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
221 break;
222 }
223 }
224
225 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
226 DEBUGOUT("PHY address command did not complete.\n");
227 status = IXGBE_ERR_PHY;
228 }
229
230 if (status == IXGBE_SUCCESS) {

--- 209 unchanged lines hidden (view full) ---

440 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
441
442 /*
443 * Clear autoneg_advertised and set new values based on input link
444 * speed.
445 */
446 hw->phy.autoneg_advertised = 0;
447
448 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
449 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
450 }
451 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
452 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
453 }
454
455 /* Setup link based on the new speed settings */
456 hw->phy.ops.setup_link(hw);
457
458 return IXGBE_SUCCESS;
459}
460
461/**

--- 56 unchanged lines hidden (view full) ---

518
519 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
520 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
521 firmware_version);
522
523 return status;
524}
525