1/******************************************************************************
2
3 Copyright (c) 2001-2013, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 247822 2013-03-04 23:07:40Z jfv $*/
34
35#include "ixgbe_api.h"
36#include "ixgbe_common.h"
37#include "ixgbe_phy.h"
38
39static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49static bool ixgbe_get_i2c_data(u32 *i2cctl);
50static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
51 u8 *sff8472_data);
52
53/**
54 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
55 * @hw: pointer to the hardware structure
56 *
57 * Initialize the function pointers.
58 **/
59s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
60{
61 struct ixgbe_phy_info *phy = &hw->phy;
62
63 DEBUGFUNC("ixgbe_init_phy_ops_generic");
64
65 /* PHY */
66 phy->ops.identify = &ixgbe_identify_phy_generic;
67 phy->ops.reset = &ixgbe_reset_phy_generic;
68 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
69 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
70 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
71 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
72 phy->ops.check_link = NULL;
73 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
74 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
75 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
76 phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic;
77 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
78 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
79 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
80 phy->ops.identify_sfp = &ixgbe_identify_module_generic;
81 phy->sfp_type = ixgbe_sfp_type_unknown;
82 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
83 return IXGBE_SUCCESS;
84}
85
86/**
87 * ixgbe_identify_phy_generic - Get physical layer module
88 * @hw: pointer to hardware structure
89 *
90 * Determines the physical layer module found on the current adapter.
91 **/
92s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
93{
94 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
95 u32 phy_addr;
96 u16 ext_ability = 0;
97
98 DEBUGFUNC("ixgbe_identify_phy_generic");
99
100 if (hw->phy.type == ixgbe_phy_unknown) {
101 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
102 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
103 hw->phy.addr = phy_addr;
104 ixgbe_get_phy_id(hw);
105 hw->phy.type =
106 ixgbe_get_phy_type_from_id(hw->phy.id);
107
108 if (hw->phy.type == ixgbe_phy_unknown) {
109 hw->phy.ops.read_reg(hw,
110 IXGBE_MDIO_PHY_EXT_ABILITY,
111 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
112 &ext_ability);
113 if (ext_ability &
114 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
115 IXGBE_MDIO_PHY_1000BASET_ABILITY))
116 hw->phy.type =
117 ixgbe_phy_cu_unknown;
118 else
119 hw->phy.type =
120 ixgbe_phy_generic;
121 }
122
123 status = IXGBE_SUCCESS;
124 break;
125 }
126 }
127 /* clear value if nothing found */
128 if (status != IXGBE_SUCCESS)
129 hw->phy.addr = 0;
130 } else {
131 status = IXGBE_SUCCESS;
132 }
133
134 return status;
135}
136
137/**
138 * ixgbe_validate_phy_addr - Determines phy address is valid
139 * @hw: pointer to hardware structure
140 *
141 **/
142bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
143{
144 u16 phy_id = 0;
145 bool valid = FALSE;
146
147 DEBUGFUNC("ixgbe_validate_phy_addr");
148
149 hw->phy.addr = phy_addr;
150 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
151 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
152
153 if (phy_id != 0xFFFF && phy_id != 0x0)
154 valid = TRUE;
155
156 return valid;
157}
158
159/**
160 * ixgbe_get_phy_id - Get the phy type
161 * @hw: pointer to hardware structure
162 *
163 **/
164s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
165{
166 u32 status;
167 u16 phy_id_high = 0;
168 u16 phy_id_low = 0;
169
170 DEBUGFUNC("ixgbe_get_phy_id");
171
172 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
173 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
174 &phy_id_high);
175
176 if (status == IXGBE_SUCCESS) {
177 hw->phy.id = (u32)(phy_id_high << 16);
178 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
179 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
180 &phy_id_low);
181 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
182 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
183 }
184 return status;
185}
186
187/**
188 * ixgbe_get_phy_type_from_id - Get the phy type
189 * @hw: pointer to hardware structure
190 *
191 **/
192enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
193{
194 enum ixgbe_phy_type phy_type;
195
196 DEBUGFUNC("ixgbe_get_phy_type_from_id");
197
198 switch (phy_id) {
199 case TN1010_PHY_ID:
200 phy_type = ixgbe_phy_tn;
201 break;
202 case X540_PHY_ID:
203 phy_type = ixgbe_phy_aq;
204 break;
205 case QT2022_PHY_ID:
206 phy_type = ixgbe_phy_qt;
207 break;
208 case ATH_PHY_ID:
209 phy_type = ixgbe_phy_nl;
210 break;
211 default:
212 phy_type = ixgbe_phy_unknown;
213 break;
214 }
215
216 DEBUGOUT1("phy type found is %d\n", phy_type);
217 return phy_type;
218}
219
220/**
221 * ixgbe_reset_phy_generic - Performs a PHY reset
222 * @hw: pointer to hardware structure
223 **/
224s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
225{
226 u32 i;
227 u16 ctrl = 0;
228 s32 status = IXGBE_SUCCESS;
229
230 DEBUGFUNC("ixgbe_reset_phy_generic");
231
232 if (hw->phy.type == ixgbe_phy_unknown)
233 status = ixgbe_identify_phy_generic(hw);
234
235 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
236 goto out;
237
238 /* Don't reset PHY if it's shut down due to overtemp. */
239 if (!hw->phy.reset_if_overtemp &&
240 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
241 goto out;
242
243 /*
244 * Perform soft PHY reset to the PHY_XS.
245 * This will cause a soft reset to the PHY
246 */
247 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
248 IXGBE_MDIO_PHY_XS_DEV_TYPE,
249 IXGBE_MDIO_PHY_XS_RESET);
250
251 /*
252 * Poll for reset bit to self-clear indicating reset is complete.
253 * Some PHYs could take up to 3 seconds to complete and need about
254 * 1.7 usec delay after the reset is complete.
255 */
256 for (i = 0; i < 30; i++) {
257 msec_delay(100);
258 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
259 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
260 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
261 usec_delay(2);
262 break;
263 }
264 }
265
266 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
267 status = IXGBE_ERR_RESET_FAILED;
268 DEBUGOUT("PHY reset polling failed to complete.\n");
269 }
270
271out:
272 return status;
273}
274
275/**
276 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
277 * @hw: pointer to hardware structure
278 * @reg_addr: 32 bit address of PHY register to read
279 * @phy_data: Pointer to read data from PHY register
280 **/
281s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
282 u32 device_type, u16 *phy_data)
283{
284 u32 command;
285 u32 i;
286 u32 data;
287 s32 status = IXGBE_SUCCESS;
288 u16 gssr;
289
290 DEBUGFUNC("ixgbe_read_phy_reg_generic");
291
292 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
293 gssr = IXGBE_GSSR_PHY1_SM;
294 else
295 gssr = IXGBE_GSSR_PHY0_SM;
296
297 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
298 status = IXGBE_ERR_SWFW_SYNC;
299
300 if (status == IXGBE_SUCCESS) {
301 /* Setup and write the address cycle command */
302 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
303 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
304 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
305 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
306
307 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
308
309 /*
310 * Check every 10 usec to see if the address cycle completed.
311 * The MDI Command bit will clear when the operation is
312 * complete
313 */
314 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
315 usec_delay(10);
316
317 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
318
319 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
320 break;
321 }
322
323 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
324 DEBUGOUT("PHY address command did not complete.\n");
325 status = IXGBE_ERR_PHY;
326 }
327
328 if (status == IXGBE_SUCCESS) {
329 /*
330 * Address cycle complete, setup and write the read
331 * command
332 */
333 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
334 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
335 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
336 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
337
338 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
339
340 /*
341 * Check every 10 usec to see if the address cycle
342 * completed. The MDI Command bit will clear when the
343 * operation is complete
344 */
345 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
346 usec_delay(10);
347
348 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
349
350 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
351 break;
352 }
353
354 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
355 DEBUGOUT("PHY read command didn't complete\n");
356 status = IXGBE_ERR_PHY;
357 } else {
358 /*
359 * Read operation is complete. Get the data
360 * from MSRWD
361 */
362 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
363 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
364 *phy_data = (u16)(data);
365 }
366 }
367
368 hw->mac.ops.release_swfw_sync(hw, gssr);
369 }
370
371 return status;
372}
373
374/**
375 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
376 * @hw: pointer to hardware structure
377 * @reg_addr: 32 bit PHY register to write
378 * @device_type: 5 bit device type
379 * @phy_data: Data to write to the PHY register
380 **/
381s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
382 u32 device_type, u16 phy_data)
383{
384 u32 command;
385 u32 i;
386 s32 status = IXGBE_SUCCESS;
387 u16 gssr;
388
389 DEBUGFUNC("ixgbe_write_phy_reg_generic");
390
391 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
392 gssr = IXGBE_GSSR_PHY1_SM;
393 else
394 gssr = IXGBE_GSSR_PHY0_SM;
395
396 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
397 status = IXGBE_ERR_SWFW_SYNC;
398
399 if (status == IXGBE_SUCCESS) {
400 /* Put the data in the MDI single read and write data register*/
401 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
402
403 /* Setup and write the address cycle command */
404 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
405 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
406 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
407 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
408
409 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
410
411 /*
412 * Check every 10 usec to see if the address cycle completed.
413 * The MDI Command bit will clear when the operation is
414 * complete
415 */
416 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
417 usec_delay(10);
418
419 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
420
421 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
422 break;
423 }
424
425 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
426 DEBUGOUT("PHY address cmd didn't complete\n");
427 status = IXGBE_ERR_PHY;
428 }
429
430 if (status == IXGBE_SUCCESS) {
431 /*
432 * Address cycle complete, setup and write the write
433 * command
434 */
435 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
436 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
437 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
438 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
439
440 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
441
442 /*
443 * Check every 10 usec to see if the address cycle
444 * completed. The MDI Command bit will clear when the
445 * operation is complete
446 */
447 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
448 usec_delay(10);
449
450 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
451
452 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
453 break;
454 }
455
456 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
457 DEBUGOUT("PHY address cmd didn't complete\n");
458 status = IXGBE_ERR_PHY;
459 }
460 }
461
462 hw->mac.ops.release_swfw_sync(hw, gssr);
463 }
464
465 return status;
466}
467
468/**
469 * ixgbe_setup_phy_link_generic - Set and restart autoneg
470 * @hw: pointer to hardware structure
471 *
472 * Restart autonegotiation and PHY and waits for completion.
473 **/
474s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
475{
476 s32 status = IXGBE_SUCCESS;
477 u32 time_out;
478 u32 max_time_out = 10;
479 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
480 bool autoneg = FALSE;
481 ixgbe_link_speed speed;
482
483 DEBUGFUNC("ixgbe_setup_phy_link_generic");
484
485 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
486
487 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
488 /* Set or unset auto-negotiation 10G advertisement */
489 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
490 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
491 &autoneg_reg);
492
493 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
494 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
495 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
496
497 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
498 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
499 autoneg_reg);
500 }
501
502 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
503 /* Set or unset auto-negotiation 1G advertisement */
504 hw->phy.ops.read_reg(hw,
505 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
506 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
507 &autoneg_reg);
508
509 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
510 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
511 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
512
513 hw->phy.ops.write_reg(hw,
514 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
515 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
516 autoneg_reg);
517 }
518
519 if (speed & IXGBE_LINK_SPEED_100_FULL) {
520 /* Set or unset auto-negotiation 100M advertisement */
521 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
522 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
523 &autoneg_reg);
524
525 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
526 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
527 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
528 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
529
530 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
531 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
532 autoneg_reg);
533 }
534
535 /* Restart PHY autonegotiation and wait for completion */
536 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
537 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
538
539 autoneg_reg |= IXGBE_MII_RESTART;
540
541 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
542 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
543
544 /* Wait for autonegotiation to finish */
545 for (time_out = 0; time_out < max_time_out; time_out++) {
546 usec_delay(10);
547 /* Restart PHY autonegotiation and wait for completion */
548 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
549 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
550 &autoneg_reg);
551
552 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
553 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
554 break;
555 }
556
557 if (time_out == max_time_out) {
558 status = IXGBE_ERR_LINK_SETUP;
559 DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
560 }
561
562 return status;
563}
564
565/**
566 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
567 * @hw: pointer to hardware structure
568 * @speed: new link speed
569 **/
570s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
571 ixgbe_link_speed speed,
572 bool autoneg_wait_to_complete)
573{
574 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
575
576 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
577
578 /*
579 * Clear autoneg_advertised and set new values based on input link
580 * speed.
581 */
582 hw->phy.autoneg_advertised = 0;
583
584 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
585 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
586
587 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
588 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
589
590 if (speed & IXGBE_LINK_SPEED_100_FULL)
591 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
592
593 /* Setup link based on the new speed settings */
594 hw->phy.ops.setup_link(hw);
595
596 return IXGBE_SUCCESS;
597}
598
599/**
600 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
601 * @hw: pointer to hardware structure
602 * @speed: pointer to link speed
603 * @autoneg: boolean auto-negotiation value
604 *
605 * Determines the link capabilities by reading the AUTOC register.
606 **/
607s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
608 ixgbe_link_speed *speed,
609 bool *autoneg)
610{
611 s32 status = IXGBE_ERR_LINK_SETUP;
612 u16 speed_ability;
613
614 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
615
616 *speed = 0;
617 *autoneg = TRUE;
618
619 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
620 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
621 &speed_ability);
622
623 if (status == IXGBE_SUCCESS) {
624 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
625 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
626 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
627 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
628 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
629 *speed |= IXGBE_LINK_SPEED_100_FULL;
630 }
631
632 return status;
633}
634
635/**
636 * ixgbe_check_phy_link_tnx - Determine link and speed status
637 * @hw: pointer to hardware structure
638 *
639 * Reads the VS1 register to determine if link is up and the current speed for
640 * the PHY.
641 **/
642s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
643 bool *link_up)
644{
645 s32 status = IXGBE_SUCCESS;
646 u32 time_out;
647 u32 max_time_out = 10;
648 u16 phy_link = 0;
649 u16 phy_speed = 0;
650 u16 phy_data = 0;
651
652 DEBUGFUNC("ixgbe_check_phy_link_tnx");
653
654 /* Initialize speed and link to default case */
655 *link_up = FALSE;
656 *speed = IXGBE_LINK_SPEED_10GB_FULL;
657
658 /*
659 * Check current speed and link status of the PHY register.
660 * This is a vendor specific register and may have to
661 * be changed for other copper PHYs.
662 */
663 for (time_out = 0; time_out < max_time_out; time_out++) {
664 usec_delay(10);
665 status = hw->phy.ops.read_reg(hw,
666 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
667 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
668 &phy_data);
669 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
670 phy_speed = phy_data &
671 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
672 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
673 *link_up = TRUE;
674 if (phy_speed ==
675 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
676 *speed = IXGBE_LINK_SPEED_1GB_FULL;
677 break;
678 }
679 }
680
681 return status;
682}
683
684/**
685 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
686 * @hw: pointer to hardware structure
687 *
688 * Restart autonegotiation and PHY and waits for completion.
689 **/
690s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
691{
692 s32 status = IXGBE_SUCCESS;
693 u32 time_out;
694 u32 max_time_out = 10;
695 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
696 bool autoneg = FALSE;
697 ixgbe_link_speed speed;
698
699 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
700
701 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
702
703 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
704 /* Set or unset auto-negotiation 10G advertisement */
705 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
706 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
707 &autoneg_reg);
708
709 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
710 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
711 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
712
713 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
714 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
715 autoneg_reg);
716 }
717
718 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
719 /* Set or unset auto-negotiation 1G advertisement */
720 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
721 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
722 &autoneg_reg);
723
724 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
725 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
726 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
727
728 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
729 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
730 autoneg_reg);
731 }
732
733 if (speed & IXGBE_LINK_SPEED_100_FULL) {
734 /* Set or unset auto-negotiation 100M advertisement */
735 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
736 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
737 &autoneg_reg);
738
739 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
740 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
741 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
742
743 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
744 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
745 autoneg_reg);
746 }
747
748 /* Restart PHY autonegotiation and wait for completion */
749 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
750 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
751
752 autoneg_reg |= IXGBE_MII_RESTART;
753
754 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
755 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
756
757 /* Wait for autonegotiation to finish */
758 for (time_out = 0; time_out < max_time_out; time_out++) {
759 usec_delay(10);
760 /* Restart PHY autonegotiation and wait for completion */
761 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
762 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
763 &autoneg_reg);
764
765 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
766 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
767 break;
768 }
769
770 if (time_out == max_time_out) {
771 status = IXGBE_ERR_LINK_SETUP;
772 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
773 }
774
775 return status;
776}
777
778/**
779 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
780 * @hw: pointer to hardware structure
781 * @firmware_version: pointer to the PHY Firmware Version
782 **/
783s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
784 u16 *firmware_version)
785{
786 s32 status = IXGBE_SUCCESS;
787
788 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
789
790 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
791 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
792 firmware_version);
793
794 return status;
795}
796
797/**
798 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
799 * @hw: pointer to hardware structure
800 * @firmware_version: pointer to the PHY Firmware Version
801 **/
802s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
803 u16 *firmware_version)
804{
805 s32 status = IXGBE_SUCCESS;
806
807 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
808
809 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
810 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
811 firmware_version);
812
813 return status;
814}
815
816/**
817 * ixgbe_reset_phy_nl - Performs a PHY reset
818 * @hw: pointer to hardware structure
819 **/
820s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
821{
822 u16 phy_offset, control, eword, edata, block_crc;
823 bool end_data = FALSE;
824 u16 list_offset, data_offset;
825 u16 phy_data = 0;
826 s32 ret_val = IXGBE_SUCCESS;
827 u32 i;
828
829 DEBUGFUNC("ixgbe_reset_phy_nl");
830
831 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
832 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
833
834 /* reset the PHY and poll for completion */
835 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
836 IXGBE_MDIO_PHY_XS_DEV_TYPE,
837 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
838
839 for (i = 0; i < 100; i++) {
840 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
841 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
842 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
843 break;
844 msec_delay(10);
845 }
846
847 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
848 DEBUGOUT("PHY reset did not complete.\n");
849 ret_val = IXGBE_ERR_PHY;
850 goto out;
851 }
852
853 /* Get init offsets */
854 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
855 &data_offset);
856 if (ret_val != IXGBE_SUCCESS)
857 goto out;
858
859 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
860 data_offset++;
861 while (!end_data) {
862 /*
863 * Read control word from PHY init contents offset
864 */
865 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
866 control = (eword & IXGBE_CONTROL_MASK_NL) >>
867 IXGBE_CONTROL_SHIFT_NL;
868 edata = eword & IXGBE_DATA_MASK_NL;
869 switch (control) {
870 case IXGBE_DELAY_NL:
871 data_offset++;
872 DEBUGOUT1("DELAY: %d MS\n", edata);
873 msec_delay(edata);
874 break;
875 case IXGBE_DATA_NL:
876 DEBUGOUT("DATA:\n");
877 data_offset++;
878 hw->eeprom.ops.read(hw, data_offset++,
879 &phy_offset);
880 for (i = 0; i < edata; i++) {
881 hw->eeprom.ops.read(hw, data_offset, &eword);
882 hw->phy.ops.write_reg(hw, phy_offset,
883 IXGBE_TWINAX_DEV, eword);
884 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
885 phy_offset);
886 data_offset++;
887 phy_offset++;
888 }
889 break;
890 case IXGBE_CONTROL_NL:
891 data_offset++;
892 DEBUGOUT("CONTROL:\n");
893 if (edata == IXGBE_CONTROL_EOL_NL) {
894 DEBUGOUT("EOL\n");
895 end_data = TRUE;
896 } else if (edata == IXGBE_CONTROL_SOL_NL) {
897 DEBUGOUT("SOL\n");
898 } else {
899 DEBUGOUT("Bad control value\n");
900 ret_val = IXGBE_ERR_PHY;
901 goto out;
902 }
903 break;
904 default:
905 DEBUGOUT("Bad control type\n");
906 ret_val = IXGBE_ERR_PHY;
907 goto out;
908 }
909 }
910
911out:
912 return ret_val;
913}
914
915/**
916 * ixgbe_identify_module_generic - Identifies module type
917 * @hw: pointer to hardware structure
918 *
919 * Determines HW type and calls appropriate function.
920 **/
921s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
922{
923 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
924
925 DEBUGFUNC("ixgbe_identify_module_generic");
926
927 switch (hw->mac.ops.get_media_type(hw)) {
928 case ixgbe_media_type_fiber:
929 status = ixgbe_identify_sfp_module_generic(hw);
930 break;
931
932
933 default:
934 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
935 status = IXGBE_ERR_SFP_NOT_PRESENT;
936 break;
937 }
938
939 return status;
940}
941
942/**
943 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
944 * @hw: pointer to hardware structure
945 *
946 * Searches for and identifies the SFP module and assigns appropriate PHY type.
947 **/
948s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
949{
950 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
951 u32 vendor_oui = 0;
952 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
953 u8 identifier = 0;
954 u8 comp_codes_1g = 0;
955 u8 comp_codes_10g = 0;
956 u8 oui_bytes[3] = {0, 0, 0};
957 u8 cable_tech = 0;
958 u8 cable_spec = 0;
959 u16 enforce_sfp = 0;
960
961 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
962
963 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
964 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
965 status = IXGBE_ERR_SFP_NOT_PRESENT;
966 goto out;
967 }
968
969 status = hw->phy.ops.read_i2c_eeprom(hw,
970 IXGBE_SFF_IDENTIFIER,
971 &identifier);
972
973 if (status != IXGBE_SUCCESS)
974 goto err_read_i2c_eeprom;
975
976 /* LAN ID is needed for sfp_type determination */
977 hw->mac.ops.set_lan_id(hw);
978
979 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
980 hw->phy.type = ixgbe_phy_sfp_unsupported;
981 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
982 } else {
983 status = hw->phy.ops.read_i2c_eeprom(hw,
984 IXGBE_SFF_1GBE_COMP_CODES,
985 &comp_codes_1g);
986
987 if (status != IXGBE_SUCCESS)
988 goto err_read_i2c_eeprom;
989
990 status = hw->phy.ops.read_i2c_eeprom(hw,
991 IXGBE_SFF_10GBE_COMP_CODES,
992 &comp_codes_10g);
993
994 if (status != IXGBE_SUCCESS)
995 goto err_read_i2c_eeprom;
996 status = hw->phy.ops.read_i2c_eeprom(hw,
997 IXGBE_SFF_CABLE_TECHNOLOGY,
998 &cable_tech);
999
1000 if (status != IXGBE_SUCCESS)
1001 goto err_read_i2c_eeprom;
1002
1003 /* ID Module
1004 * =========
1005 * 0 SFP_DA_CU
1006 * 1 SFP_SR
1007 * 2 SFP_LR
1008 * 3 SFP_DA_CORE0 - 82599-specific
1009 * 4 SFP_DA_CORE1 - 82599-specific
1010 * 5 SFP_SR/LR_CORE0 - 82599-specific
1011 * 6 SFP_SR/LR_CORE1 - 82599-specific
1012 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1013 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1014 * 9 SFP_1g_cu_CORE0 - 82599-specific
1015 * 10 SFP_1g_cu_CORE1 - 82599-specific
1016 * 11 SFP_1g_sx_CORE0 - 82599-specific
1017 * 12 SFP_1g_sx_CORE1 - 82599-specific
1018 */
1019 if (hw->mac.type == ixgbe_mac_82598EB) {
1020 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1021 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1022 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1023 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1024 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1025 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1026 else
1027 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1028 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1029 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1030 if (hw->bus.lan_id == 0)
1031 hw->phy.sfp_type =
1032 ixgbe_sfp_type_da_cu_core0;
1033 else
1034 hw->phy.sfp_type =
1035 ixgbe_sfp_type_da_cu_core1;
1036 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1037 hw->phy.ops.read_i2c_eeprom(
1038 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1039 &cable_spec);
1040 if (cable_spec &
1041 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1042 if (hw->bus.lan_id == 0)
1043 hw->phy.sfp_type =
1044 ixgbe_sfp_type_da_act_lmt_core0;
1045 else
1046 hw->phy.sfp_type =
1047 ixgbe_sfp_type_da_act_lmt_core1;
1048 } else {
1049 hw->phy.sfp_type =
1050 ixgbe_sfp_type_unknown;
1051 }
1052 } else if (comp_codes_10g &
1053 (IXGBE_SFF_10GBASESR_CAPABLE |
1054 IXGBE_SFF_10GBASELR_CAPABLE)) {
1055 if (hw->bus.lan_id == 0)
1056 hw->phy.sfp_type =
1057 ixgbe_sfp_type_srlr_core0;
1058 else
1059 hw->phy.sfp_type =
1060 ixgbe_sfp_type_srlr_core1;
1061 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1062 if (hw->bus.lan_id == 0)
1063 hw->phy.sfp_type =
1064 ixgbe_sfp_type_1g_cu_core0;
1065 else
1066 hw->phy.sfp_type =
1067 ixgbe_sfp_type_1g_cu_core1;
1068 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1069 if (hw->bus.lan_id == 0)
1070 hw->phy.sfp_type =
1071 ixgbe_sfp_type_1g_sx_core0;
1072 else
1073 hw->phy.sfp_type =
1074 ixgbe_sfp_type_1g_sx_core1;
1075 } else {
1076 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1077 }
1078 }
1079
1080 if (hw->phy.sfp_type != stored_sfp_type)
1081 hw->phy.sfp_setup_needed = TRUE;
1082
1083 /* Determine if the SFP+ PHY is dual speed or not. */
1084 hw->phy.multispeed_fiber = FALSE;
1085 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1086 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1087 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1088 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1089 hw->phy.multispeed_fiber = TRUE;
1090
1091 /* Determine PHY vendor */
1092 if (hw->phy.type != ixgbe_phy_nl) {
1093 hw->phy.id = identifier;
1094 status = hw->phy.ops.read_i2c_eeprom(hw,
1095 IXGBE_SFF_VENDOR_OUI_BYTE0,
1096 &oui_bytes[0]);
1097
1098 if (status != IXGBE_SUCCESS)
1099 goto err_read_i2c_eeprom;
1100
1101 status = hw->phy.ops.read_i2c_eeprom(hw,
1102 IXGBE_SFF_VENDOR_OUI_BYTE1,
1103 &oui_bytes[1]);
1104
1105 if (status != IXGBE_SUCCESS)
1106 goto err_read_i2c_eeprom;
1107
1108 status = hw->phy.ops.read_i2c_eeprom(hw,
1109 IXGBE_SFF_VENDOR_OUI_BYTE2,
1110 &oui_bytes[2]);
1111
1112 if (status != IXGBE_SUCCESS)
1113 goto err_read_i2c_eeprom;
1114
1115 vendor_oui =
1116 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1117 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1118 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1119
1120 switch (vendor_oui) {
1121 case IXGBE_SFF_VENDOR_OUI_TYCO:
1122 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1123 hw->phy.type =
1124 ixgbe_phy_sfp_passive_tyco;
1125 break;
1126 case IXGBE_SFF_VENDOR_OUI_FTL:
1127 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1128 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1129 else
1130 hw->phy.type = ixgbe_phy_sfp_ftl;
1131 break;
1132 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1133 hw->phy.type = ixgbe_phy_sfp_avago;
1134 break;
1135 case IXGBE_SFF_VENDOR_OUI_INTEL:
1136 hw->phy.type = ixgbe_phy_sfp_intel;
1137 break;
1138 default:
1139 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1140 hw->phy.type =
1141 ixgbe_phy_sfp_passive_unknown;
1142 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1143 hw->phy.type =
1144 ixgbe_phy_sfp_active_unknown;
1145 else
1146 hw->phy.type = ixgbe_phy_sfp_unknown;
1147 break;
1148 }
1149 }
1150
1151 /* Allow any DA cable vendor */
1152 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1153 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1154 status = IXGBE_SUCCESS;
1155 goto out;
1156 }
1157
1158 /* Verify supported 1G SFP modules */
1159 if (comp_codes_10g == 0 &&
1160 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1161 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1162 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1163 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1164 hw->phy.type = ixgbe_phy_sfp_unsupported;
1165 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1166 goto out;
1167 }
1168
1169 /* Anything else 82598-based is supported */
1170 if (hw->mac.type == ixgbe_mac_82598EB) {
1171 status = IXGBE_SUCCESS;
1172 goto out;
1173 }
1174
1175 ixgbe_get_device_caps(hw, &enforce_sfp);
1176 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1177 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1178 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
1179 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||
1180 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
1181 /* Make sure we're a supported PHY type */
1182 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1183 status = IXGBE_SUCCESS;
1184 } else {
1185 if (hw->allow_unsupported_sfp == TRUE) {
1186 EWARN(hw, "WARNING: Intel (R) Network "
1187 "Connections are quality tested "
1188 "using Intel (R) Ethernet Optics."
1189 " Using untested modules is not "
1190 "supported and may cause unstable"
1191 " operation or damage to the "
1192 "module or the adapter. Intel "
1193 "Corporation is not responsible "
1194 "for any harm caused by using "
1195 "untested modules.\n", status);
1196 status = IXGBE_SUCCESS;
1197 } else {
1198 DEBUGOUT("SFP+ module not supported\n");
1199 hw->phy.type =
1200 ixgbe_phy_sfp_unsupported;
1201 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1202 }
1203 }
1204 } else {
1205 status = IXGBE_SUCCESS;
1206 }
1207 }
1208
1209out:
1210 return status;
1211
1212err_read_i2c_eeprom:
1213 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1214 if (hw->phy.type != ixgbe_phy_nl) {
1215 hw->phy.id = 0;
1216 hw->phy.type = ixgbe_phy_unknown;
1217 }
1218 return IXGBE_ERR_SFP_NOT_PRESENT;
1219}
1220
1221
1222
1223/**
1224 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1225 * @hw: pointer to hardware structure
1226 * @list_offset: offset to the SFP ID list
1227 * @data_offset: offset to the SFP data block
1228 *
1229 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1230 * so it returns the offsets to the phy init sequence block.
1231 **/
1232s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1233 u16 *list_offset,
1234 u16 *data_offset)
1235{
1236 u16 sfp_id;
1237 u16 sfp_type = hw->phy.sfp_type;
1238
1239 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1240
1241 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1242 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1243
1244 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1245 return IXGBE_ERR_SFP_NOT_PRESENT;
1246
1247 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1248 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1249 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1250
1251 /*
1252 * Limiting active cables and 1G Phys must be initialized as
1253 * SR modules
1254 */
1255 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1256 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1257 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1258 sfp_type = ixgbe_sfp_type_srlr_core0;
1259 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1260 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1261 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1262 sfp_type = ixgbe_sfp_type_srlr_core1;
1263
1264 /* Read offset to PHY init contents */
1265 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1266
1267 if ((!*list_offset) || (*list_offset == 0xFFFF))
1268 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1269
1270 /* Shift offset to first ID word */
1271 (*list_offset)++;
1272
1273 /*
1274 * Find the matching SFP ID in the EEPROM
1275 * and program the init sequence
1276 */
1277 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1278
1279 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1280 if (sfp_id == sfp_type) {
1281 (*list_offset)++;
1282 hw->eeprom.ops.read(hw, *list_offset, data_offset);
1283 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1284 DEBUGOUT("SFP+ module not supported\n");
1285 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1286 } else {
1287 break;
1288 }
1289 } else {
1290 (*list_offset) += 2;
1291 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1292 return IXGBE_ERR_PHY;
1293 }
1294 }
1295
1296 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1297 DEBUGOUT("No matching SFP+ module found\n");
1298 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1299 }
1300
1301 return IXGBE_SUCCESS;
1302}
1303
1304/**
1305 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1306 * @hw: pointer to hardware structure
1307 * @byte_offset: EEPROM byte offset to read
1308 * @eeprom_data: value read
1309 *
1310 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1311 **/
1312s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1313 u8 *eeprom_data)
1314{
1315 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1316
1317 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1318 IXGBE_I2C_EEPROM_DEV_ADDR,
1319 eeprom_data);
1320}
1321
1322/**
1323 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1324 * @hw: pointer to hardware structure
1325 * @byte_offset: byte offset at address 0xA2
1326 * @eeprom_data: value read
1327 *
1328 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1329 **/
1330static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1331 u8 *sff8472_data)
1332{
1333 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1334 IXGBE_I2C_EEPROM_DEV_ADDR2,
1335 sff8472_data);
1336}
1337
1338/**
1339 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1340 * @hw: pointer to hardware structure
1341 * @byte_offset: EEPROM byte offset to write
1342 * @eeprom_data: value to write
1343 *
1344 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1345 **/
1346s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1347 u8 eeprom_data)
1348{
1349 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1350
1351 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1352 IXGBE_I2C_EEPROM_DEV_ADDR,
1353 eeprom_data);
1354}
1355
1356/**
1357 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1358 * @hw: pointer to hardware structure
1359 * @byte_offset: byte offset to read
1360 * @data: value read
1361 *
1362 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1363 * a specified device address.
1364 **/
1365s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1366 u8 dev_addr, u8 *data)
1367{
1368 s32 status = IXGBE_SUCCESS;
1369 u32 max_retry = 10;
1370 u32 retry = 0;
1371 u16 swfw_mask = 0;
1372 bool nack = 1;
1373 *data = 0;
1374
1375 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1376
1377 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1378 swfw_mask = IXGBE_GSSR_PHY1_SM;
1379 else
1380 swfw_mask = IXGBE_GSSR_PHY0_SM;
1381
1382 do {
1383 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1384 != IXGBE_SUCCESS) {
1385 status = IXGBE_ERR_SWFW_SYNC;
1386 goto read_byte_out;
1387 }
1388
1389 ixgbe_i2c_start(hw);
1390
1391 /* Device Address and write indication */
1392 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1393 if (status != IXGBE_SUCCESS)
1394 goto fail;
1395
1396 status = ixgbe_get_i2c_ack(hw);
1397 if (status != IXGBE_SUCCESS)
1398 goto fail;
1399
1400 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1401 if (status != IXGBE_SUCCESS)
1402 goto fail;
1403
1404 status = ixgbe_get_i2c_ack(hw);
1405 if (status != IXGBE_SUCCESS)
1406 goto fail;
1407
1408 ixgbe_i2c_start(hw);
1409
1410 /* Device Address and read indication */
1411 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1412 if (status != IXGBE_SUCCESS)
1413 goto fail;
1414
1415 status = ixgbe_get_i2c_ack(hw);
1416 if (status != IXGBE_SUCCESS)
1417 goto fail;
1418
1419 status = ixgbe_clock_in_i2c_byte(hw, data);
1420 if (status != IXGBE_SUCCESS)
1421 goto fail;
1422
1423 status = ixgbe_clock_out_i2c_bit(hw, nack);
1424 if (status != IXGBE_SUCCESS)
1425 goto fail;
1426
1427 ixgbe_i2c_stop(hw);
1428 break;
1429
1430fail:
1431 ixgbe_i2c_bus_clear(hw);
1432 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1433 msec_delay(100);
1434 retry++;
1435 if (retry < max_retry)
1436 DEBUGOUT("I2C byte read error - Retrying.\n");
1437 else
1438 DEBUGOUT("I2C byte read error.\n");
1439
1440 } while (retry < max_retry);
1441
1442 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1443
1444read_byte_out:
1445 return status;
1446}
1447
1448/**
1449 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1450 * @hw: pointer to hardware structure
1451 * @byte_offset: byte offset to write
1452 * @data: value to write
1453 *
1454 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1455 * a specified device address.
1456 **/
1457s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1458 u8 dev_addr, u8 data)
1459{
1460 s32 status = IXGBE_SUCCESS;
1461 u32 max_retry = 1;
1462 u32 retry = 0;
1463 u16 swfw_mask = 0;
1464
1465 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1466
1467 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1468 swfw_mask = IXGBE_GSSR_PHY1_SM;
1469 else
1470 swfw_mask = IXGBE_GSSR_PHY0_SM;
1471
1472 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1473 status = IXGBE_ERR_SWFW_SYNC;
1474 goto write_byte_out;
1475 }
1476
1477 do {
1478 ixgbe_i2c_start(hw);
1479
1480 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1481 if (status != IXGBE_SUCCESS)
1482 goto fail;
1483
1484 status = ixgbe_get_i2c_ack(hw);
1485 if (status != IXGBE_SUCCESS)
1486 goto fail;
1487
1488 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1489 if (status != IXGBE_SUCCESS)
1490 goto fail;
1491
1492 status = ixgbe_get_i2c_ack(hw);
1493 if (status != IXGBE_SUCCESS)
1494 goto fail;
1495
1496 status = ixgbe_clock_out_i2c_byte(hw, data);
1497 if (status != IXGBE_SUCCESS)
1498 goto fail;
1499
1500 status = ixgbe_get_i2c_ack(hw);
1501 if (status != IXGBE_SUCCESS)
1502 goto fail;
1503
1504 ixgbe_i2c_stop(hw);
1505 break;
1506
1507fail:
1508 ixgbe_i2c_bus_clear(hw);
1509 retry++;
1510 if (retry < max_retry)
1511 DEBUGOUT("I2C byte write error - Retrying.\n");
1512 else
1513 DEBUGOUT("I2C byte write error.\n");
1514 } while (retry < max_retry);
1515
1516 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1517
1518write_byte_out:
1519 return status;
1520}
1521
1522/**
1523 * ixgbe_i2c_start - Sets I2C start condition
1524 * @hw: pointer to hardware structure
1525 *
1526 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1527 **/
1528static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1529{
1530 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1531
1532 DEBUGFUNC("ixgbe_i2c_start");
1533
1534 /* Start condition must begin with data and clock high */
1535 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1536 ixgbe_raise_i2c_clk(hw, &i2cctl);
1537
1538 /* Setup time for start condition (4.7us) */
1539 usec_delay(IXGBE_I2C_T_SU_STA);
1540
1541 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1542
1543 /* Hold time for start condition (4us) */
1544 usec_delay(IXGBE_I2C_T_HD_STA);
1545
1546 ixgbe_lower_i2c_clk(hw, &i2cctl);
1547
1548 /* Minimum low period of clock is 4.7 us */
1549 usec_delay(IXGBE_I2C_T_LOW);
1550
1551}
1552
1553/**
1554 * ixgbe_i2c_stop - Sets I2C stop condition
1555 * @hw: pointer to hardware structure
1556 *
1557 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1558 **/
1559static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1560{
1561 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1562
1563 DEBUGFUNC("ixgbe_i2c_stop");
1564
1565 /* Stop condition must begin with data low and clock high */
1566 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1567 ixgbe_raise_i2c_clk(hw, &i2cctl);
1568
1569 /* Setup time for stop condition (4us) */
1570 usec_delay(IXGBE_I2C_T_SU_STO);
1571
1572 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1573
1574 /* bus free time between stop and start (4.7us)*/
1575 usec_delay(IXGBE_I2C_T_BUF);
1576}
1577
1578/**
1579 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1580 * @hw: pointer to hardware structure
1581 * @data: data byte to clock in
1582 *
1583 * Clocks in one byte data via I2C data/clock
1584 **/
1585static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1586{
1587 s32 i;
1588 bool bit = 0;
1589
1590 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1591
1592 for (i = 7; i >= 0; i--) {
1593 ixgbe_clock_in_i2c_bit(hw, &bit);
1594 *data |= bit << i;
1595 }
1596
1597 return IXGBE_SUCCESS;
1598}
1599
1600/**
1601 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1602 * @hw: pointer to hardware structure
1603 * @data: data byte clocked out
1604 *
1605 * Clocks out one byte data via I2C data/clock
1606 **/
1607static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1608{
1609 s32 status = IXGBE_SUCCESS;
1610 s32 i;
1611 u32 i2cctl;
1612 bool bit = 0;
1613
1614 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1615
1616 for (i = 7; i >= 0; i--) {
1617 bit = (data >> i) & 0x1;
1618 status = ixgbe_clock_out_i2c_bit(hw, bit);
1619
1620 if (status != IXGBE_SUCCESS)
1621 break;
1622 }
1623
1624 /* Release SDA line (set high) */
1625 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1626 i2cctl |= IXGBE_I2C_DATA_OUT;
1627 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1628 IXGBE_WRITE_FLUSH(hw);
1629
1630 return status;
1631}
1632
1633/**
1634 * ixgbe_get_i2c_ack - Polls for I2C ACK
1635 * @hw: pointer to hardware structure
1636 *
1637 * Clocks in/out one bit via I2C data/clock
1638 **/
1639static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1640{
1641 s32 status = IXGBE_SUCCESS;
1642 u32 i = 0;
1643 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1644 u32 timeout = 10;
1645 bool ack = 1;
1646
1647 DEBUGFUNC("ixgbe_get_i2c_ack");
1648
1649 ixgbe_raise_i2c_clk(hw, &i2cctl);
1650
1651
1652 /* Minimum high period of clock is 4us */
1653 usec_delay(IXGBE_I2C_T_HIGH);
1654
1655 /* Poll for ACK. Note that ACK in I2C spec is
1656 * transition from 1 to 0 */
1657 for (i = 0; i < timeout; i++) {
1658 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1659 ack = ixgbe_get_i2c_data(&i2cctl);
1660
1661 usec_delay(1);
1662 if (ack == 0)
1663 break;
1664 }
1665
1666 if (ack == 1) {
1667 DEBUGOUT("I2C ack was not received.\n");
1668 status = IXGBE_ERR_I2C;
1669 }
1670
1671 ixgbe_lower_i2c_clk(hw, &i2cctl);
1672
1673 /* Minimum low period of clock is 4.7 us */
1674 usec_delay(IXGBE_I2C_T_LOW);
1675
1676 return status;
1677}
1678
1679/**
1680 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1681 * @hw: pointer to hardware structure
1682 * @data: read data value
1683 *
1684 * Clocks in one bit via I2C data/clock
1685 **/
1686static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1687{
1688 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1689
1690 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1691
1692 ixgbe_raise_i2c_clk(hw, &i2cctl);
1693
1694 /* Minimum high period of clock is 4us */
1695 usec_delay(IXGBE_I2C_T_HIGH);
1696
1697 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1698 *data = ixgbe_get_i2c_data(&i2cctl);
1699
1700 ixgbe_lower_i2c_clk(hw, &i2cctl);
1701
1702 /* Minimum low period of clock is 4.7 us */
1703 usec_delay(IXGBE_I2C_T_LOW);
1704
1705 return IXGBE_SUCCESS;
1706}
1707
1708/**
1709 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1710 * @hw: pointer to hardware structure
1711 * @data: data value to write
1712 *
1713 * Clocks out one bit via I2C data/clock
1714 **/
1715static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1716{
1717 s32 status;
1718 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1719
1720 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1721
1722 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1723 if (status == IXGBE_SUCCESS) {
1724 ixgbe_raise_i2c_clk(hw, &i2cctl);
1725
1726 /* Minimum high period of clock is 4us */
1727 usec_delay(IXGBE_I2C_T_HIGH);
1728
1729 ixgbe_lower_i2c_clk(hw, &i2cctl);
1730
1731 /* Minimum low period of clock is 4.7 us.
1732 * This also takes care of the data hold time.
1733 */
1734 usec_delay(IXGBE_I2C_T_LOW);
1735 } else {
1736 status = IXGBE_ERR_I2C;
1737 DEBUGOUT1("I2C data was not set to %X\n", data);
1738 }
1739
1740 return status;
1741}
1742/**
1743 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1744 * @hw: pointer to hardware structure
1745 * @i2cctl: Current value of I2CCTL register
1746 *
1747 * Raises the I2C clock line '0'->'1'
1748 **/
1749static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1750{
1751 u32 i = 0;
1752 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1753 u32 i2cctl_r = 0;
1754
1755 DEBUGFUNC("ixgbe_raise_i2c_clk");
1756
1757 for (i = 0; i < timeout; i++) {
1758 *i2cctl |= IXGBE_I2C_CLK_OUT;
1759
1760 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1761 IXGBE_WRITE_FLUSH(hw);
1762 /* SCL rise time (1000ns) */
1763 usec_delay(IXGBE_I2C_T_RISE);
1764
1765 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1766 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1767 break;
1768 }
1769}
1770
1771/**
1772 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1773 * @hw: pointer to hardware structure
1774 * @i2cctl: Current value of I2CCTL register
1775 *
1776 * Lowers the I2C clock line '1'->'0'
1777 **/
1778static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1779{
1780
1781 DEBUGFUNC("ixgbe_lower_i2c_clk");
1782
1783 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1784
1785 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1786 IXGBE_WRITE_FLUSH(hw);
1787
1788 /* SCL fall time (300ns) */
1789 usec_delay(IXGBE_I2C_T_FALL);
1790}
1791
1792/**
1793 * ixgbe_set_i2c_data - Sets the I2C data bit
1794 * @hw: pointer to hardware structure
1795 * @i2cctl: Current value of I2CCTL register
1796 * @data: I2C data value (0 or 1) to set
1797 *
1798 * Sets the I2C data bit
1799 **/
1800static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1801{
1802 s32 status = IXGBE_SUCCESS;
1803
1804 DEBUGFUNC("ixgbe_set_i2c_data");
1805
1806 if (data)
1807 *i2cctl |= IXGBE_I2C_DATA_OUT;
1808 else
1809 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1810
1811 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1812 IXGBE_WRITE_FLUSH(hw);
1813
1814 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1815 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1816
1817 /* Verify data was set correctly */
1818 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1819 if (data != ixgbe_get_i2c_data(i2cctl)) {
1820 status = IXGBE_ERR_I2C;
1821 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
1822 }
1823
1824 return status;
1825}
1826
1827/**
1828 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1829 * @hw: pointer to hardware structure
1830 * @i2cctl: Current value of I2CCTL register
1831 *
1832 * Returns the I2C data bit value
1833 **/
1834static bool ixgbe_get_i2c_data(u32 *i2cctl)
1835{
1836 bool data;
1837
1838 DEBUGFUNC("ixgbe_get_i2c_data");
1839
1840 if (*i2cctl & IXGBE_I2C_DATA_IN)
1841 data = 1;
1842 else
1843 data = 0;
1844
1845 return data;
1846}
1847
1848/**
1849 * ixgbe_i2c_bus_clear - Clears the I2C bus
1850 * @hw: pointer to hardware structure
1851 *
1852 * Clears the I2C bus by sending nine clock pulses.
1853 * Used when data line is stuck low.
1854 **/
1855void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1856{
1857 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1858 u32 i;
1859
1860 DEBUGFUNC("ixgbe_i2c_bus_clear");
1861
1862 ixgbe_i2c_start(hw);
1863
1864 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1865
1866 for (i = 0; i < 9; i++) {
1867 ixgbe_raise_i2c_clk(hw, &i2cctl);
1868
1869 /* Min high period of clock is 4us */
1870 usec_delay(IXGBE_I2C_T_HIGH);
1871
1872 ixgbe_lower_i2c_clk(hw, &i2cctl);
1873
1874 /* Min low period of clock is 4.7us*/
1875 usec_delay(IXGBE_I2C_T_LOW);
1876 }
1877
1878 ixgbe_i2c_start(hw);
1879
1880 /* Put the i2c bus back to default state */
1881 ixgbe_i2c_stop(hw);
1882}
1883
1884/**
1885 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1886 * @hw: pointer to hardware structure
1887 *
1888 * Checks if the LASI temp alarm status was triggered due to overtemp
1889 **/
1890s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1891{
1892 s32 status = IXGBE_SUCCESS;
1893 u16 phy_data = 0;
1894
1895 DEBUGFUNC("ixgbe_tn_check_overtemp");
1896
1897 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1898 goto out;
1899
1900 /* Check that the LASI temp alarm status was triggered */
1901 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1902 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1903
1904 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1905 goto out;
1906
1907 status = IXGBE_ERR_OVERTEMP;
1908out:
1909 return status;
1910}
2
3 Copyright (c) 2001-2013, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 247822 2013-03-04 23:07:40Z jfv $*/
34
35#include "ixgbe_api.h"
36#include "ixgbe_common.h"
37#include "ixgbe_phy.h"
38
39static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49static bool ixgbe_get_i2c_data(u32 *i2cctl);
50static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
51 u8 *sff8472_data);
52
53/**
54 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
55 * @hw: pointer to the hardware structure
56 *
57 * Initialize the function pointers.
58 **/
59s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
60{
61 struct ixgbe_phy_info *phy = &hw->phy;
62
63 DEBUGFUNC("ixgbe_init_phy_ops_generic");
64
65 /* PHY */
66 phy->ops.identify = &ixgbe_identify_phy_generic;
67 phy->ops.reset = &ixgbe_reset_phy_generic;
68 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
69 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
70 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
71 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
72 phy->ops.check_link = NULL;
73 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
74 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
75 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
76 phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic;
77 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
78 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
79 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
80 phy->ops.identify_sfp = &ixgbe_identify_module_generic;
81 phy->sfp_type = ixgbe_sfp_type_unknown;
82 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
83 return IXGBE_SUCCESS;
84}
85
86/**
87 * ixgbe_identify_phy_generic - Get physical layer module
88 * @hw: pointer to hardware structure
89 *
90 * Determines the physical layer module found on the current adapter.
91 **/
92s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
93{
94 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
95 u32 phy_addr;
96 u16 ext_ability = 0;
97
98 DEBUGFUNC("ixgbe_identify_phy_generic");
99
100 if (hw->phy.type == ixgbe_phy_unknown) {
101 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
102 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
103 hw->phy.addr = phy_addr;
104 ixgbe_get_phy_id(hw);
105 hw->phy.type =
106 ixgbe_get_phy_type_from_id(hw->phy.id);
107
108 if (hw->phy.type == ixgbe_phy_unknown) {
109 hw->phy.ops.read_reg(hw,
110 IXGBE_MDIO_PHY_EXT_ABILITY,
111 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
112 &ext_ability);
113 if (ext_ability &
114 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
115 IXGBE_MDIO_PHY_1000BASET_ABILITY))
116 hw->phy.type =
117 ixgbe_phy_cu_unknown;
118 else
119 hw->phy.type =
120 ixgbe_phy_generic;
121 }
122
123 status = IXGBE_SUCCESS;
124 break;
125 }
126 }
127 /* clear value if nothing found */
128 if (status != IXGBE_SUCCESS)
129 hw->phy.addr = 0;
130 } else {
131 status = IXGBE_SUCCESS;
132 }
133
134 return status;
135}
136
137/**
138 * ixgbe_validate_phy_addr - Determines phy address is valid
139 * @hw: pointer to hardware structure
140 *
141 **/
142bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
143{
144 u16 phy_id = 0;
145 bool valid = FALSE;
146
147 DEBUGFUNC("ixgbe_validate_phy_addr");
148
149 hw->phy.addr = phy_addr;
150 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
151 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
152
153 if (phy_id != 0xFFFF && phy_id != 0x0)
154 valid = TRUE;
155
156 return valid;
157}
158
159/**
160 * ixgbe_get_phy_id - Get the phy type
161 * @hw: pointer to hardware structure
162 *
163 **/
164s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
165{
166 u32 status;
167 u16 phy_id_high = 0;
168 u16 phy_id_low = 0;
169
170 DEBUGFUNC("ixgbe_get_phy_id");
171
172 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
173 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
174 &phy_id_high);
175
176 if (status == IXGBE_SUCCESS) {
177 hw->phy.id = (u32)(phy_id_high << 16);
178 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
179 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
180 &phy_id_low);
181 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
182 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
183 }
184 return status;
185}
186
187/**
188 * ixgbe_get_phy_type_from_id - Get the phy type
189 * @hw: pointer to hardware structure
190 *
191 **/
192enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
193{
194 enum ixgbe_phy_type phy_type;
195
196 DEBUGFUNC("ixgbe_get_phy_type_from_id");
197
198 switch (phy_id) {
199 case TN1010_PHY_ID:
200 phy_type = ixgbe_phy_tn;
201 break;
202 case X540_PHY_ID:
203 phy_type = ixgbe_phy_aq;
204 break;
205 case QT2022_PHY_ID:
206 phy_type = ixgbe_phy_qt;
207 break;
208 case ATH_PHY_ID:
209 phy_type = ixgbe_phy_nl;
210 break;
211 default:
212 phy_type = ixgbe_phy_unknown;
213 break;
214 }
215
216 DEBUGOUT1("phy type found is %d\n", phy_type);
217 return phy_type;
218}
219
220/**
221 * ixgbe_reset_phy_generic - Performs a PHY reset
222 * @hw: pointer to hardware structure
223 **/
224s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
225{
226 u32 i;
227 u16 ctrl = 0;
228 s32 status = IXGBE_SUCCESS;
229
230 DEBUGFUNC("ixgbe_reset_phy_generic");
231
232 if (hw->phy.type == ixgbe_phy_unknown)
233 status = ixgbe_identify_phy_generic(hw);
234
235 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
236 goto out;
237
238 /* Don't reset PHY if it's shut down due to overtemp. */
239 if (!hw->phy.reset_if_overtemp &&
240 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
241 goto out;
242
243 /*
244 * Perform soft PHY reset to the PHY_XS.
245 * This will cause a soft reset to the PHY
246 */
247 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
248 IXGBE_MDIO_PHY_XS_DEV_TYPE,
249 IXGBE_MDIO_PHY_XS_RESET);
250
251 /*
252 * Poll for reset bit to self-clear indicating reset is complete.
253 * Some PHYs could take up to 3 seconds to complete and need about
254 * 1.7 usec delay after the reset is complete.
255 */
256 for (i = 0; i < 30; i++) {
257 msec_delay(100);
258 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
259 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
260 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
261 usec_delay(2);
262 break;
263 }
264 }
265
266 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
267 status = IXGBE_ERR_RESET_FAILED;
268 DEBUGOUT("PHY reset polling failed to complete.\n");
269 }
270
271out:
272 return status;
273}
274
275/**
276 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
277 * @hw: pointer to hardware structure
278 * @reg_addr: 32 bit address of PHY register to read
279 * @phy_data: Pointer to read data from PHY register
280 **/
281s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
282 u32 device_type, u16 *phy_data)
283{
284 u32 command;
285 u32 i;
286 u32 data;
287 s32 status = IXGBE_SUCCESS;
288 u16 gssr;
289
290 DEBUGFUNC("ixgbe_read_phy_reg_generic");
291
292 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
293 gssr = IXGBE_GSSR_PHY1_SM;
294 else
295 gssr = IXGBE_GSSR_PHY0_SM;
296
297 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
298 status = IXGBE_ERR_SWFW_SYNC;
299
300 if (status == IXGBE_SUCCESS) {
301 /* Setup and write the address cycle command */
302 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
303 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
304 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
305 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
306
307 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
308
309 /*
310 * Check every 10 usec to see if the address cycle completed.
311 * The MDI Command bit will clear when the operation is
312 * complete
313 */
314 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
315 usec_delay(10);
316
317 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
318
319 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
320 break;
321 }
322
323 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
324 DEBUGOUT("PHY address command did not complete.\n");
325 status = IXGBE_ERR_PHY;
326 }
327
328 if (status == IXGBE_SUCCESS) {
329 /*
330 * Address cycle complete, setup and write the read
331 * command
332 */
333 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
334 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
335 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
336 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
337
338 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
339
340 /*
341 * Check every 10 usec to see if the address cycle
342 * completed. The MDI Command bit will clear when the
343 * operation is complete
344 */
345 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
346 usec_delay(10);
347
348 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
349
350 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
351 break;
352 }
353
354 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
355 DEBUGOUT("PHY read command didn't complete\n");
356 status = IXGBE_ERR_PHY;
357 } else {
358 /*
359 * Read operation is complete. Get the data
360 * from MSRWD
361 */
362 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
363 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
364 *phy_data = (u16)(data);
365 }
366 }
367
368 hw->mac.ops.release_swfw_sync(hw, gssr);
369 }
370
371 return status;
372}
373
374/**
375 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
376 * @hw: pointer to hardware structure
377 * @reg_addr: 32 bit PHY register to write
378 * @device_type: 5 bit device type
379 * @phy_data: Data to write to the PHY register
380 **/
381s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
382 u32 device_type, u16 phy_data)
383{
384 u32 command;
385 u32 i;
386 s32 status = IXGBE_SUCCESS;
387 u16 gssr;
388
389 DEBUGFUNC("ixgbe_write_phy_reg_generic");
390
391 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
392 gssr = IXGBE_GSSR_PHY1_SM;
393 else
394 gssr = IXGBE_GSSR_PHY0_SM;
395
396 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
397 status = IXGBE_ERR_SWFW_SYNC;
398
399 if (status == IXGBE_SUCCESS) {
400 /* Put the data in the MDI single read and write data register*/
401 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
402
403 /* Setup and write the address cycle command */
404 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
405 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
406 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
407 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
408
409 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
410
411 /*
412 * Check every 10 usec to see if the address cycle completed.
413 * The MDI Command bit will clear when the operation is
414 * complete
415 */
416 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
417 usec_delay(10);
418
419 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
420
421 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
422 break;
423 }
424
425 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
426 DEBUGOUT("PHY address cmd didn't complete\n");
427 status = IXGBE_ERR_PHY;
428 }
429
430 if (status == IXGBE_SUCCESS) {
431 /*
432 * Address cycle complete, setup and write the write
433 * command
434 */
435 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
436 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
437 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
438 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
439
440 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
441
442 /*
443 * Check every 10 usec to see if the address cycle
444 * completed. The MDI Command bit will clear when the
445 * operation is complete
446 */
447 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
448 usec_delay(10);
449
450 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
451
452 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
453 break;
454 }
455
456 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
457 DEBUGOUT("PHY address cmd didn't complete\n");
458 status = IXGBE_ERR_PHY;
459 }
460 }
461
462 hw->mac.ops.release_swfw_sync(hw, gssr);
463 }
464
465 return status;
466}
467
468/**
469 * ixgbe_setup_phy_link_generic - Set and restart autoneg
470 * @hw: pointer to hardware structure
471 *
472 * Restart autonegotiation and PHY and waits for completion.
473 **/
474s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
475{
476 s32 status = IXGBE_SUCCESS;
477 u32 time_out;
478 u32 max_time_out = 10;
479 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
480 bool autoneg = FALSE;
481 ixgbe_link_speed speed;
482
483 DEBUGFUNC("ixgbe_setup_phy_link_generic");
484
485 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
486
487 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
488 /* Set or unset auto-negotiation 10G advertisement */
489 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
490 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
491 &autoneg_reg);
492
493 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
494 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
495 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
496
497 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
498 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
499 autoneg_reg);
500 }
501
502 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
503 /* Set or unset auto-negotiation 1G advertisement */
504 hw->phy.ops.read_reg(hw,
505 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
506 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
507 &autoneg_reg);
508
509 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
510 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
511 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
512
513 hw->phy.ops.write_reg(hw,
514 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
515 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
516 autoneg_reg);
517 }
518
519 if (speed & IXGBE_LINK_SPEED_100_FULL) {
520 /* Set or unset auto-negotiation 100M advertisement */
521 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
522 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
523 &autoneg_reg);
524
525 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
526 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
527 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
528 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
529
530 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
531 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
532 autoneg_reg);
533 }
534
535 /* Restart PHY autonegotiation and wait for completion */
536 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
537 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
538
539 autoneg_reg |= IXGBE_MII_RESTART;
540
541 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
542 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
543
544 /* Wait for autonegotiation to finish */
545 for (time_out = 0; time_out < max_time_out; time_out++) {
546 usec_delay(10);
547 /* Restart PHY autonegotiation and wait for completion */
548 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
549 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
550 &autoneg_reg);
551
552 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
553 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
554 break;
555 }
556
557 if (time_out == max_time_out) {
558 status = IXGBE_ERR_LINK_SETUP;
559 DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
560 }
561
562 return status;
563}
564
565/**
566 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
567 * @hw: pointer to hardware structure
568 * @speed: new link speed
569 **/
570s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
571 ixgbe_link_speed speed,
572 bool autoneg_wait_to_complete)
573{
574 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
575
576 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
577
578 /*
579 * Clear autoneg_advertised and set new values based on input link
580 * speed.
581 */
582 hw->phy.autoneg_advertised = 0;
583
584 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
585 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
586
587 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
588 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
589
590 if (speed & IXGBE_LINK_SPEED_100_FULL)
591 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
592
593 /* Setup link based on the new speed settings */
594 hw->phy.ops.setup_link(hw);
595
596 return IXGBE_SUCCESS;
597}
598
599/**
600 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
601 * @hw: pointer to hardware structure
602 * @speed: pointer to link speed
603 * @autoneg: boolean auto-negotiation value
604 *
605 * Determines the link capabilities by reading the AUTOC register.
606 **/
607s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
608 ixgbe_link_speed *speed,
609 bool *autoneg)
610{
611 s32 status = IXGBE_ERR_LINK_SETUP;
612 u16 speed_ability;
613
614 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
615
616 *speed = 0;
617 *autoneg = TRUE;
618
619 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
620 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
621 &speed_ability);
622
623 if (status == IXGBE_SUCCESS) {
624 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
625 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
626 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
627 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
628 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
629 *speed |= IXGBE_LINK_SPEED_100_FULL;
630 }
631
632 return status;
633}
634
635/**
636 * ixgbe_check_phy_link_tnx - Determine link and speed status
637 * @hw: pointer to hardware structure
638 *
639 * Reads the VS1 register to determine if link is up and the current speed for
640 * the PHY.
641 **/
642s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
643 bool *link_up)
644{
645 s32 status = IXGBE_SUCCESS;
646 u32 time_out;
647 u32 max_time_out = 10;
648 u16 phy_link = 0;
649 u16 phy_speed = 0;
650 u16 phy_data = 0;
651
652 DEBUGFUNC("ixgbe_check_phy_link_tnx");
653
654 /* Initialize speed and link to default case */
655 *link_up = FALSE;
656 *speed = IXGBE_LINK_SPEED_10GB_FULL;
657
658 /*
659 * Check current speed and link status of the PHY register.
660 * This is a vendor specific register and may have to
661 * be changed for other copper PHYs.
662 */
663 for (time_out = 0; time_out < max_time_out; time_out++) {
664 usec_delay(10);
665 status = hw->phy.ops.read_reg(hw,
666 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
667 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
668 &phy_data);
669 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
670 phy_speed = phy_data &
671 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
672 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
673 *link_up = TRUE;
674 if (phy_speed ==
675 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
676 *speed = IXGBE_LINK_SPEED_1GB_FULL;
677 break;
678 }
679 }
680
681 return status;
682}
683
684/**
685 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
686 * @hw: pointer to hardware structure
687 *
688 * Restart autonegotiation and PHY and waits for completion.
689 **/
690s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
691{
692 s32 status = IXGBE_SUCCESS;
693 u32 time_out;
694 u32 max_time_out = 10;
695 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
696 bool autoneg = FALSE;
697 ixgbe_link_speed speed;
698
699 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
700
701 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
702
703 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
704 /* Set or unset auto-negotiation 10G advertisement */
705 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
706 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
707 &autoneg_reg);
708
709 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
710 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
711 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
712
713 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
714 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
715 autoneg_reg);
716 }
717
718 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
719 /* Set or unset auto-negotiation 1G advertisement */
720 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
721 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
722 &autoneg_reg);
723
724 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
725 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
726 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
727
728 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
729 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
730 autoneg_reg);
731 }
732
733 if (speed & IXGBE_LINK_SPEED_100_FULL) {
734 /* Set or unset auto-negotiation 100M advertisement */
735 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
736 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
737 &autoneg_reg);
738
739 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
740 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
741 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
742
743 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
744 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
745 autoneg_reg);
746 }
747
748 /* Restart PHY autonegotiation and wait for completion */
749 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
750 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
751
752 autoneg_reg |= IXGBE_MII_RESTART;
753
754 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
755 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
756
757 /* Wait for autonegotiation to finish */
758 for (time_out = 0; time_out < max_time_out; time_out++) {
759 usec_delay(10);
760 /* Restart PHY autonegotiation and wait for completion */
761 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
762 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
763 &autoneg_reg);
764
765 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
766 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
767 break;
768 }
769
770 if (time_out == max_time_out) {
771 status = IXGBE_ERR_LINK_SETUP;
772 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
773 }
774
775 return status;
776}
777
778/**
779 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
780 * @hw: pointer to hardware structure
781 * @firmware_version: pointer to the PHY Firmware Version
782 **/
783s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
784 u16 *firmware_version)
785{
786 s32 status = IXGBE_SUCCESS;
787
788 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
789
790 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
791 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
792 firmware_version);
793
794 return status;
795}
796
797/**
798 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
799 * @hw: pointer to hardware structure
800 * @firmware_version: pointer to the PHY Firmware Version
801 **/
802s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
803 u16 *firmware_version)
804{
805 s32 status = IXGBE_SUCCESS;
806
807 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
808
809 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
810 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
811 firmware_version);
812
813 return status;
814}
815
816/**
817 * ixgbe_reset_phy_nl - Performs a PHY reset
818 * @hw: pointer to hardware structure
819 **/
820s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
821{
822 u16 phy_offset, control, eword, edata, block_crc;
823 bool end_data = FALSE;
824 u16 list_offset, data_offset;
825 u16 phy_data = 0;
826 s32 ret_val = IXGBE_SUCCESS;
827 u32 i;
828
829 DEBUGFUNC("ixgbe_reset_phy_nl");
830
831 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
832 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
833
834 /* reset the PHY and poll for completion */
835 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
836 IXGBE_MDIO_PHY_XS_DEV_TYPE,
837 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
838
839 for (i = 0; i < 100; i++) {
840 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
841 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
842 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
843 break;
844 msec_delay(10);
845 }
846
847 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
848 DEBUGOUT("PHY reset did not complete.\n");
849 ret_val = IXGBE_ERR_PHY;
850 goto out;
851 }
852
853 /* Get init offsets */
854 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
855 &data_offset);
856 if (ret_val != IXGBE_SUCCESS)
857 goto out;
858
859 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
860 data_offset++;
861 while (!end_data) {
862 /*
863 * Read control word from PHY init contents offset
864 */
865 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
866 control = (eword & IXGBE_CONTROL_MASK_NL) >>
867 IXGBE_CONTROL_SHIFT_NL;
868 edata = eword & IXGBE_DATA_MASK_NL;
869 switch (control) {
870 case IXGBE_DELAY_NL:
871 data_offset++;
872 DEBUGOUT1("DELAY: %d MS\n", edata);
873 msec_delay(edata);
874 break;
875 case IXGBE_DATA_NL:
876 DEBUGOUT("DATA:\n");
877 data_offset++;
878 hw->eeprom.ops.read(hw, data_offset++,
879 &phy_offset);
880 for (i = 0; i < edata; i++) {
881 hw->eeprom.ops.read(hw, data_offset, &eword);
882 hw->phy.ops.write_reg(hw, phy_offset,
883 IXGBE_TWINAX_DEV, eword);
884 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
885 phy_offset);
886 data_offset++;
887 phy_offset++;
888 }
889 break;
890 case IXGBE_CONTROL_NL:
891 data_offset++;
892 DEBUGOUT("CONTROL:\n");
893 if (edata == IXGBE_CONTROL_EOL_NL) {
894 DEBUGOUT("EOL\n");
895 end_data = TRUE;
896 } else if (edata == IXGBE_CONTROL_SOL_NL) {
897 DEBUGOUT("SOL\n");
898 } else {
899 DEBUGOUT("Bad control value\n");
900 ret_val = IXGBE_ERR_PHY;
901 goto out;
902 }
903 break;
904 default:
905 DEBUGOUT("Bad control type\n");
906 ret_val = IXGBE_ERR_PHY;
907 goto out;
908 }
909 }
910
911out:
912 return ret_val;
913}
914
915/**
916 * ixgbe_identify_module_generic - Identifies module type
917 * @hw: pointer to hardware structure
918 *
919 * Determines HW type and calls appropriate function.
920 **/
921s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
922{
923 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
924
925 DEBUGFUNC("ixgbe_identify_module_generic");
926
927 switch (hw->mac.ops.get_media_type(hw)) {
928 case ixgbe_media_type_fiber:
929 status = ixgbe_identify_sfp_module_generic(hw);
930 break;
931
932
933 default:
934 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
935 status = IXGBE_ERR_SFP_NOT_PRESENT;
936 break;
937 }
938
939 return status;
940}
941
942/**
943 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
944 * @hw: pointer to hardware structure
945 *
946 * Searches for and identifies the SFP module and assigns appropriate PHY type.
947 **/
948s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
949{
950 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
951 u32 vendor_oui = 0;
952 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
953 u8 identifier = 0;
954 u8 comp_codes_1g = 0;
955 u8 comp_codes_10g = 0;
956 u8 oui_bytes[3] = {0, 0, 0};
957 u8 cable_tech = 0;
958 u8 cable_spec = 0;
959 u16 enforce_sfp = 0;
960
961 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
962
963 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
964 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
965 status = IXGBE_ERR_SFP_NOT_PRESENT;
966 goto out;
967 }
968
969 status = hw->phy.ops.read_i2c_eeprom(hw,
970 IXGBE_SFF_IDENTIFIER,
971 &identifier);
972
973 if (status != IXGBE_SUCCESS)
974 goto err_read_i2c_eeprom;
975
976 /* LAN ID is needed for sfp_type determination */
977 hw->mac.ops.set_lan_id(hw);
978
979 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
980 hw->phy.type = ixgbe_phy_sfp_unsupported;
981 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
982 } else {
983 status = hw->phy.ops.read_i2c_eeprom(hw,
984 IXGBE_SFF_1GBE_COMP_CODES,
985 &comp_codes_1g);
986
987 if (status != IXGBE_SUCCESS)
988 goto err_read_i2c_eeprom;
989
990 status = hw->phy.ops.read_i2c_eeprom(hw,
991 IXGBE_SFF_10GBE_COMP_CODES,
992 &comp_codes_10g);
993
994 if (status != IXGBE_SUCCESS)
995 goto err_read_i2c_eeprom;
996 status = hw->phy.ops.read_i2c_eeprom(hw,
997 IXGBE_SFF_CABLE_TECHNOLOGY,
998 &cable_tech);
999
1000 if (status != IXGBE_SUCCESS)
1001 goto err_read_i2c_eeprom;
1002
1003 /* ID Module
1004 * =========
1005 * 0 SFP_DA_CU
1006 * 1 SFP_SR
1007 * 2 SFP_LR
1008 * 3 SFP_DA_CORE0 - 82599-specific
1009 * 4 SFP_DA_CORE1 - 82599-specific
1010 * 5 SFP_SR/LR_CORE0 - 82599-specific
1011 * 6 SFP_SR/LR_CORE1 - 82599-specific
1012 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1013 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1014 * 9 SFP_1g_cu_CORE0 - 82599-specific
1015 * 10 SFP_1g_cu_CORE1 - 82599-specific
1016 * 11 SFP_1g_sx_CORE0 - 82599-specific
1017 * 12 SFP_1g_sx_CORE1 - 82599-specific
1018 */
1019 if (hw->mac.type == ixgbe_mac_82598EB) {
1020 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1021 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1022 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1023 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1024 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1025 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1026 else
1027 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1028 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1029 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1030 if (hw->bus.lan_id == 0)
1031 hw->phy.sfp_type =
1032 ixgbe_sfp_type_da_cu_core0;
1033 else
1034 hw->phy.sfp_type =
1035 ixgbe_sfp_type_da_cu_core1;
1036 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1037 hw->phy.ops.read_i2c_eeprom(
1038 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1039 &cable_spec);
1040 if (cable_spec &
1041 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1042 if (hw->bus.lan_id == 0)
1043 hw->phy.sfp_type =
1044 ixgbe_sfp_type_da_act_lmt_core0;
1045 else
1046 hw->phy.sfp_type =
1047 ixgbe_sfp_type_da_act_lmt_core1;
1048 } else {
1049 hw->phy.sfp_type =
1050 ixgbe_sfp_type_unknown;
1051 }
1052 } else if (comp_codes_10g &
1053 (IXGBE_SFF_10GBASESR_CAPABLE |
1054 IXGBE_SFF_10GBASELR_CAPABLE)) {
1055 if (hw->bus.lan_id == 0)
1056 hw->phy.sfp_type =
1057 ixgbe_sfp_type_srlr_core0;
1058 else
1059 hw->phy.sfp_type =
1060 ixgbe_sfp_type_srlr_core1;
1061 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1062 if (hw->bus.lan_id == 0)
1063 hw->phy.sfp_type =
1064 ixgbe_sfp_type_1g_cu_core0;
1065 else
1066 hw->phy.sfp_type =
1067 ixgbe_sfp_type_1g_cu_core1;
1068 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1069 if (hw->bus.lan_id == 0)
1070 hw->phy.sfp_type =
1071 ixgbe_sfp_type_1g_sx_core0;
1072 else
1073 hw->phy.sfp_type =
1074 ixgbe_sfp_type_1g_sx_core1;
1075 } else {
1076 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1077 }
1078 }
1079
1080 if (hw->phy.sfp_type != stored_sfp_type)
1081 hw->phy.sfp_setup_needed = TRUE;
1082
1083 /* Determine if the SFP+ PHY is dual speed or not. */
1084 hw->phy.multispeed_fiber = FALSE;
1085 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1086 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1087 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1088 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1089 hw->phy.multispeed_fiber = TRUE;
1090
1091 /* Determine PHY vendor */
1092 if (hw->phy.type != ixgbe_phy_nl) {
1093 hw->phy.id = identifier;
1094 status = hw->phy.ops.read_i2c_eeprom(hw,
1095 IXGBE_SFF_VENDOR_OUI_BYTE0,
1096 &oui_bytes[0]);
1097
1098 if (status != IXGBE_SUCCESS)
1099 goto err_read_i2c_eeprom;
1100
1101 status = hw->phy.ops.read_i2c_eeprom(hw,
1102 IXGBE_SFF_VENDOR_OUI_BYTE1,
1103 &oui_bytes[1]);
1104
1105 if (status != IXGBE_SUCCESS)
1106 goto err_read_i2c_eeprom;
1107
1108 status = hw->phy.ops.read_i2c_eeprom(hw,
1109 IXGBE_SFF_VENDOR_OUI_BYTE2,
1110 &oui_bytes[2]);
1111
1112 if (status != IXGBE_SUCCESS)
1113 goto err_read_i2c_eeprom;
1114
1115 vendor_oui =
1116 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1117 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1118 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1119
1120 switch (vendor_oui) {
1121 case IXGBE_SFF_VENDOR_OUI_TYCO:
1122 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1123 hw->phy.type =
1124 ixgbe_phy_sfp_passive_tyco;
1125 break;
1126 case IXGBE_SFF_VENDOR_OUI_FTL:
1127 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1128 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1129 else
1130 hw->phy.type = ixgbe_phy_sfp_ftl;
1131 break;
1132 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1133 hw->phy.type = ixgbe_phy_sfp_avago;
1134 break;
1135 case IXGBE_SFF_VENDOR_OUI_INTEL:
1136 hw->phy.type = ixgbe_phy_sfp_intel;
1137 break;
1138 default:
1139 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1140 hw->phy.type =
1141 ixgbe_phy_sfp_passive_unknown;
1142 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1143 hw->phy.type =
1144 ixgbe_phy_sfp_active_unknown;
1145 else
1146 hw->phy.type = ixgbe_phy_sfp_unknown;
1147 break;
1148 }
1149 }
1150
1151 /* Allow any DA cable vendor */
1152 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1153 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1154 status = IXGBE_SUCCESS;
1155 goto out;
1156 }
1157
1158 /* Verify supported 1G SFP modules */
1159 if (comp_codes_10g == 0 &&
1160 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1161 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1162 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1163 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1164 hw->phy.type = ixgbe_phy_sfp_unsupported;
1165 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1166 goto out;
1167 }
1168
1169 /* Anything else 82598-based is supported */
1170 if (hw->mac.type == ixgbe_mac_82598EB) {
1171 status = IXGBE_SUCCESS;
1172 goto out;
1173 }
1174
1175 ixgbe_get_device_caps(hw, &enforce_sfp);
1176 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1177 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1178 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
1179 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||
1180 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
1181 /* Make sure we're a supported PHY type */
1182 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1183 status = IXGBE_SUCCESS;
1184 } else {
1185 if (hw->allow_unsupported_sfp == TRUE) {
1186 EWARN(hw, "WARNING: Intel (R) Network "
1187 "Connections are quality tested "
1188 "using Intel (R) Ethernet Optics."
1189 " Using untested modules is not "
1190 "supported and may cause unstable"
1191 " operation or damage to the "
1192 "module or the adapter. Intel "
1193 "Corporation is not responsible "
1194 "for any harm caused by using "
1195 "untested modules.\n", status);
1196 status = IXGBE_SUCCESS;
1197 } else {
1198 DEBUGOUT("SFP+ module not supported\n");
1199 hw->phy.type =
1200 ixgbe_phy_sfp_unsupported;
1201 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1202 }
1203 }
1204 } else {
1205 status = IXGBE_SUCCESS;
1206 }
1207 }
1208
1209out:
1210 return status;
1211
1212err_read_i2c_eeprom:
1213 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1214 if (hw->phy.type != ixgbe_phy_nl) {
1215 hw->phy.id = 0;
1216 hw->phy.type = ixgbe_phy_unknown;
1217 }
1218 return IXGBE_ERR_SFP_NOT_PRESENT;
1219}
1220
1221
1222
1223/**
1224 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1225 * @hw: pointer to hardware structure
1226 * @list_offset: offset to the SFP ID list
1227 * @data_offset: offset to the SFP data block
1228 *
1229 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1230 * so it returns the offsets to the phy init sequence block.
1231 **/
1232s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1233 u16 *list_offset,
1234 u16 *data_offset)
1235{
1236 u16 sfp_id;
1237 u16 sfp_type = hw->phy.sfp_type;
1238
1239 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1240
1241 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1242 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1243
1244 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1245 return IXGBE_ERR_SFP_NOT_PRESENT;
1246
1247 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1248 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1249 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1250
1251 /*
1252 * Limiting active cables and 1G Phys must be initialized as
1253 * SR modules
1254 */
1255 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1256 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1257 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1258 sfp_type = ixgbe_sfp_type_srlr_core0;
1259 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1260 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1261 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1262 sfp_type = ixgbe_sfp_type_srlr_core1;
1263
1264 /* Read offset to PHY init contents */
1265 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1266
1267 if ((!*list_offset) || (*list_offset == 0xFFFF))
1268 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1269
1270 /* Shift offset to first ID word */
1271 (*list_offset)++;
1272
1273 /*
1274 * Find the matching SFP ID in the EEPROM
1275 * and program the init sequence
1276 */
1277 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1278
1279 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1280 if (sfp_id == sfp_type) {
1281 (*list_offset)++;
1282 hw->eeprom.ops.read(hw, *list_offset, data_offset);
1283 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1284 DEBUGOUT("SFP+ module not supported\n");
1285 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1286 } else {
1287 break;
1288 }
1289 } else {
1290 (*list_offset) += 2;
1291 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1292 return IXGBE_ERR_PHY;
1293 }
1294 }
1295
1296 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1297 DEBUGOUT("No matching SFP+ module found\n");
1298 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1299 }
1300
1301 return IXGBE_SUCCESS;
1302}
1303
1304/**
1305 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1306 * @hw: pointer to hardware structure
1307 * @byte_offset: EEPROM byte offset to read
1308 * @eeprom_data: value read
1309 *
1310 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1311 **/
1312s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1313 u8 *eeprom_data)
1314{
1315 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1316
1317 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1318 IXGBE_I2C_EEPROM_DEV_ADDR,
1319 eeprom_data);
1320}
1321
1322/**
1323 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1324 * @hw: pointer to hardware structure
1325 * @byte_offset: byte offset at address 0xA2
1326 * @eeprom_data: value read
1327 *
1328 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1329 **/
1330static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1331 u8 *sff8472_data)
1332{
1333 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1334 IXGBE_I2C_EEPROM_DEV_ADDR2,
1335 sff8472_data);
1336}
1337
1338/**
1339 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1340 * @hw: pointer to hardware structure
1341 * @byte_offset: EEPROM byte offset to write
1342 * @eeprom_data: value to write
1343 *
1344 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1345 **/
1346s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1347 u8 eeprom_data)
1348{
1349 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1350
1351 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1352 IXGBE_I2C_EEPROM_DEV_ADDR,
1353 eeprom_data);
1354}
1355
1356/**
1357 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1358 * @hw: pointer to hardware structure
1359 * @byte_offset: byte offset to read
1360 * @data: value read
1361 *
1362 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1363 * a specified device address.
1364 **/
1365s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1366 u8 dev_addr, u8 *data)
1367{
1368 s32 status = IXGBE_SUCCESS;
1369 u32 max_retry = 10;
1370 u32 retry = 0;
1371 u16 swfw_mask = 0;
1372 bool nack = 1;
1373 *data = 0;
1374
1375 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1376
1377 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1378 swfw_mask = IXGBE_GSSR_PHY1_SM;
1379 else
1380 swfw_mask = IXGBE_GSSR_PHY0_SM;
1381
1382 do {
1383 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1384 != IXGBE_SUCCESS) {
1385 status = IXGBE_ERR_SWFW_SYNC;
1386 goto read_byte_out;
1387 }
1388
1389 ixgbe_i2c_start(hw);
1390
1391 /* Device Address and write indication */
1392 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1393 if (status != IXGBE_SUCCESS)
1394 goto fail;
1395
1396 status = ixgbe_get_i2c_ack(hw);
1397 if (status != IXGBE_SUCCESS)
1398 goto fail;
1399
1400 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1401 if (status != IXGBE_SUCCESS)
1402 goto fail;
1403
1404 status = ixgbe_get_i2c_ack(hw);
1405 if (status != IXGBE_SUCCESS)
1406 goto fail;
1407
1408 ixgbe_i2c_start(hw);
1409
1410 /* Device Address and read indication */
1411 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1412 if (status != IXGBE_SUCCESS)
1413 goto fail;
1414
1415 status = ixgbe_get_i2c_ack(hw);
1416 if (status != IXGBE_SUCCESS)
1417 goto fail;
1418
1419 status = ixgbe_clock_in_i2c_byte(hw, data);
1420 if (status != IXGBE_SUCCESS)
1421 goto fail;
1422
1423 status = ixgbe_clock_out_i2c_bit(hw, nack);
1424 if (status != IXGBE_SUCCESS)
1425 goto fail;
1426
1427 ixgbe_i2c_stop(hw);
1428 break;
1429
1430fail:
1431 ixgbe_i2c_bus_clear(hw);
1432 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1433 msec_delay(100);
1434 retry++;
1435 if (retry < max_retry)
1436 DEBUGOUT("I2C byte read error - Retrying.\n");
1437 else
1438 DEBUGOUT("I2C byte read error.\n");
1439
1440 } while (retry < max_retry);
1441
1442 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1443
1444read_byte_out:
1445 return status;
1446}
1447
1448/**
1449 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1450 * @hw: pointer to hardware structure
1451 * @byte_offset: byte offset to write
1452 * @data: value to write
1453 *
1454 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1455 * a specified device address.
1456 **/
1457s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1458 u8 dev_addr, u8 data)
1459{
1460 s32 status = IXGBE_SUCCESS;
1461 u32 max_retry = 1;
1462 u32 retry = 0;
1463 u16 swfw_mask = 0;
1464
1465 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1466
1467 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1468 swfw_mask = IXGBE_GSSR_PHY1_SM;
1469 else
1470 swfw_mask = IXGBE_GSSR_PHY0_SM;
1471
1472 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1473 status = IXGBE_ERR_SWFW_SYNC;
1474 goto write_byte_out;
1475 }
1476
1477 do {
1478 ixgbe_i2c_start(hw);
1479
1480 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1481 if (status != IXGBE_SUCCESS)
1482 goto fail;
1483
1484 status = ixgbe_get_i2c_ack(hw);
1485 if (status != IXGBE_SUCCESS)
1486 goto fail;
1487
1488 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1489 if (status != IXGBE_SUCCESS)
1490 goto fail;
1491
1492 status = ixgbe_get_i2c_ack(hw);
1493 if (status != IXGBE_SUCCESS)
1494 goto fail;
1495
1496 status = ixgbe_clock_out_i2c_byte(hw, data);
1497 if (status != IXGBE_SUCCESS)
1498 goto fail;
1499
1500 status = ixgbe_get_i2c_ack(hw);
1501 if (status != IXGBE_SUCCESS)
1502 goto fail;
1503
1504 ixgbe_i2c_stop(hw);
1505 break;
1506
1507fail:
1508 ixgbe_i2c_bus_clear(hw);
1509 retry++;
1510 if (retry < max_retry)
1511 DEBUGOUT("I2C byte write error - Retrying.\n");
1512 else
1513 DEBUGOUT("I2C byte write error.\n");
1514 } while (retry < max_retry);
1515
1516 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1517
1518write_byte_out:
1519 return status;
1520}
1521
1522/**
1523 * ixgbe_i2c_start - Sets I2C start condition
1524 * @hw: pointer to hardware structure
1525 *
1526 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1527 **/
1528static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1529{
1530 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1531
1532 DEBUGFUNC("ixgbe_i2c_start");
1533
1534 /* Start condition must begin with data and clock high */
1535 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1536 ixgbe_raise_i2c_clk(hw, &i2cctl);
1537
1538 /* Setup time for start condition (4.7us) */
1539 usec_delay(IXGBE_I2C_T_SU_STA);
1540
1541 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1542
1543 /* Hold time for start condition (4us) */
1544 usec_delay(IXGBE_I2C_T_HD_STA);
1545
1546 ixgbe_lower_i2c_clk(hw, &i2cctl);
1547
1548 /* Minimum low period of clock is 4.7 us */
1549 usec_delay(IXGBE_I2C_T_LOW);
1550
1551}
1552
1553/**
1554 * ixgbe_i2c_stop - Sets I2C stop condition
1555 * @hw: pointer to hardware structure
1556 *
1557 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1558 **/
1559static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1560{
1561 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1562
1563 DEBUGFUNC("ixgbe_i2c_stop");
1564
1565 /* Stop condition must begin with data low and clock high */
1566 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1567 ixgbe_raise_i2c_clk(hw, &i2cctl);
1568
1569 /* Setup time for stop condition (4us) */
1570 usec_delay(IXGBE_I2C_T_SU_STO);
1571
1572 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1573
1574 /* bus free time between stop and start (4.7us)*/
1575 usec_delay(IXGBE_I2C_T_BUF);
1576}
1577
1578/**
1579 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1580 * @hw: pointer to hardware structure
1581 * @data: data byte to clock in
1582 *
1583 * Clocks in one byte data via I2C data/clock
1584 **/
1585static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1586{
1587 s32 i;
1588 bool bit = 0;
1589
1590 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1591
1592 for (i = 7; i >= 0; i--) {
1593 ixgbe_clock_in_i2c_bit(hw, &bit);
1594 *data |= bit << i;
1595 }
1596
1597 return IXGBE_SUCCESS;
1598}
1599
1600/**
1601 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1602 * @hw: pointer to hardware structure
1603 * @data: data byte clocked out
1604 *
1605 * Clocks out one byte data via I2C data/clock
1606 **/
1607static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1608{
1609 s32 status = IXGBE_SUCCESS;
1610 s32 i;
1611 u32 i2cctl;
1612 bool bit = 0;
1613
1614 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1615
1616 for (i = 7; i >= 0; i--) {
1617 bit = (data >> i) & 0x1;
1618 status = ixgbe_clock_out_i2c_bit(hw, bit);
1619
1620 if (status != IXGBE_SUCCESS)
1621 break;
1622 }
1623
1624 /* Release SDA line (set high) */
1625 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1626 i2cctl |= IXGBE_I2C_DATA_OUT;
1627 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1628 IXGBE_WRITE_FLUSH(hw);
1629
1630 return status;
1631}
1632
1633/**
1634 * ixgbe_get_i2c_ack - Polls for I2C ACK
1635 * @hw: pointer to hardware structure
1636 *
1637 * Clocks in/out one bit via I2C data/clock
1638 **/
1639static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1640{
1641 s32 status = IXGBE_SUCCESS;
1642 u32 i = 0;
1643 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1644 u32 timeout = 10;
1645 bool ack = 1;
1646
1647 DEBUGFUNC("ixgbe_get_i2c_ack");
1648
1649 ixgbe_raise_i2c_clk(hw, &i2cctl);
1650
1651
1652 /* Minimum high period of clock is 4us */
1653 usec_delay(IXGBE_I2C_T_HIGH);
1654
1655 /* Poll for ACK. Note that ACK in I2C spec is
1656 * transition from 1 to 0 */
1657 for (i = 0; i < timeout; i++) {
1658 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1659 ack = ixgbe_get_i2c_data(&i2cctl);
1660
1661 usec_delay(1);
1662 if (ack == 0)
1663 break;
1664 }
1665
1666 if (ack == 1) {
1667 DEBUGOUT("I2C ack was not received.\n");
1668 status = IXGBE_ERR_I2C;
1669 }
1670
1671 ixgbe_lower_i2c_clk(hw, &i2cctl);
1672
1673 /* Minimum low period of clock is 4.7 us */
1674 usec_delay(IXGBE_I2C_T_LOW);
1675
1676 return status;
1677}
1678
1679/**
1680 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1681 * @hw: pointer to hardware structure
1682 * @data: read data value
1683 *
1684 * Clocks in one bit via I2C data/clock
1685 **/
1686static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1687{
1688 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1689
1690 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1691
1692 ixgbe_raise_i2c_clk(hw, &i2cctl);
1693
1694 /* Minimum high period of clock is 4us */
1695 usec_delay(IXGBE_I2C_T_HIGH);
1696
1697 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1698 *data = ixgbe_get_i2c_data(&i2cctl);
1699
1700 ixgbe_lower_i2c_clk(hw, &i2cctl);
1701
1702 /* Minimum low period of clock is 4.7 us */
1703 usec_delay(IXGBE_I2C_T_LOW);
1704
1705 return IXGBE_SUCCESS;
1706}
1707
1708/**
1709 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1710 * @hw: pointer to hardware structure
1711 * @data: data value to write
1712 *
1713 * Clocks out one bit via I2C data/clock
1714 **/
1715static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1716{
1717 s32 status;
1718 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1719
1720 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1721
1722 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1723 if (status == IXGBE_SUCCESS) {
1724 ixgbe_raise_i2c_clk(hw, &i2cctl);
1725
1726 /* Minimum high period of clock is 4us */
1727 usec_delay(IXGBE_I2C_T_HIGH);
1728
1729 ixgbe_lower_i2c_clk(hw, &i2cctl);
1730
1731 /* Minimum low period of clock is 4.7 us.
1732 * This also takes care of the data hold time.
1733 */
1734 usec_delay(IXGBE_I2C_T_LOW);
1735 } else {
1736 status = IXGBE_ERR_I2C;
1737 DEBUGOUT1("I2C data was not set to %X\n", data);
1738 }
1739
1740 return status;
1741}
1742/**
1743 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1744 * @hw: pointer to hardware structure
1745 * @i2cctl: Current value of I2CCTL register
1746 *
1747 * Raises the I2C clock line '0'->'1'
1748 **/
1749static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1750{
1751 u32 i = 0;
1752 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1753 u32 i2cctl_r = 0;
1754
1755 DEBUGFUNC("ixgbe_raise_i2c_clk");
1756
1757 for (i = 0; i < timeout; i++) {
1758 *i2cctl |= IXGBE_I2C_CLK_OUT;
1759
1760 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1761 IXGBE_WRITE_FLUSH(hw);
1762 /* SCL rise time (1000ns) */
1763 usec_delay(IXGBE_I2C_T_RISE);
1764
1765 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1766 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1767 break;
1768 }
1769}
1770
1771/**
1772 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1773 * @hw: pointer to hardware structure
1774 * @i2cctl: Current value of I2CCTL register
1775 *
1776 * Lowers the I2C clock line '1'->'0'
1777 **/
1778static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1779{
1780
1781 DEBUGFUNC("ixgbe_lower_i2c_clk");
1782
1783 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1784
1785 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1786 IXGBE_WRITE_FLUSH(hw);
1787
1788 /* SCL fall time (300ns) */
1789 usec_delay(IXGBE_I2C_T_FALL);
1790}
1791
1792/**
1793 * ixgbe_set_i2c_data - Sets the I2C data bit
1794 * @hw: pointer to hardware structure
1795 * @i2cctl: Current value of I2CCTL register
1796 * @data: I2C data value (0 or 1) to set
1797 *
1798 * Sets the I2C data bit
1799 **/
1800static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1801{
1802 s32 status = IXGBE_SUCCESS;
1803
1804 DEBUGFUNC("ixgbe_set_i2c_data");
1805
1806 if (data)
1807 *i2cctl |= IXGBE_I2C_DATA_OUT;
1808 else
1809 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1810
1811 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1812 IXGBE_WRITE_FLUSH(hw);
1813
1814 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1815 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1816
1817 /* Verify data was set correctly */
1818 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1819 if (data != ixgbe_get_i2c_data(i2cctl)) {
1820 status = IXGBE_ERR_I2C;
1821 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
1822 }
1823
1824 return status;
1825}
1826
1827/**
1828 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1829 * @hw: pointer to hardware structure
1830 * @i2cctl: Current value of I2CCTL register
1831 *
1832 * Returns the I2C data bit value
1833 **/
1834static bool ixgbe_get_i2c_data(u32 *i2cctl)
1835{
1836 bool data;
1837
1838 DEBUGFUNC("ixgbe_get_i2c_data");
1839
1840 if (*i2cctl & IXGBE_I2C_DATA_IN)
1841 data = 1;
1842 else
1843 data = 0;
1844
1845 return data;
1846}
1847
1848/**
1849 * ixgbe_i2c_bus_clear - Clears the I2C bus
1850 * @hw: pointer to hardware structure
1851 *
1852 * Clears the I2C bus by sending nine clock pulses.
1853 * Used when data line is stuck low.
1854 **/
1855void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1856{
1857 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1858 u32 i;
1859
1860 DEBUGFUNC("ixgbe_i2c_bus_clear");
1861
1862 ixgbe_i2c_start(hw);
1863
1864 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1865
1866 for (i = 0; i < 9; i++) {
1867 ixgbe_raise_i2c_clk(hw, &i2cctl);
1868
1869 /* Min high period of clock is 4us */
1870 usec_delay(IXGBE_I2C_T_HIGH);
1871
1872 ixgbe_lower_i2c_clk(hw, &i2cctl);
1873
1874 /* Min low period of clock is 4.7us*/
1875 usec_delay(IXGBE_I2C_T_LOW);
1876 }
1877
1878 ixgbe_i2c_start(hw);
1879
1880 /* Put the i2c bus back to default state */
1881 ixgbe_i2c_stop(hw);
1882}
1883
1884/**
1885 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1886 * @hw: pointer to hardware structure
1887 *
1888 * Checks if the LASI temp alarm status was triggered due to overtemp
1889 **/
1890s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1891{
1892 s32 status = IXGBE_SUCCESS;
1893 u16 phy_data = 0;
1894
1895 DEBUGFUNC("ixgbe_tn_check_overtemp");
1896
1897 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1898 goto out;
1899
1900 /* Check that the LASI temp alarm status was triggered */
1901 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1902 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1903
1904 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1905 goto out;
1906
1907 status = IXGBE_ERR_OVERTEMP;
1908out:
1909 return status;
1910}