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ixgbe_common.c (190873) ixgbe_common.c (194875)
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 190873 2009-04-10 00:22:48Z jfv $*/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 194875 2009-06-24 18:27:07Z jfv $*/
34
35#include "ixgbe_common.h"
36#include "ixgbe_api.h"
37
38static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
39static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);

--- 40 unchanged lines hidden (view full) ---

82 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
83 mac->ops.get_media_type = NULL;
84 mac->ops.get_supported_physical_layer = NULL;
85 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
86 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
87 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
88 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
89 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
34
35#include "ixgbe_common.h"
36#include "ixgbe_api.h"
37
38static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
39static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);

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82 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
83 mac->ops.get_media_type = NULL;
84 mac->ops.get_supported_physical_layer = NULL;
85 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
86 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
87 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
88 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
89 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
90 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
91 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
90
91 /* LEDs */
92 mac->ops.led_on = &ixgbe_led_on_generic;
93 mac->ops.led_off = &ixgbe_led_off_generic;
94 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
95 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
96
97 /* RAR, Multicast, VLAN */

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787 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
788 * @hw: pointer to hardware structure
789 *
790 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
791 **/
792static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
793{
794 s32 status = IXGBE_ERR_EEPROM;
92
93 /* LEDs */
94 mac->ops.led_on = &ixgbe_led_on_generic;
95 mac->ops.led_off = &ixgbe_led_off_generic;
96 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
97 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
98
99 /* RAR, Multicast, VLAN */

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789 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
790 * @hw: pointer to hardware structure
791 *
792 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
793 **/
794static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
795{
796 s32 status = IXGBE_ERR_EEPROM;
795 u32 timeout;
797 u32 timeout = 2000;
796 u32 i;
797 u32 swsm;
798
798 u32 i;
799 u32 swsm;
800
799 /* Set timeout value based on size of EEPROM */
800 timeout = hw->eeprom.word_size + 1;
801
802 /* Get SMBI software semaphore between device drivers first */
803 for (i = 0; i < timeout; i++) {
804 /*
805 * If the SMBI bit is 0 when we read it, then the bit will be
806 * set and we have the semaphore
807 */
808 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
809 if (!(swsm & IXGBE_SWSM_SMBI)) {

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1073
1074 usec_delay(1);
1075
1076 /* Stop requesting EEPROM access */
1077 eec &= ~IXGBE_EEC_REQ;
1078 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1079
1080 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
801 /* Get SMBI software semaphore between device drivers first */
802 for (i = 0; i < timeout; i++) {
803 /*
804 * If the SMBI bit is 0 when we read it, then the bit will be
805 * set and we have the semaphore
806 */
807 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
808 if (!(swsm & IXGBE_SWSM_SMBI)) {

--- 263 unchanged lines hidden (view full) ---

1072
1073 usec_delay(1);
1074
1075 /* Stop requesting EEPROM access */
1076 eec &= ~IXGBE_EEC_REQ;
1077 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1078
1079 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1080
1081 /* Delay before attempt to obtain semaphore again to allow FW access */
1082 msec_delay(hw->eeprom.semaphore_delay);
1081}
1082
1083/**
1084 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1085 * @hw: pointer to hardware structure
1086 **/
1087static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
1088{

--- 539 unchanged lines hidden (view full) ---

1628 *
1629 * Enable flow control according to the current settings.
1630 **/
1631s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1632{
1633 s32 ret_val = IXGBE_SUCCESS;
1634 u32 mflcn_reg, fccfg_reg;
1635 u32 reg;
1083}
1084
1085/**
1086 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1087 * @hw: pointer to hardware structure
1088 **/
1089static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
1090{

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1630 *
1631 * Enable flow control according to the current settings.
1632 **/
1633s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1634{
1635 s32 ret_val = IXGBE_SUCCESS;
1636 u32 mflcn_reg, fccfg_reg;
1637 u32 reg;
1638 u32 rx_pba_size;
1636
1637 DEBUGFUNC("ixgbe_fc_enable_generic");
1638
1639 /* Negotiate the fc mode to use */
1640 ret_val = ixgbe_fc_autoneg(hw);
1641 if (ret_val)
1642 goto out;
1643

--- 50 unchanged lines hidden (view full) ---

1694 break;
1695 }
1696
1697 /* Set 802.3x based flow control settings. */
1698 mflcn_reg |= IXGBE_MFLCN_DPF;
1699 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1700 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1701
1639
1640 DEBUGFUNC("ixgbe_fc_enable_generic");
1641
1642 /* Negotiate the fc mode to use */
1643 ret_val = ixgbe_fc_autoneg(hw);
1644 if (ret_val)
1645 goto out;
1646

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1697 break;
1698 }
1699
1700 /* Set 802.3x based flow control settings. */
1701 mflcn_reg |= IXGBE_MFLCN_DPF;
1702 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1703 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1704
1702 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
1703 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1704 if (hw->fc.send_xon) {
1705 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
1706 (hw->fc.low_water | IXGBE_FCRTL_XONE));
1707 } else {
1708 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
1709 hw->fc.low_water);
1710 }
1705 reg = IXGBE_READ_REG(hw, IXGBE_MTQC);
1706 /* Thresholds are different for link flow control when in DCB mode */
1707 if (reg & IXGBE_MTQC_RT_ENA) {
1708 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
1711
1709
1712 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
1713 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
1710 /* Always disable XON for LFC when in DCB mode */
1711 reg = (rx_pba_size >> 5) & 0xFFE0;
1712 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg);
1713
1714 reg = (rx_pba_size >> 2) & 0xFFE0;
1715 if (hw->fc.current_mode & ixgbe_fc_tx_pause)
1716 reg |= IXGBE_FCRTH_FCEN;
1717 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg);
1718 } else {
1719 /* Set up and enable Rx high/low water mark thresholds,
1720 * enable XON. */
1721 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1722 if (hw->fc.send_xon) {
1723 IXGBE_WRITE_REG(hw,
1724 IXGBE_FCRTL_82599(packetbuf_num),
1725 (hw->fc.low_water |
1726 IXGBE_FCRTL_XONE));
1727 } else {
1728 IXGBE_WRITE_REG(hw,
1729 IXGBE_FCRTL_82599(packetbuf_num),
1730 hw->fc.low_water);
1731 }
1732
1733 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
1734 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
1735 }
1714 }
1715
1716 /* Configure pause time (2 TCs per register) */
1736 }
1737
1738 /* Configure pause time (2 TCs per register) */
1717 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
1739 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
1718 if ((packetbuf_num & 1) == 0)
1719 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1720 else
1721 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1722 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1723
1724 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1725

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2038
2039 ixgbe_get_eeprom_semaphore(hw);
2040
2041 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2042 gssr &= ~swmask;
2043 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2044
2045 ixgbe_release_eeprom_semaphore(hw);
1740 if ((packetbuf_num & 1) == 0)
1741 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1742 else
1743 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1744 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1745
1746 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1747

--- 312 unchanged lines hidden (view full) ---

2060
2061 ixgbe_get_eeprom_semaphore(hw);
2062
2063 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2064 gssr &= ~swmask;
2065 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2066
2067 ixgbe_release_eeprom_semaphore(hw);
2046
2047 /* Delay before attempt to obtain semaphore again to allow FW access */
2048 msec_delay(hw->eeprom.semaphore_delay);
2049}
2050
2051/**
2052 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2053 * @hw: pointer to hardware structure
2054 * @regval: register value to write to RXCTRL
2055 *
2056 * Enables the Rx DMA unit

--- 19 unchanged lines hidden (view full) ---

2076
2077 /*
2078 * Link must be up to auto-blink the LEDs;
2079 * Force it if link is down.
2080 */
2081 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2082
2083 if (!link_up) {
2068}
2069
2070/**
2071 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2072 * @hw: pointer to hardware structure
2073 * @regval: register value to write to RXCTRL
2074 *
2075 * Enables the Rx DMA unit

--- 19 unchanged lines hidden (view full) ---

2095
2096 /*
2097 * Link must be up to auto-blink the LEDs;
2098 * Force it if link is down.
2099 */
2100 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2101
2102 if (!link_up) {
2103
2104 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2084 autoc_reg |= IXGBE_AUTOC_FLU;
2085 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2086 msec_delay(10);
2087 }
2088
2089 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2090 led_reg |= IXGBE_LED_BLINK(index);
2091 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);

--- 7 unchanged lines hidden (view full) ---

2099 * @hw: pointer to hardware structure
2100 * @index: led number to stop blinking
2101 **/
2102s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2103{
2104 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2105 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2106
2105 autoc_reg |= IXGBE_AUTOC_FLU;
2106 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2107 msec_delay(10);
2108 }
2109
2110 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2111 led_reg |= IXGBE_LED_BLINK(index);
2112 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);

--- 7 unchanged lines hidden (view full) ---

2120 * @hw: pointer to hardware structure
2121 * @index: led number to stop blinking
2122 **/
2123s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2124{
2125 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2126 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2127
2128
2107 autoc_reg &= ~IXGBE_AUTOC_FLU;
2108 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2109 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2110
2111 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2112 led_reg &= ~IXGBE_LED_BLINK(index);
2113 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2114 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2115 IXGBE_WRITE_FLUSH(hw);
2116
2117 return IXGBE_SUCCESS;
2118}
2119
2129 autoc_reg &= ~IXGBE_AUTOC_FLU;
2130 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2131 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2132
2133 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2134 led_reg &= ~IXGBE_LED_BLINK(index);
2135 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2136 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2137 IXGBE_WRITE_FLUSH(hw);
2138
2139 return IXGBE_SUCCESS;
2140}
2141