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ixgbe_82598.c (181003) ixgbe_82598.c (185352)
1/******************************************************************************
2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82598.c 181003 2008-07-30 18:15:18Z jfv $*/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82598.c 185352 2008-11-26 23:41:18Z jfv $*/
34
35#include "ixgbe_type.h"
36#include "ixgbe_api.h"
37#include "ixgbe_common.h"
38#include "ixgbe_phy.h"
39
40s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
34
35#include "ixgbe_type.h"
36#include "ixgbe_api.h"
37#include "ixgbe_common.h"
38#include "ixgbe_phy.h"
39
40s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
41s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
41static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
45 ixgbe_link_speed *speed,
46 bool *autoneg);
44s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
45 ixgbe_link_speed *speed,
46 bool *autoneg);
47enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
47static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
48s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
48s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
49s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw);
50s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
51 ixgbe_link_speed *speed,
52 bool *link_up, bool link_up_wait_to_complete);
53s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
54 ixgbe_link_speed speed,
55 bool autoneg,
56 bool autoneg_wait_to_complete);
57s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
58s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
59 ixgbe_link_speed speed,
60 bool autoneg,
61 bool autoneg_wait_to_complete);
49s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
50static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw);
51static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
52 ixgbe_link_speed *speed, bool *link_up,
53 bool link_up_wait_to_complete);
54static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
55 ixgbe_link_speed speed,
56 bool autoneg,
57 bool autoneg_wait_to_complete);
58static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
59static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
60 ixgbe_link_speed speed,
61 bool autoneg,
62 bool autoneg_wait_to_complete);
62#ifndef NO_82598_A0_SUPPORT
63s32 ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw);
64#endif
63#ifndef NO_82598_A0_SUPPORT
64s32 ixgbe_reset_hw_rev_0_82598(struct ixgbe_hw *hw);
65#endif
65s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
66s32 ixgbe_configure_fiber_serdes_fc_82598(struct ixgbe_hw *hw);
67s32 ixgbe_setup_fiber_serdes_link_82598(struct ixgbe_hw *hw);
66static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
68s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
67s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
69s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
68static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
70s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan,
69s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan,
71 u32 vind, bool vlan_on);
72s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
73s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index);
74s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index);
70 u32 vind, bool vlan_on);
71static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
72static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index);
73static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index);
74s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
75s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
76s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
77 u8 *eeprom_data);
78u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
75
76/**
77 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
78 * @hw: pointer to hardware structure
79 *
80 * Initialize the function pointers and assign the MAC type for 82598.
81 * Does not touch the hardware.
82 **/
83s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
84{
85 struct ixgbe_mac_info *mac = &hw->mac;
86 struct ixgbe_phy_info *phy = &hw->phy;
87 s32 ret_val;
79
80/**
81 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
82 * @hw: pointer to hardware structure
83 *
84 * Initialize the function pointers and assign the MAC type for 82598.
85 * Does not touch the hardware.
86 **/
87s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
88{
89 struct ixgbe_mac_info *mac = &hw->mac;
90 struct ixgbe_phy_info *phy = &hw->phy;
91 s32 ret_val;
92 u16 list_offset, data_offset;
88
89 ret_val = ixgbe_init_phy_ops_generic(hw);
90 ret_val = ixgbe_init_ops_generic(hw);
91
92 /* MAC */
93#ifndef NO_82598_A0_SUPPORT
94 if (hw->revision_id == 0)
95 mac->ops.reset_hw = &ixgbe_reset_hw_rev_0_82598;
96 else
97 mac->ops.reset_hw = &ixgbe_reset_hw_82598;
98#else
99 mac->ops.reset_hw = &ixgbe_reset_hw_82598;
100#endif
101 mac->ops.get_media_type = &ixgbe_get_media_type_82598;
93
94 ret_val = ixgbe_init_phy_ops_generic(hw);
95 ret_val = ixgbe_init_ops_generic(hw);
96
97 /* MAC */
98#ifndef NO_82598_A0_SUPPORT
99 if (hw->revision_id == 0)
100 mac->ops.reset_hw = &ixgbe_reset_hw_rev_0_82598;
101 else
102 mac->ops.reset_hw = &ixgbe_reset_hw_82598;
103#else
104 mac->ops.reset_hw = &ixgbe_reset_hw_82598;
105#endif
106 mac->ops.get_media_type = &ixgbe_get_media_type_82598;
107 mac->ops.get_supported_physical_layer =
108 &ixgbe_get_supported_physical_layer_82598;
109 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
110 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
102
103 /* LEDs */
104 mac->ops.blink_led_start = &ixgbe_blink_led_start_82598;
105 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_82598;
106
107 /* RAR, Multicast, VLAN */
108 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
109 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
110 mac->ops.set_vfta = &ixgbe_set_vfta_82598;
111 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
112
113 /* Flow Control */
114 mac->ops.setup_fc = &ixgbe_setup_fc_82598;
115
111
112 /* LEDs */
113 mac->ops.blink_led_start = &ixgbe_blink_led_start_82598;
114 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_82598;
115
116 /* RAR, Multicast, VLAN */
117 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
118 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
119 mac->ops.set_vfta = &ixgbe_set_vfta_82598;
120 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
121
122 /* Flow Control */
123 mac->ops.setup_fc = &ixgbe_setup_fc_82598;
124
116 /* Call PHY identify routine to get the phy type */
117 phy->ops.identify(hw);
118
119 /* PHY Init */
120 switch (hw->phy.type) {
121 case ixgbe_phy_tn:
122 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
123 phy->ops.get_firmware_version =
124 &ixgbe_get_phy_firmware_version_tnx;
125 break;
126 default:
127 break;
128 }
129
130 /* Link */
131 mac->ops.check_link = &ixgbe_check_mac_link_82598;
132 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
133 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
134 mac->ops.setup_link_speed =
135 &ixgbe_setup_copper_link_speed_82598;
136 mac->ops.get_link_capabilities =
137 &ixgbe_get_copper_link_capabilities_82598;

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143 }
144
145 mac->mcft_size = 128;
146 mac->vft_size = 128;
147 mac->num_rar_entries = 16;
148 mac->max_tx_queues = 32;
149 mac->max_rx_queues = 64;
150
125 /* Link */
126 mac->ops.check_link = &ixgbe_check_mac_link_82598;
127 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
128 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
129 mac->ops.setup_link_speed =
130 &ixgbe_setup_copper_link_speed_82598;
131 mac->ops.get_link_capabilities =
132 &ixgbe_get_copper_link_capabilities_82598;

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138 }
139
140 mac->mcft_size = 128;
141 mac->vft_size = 128;
142 mac->num_rar_entries = 16;
143 mac->max_tx_queues = 32;
144 mac->max_rx_queues = 64;
145
151 return IXGBE_SUCCESS;
146 /* SFP+ Module */
147 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
148
149 /* Call PHY identify routine to get the phy type */
150 phy->ops.identify(hw);
151
152 /* PHY Init */
153 switch (hw->phy.type) {
154 case ixgbe_phy_tn:
155 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
156 phy->ops.get_firmware_version =
157 &ixgbe_get_phy_firmware_version_tnx;
158 break;
159 case ixgbe_phy_nl:
160 phy->ops.reset = &ixgbe_reset_phy_nl;
161
162 /* Call SFP+ identify routine to get the SFP+ module type */
163 ret_val = phy->ops.identify_sfp(hw);
164 if (ret_val != IXGBE_SUCCESS)
165 goto out;
166 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
167 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
168 goto out;
169 }
170
171 /* Check to see if SFP+ module is supported */
172 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
173 &list_offset,
174 &data_offset);
175 if (ret_val != IXGBE_SUCCESS) {
176 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
177 goto out;
178 }
179 break;
180 default:
181 break;
182 }
183
184out:
185 return ret_val;
152}
153
154/**
155 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
156 * @hw: pointer to hardware structure
157 * @speed: pointer to link speed
158 * @autoneg: boolean auto-negotiation value
159 *
160 * Determines the link capabilities by reading the AUTOC register.
161 **/
186}
187
188/**
189 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
190 * @hw: pointer to hardware structure
191 * @speed: pointer to link speed
192 * @autoneg: boolean auto-negotiation value
193 *
194 * Determines the link capabilities by reading the AUTOC register.
195 **/
162s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
163 ixgbe_link_speed *speed,
164 bool *autoneg)
196static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
197 ixgbe_link_speed *speed,
198 bool *autoneg)
165{
166 s32 status = IXGBE_SUCCESS;
167 s32 autoc_reg;
168
169 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
170
171 if (hw->mac.link_settings_loaded) {
172 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;

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223{
224 s32 status = IXGBE_ERR_LINK_SETUP;
225 u16 speed_ability;
226
227 *speed = 0;
228 *autoneg = TRUE;
229
230 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
199{
200 s32 status = IXGBE_SUCCESS;
201 s32 autoc_reg;
202
203 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
204
205 if (hw->mac.link_settings_loaded) {
206 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;

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257{
258 s32 status = IXGBE_ERR_LINK_SETUP;
259 u16 speed_ability;
260
261 *speed = 0;
262 *autoneg = TRUE;
263
264 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
231 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
232 &speed_ability);
265 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
266 &speed_ability);
233
234 if (status == IXGBE_SUCCESS) {
235 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
236 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
237 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
238 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
239 }
240
241 return status;
242}
243
244/**
245 * ixgbe_get_media_type_82598 - Determines media type
246 * @hw: pointer to hardware structure
247 *
248 * Returns the media type (fiber, copper, backplane)
249 **/
267
268 if (status == IXGBE_SUCCESS) {
269 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
270 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
271 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
272 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
273 }
274
275 return status;
276}
277
278/**
279 * ixgbe_get_media_type_82598 - Determines media type
280 * @hw: pointer to hardware structure
281 *
282 * Returns the media type (fiber, copper, backplane)
283 **/
250enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
284static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
251{
252 enum ixgbe_media_type media_type;
253
254 /* Media type for I82598 is based on device ID */
255 switch (hw->device_id) {
285{
286 enum ixgbe_media_type media_type;
287
288 /* Media type for I82598 is based on device ID */
289 switch (hw->device_id) {
290 case IXGBE_DEV_ID_82598:
291 /* Default device ID is mezzanine card KX/KX4 */
292 media_type = ixgbe_media_type_backplane;
293 break;
256 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
257 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
258 case IXGBE_DEV_ID_82598EB_CX4:
259 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
294 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
295 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
296 case IXGBE_DEV_ID_82598EB_CX4:
297 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
298 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
299 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
260 case IXGBE_DEV_ID_82598EB_XF_LR:
300 case IXGBE_DEV_ID_82598EB_XF_LR:
301 case IXGBE_DEV_ID_82598EB_SFP_LOM:
261 media_type = ixgbe_media_type_fiber;
262 break;
263 case IXGBE_DEV_ID_82598AT:
264 media_type = ixgbe_media_type_copper;
265 break;
302 media_type = ixgbe_media_type_fiber;
303 break;
304 case IXGBE_DEV_ID_82598AT:
305 media_type = ixgbe_media_type_copper;
306 break;
266 case IXGBE_DEV_ID_82598AT_DUAL_PORT:
267 media_type = ixgbe_media_type_copper;
268 break;
269 default:
270 media_type = ixgbe_media_type_unknown;
271 break;
272 }
273
274 return media_type;
275}
276
277/**
307 default:
308 media_type = ixgbe_media_type_unknown;
309 break;
310 }
311
312 return media_type;
313}
314
315/**
278 * ixgbe_setup_fc_82598 - Configure flow control settings
316 * ixgbe_fc_enable_82598 - Enable flow control
279 * @hw: pointer to hardware structure
280 * @packetbuf_num: packet buffer number (0-7)
281 *
317 * @hw: pointer to hardware structure
318 * @packetbuf_num: packet buffer number (0-7)
319 *
282 * Configures the flow control settings based on SW configuration. This
283 * function is used for 802.3x flow control configuration only.
320 * Enable flow control according to the current settings.
284 **/
321 **/
285s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
322s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
286{
323{
287 u32 frctl_reg;
324 s32 ret_val = IXGBE_SUCCESS;
325 u32 fctrl_reg;
288 u32 rmcs_reg;
326 u32 rmcs_reg;
327 u32 reg;
289
328
290 if (packetbuf_num < 0 || packetbuf_num > 7) {
291 DEBUGOUT1("Invalid packet buffer number [%d], expected range is"
292 " 0-7\n", packetbuf_num);
293 ASSERT(0);
294 }
329 DEBUGFUNC("ixgbe_fc_enable_82598");
295
330
296 frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
297 frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
331 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
332 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
298
299 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
300 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
301
302 /*
333
334 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
335 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
336
337 /*
303 * 10 gig parts do not have a word in the EEPROM to determine the
304 * default flow control setting, so we explicitly set it to full.
305 */
306 if (hw->fc.type == ixgbe_fc_default)
307 hw->fc.type = ixgbe_fc_full;
308
309 /*
310 * We want to save off the original Flow Control configuration just in
311 * case we get disconnected and then reconnected into a different hub
312 * or switch with different Flow Control capabilities.
313 */
314 hw->fc.original_type = hw->fc.type;
315
316 /*
317 * The possible values of the "flow_control" parameter are:
338 * The possible values of fc.current_mode are:
318 * 0: Flow control is completely disabled
339 * 0: Flow control is completely disabled
319 * 1: Rx flow control is enabled (we can receive pause frames but not
320 * send pause frames).
321 * 2: Tx flow control is enabled (we can send pause frames but we do not
322 * support receiving pause frames)
340 * 1: Rx flow control is enabled (we can receive pause frames,
341 * but not send pause frames).
342 * 2: Tx flow control is enabled (we can send pause frames but
343 * we do not support receiving pause frames).
323 * 3: Both Rx and Tx flow control (symmetric) are enabled.
324 * other: Invalid.
325 */
344 * 3: Both Rx and Tx flow control (symmetric) are enabled.
345 * other: Invalid.
346 */
326 switch (hw->fc.type) {
347 switch (hw->fc.current_mode) {
327 case ixgbe_fc_none:
348 case ixgbe_fc_none:
349 /* Flow control completely disabled by software override. */
328 break;
329 case ixgbe_fc_rx_pause:
330 /*
350 break;
351 case ixgbe_fc_rx_pause:
352 /*
331 * Rx Flow control is enabled,
332 * and Tx Flow control is disabled.
353 * Rx Flow control is enabled and Tx Flow control is
354 * disabled by software override. Since there really
355 * isn't a way to advertise that we are capable of RX
356 * Pause ONLY, we will advertise that we support both
357 * symmetric and asymmetric Rx PAUSE. Later, we will
358 * disable the adapter's ability to send PAUSE frames.
333 */
359 */
334 frctl_reg |= IXGBE_FCTRL_RFCE;
360 fctrl_reg |= IXGBE_FCTRL_RFCE;
335 break;
336 case ixgbe_fc_tx_pause:
337 /*
361 break;
362 case ixgbe_fc_tx_pause:
363 /*
338 * Tx Flow control is enabled, and Rx Flow control is disabled,
339 * by a software over-ride.
364 * Tx Flow control is enabled, and Rx Flow control is
365 * disabled by software override.
340 */
341 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
342 break;
343 case ixgbe_fc_full:
366 */
367 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
368 break;
369 case ixgbe_fc_full:
344 /*
345 * Flow control (both Rx and Tx) is enabled by a software
346 * over-ride.
347 */
348 frctl_reg |= IXGBE_FCTRL_RFCE;
370 /* Flow control (both Rx and Tx) is enabled by SW override. */
371 fctrl_reg |= IXGBE_FCTRL_RFCE;
349 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
350 break;
351 default:
372 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
373 break;
374 default:
352 /* We should never get here. The value should be 0-3. */
353 DEBUGOUT("Flow control param set incorrectly\n");
375 DEBUGOUT("Flow control param set incorrectly\n");
354 ASSERT(0);
376 ret_val = -IXGBE_ERR_CONFIG;
377 goto out;
355 break;
356 }
357
358 /* Enable 802.3x based flow control settings. */
378 break;
379 }
380
381 /* Enable 802.3x based flow control settings. */
359 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg);
382 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
360 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
361
383 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
384
362 /*
363 * Check for invalid software configuration, zeros are completely
364 * invalid for all parameters used past this point, and if we enable
365 * flow control with zero water marks, we blast flow control packets.
366 */
367 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
368 DEBUGOUT("Flow control structure initialized incorrectly\n");
369 return IXGBE_ERR_INVALID_LINK_SETTINGS;
370 }
371
372 /*
373 * We need to set up the Receive Threshold high and low water
374 * marks as well as (optionally) enabling the transmission of
375 * XON frames.
376 */
377 if (hw->fc.type & ixgbe_fc_tx_pause) {
385 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
386 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
378 if (hw->fc.send_xon) {
379 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
380 (hw->fc.low_water | IXGBE_FCRTL_XONE));
381 } else {
382 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
383 hw->fc.low_water);
384 }
387 if (hw->fc.send_xon) {
388 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
389 (hw->fc.low_water | IXGBE_FCRTL_XONE));
390 } else {
391 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
392 hw->fc.low_water);
393 }
394
385 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
395 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
386 (hw->fc.high_water)|IXGBE_FCRTH_FCEN);
396 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
387 }
388
397 }
398
389 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time);
399 /* Configure pause time (2 TCs per register) */
400 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
401 if ((packetbuf_num & 1) == 0)
402 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
403 else
404 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
405 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
406
390 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
391
407 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
408
392 return IXGBE_SUCCESS;
409out:
410 return ret_val;
393}
394
395/**
411}
412
413/**
414 * ixgbe_setup_fc_82598 - Set up flow control
415 * @hw: pointer to hardware structure
416 *
417 * Sets up flow control.
418 **/
419s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
420{
421 s32 ret_val = IXGBE_SUCCESS;
422 ixgbe_link_speed speed;
423 bool link_up;
424
425 /* Validate the packetbuf configuration */
426 if (packetbuf_num < 0 || packetbuf_num > 7) {
427 DEBUGOUT1("Invalid packet buffer number [%d], expected range is"
428 " 0-7\n", packetbuf_num);
429 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
430 goto out;
431 }
432
433 /*
434 * Validate the water mark configuration. Zero water marks are invalid
435 * because it causes the controller to just blast out fc packets.
436 */
437 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
438 DEBUGOUT("Invalid water mark configuration\n");
439 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
440 goto out;
441 }
442
443 /*
444 * Validate the requested mode. Strict IEEE mode does not allow
445 * ixgbe_fc_rx_pause because it will cause testing anomalies.
446 */
447 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
448 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
449 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
450 goto out;
451 }
452
453 /*
454 * 10gig parts do not have a word in the EEPROM to determine the
455 * default flow control setting, so we explicitly set it to full.
456 */
457 if (hw->fc.requested_mode == ixgbe_fc_default)
458 hw->fc.requested_mode = ixgbe_fc_full;
459
460 /*
461 * Save off the requested flow control mode for use later. Depending
462 * on the link partner's capabilities, we may or may not use this mode.
463 */
464 hw->fc.current_mode = hw->fc.requested_mode;
465
466 /* Decide whether to use autoneg or not. */
467 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
468 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL))
469 ret_val = ixgbe_fc_autoneg(hw);
470
471 if (ret_val)
472 goto out;
473
474 ret_val = ixgbe_fc_enable_82598(hw, packetbuf_num);
475
476out:
477 return ret_val;
478}
479
480/**
396 * ixgbe_setup_mac_link_82598 - Configures MAC link settings
397 * @hw: pointer to hardware structure
398 *
399 * Configures link settings based on values in the ixgbe_hw struct.
400 * Restarts the link. Performs autonegotiation if needed.
401 **/
481 * ixgbe_setup_mac_link_82598 - Configures MAC link settings
482 * @hw: pointer to hardware structure
483 *
484 * Configures link settings based on values in the ixgbe_hw struct.
485 * Restarts the link. Performs autonegotiation if needed.
486 **/
402s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
487static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
403{
488{
404 ixgbe_link_speed speed;
405 bool link_up;
406 u32 autoc_reg;
407 u32 links_reg;
408 u32 i;
409 s32 status = IXGBE_SUCCESS;
410
411 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
412
413 if (hw->mac.link_settings_loaded) {

--- 24 unchanged lines hidden (view full) ---

438 }
439 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
440 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
441 DEBUGOUT("Autonegotiation did not complete.\n");
442 }
443 }
444 }
445
489 u32 autoc_reg;
490 u32 links_reg;
491 u32 i;
492 s32 status = IXGBE_SUCCESS;
493
494 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
495
496 if (hw->mac.link_settings_loaded) {

--- 24 unchanged lines hidden (view full) ---

521 }
522 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
523 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
524 DEBUGOUT("Autonegotiation did not complete.\n");
525 }
526 }
527 }
528
446 /*
447 * We want to save off the original Flow Control configuration just in
448 * case we get disconnected and then reconnected into a different hub
449 * or switch with different Flow Control capabilities.
450 */
451 hw->fc.original_type = hw->fc.type;
452 /*
453 * Set up the SerDes link if in 1Gb mode, otherwise just set up
454 * 10Gb flow control.
455 */
456 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
457 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
458 status = ixgbe_setup_fiber_serdes_link_82598(hw);
459 else
460 ixgbe_setup_fc_82598(hw, 0);
529 /* Set up flow control */
530 status = ixgbe_setup_fc_82598(hw, 0);
461
462 /* Add delay to filter out noises during initial link setup */
463 msec_delay(50);
464
465 return status;
466}
467
468/**
469 * ixgbe_check_mac_link_82598 - Get link/speed status
470 * @hw: pointer to hardware structure
471 * @speed: pointer to link speed
472 * @link_up: TRUE is link is up, FALSE otherwise
473 * @link_up_wait_to_complete: bool used to wait for link up or not
474 *
475 * Reads the links register to determine if link is up and the current speed
476 **/
531
532 /* Add delay to filter out noises during initial link setup */
533 msec_delay(50);
534
535 return status;
536}
537
538/**
539 * ixgbe_check_mac_link_82598 - Get link/speed status
540 * @hw: pointer to hardware structure
541 * @speed: pointer to link speed
542 * @link_up: TRUE is link is up, FALSE otherwise
543 * @link_up_wait_to_complete: bool used to wait for link up or not
544 *
545 * Reads the links register to determine if link is up and the current speed
546 **/
477s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
478 bool *link_up, bool link_up_wait_to_complete)
547static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
548 ixgbe_link_speed *speed, bool *link_up,
549 bool link_up_wait_to_complete)
479{
480 u32 links_reg;
481 u32 i;
550{
551 u32 links_reg;
552 u32 i;
553 u16 link_reg, adapt_comp_reg;
482
554
555 /*
556 * SERDES PHY requires us to read link status from undocumented
557 * register 0xC79F. Bit 0 set indicates link is up/ready; clear
558 * indicates link down. OxC00C is read to check that the XAUI lanes
559 * are active. Bit 0 clear indicates active; set indicates inactive.
560 */
561 if (hw->phy.type == ixgbe_phy_nl) {
562 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
563 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
564 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
565 &adapt_comp_reg);
566 if (link_up_wait_to_complete) {
567 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
568 if ((link_reg & 1) &&
569 ((adapt_comp_reg & 1) == 0)) {
570 *link_up = TRUE;
571 break;
572 } else {
573 *link_up = FALSE;
574 }
575 msec_delay(100);
576 hw->phy.ops.read_reg(hw, 0xC79F,
577 IXGBE_TWINAX_DEV,
578 &link_reg);
579 hw->phy.ops.read_reg(hw, 0xC00C,
580 IXGBE_TWINAX_DEV,
581 &adapt_comp_reg);
582 }
583 } else {
584 if ((link_reg & 1) &&
585 ((adapt_comp_reg & 1) == 0))
586 *link_up = TRUE;
587 else
588 *link_up = FALSE;
589 }
590
591 if (*link_up == FALSE)
592 goto out;
593 }
594
483 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
484 if (link_up_wait_to_complete) {
485 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
486 if (links_reg & IXGBE_LINKS_UP) {
487 *link_up = TRUE;
488 break;
489 } else {
490 *link_up = FALSE;

--- 8 unchanged lines hidden (view full) ---

499 *link_up = FALSE;
500 }
501
502 if (links_reg & IXGBE_LINKS_SPEED)
503 *speed = IXGBE_LINK_SPEED_10GB_FULL;
504 else
505 *speed = IXGBE_LINK_SPEED_1GB_FULL;
506
595 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
596 if (link_up_wait_to_complete) {
597 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
598 if (links_reg & IXGBE_LINKS_UP) {
599 *link_up = TRUE;
600 break;
601 } else {
602 *link_up = FALSE;

--- 8 unchanged lines hidden (view full) ---

611 *link_up = FALSE;
612 }
613
614 if (links_reg & IXGBE_LINKS_SPEED)
615 *speed = IXGBE_LINK_SPEED_10GB_FULL;
616 else
617 *speed = IXGBE_LINK_SPEED_1GB_FULL;
618
507 return IXGBE_SUCCESS;
508}
509
510/**
511 * ixgbe_configure_fiber_serdes_fc_82598 - Configure fiber flow control
512 * @hw: pointer to hardware structure
513 *
514 * Reads PCS registers and sets flow control settings, based on
515 * link-partner's abilities.
516 **/
517s32 ixgbe_configure_fiber_serdes_fc_82598(struct ixgbe_hw *hw)
518{
519 s32 ret_val = IXGBE_SUCCESS;
520 u32 pcs_anadv_reg, pcs_lpab_reg, pcs_lstat_reg, i;
521 DEBUGFUNC("ixgbe_configure_fiber_serdes_fc_82598");
522
523 /* Check that autonegotiation has completed */
524 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
525 msec_delay(10);
526 pcs_lstat_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
527 if (pcs_lstat_reg & IXGBE_PCS1GLSTA_LINK_OK) {
528 if (pcs_lstat_reg & IXGBE_PCS1GLSTA_AN_COMPLETE) {
529 if (!(pcs_lstat_reg &
530 (IXGBE_PCS1GLSTA_AN_TIMED_OUT)))
531 hw->mac.autoneg_failed = 0;
532 else
533 hw->mac.autoneg_failed = 1;
534 break;
535 } else {
536 hw->mac.autoneg_failed = 1;
537 break;
538 }
539 }
540 }
541
542 if (hw->mac.autoneg_failed) {
543 /*
544 * AutoNeg failed to achieve a link, so we will turn
545 * flow control off.
546 */
547 hw->fc.type = ixgbe_fc_none;
548 DEBUGOUT("Flow Control = NONE.\n");
549 ret_val = ixgbe_setup_fc_82598(hw, 0);
550 goto out;
551 }
552
553 /*
554 * Read the AN advertisement and LP ability registers and resolve
555 * local flow control settings accordingly
556 */
557 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
558 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
559 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
560 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
561 /*
562 * Now we need to check if the user selected Rx ONLY
563 * of pause frames. In this case, we had to advertise
564 * FULL flow control because we could not advertise RX
565 * ONLY. Hence, we must now check to see if we need to
566 * turn OFF the TRANSMISSION of PAUSE frames.
567 */
568 if (hw->fc.original_type == ixgbe_fc_full) {
569 hw->fc.type = ixgbe_fc_full;
570 DEBUGOUT("Flow Control = FULL.\n");
571 } else {
572 hw->fc.type = ixgbe_fc_rx_pause;
573 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
574 }
575 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
576 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
577 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
578 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
579 hw->fc.type = ixgbe_fc_tx_pause;
580 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
581 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
582 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
583 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
584 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
585 hw->fc.type = ixgbe_fc_rx_pause;
586 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
587 } else {
588 hw->fc.type = ixgbe_fc_none;
589 DEBUGOUT("Flow Control = NONE.\n");
590 }
591
592 ret_val = ixgbe_setup_fc_82598(hw, 0);
593 if (ret_val) {
594 DEBUGOUT("Error forcing flow control settings\n");
595 goto out;
596 }
597
598out:
619out:
599 return ret_val;
600}
601
602/**
603 * ixgbe_setup_fiber_serdes_link_82598 - Configure fiber serdes link
604 * @hw: pointer to hardware structure
605 *
606 * Sets up PCS registers and sets flow control settings, based on
607 * link-partner's abilities.
608 **/
609s32 ixgbe_setup_fiber_serdes_link_82598(struct ixgbe_hw *hw)
610{
611 u32 reg;
612 s32 ret_val;
613
614 DEBUGFUNC("ixgbe_setup_fiber_serdes_link_82598");
615
616 /*
617 * 10 gig parts do not have a word in the EEPROM to determine the
618 * default flow control setting, so we explicitly set it to full.
619 */
620 if (hw->fc.type == ixgbe_fc_default)
621 hw->fc.type = ixgbe_fc_full;
622
623 /*
624 * 82598 fiber/serdes devices require that flow control be resolved in
625 * software.
626 */
627 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
628
629 /*
630 * The possible values of the "fc" parameter are:
631 * 0: Flow control is completely disabled
632 * 1: Rx flow control is enabled (we can receive pause frames,
633 * but not send pause frames).
634 * 2: Tx flow control is enabled (we can send pause frames but
635 * we do not support receiving pause frames).
636 * 3: Both Rx and Tx flow control (symmetric) are enabled.
637 */
638 switch (hw->fc.type) {
639 case ixgbe_fc_none:
640 /*
641 * Flow control completely disabled by a software
642 * over-ride.
643 */
644 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
645 break;
646 case ixgbe_fc_rx_pause:
647 /*
648 * Rx Flow control is enabled and Tx Flow control is
649 * disabled by a software over-ride. Since there really
650 * isn't a way to advertise that we are capable of RX
651 * Pause ONLY, we will advertise that we support both
652 * symmetric and asymmetric Rx PAUSE. Later, we will
653 * disable the adapter's ability to send PAUSE frames.
654 */
655 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
656 break;
657 case ixgbe_fc_tx_pause:
658 /*
659 * Tx Flow control is enabled, and Rx Flow control is
660 * disabled, by a software over-ride.
661 */
662 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
663 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
664 break;
665 case ixgbe_fc_full:
666 /*
667 * Flow control (both Rx and Tx) is enabled by a
668 * software over-ride.
669 */
670 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
671 break;
672 default:
673 DEBUGOUT("Flow control param set incorrectly\n");
674 ret_val = -IXGBE_ERR_CONFIG;
675 goto out;
676 break;
677 }
678
679 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
680 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
681
682 /* Set PCS register for autoneg */
683 /* Enable and restart autoneg */
684 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART;
685
686 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; /* Disable AN timeout */
687 DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
688 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
689
690 /*
691 * Configure flow control. If we aren't auto-negotiating,
692 * just setup the flow control and do not worry about PCS autoneg.
693 */
694 ixgbe_configure_fiber_serdes_fc_82598(hw);
695
696out:
697 return IXGBE_SUCCESS;
698}
699
700/**
701 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
702 * @hw: pointer to hardware structure
703 * @speed: new link speed
620 return IXGBE_SUCCESS;
621}
622
623/**
624 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
625 * @hw: pointer to hardware structure
626 * @speed: new link speed
704 * @autoneg: TRUE if auto-negotiation enabled
705 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
627 * @autoneg: TRUE if autonegotiation enabled
628 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
706 *
707 * Set the link speed in the AUTOC register and restarts link.
708 **/
629 *
630 * Set the link speed in the AUTOC register and restarts link.
631 **/
709s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
710 ixgbe_link_speed speed, bool autoneg,
711 bool autoneg_wait_to_complete)
632static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
633 ixgbe_link_speed speed, bool autoneg,
634 bool autoneg_wait_to_complete)
712{
713 s32 status = IXGBE_SUCCESS;
714
715 /* If speed is 10G, then check for CX4 or XAUI. */
716 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
717 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) {
718 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
719 } else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) {

--- 12 unchanged lines hidden (view full) ---

732 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
733
734 hw->mac.link_settings_loaded = TRUE;
735 /*
736 * Setup and restart the link based on the new values in
737 * ixgbe_hw This will write the AUTOC register based on the new
738 * stored values
739 */
635{
636 s32 status = IXGBE_SUCCESS;
637
638 /* If speed is 10G, then check for CX4 or XAUI. */
639 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
640 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) {
641 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
642 } else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) {

--- 12 unchanged lines hidden (view full) ---

655 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
656
657 hw->mac.link_settings_loaded = TRUE;
658 /*
659 * Setup and restart the link based on the new values in
660 * ixgbe_hw This will write the AUTOC register based on the new
661 * stored values
662 */
740 ixgbe_setup_mac_link_82598(hw);
663 status = ixgbe_setup_mac_link_82598(hw);
741 }
742
743 return status;
744}
745
746
747/**
748 * ixgbe_setup_copper_link_82598 - Setup copper link settings
749 * @hw: pointer to hardware structure
750 *
751 * Configures link settings based on values in the ixgbe_hw struct.
752 * Restarts the link. Performs autonegotiation if needed. Restart
753 * phy and wait for autonegotiate to finish. Then synchronize the
754 * MAC and PHY.
755 **/
664 }
665
666 return status;
667}
668
669
670/**
671 * ixgbe_setup_copper_link_82598 - Setup copper link settings
672 * @hw: pointer to hardware structure
673 *
674 * Configures link settings based on values in the ixgbe_hw struct.
675 * Restarts the link. Performs autonegotiation if needed. Restart
676 * phy and wait for autonegotiate to finish. Then synchronize the
677 * MAC and PHY.
678 **/
756s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
679static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
757{
758 s32 status;
759
760 /* Restart autonegotiation on PHY */
761 status = hw->phy.ops.setup_link(hw);
762
763 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
764 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);

--- 9 unchanged lines hidden (view full) ---

774 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
775 * @hw: pointer to hardware structure
776 * @speed: new link speed
777 * @autoneg: TRUE if autonegotiation enabled
778 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
779 *
780 * Sets the link speed in the AUTOC register in the MAC and restarts link.
781 **/
680{
681 s32 status;
682
683 /* Restart autonegotiation on PHY */
684 status = hw->phy.ops.setup_link(hw);
685
686 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
687 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);

--- 9 unchanged lines hidden (view full) ---

697 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
698 * @hw: pointer to hardware structure
699 * @speed: new link speed
700 * @autoneg: TRUE if autonegotiation enabled
701 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
702 *
703 * Sets the link speed in the AUTOC register in the MAC and restarts link.
704 **/
782s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
783 ixgbe_link_speed speed,
784 bool autoneg,
785 bool autoneg_wait_to_complete)
705static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
706 ixgbe_link_speed speed,
707 bool autoneg,
708 bool autoneg_wait_to_complete)
786{
787 s32 status;
788
789 /* Setup the PHY according to input speed */
790 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
709{
710 s32 status;
711
712 /* Setup the PHY according to input speed */
713 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
791 autoneg_wait_to_complete);
714 autoneg_wait_to_complete);
792
793 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
794 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
795 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
796
797 /* Set up MAC */
798 ixgbe_setup_mac_link_82598(hw);
799

--- 96 unchanged lines hidden (view full) ---

896/**
897 * ixgbe_reset_hw_82598 - Performs hardware reset
898 * @hw: pointer to hardware structure
899 *
900 * Resets the hardware by resetting the transmit and receive units, masks and
901 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
902 * reset.
903 **/
715
716 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
717 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
718 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
719
720 /* Set up MAC */
721 ixgbe_setup_mac_link_82598(hw);
722

--- 96 unchanged lines hidden (view full) ---

819/**
820 * ixgbe_reset_hw_82598 - Performs hardware reset
821 * @hw: pointer to hardware structure
822 *
823 * Resets the hardware by resetting the transmit and receive units, masks and
824 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
825 * reset.
826 **/
904s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
827static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
905{
906 s32 status = IXGBE_SUCCESS;
907 u32 ctrl;
908 u32 gheccr;
909 u32 i;
910 u32 autoc;
911 u8 analog_val;
912

--- 11 unchanged lines hidden (view full) ---

924 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
925 &analog_val);
926 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
927 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
928 analog_val);
929
930 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
931 &analog_val);
828{
829 s32 status = IXGBE_SUCCESS;
830 u32 ctrl;
831 u32 gheccr;
832 u32 i;
833 u32 autoc;
834 u8 analog_val;
835

--- 11 unchanged lines hidden (view full) ---

847 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
848 &analog_val);
849 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
850 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
851 analog_val);
852
853 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
854 &analog_val);
932 analog_val &= ~ IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
855 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
933 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
934 analog_val);
935
936 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
937 &analog_val);
938 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
939 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
940 analog_val);

--- 89 unchanged lines hidden (view full) ---

1030}
1031
1032/**
1033 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
1034 * @hw: pointer to hardware struct
1035 * @rar: receive address register index to associate with a VMDq index
1036 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
1037 **/
856 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
857 analog_val);
858
859 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
860 &analog_val);
861 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
862 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
863 analog_val);

--- 89 unchanged lines hidden (view full) ---

953}
954
955/**
956 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
957 * @hw: pointer to hardware struct
958 * @rar: receive address register index to associate with a VMDq index
959 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
960 **/
1038s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
961static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
1039{
1040 u32 rar_high;
1041 u32 rar_entries = hw->mac.num_rar_entries;
1042
962{
963 u32 rar_high;
964 u32 rar_entries = hw->mac.num_rar_entries;
965
1043 UNREFERENCED_PARAMETER(vmdq);
966 UNREFERENCED_PARAMETER(vmdq);
1044
1045 if (rar < rar_entries) {
1046 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
1047 if (rar_high & IXGBE_RAH_VIND_MASK) {
1048 rar_high &= ~IXGBE_RAH_VIND_MASK;
1049 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
1050 }
1051 } else {

--- 15 unchanged lines hidden (view full) ---

1067s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1068 bool vlan_on)
1069{
1070 u32 regindex;
1071 u32 bitindex;
1072 u32 bits;
1073 u32 vftabyte;
1074
967
968 if (rar < rar_entries) {
969 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
970 if (rar_high & IXGBE_RAH_VIND_MASK) {
971 rar_high &= ~IXGBE_RAH_VIND_MASK;
972 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
973 }
974 } else {

--- 15 unchanged lines hidden (view full) ---

990s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
991 bool vlan_on)
992{
993 u32 regindex;
994 u32 bitindex;
995 u32 bits;
996 u32 vftabyte;
997
1075 if (vlan < 1 || vlan > 4095)
998 if (vlan > 4095)
1076 return IXGBE_ERR_PARAM;
1077
1078 /* Determine 32-bit word position in array */
1079 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
1080
1081 /* Determine the location of the (VMD) queue index */
1082 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
1083 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */

--- 20 unchanged lines hidden (view full) ---

1104}
1105
1106/**
1107 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
1108 * @hw: pointer to hardware structure
1109 *
1110 * Clears the VLAN filer table, and the VMDq index associated with the filter
1111 **/
999 return IXGBE_ERR_PARAM;
1000
1001 /* Determine 32-bit word position in array */
1002 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
1003
1004 /* Determine the location of the (VMD) queue index */
1005 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
1006 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */

--- 20 unchanged lines hidden (view full) ---

1027}
1028
1029/**
1030 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
1031 * @hw: pointer to hardware structure
1032 *
1033 * Clears the VLAN filer table, and the VMDq index associated with the filter
1034 **/
1112s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
1035static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
1113{
1114 u32 offset;
1115 u32 vlanbyte;
1116
1117 for (offset = 0; offset < hw->mac.vft_size; offset++)
1118 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1119
1120 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
1121 for (offset = 0; offset < hw->mac.vft_size; offset++)
1122 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
1036{
1037 u32 offset;
1038 u32 vlanbyte;
1039
1040 for (offset = 0; offset < hw->mac.vft_size; offset++)
1041 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1042
1043 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
1044 for (offset = 0; offset < hw->mac.vft_size; offset++)
1045 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
1123 0);
1046 0);
1124
1125 return IXGBE_SUCCESS;
1126}
1127
1128/**
1129 * ixgbe_blink_led_start_82598 - Blink LED based on index.
1130 * @hw: pointer to hardware structure
1131 * @index: led number to blink
1132 **/
1047
1048 return IXGBE_SUCCESS;
1049}
1050
1051/**
1052 * ixgbe_blink_led_start_82598 - Blink LED based on index.
1053 * @hw: pointer to hardware structure
1054 * @index: led number to blink
1055 **/
1133s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
1056static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
1134{
1135 ixgbe_link_speed speed = 0;
1136 bool link_up = 0;
1137 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1138 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1139
1140 /*
1141 * Link must be up to auto-blink the LEDs on the 82598EB MAC;

--- 15 unchanged lines hidden (view full) ---

1157 return IXGBE_SUCCESS;
1158}
1159
1160/**
1161 * ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
1162 * @hw: pointer to hardware structure
1163 * @index: led number to stop blinking
1164 **/
1057{
1058 ixgbe_link_speed speed = 0;
1059 bool link_up = 0;
1060 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1061 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1062
1063 /*
1064 * Link must be up to auto-blink the LEDs on the 82598EB MAC;

--- 15 unchanged lines hidden (view full) ---

1080 return IXGBE_SUCCESS;
1081}
1082
1083/**
1084 * ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
1085 * @hw: pointer to hardware structure
1086 * @index: led number to stop blinking
1087 **/
1165s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
1088static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
1166{
1167 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1168 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1169
1170 autoc_reg &= ~IXGBE_AUTOC_FLU;
1089{
1090 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1091 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1092
1093 autoc_reg &= ~IXGBE_AUTOC_FLU;
1094 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
1171 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
1172
1173 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1174 led_reg &= ~IXGBE_LED_BLINK(index);
1095 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
1096
1097 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1098 led_reg &= ~IXGBE_LED_BLINK(index);
1099 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
1175 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1176 IXGBE_WRITE_FLUSH(hw);
1177
1178 return IXGBE_SUCCESS;
1179}
1100 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1101 IXGBE_WRITE_FLUSH(hw);
1102
1103 return IXGBE_SUCCESS;
1104}
1105
1106/**
1107 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
1108 * @hw: pointer to hardware structure
1109 * @reg: analog register to read
1110 * @val: read value
1111 *
1112 * Performs read operation to Atlas analog register specified.
1113 **/
1114s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
1115{
1116 u32 atlas_ctl;
1117
1118 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
1119 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1120 IXGBE_WRITE_FLUSH(hw);
1121 usec_delay(10);
1122 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1123 *val = (u8)atlas_ctl;
1124
1125 return IXGBE_SUCCESS;
1126}
1127
1128/**
1129 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
1130 * @hw: pointer to hardware structure
1131 * @reg: atlas register to write
1132 * @val: value to write
1133 *
1134 * Performs write operation to Atlas analog register specified.
1135 **/
1136s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1137{
1138 u32 atlas_ctl;
1139
1140 atlas_ctl = (reg << 8) | val;
1141 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1142 IXGBE_WRITE_FLUSH(hw);
1143 usec_delay(10);
1144
1145 return IXGBE_SUCCESS;
1146}
1147
1148/**
1149 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1150 * @hw: pointer to hardware structure
1151 * @byte_offset: EEPROM byte offset to read
1152 * @eeprom_data: value read
1153 *
1154 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1155 **/
1156s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1157 u8 *eeprom_data)
1158{
1159 s32 status = IXGBE_SUCCESS;
1160 u16 sfp_addr = 0;
1161 u16 sfp_data = 0;
1162 u16 sfp_stat = 0;
1163 u32 i;
1164
1165 if (hw->phy.type == ixgbe_phy_nl) {
1166 /*
1167 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
1168 * 0xC30D. These registers are used to talk to the SFP+
1169 * module's EEPROM through the SDA/SCL (I2C) interface.
1170 */
1171 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1172 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1173 hw->phy.ops.write_reg(hw,
1174 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1175 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1176 sfp_addr);
1177
1178 /* Poll status */
1179 for (i = 0; i < 100; i++) {
1180 hw->phy.ops.read_reg(hw,
1181 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1182 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1183 &sfp_stat);
1184 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1185 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1186 break;
1187 msec_delay(10);
1188 }
1189
1190 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1191 DEBUGOUT("EEPROM read did not pass.\n");
1192 status = IXGBE_ERR_SFP_NOT_PRESENT;
1193 goto out;
1194 }
1195
1196 /* Read data */
1197 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1198 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1199
1200 *eeprom_data = (u8)(sfp_data >> 8);
1201 } else {
1202 status = IXGBE_ERR_PHY;
1203 goto out;
1204 }
1205
1206out:
1207 return status;
1208}
1209
1210/**
1211 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1212 * @hw: pointer to hardware structure
1213 *
1214 * Determines physical layer capabilities of the current configuration.
1215 **/
1216u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1217{
1218 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1219
1220 switch (hw->device_id) {
1221 case IXGBE_DEV_ID_82598:
1222 /* Default device ID is mezzanine card KX/KX4 */
1223 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1224 IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1225 break;
1226 case IXGBE_DEV_ID_82598EB_CX4:
1227 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1228 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1229 break;
1230 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1231 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1232 break;
1233 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1234 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1235 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1236 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1237 break;
1238 case IXGBE_DEV_ID_82598EB_XF_LR:
1239 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1240 break;
1241 case IXGBE_DEV_ID_82598AT:
1242 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
1243 IXGBE_PHYSICAL_LAYER_1000BASE_T);
1244 break;
1245 case IXGBE_DEV_ID_82598EB_SFP_LOM:
1246 hw->phy.ops.identify_sfp(hw);
1247
1248 switch (hw->phy.sfp_type) {
1249 case ixgbe_sfp_type_da_cu:
1250 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1251 break;
1252 case ixgbe_sfp_type_sr:
1253 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1254 break;
1255 case ixgbe_sfp_type_lr:
1256 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1257 break;
1258 default:
1259 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1260 break;
1261 }
1262 break;
1263
1264 default:
1265 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1266 break;
1267 }
1268
1269 return physical_layer;
1270}