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ixgbe.h (181003) ixgbe.h (185352)
1/******************************************************************************
2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe.h 181003 2008-07-30 18:15:18Z jfv $*/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe.h 185352 2008-11-26 23:41:18Z jfv $*/
34
34
35
35#ifndef _IXGBE_H_
36#define _IXGBE_H_
37
38
39#include <sys/param.h>
40#include <sys/systm.h>
41#include <sys/mbuf.h>
42#include <sys/protosw.h>

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58#include <net/if_vlan_var.h>
59
60#include <netinet/in_systm.h>
61#include <netinet/in.h>
62#include <netinet/if_ether.h>
63#include <netinet/ip.h>
64#include <netinet/ip6.h>
65#include <netinet/tcp.h>
36#ifndef _IXGBE_H_
37#define _IXGBE_H_
38
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/mbuf.h>
43#include <sys/protosw.h>

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59#include <net/if_vlan_var.h>
60
61#include <netinet/in_systm.h>
62#include <netinet/in.h>
63#include <netinet/if_ether.h>
64#include <netinet/ip.h>
65#include <netinet/ip6.h>
66#include <netinet/tcp.h>
66#include <netinet/tcp_lro.h>
67#include <netinet/udp.h>
68
69#include <machine/in_cksum.h>
70
71#include <sys/bus.h>
72#include <machine/bus.h>
73#include <sys/rman.h>
74#include <machine/resource.h>

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79#include <dev/pci/pcireg.h>
80#include <sys/proc.h>
81#include <sys/sysctl.h>
82#include <sys/endian.h>
83#include <sys/taskqueue.h>
84#include <sys/pcpu.h>
85
86#include "ixgbe_api.h"
67#include <netinet/udp.h>
68
69#include <machine/in_cksum.h>
70
71#include <sys/bus.h>
72#include <machine/bus.h>
73#include <sys/rman.h>
74#include <machine/resource.h>

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79#include <dev/pci/pcireg.h>
80#include <sys/proc.h>
81#include <sys/sysctl.h>
82#include <sys/endian.h>
83#include <sys/taskqueue.h>
84#include <sys/pcpu.h>
85
86#include "ixgbe_api.h"
87#include "tcp_lro.h"
87
88/* Tunables */
89
90/*
91 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
92 * number of transmit descriptors allocated by the driver. Increasing this
93 * value allows the driver to queue more transmits. Each descriptor is 16
94 * bytes. Performance tests have show the 2K value to be optimal for top

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116
117/* Alignment for rings */
118#define DBA_ALIGN 128
119
120/*
121 * This parameter controls the maximum no of times the driver will loop in
122 * the isr. Minimum Value = 1
123 */
88
89/* Tunables */
90
91/*
92 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
93 * number of transmit descriptors allocated by the driver. Increasing this
94 * value allows the driver to queue more transmits. Each descriptor is 16
95 * bytes. Performance tests have show the 2K value to be optimal for top

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117
118/* Alignment for rings */
119#define DBA_ALIGN 128
120
121/*
122 * This parameter controls the maximum no of times the driver will loop in
123 * the isr. Minimum Value = 1
124 */
124#define MAX_INTR 10
125#define MAX_LOOP 10
125
126/*
127 * This parameter controls the duration of transmit watchdog timer.
128 */
129#define IXGBE_TX_TIMEOUT 5 /* set to 5 seconds */
130
131/*
132 * This parameters control when the driver calls the routine to reclaim

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154#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
155#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
156#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
157#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
158#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
159
160#define MAX_NUM_MULTICAST_ADDRESSES 128
161#define IXGBE_MAX_SCATTER 100
126
127/*
128 * This parameter controls the duration of transmit watchdog timer.
129 */
130#define IXGBE_TX_TIMEOUT 5 /* set to 5 seconds */
131
132/*
133 * This parameters control when the driver calls the routine to reclaim

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155#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
156#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
157#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
158#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
159#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
160
161#define MAX_NUM_MULTICAST_ADDRESSES 128
162#define IXGBE_MAX_SCATTER 100
162#define IXGBE_MSIX_BAR 3
163#define MSIX_82598_BAR 3
164#define MSIX_82599_BAR 4
163#define IXGBE_TSO_SIZE 65535
164#define IXGBE_TX_BUFFER_SIZE ((u32) 1514)
165#define IXGBE_TSO_SIZE 65535
166#define IXGBE_TX_BUFFER_SIZE ((u32) 1514)
165#define IXGBE_RX_HDR_SIZE ((u32) 256)
167#define IXGBE_RX_HDR 128
166#define CSUM_OFFLOAD 7 /* Bits in csum flags */
167
168/* The number of MSIX messages the 82598 supports */
169#define IXGBE_MSGS 18
170
171/* For 6.X code compatibility */
172#if __FreeBSD_version < 700000
173#define ETHER_BPF_MTAP BPF_MTAP
174#define CSUM_TSO 0
175#define IFCAP_TSO4 0
176#define FILTER_STRAY
177#define FILTER_HANDLED
178#endif
179
180/*
181 * Interrupt Moderation parameters
168#define CSUM_OFFLOAD 7 /* Bits in csum flags */
169
170/* The number of MSIX messages the 82598 supports */
171#define IXGBE_MSGS 18
172
173/* For 6.X code compatibility */
174#if __FreeBSD_version < 700000
175#define ETHER_BPF_MTAP BPF_MTAP
176#define CSUM_TSO 0
177#define IFCAP_TSO4 0
178#define FILTER_STRAY
179#define FILTER_HANDLED
180#endif
181
182/*
183 * Interrupt Moderation parameters
182 * for now we hardcode, later
183 * it would be nice to do dynamic
184 */
184 */
185#define MAX_IRQ_SEC 8000
186#define DEFAULT_ITR 1000000000/(MAX_IRQ_SEC * 256)
187#define LINK_ITR 1000000000/(1950 * 256)
185#define IXGBE_LOW_LATENCY 128
186#define IXGBE_AVE_LATENCY 400
187#define IXGBE_BULK_LATENCY 1200
188#define IXGBE_LINK_ITR 2000
188
189
190/* Header split args for get_bug */
191#define IXGBE_CLEAN_HDR 1
192#define IXGBE_CLEAN_PKT 2
193#define IXGBE_CLEAN_ALL 3
194
189/* Used for auto RX queue configuration */
190extern int mp_ncpus;
191
192/*
195/* Used for auto RX queue configuration */
196extern int mp_ncpus;
197
198/*
193 * ******************************************************************************
199 *****************************************************************************
194 * vendor_info_array
195 *
196 * This array contains the list of Subvendor/Subdevice IDs on which the driver
197 * should load.
198 *
200 * vendor_info_array
201 *
202 * This array contains the list of Subvendor/Subdevice IDs on which the driver
203 * should load.
204 *
199*****************************************************************************
205 *****************************************************************************
200 */
201typedef struct _ixgbe_vendor_info_t {
202 unsigned int vendor_id;
203 unsigned int device_id;
204 unsigned int subvendor_id;
205 unsigned int subdevice_id;
206 unsigned int index;
206 */
207typedef struct _ixgbe_vendor_info_t {
208 unsigned int vendor_id;
209 unsigned int device_id;
210 unsigned int subvendor_id;
211 unsigned int subdevice_id;
212 unsigned int index;
207} ixgbe_vendor_info_t;
213} ixgbe_vendor_info_t;
208
209
210struct ixgbe_tx_buf {
211 struct mbuf *m_head;
212 bus_dmamap_t map;
213};
214
215struct ixgbe_rx_buf {
216 struct mbuf *m_head;
214
215
216struct ixgbe_tx_buf {
217 struct mbuf *m_head;
218 bus_dmamap_t map;
219};
220
221struct ixgbe_rx_buf {
222 struct mbuf *m_head;
217 boolean_t bigbuf;
218 /* one small and one large map */
219 bus_dmamap_t map[2];
223 struct mbuf *m_pack;
224 bus_dmamap_t map;
220};
221
222/*
223 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free.
224 */
225struct ixgbe_dma_alloc {
226 bus_addr_t dma_paddr;
227 caddr_t dma_vaddr;

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248 struct task tx_task;
249 struct taskqueue *tq;
250 u32 next_avail_tx_desc;
251 u32 next_tx_to_clean;
252 struct ixgbe_tx_buf *tx_buffers;
253 volatile u16 tx_avail;
254 u32 txd_cmd;
255 bus_dma_tag_t txtag;
225};
226
227/*
228 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free.
229 */
230struct ixgbe_dma_alloc {
231 bus_addr_t dma_paddr;
232 caddr_t dma_vaddr;

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253 struct task tx_task;
254 struct taskqueue *tq;
255 u32 next_avail_tx_desc;
256 u32 next_tx_to_clean;
257 struct ixgbe_tx_buf *tx_buffers;
258 volatile u16 tx_avail;
259 u32 txd_cmd;
260 bus_dma_tag_t txtag;
261 char mtx_name[16];
256 /* Soft Stats */
257 u32 no_tx_desc_avail;
258 u32 no_tx_desc_late;
259 u64 tx_irq;
262 /* Soft Stats */
263 u32 no_tx_desc_avail;
264 u32 no_tx_desc_late;
265 u64 tx_irq;
260 u64 tx_packets;
266 u64 total_packets;
261};
262
263
264/*
265 * The Receive ring, one per rx queue
266 */
267struct rx_ring {
268 struct adapter *adapter;

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274 struct task rx_task;
275 struct taskqueue *tq;
276 union ixgbe_adv_rx_desc *rx_base;
277 struct ixgbe_dma_alloc rxdma;
278 struct lro_ctrl lro;
279 unsigned int last_cleaned;
280 unsigned int next_to_check;
281 struct ixgbe_rx_buf *rx_buffers;
267};
268
269
270/*
271 * The Receive ring, one per rx queue
272 */
273struct rx_ring {
274 struct adapter *adapter;

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280 struct task rx_task;
281 struct taskqueue *tq;
282 union ixgbe_adv_rx_desc *rx_base;
283 struct ixgbe_dma_alloc rxdma;
284 struct lro_ctrl lro;
285 unsigned int last_cleaned;
286 unsigned int next_to_check;
287 struct ixgbe_rx_buf *rx_buffers;
282 bus_dma_tag_t rxtag[2];
283 bus_dmamap_t spare_map[2];
288 bus_dma_tag_t rxtag;
289 bus_dmamap_t spare_map;
284 struct mbuf *fmp;
285 struct mbuf *lmp;
290 struct mbuf *fmp;
291 struct mbuf *lmp;
292 char mtx_name[16];
293
294 u32 bytes; /* Used for AIM calc */
295 u32 eitr_setting;
296
286 /* Soft stats */
287 u64 rx_irq;
297 /* Soft stats */
298 u64 rx_irq;
288 u64 packet_count;
289 u64 byte_count;
299 u64 rx_split_packets;
300 u64 rx_packets;
301 u64 rx_bytes;
290};
291
292/* Our adapter structure */
293struct adapter {
294 struct ifnet *ifp;
295 struct ixgbe_hw hw;
296
302};
303
304/* Our adapter structure */
305struct adapter {
306 struct ifnet *ifp;
307 struct ixgbe_hw hw;
308
297 /* FreeBSD operating-system-specific structures */
298 struct ixgbe_osdep osdep;
299 struct device *dev;
300
301 struct resource *pci_mem;
302 struct resource *msix_mem;
303
304 /*
305 * Interrupt resources:
306 * Oplin has 20 MSIX messages
307 * so allocate that for now.
308 */
309 void *tag[IXGBE_MSGS];
310 struct resource *res[IXGBE_MSGS];
311 int rid[IXGBE_MSGS];
309 struct ixgbe_osdep osdep;
310 struct device *dev;
311
312 struct resource *pci_mem;
313 struct resource *msix_mem;
314
315 /*
316 * Interrupt resources:
317 * Oplin has 20 MSIX messages
318 * so allocate that for now.
319 */
320 void *tag[IXGBE_MSGS];
321 struct resource *res[IXGBE_MSGS];
322 int rid[IXGBE_MSGS];
312 u32 eims_mask;
313
314 struct ifmedia media;
315 struct callout timer;
316 int msix;
317 int if_flags;
318
319 struct mtx core_mtx;
320
323
324 struct ifmedia media;
325 struct callout timer;
326 int msix;
327 int if_flags;
328
329 struct mtx core_mtx;
330
321 /* Legacy Fast Intr handling */
322 struct task link_task;
323
324 /* Info about the board itself */
325 u32 part_num;
331 /* Info about the board itself */
332 u32 part_num;
333 u32 optics;
326 bool link_active;
327 u16 max_frame_size;
328 u32 link_speed;
334 bool link_active;
335 u16 max_frame_size;
336 u32 link_speed;
337 u32 linkvec;
329 u32 tx_int_delay;
330 u32 tx_abs_int_delay;
331 u32 rx_int_delay;
332 u32 rx_abs_int_delay;
333
338 u32 tx_int_delay;
339 u32 tx_abs_int_delay;
340 u32 rx_int_delay;
341 u32 rx_abs_int_delay;
342
334 /* Indicates the cluster size to use */
335 bool bigbufs;
343 /* Mbuf cluster size */
344 u32 rx_mbuf_sz;
336
345
346 /* Check for missing optics */
347 bool sfp_probe;
348
337 /*
338 * Transmit rings:
339 * Allocated at run time, an array of rings.
340 */
341 struct tx_ring *tx_rings;
342 int num_tx_desc;
343 int num_tx_queues;
344
345 /*
346 * Receive rings:
347 * Allocated at run time, an array of rings.
348 */
349 struct rx_ring *rx_rings;
350 int num_rx_desc;
351 int num_rx_queues;
349 /*
350 * Transmit rings:
351 * Allocated at run time, an array of rings.
352 */
353 struct tx_ring *tx_rings;
354 int num_tx_desc;
355 int num_tx_queues;
356
357 /*
358 * Receive rings:
359 * Allocated at run time, an array of rings.
360 */
361 struct rx_ring *rx_rings;
362 int num_rx_desc;
363 int num_rx_queues;
364 u32 rx_mask;
352 u32 rx_process_limit;
353
365 u32 rx_process_limit;
366
354 eventhandler_tag vlan_attach;
355 eventhandler_tag vlan_detach;
356
357 /* Misc stats maintained by the driver */
358 unsigned long dropped_pkts;
367 /* Misc stats maintained by the driver */
368 unsigned long dropped_pkts;
359 unsigned long mbuf_alloc_failed;
360 unsigned long mbuf_cluster_failed;
369 unsigned long mbuf_defrag_failed;
370 unsigned long mbuf_header_failed;
371 unsigned long mbuf_packet_failed;
361 unsigned long no_tx_map_avail;
362 unsigned long no_tx_dma_setup;
363 unsigned long watchdog_events;
364 unsigned long tso_tx;
372 unsigned long no_tx_map_avail;
373 unsigned long no_tx_dma_setup;
374 unsigned long watchdog_events;
375 unsigned long tso_tx;
365 unsigned long linkvec;
366 unsigned long link_irq;
367
368 struct ixgbe_hw_stats stats;
369};
370
371#define IXGBE_CORE_LOCK_INIT(_sc, _name) \
372 mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF)
373#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)

--- 13 unchanged lines hidden --- 		376 unsigned long link_irq;
377
378 struct ixgbe_hw_stats stats;
379};
380
381#define IXGBE_CORE_LOCK_INIT(_sc, _name) \
382 mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF)
383#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)

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